Trainer Model: ETEK HCS-8000-03

QAM Modulator

ETEK TECHNOLOGY CO., LTD.

E-mail: [email protected]
[email protected]
http: // www.etek21.com.tw
 Education Trainer for QAM Modulator by ETEK Technology Company

I. Curriculum Objectives
1. To understand the operation theory of Quadrature Amplitude
Modulation (QAM) and the application at communication system.

2. To understand the operation theory of QAM modulator.

3. Design and implementation of QAM modulator.

4. Measurement and adjustment of QAM modulator.

II. Curriculum Theory

The objective of modulation is to transmit and overcome the limitation of

hardware effectively. For example, the transmission of audio without modulation,

which utilizes the baseband directly, the length of the antenna is

λ = c / f = (3×108 ) / (5×10 3 ) = 6 ×10 4 (assume that the audio frequency is less than 5

kHz), the result is impractically. If the transmitted frequency is 100 MHz, then the

length of the antenna is only 1 meter. Moreover, modulation can also reduce the noise

and interference, therefore, the above-mentioned are the reasons why the signal needs

to be modulated.

In case of too many users use the same frequency at the same area, it is possible

that interference will occur to each other. However, in order to prevent interference,

we utilize modulation, which can distribute and control the frequency channels and

then every user can use the appropriate channel.

Quadrature Amplitude Modulation (QAM) is the combination of two DSB

modulated signals. The carrier signals of these two groups of DSB signals are

cos 2πf c t and sin 2πf c t . As a result of the two carrier signals are orthogonal,

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High Level Digital Communication Systems (ETEK HCS-8000)

therefore, we can use the same carrier frequency to transmit two different signals. But

why cos 2πf c t and sin 2πf c t are orthogonal? By using Fourier Transform, we

know that in a set of cos nωt , sin nωt (where n = 0, 1, 2, …), any two functions are

independent and orthogonal to each other. Assuming that n = 1, ω = 2πf c t , then

according to the internal integration, we get

∫ cos 2πf t * sin 2πf t = 0

T
c c (5-1)

The internal integration of the function is zero, which is similar to the internal

integration of the vector, therefore, these functions are orthogonal to each other.

Although the carrier of cos 2πf c t and the carrier of sin 2πf c t are transmitted at the

same frequency channel, the signals are not affect to each other due to the orthogonal

and independent characteristics. Also, during demodulation, the signals can be

demodulated to two independent signals.

For the binary system in digital communication system, during the duration of

transmission, only 1 bit of signal can be transmitted. However, for other applications,

generally, we request for better efficiency, which means more bits can be transmitted

for every transmission. Therefore, there occurs a M value digital modulation and

during the transmission, it will transmit log 2 M bits of signal. For example, when M

= 4, the data which will be transmitted are (00, 01, 10, 11), each level uses log 2 4 = 2

bits. So, for every transmission of one level, there will be 2 bits of data being

transmitted each time. And the modulations for every transmission of one level, which

can transmit more than 2 bits are QPSK, 8-QAM, 16-QAM and so on. Most of the

modulations are using phase and amplitude for the first priority.

In next section, we use the constellation diagram of to represent the QPSK

modulation and 8-QAM modulation.

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cos ωt
01 00

sin ωt

10 11

Figure 5-1 Constellation diagram of QPSK modulation.

From figure 5-1, we can see that the QPSK modulation is depended on which

quadrant to determine the data signal. The advantage of this type of modulation is

when interference causes the phase shifted, as long as the phase locates at the first

quadrant, the demodulator still can demodulate the original signal. Due to this

advantage, we select the phase at 45 degree of each quadrant, so that every data has

45 degree of error range.

cos ωt

101 111

100 110

sin ωt

000 010

001 011

Figure 5-2 Constellation diagram of 8-QAM modulation.

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Figure 5-2 is the constellation diagram of 8-QAM modulation. Each quadrant has

the variations of phase and amplitude, which also represents the data is only different

with 1 bit. For example, in the first quadrant, the variations of the data are 110 and

111. Therefore, from figure 5-2, we know that there are 8 combinations in 8-QAM

modulation, which are 4 types of phase variations and 4 types of amplitude variations.

Figure 5-3 shows the circuit block diagram of 8-QAM modulation. From figure

5-3, we can classify the block diagram into three sections for explanation. The first

part is the bit splitter. The function of bit splitter is to convert the series data to

parallel data. In this case, there are 3 bits, therefore, the output data will be 1/3 of the

input signal. QAM modulation can transmit multi bits data is because it utilizes the bit

splitter to achieve. At the same time, for I channel, there are I and C channels for data

output; similarly, for Q channel, there are Q and C channels for data output.

PAM
I Channel 2 to 4 level O/P
converter
fb / 3
+
90° Phase Shift
Data fb / 3 8-QAM
I Q C O/P
OSC
+

fb / 3 2 to 4 level
Q Channel converter PAM
O/P

Figure 5-3 The circuit block diagram of 8-QAM modulation.

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 Education Trainer for QAM Modulator by ETEK Technology Company

Next is the 2 to 4 voltage level converter. The functions of 2 to 4 voltage level

converter is to convert the I, Q, C output data to its correspondence analog voltage. As

we have mentioned before, The I channel consists of I and C data outputs and the Q

channel consists of Q and C data outputs. Therefore, for every combination, there are

2 bits, which has 4 types of variation (00, 01, 10, 11). This is why it is named as 2 to 4

level converter. Table 5-1 is the truth table of 2 to 4 voltage level converter.

Table 5-1 The truth table of 2 to 4 voltage level converter.

I/Q C Output Voltage

0 0 -0.541 V

0 1 -1.304 V

1 0 0.541 V

1 1 1.304 V

The final part is the QPSK modulation. The function of QPSK modulation is to

multiply the voltage level from the converter with the carrier signal. For example, if

(Q I C) = (0 0 0), then from figure 5-3 and table 5-1, we know that at I channel, when

I = 0 and C = 0, the output voltage is –0.541 V; similarly at Q channel, when Q = 0

and C = 0, the output voltage is also –0.541 V. After passed through the multiplier, for

I channel, the PAM signal will multiply with sin ω c t , then the output is

I = (−0.541) × (sin ω c t ) = −0.541 sin ω c t (5-2)

For Q channel, the PAM signal will multiply with cos ω c t , then the output is

Q = (−0.541) × (cos ω c t ) = −0.541 cos ω c t (5-3)

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High Level Digital Communication Systems (ETEK HCS-8000)

Finally, by using the linear summer to combine the I and Q modulated signals,

we get

QAM = (−0.541sin ω c t ) + (−0.541 cos ω c t )

(5-4)
= 0.765 sin(ω c t − 135°)

Similarly, for other codes (001, 010, 011, 100, 101, 110, 111), we can obtain the

correspondence analog voltage as shown in table 5-2.

Table 5-2 The truth table of 8-QAM modulator.

Q I C Amplitudes Phases

0 0 0 0.765 V -135°

0 0 1 1.848 V -135°

0 1 0 0.765 V -45°

0 1 1 1.848 V -45°

1 0 0 0.765 V +135°

1 0 1 1.848 V +135°

1 1 0 0.765 V +45°

1 1 1 1.848 V +45°

5-1 The Design and Implementation of QAM Modulator

In this section, we will implement the 8-QAM modulator in accordance with the

circuit block diagram in figure 5-3. At the same time, we will add a pseudo random

signal generator at the input terminal of digital data.

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5-1-1 Pseudo Random Signal Generator

The transmitted signal in the communication system is not regulated as the 0101

signals. Therefore, we design a pseudo random signal generator as the data signal. As

a result of digital circuit utilizes clock as the basis to transmit data, therefore, after the

pseudo random signal generator, the clock generator will be the second important

circuit. Figure 5-4 shows the circuit diagram of clock generator. We utilizes NE555 to

implement the astable multivibrator. The output frequency of this generator is

1 1
f= = (5-5)
T 0.707 * [2 * (CLKR 1 + CLKVR 1 ) + CLKR 2 ] * CLKC1

We added a variable resistor CLKVR1, which the output frequency can be adjustable.

The function of diodes CLKD1 and CLKD2 are to let the output signals become an

equal ratio square wave, which the duty cycle is 50 %. In order to know the speed of

the signal, we add a LED at the output of the clock generator. When the clock is

getting faster, the LED will flash faster; or else, the LED will flash slower. The

function of diodes CLKD3 at the output port of clock generator is to prevent the

output status of the LED affect the circuit at the next stage.

We utilize exclusion OR gate (XOR) to implement the pseudo random generator.

When input two different values, the output is either 1 or 0. Figure 5-5 is the circuit

diagram of pseudo random generator, which the period is 4 cycles. Then the output

can be represented as

Data = Q1A ⊗ Q1B (5-6)

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High Level Digital Communication Systems (ETEK HCS-8000)

Figure 5-4 The circuit diagram of clock generator.

Figure 5-5 The circuit diagram of pseudo random data generator.

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In order to increase the cycles of the period, we need to add another D-type

flip-flop and exclusion OR gate. The reason that Q1B is connected to exclusion OR

gate is because we need to let the output become 1 during reset, then there will be a

trigger signal at the output port.

5-1-2 Bit Splitter

The function of bit splitter is to convert the series data to parallel data. As we

have mentioned before that the QPSK modulation utilizes orthogonal functions to

transmit 2 bits data at the same time. If the output bit of the bit splitter is increased,

then we can transmit more bits of data at the same time. In this chapter, we implement

the 8-QAM modulator, therefore, the output of the bit splitter is 3 bits, i.e. 23 = 8.

Similarly, if we want to implement 16-QAM modulator, then the output of the bit

splitter is 4 bits.

Figure 5-6 shows the circuit diagram of bit splitter. We utilize a counter to

determine the transmission of the data signal to certain channel, i.e. I channel, Q

channel and C channel. Then, by using the AND gate, we can obtain the data signal

from channel.

Figure 5-6 The circuit diagram of bit splitter.

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5-1-3 2 to 4 Voltage Level Converter

From figure 5-3, we know that the output from the bit splitter is the data, which

we want to transmit to the QPSK modulator. However, before the data transmit to the

QPSK modulator, the signal needs to pass through a 2 to 4 voltage level converter.

The main function of 2 to 4 voltage level converter is to convert the output of I data

and C data to its correspondence analog voltage, so that the output is a ladder wave

signal. Figure 5-7 is the circuit diagram of 2 to 4 voltage level converter. From figure

5-7, we utilize the counter to determine whether which voltage for the output, either

the VCC or the voltage division after the variable resistor. Next, we use the analog

switch as the transmitting switch. In figure 5-7, the diode is to prevent the interference

between the two signals and the capacitor is to filter the noise during signal switching.

Finally, we can obtain the ladder wave signal at the output port and the variable

resistor is to adjust the height of the ladder wave.

As a result of QAM modulation includes the variations of phase and amplitude,

therefore, in order to cause the variation of phase, the positive voltage must be

reduced to negative voltage or the negative voltage must be increased to positive

voltage. The output voltage from the 2 to 4 voltage level converter is either equal to

zero or more than zero, so, we need to implement a positive and negative voltage level

adjuster, which can let the ladder wave has the variation of positive and negative

voltage. Figure 5-8 shows the amplifier and the voltage level adjuster. By using the

variable resistor, we can adjust the ladder wave to positive voltage or negative

voltage.

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Figure 5-7 The circuit diagram of 2 to 4 level converter.

Figure 5-8 The circuit diagram of level adjuster.

5-1-4 QPSK Modulator

As we have mentioned before, we utilize the orthogonal functions to transmit

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High Level Digital Communication Systems (ETEK HCS-8000)

the carrier signals cos 2πf c t and sin 2πf c t at the same channel. Due to the

characteristics of orthogonal, these two signals are independent and can be

demodulated to two different and independent signals during demodulation. Therefore,

we utilize the balanced modulator to multiply cos 2πf c t and I signal, sin 2πf c t and

Q signal, then by combining these two signals, we can obtain the QPSK modulated

signal. Figure 5-9 is the circuit diagram of balanced modulator. However, in order to

implement QPSK modulator, we need two groups of balanced modulator. In figure

5-9, the balanced modulator is comprised by MC1496. The carrier signal and data

signal are belonging to single ended input. The carrier signal is inputted at pin 10 and

the data signal is inputted at pin 1. Resistor (R13) determines the gain of the circuit.

Resistor (R14) determines the bias current of the circuit. We can change the value of

variable resistor (VR1) or the amplitude of the digital data signal to prevent the

distortion of the modulated signal. Operational Amplifier (uA741), C3, C5, R17, R18

and R19 comprise a filter, which can remove the unwanted signal and the output of

PSK signal will be optimized. After that the signal will pass through the phase shifter,

which can divide the input carrier signal to cos 2πf c t and sin 2πf c t signals. Figure

5-10 shows the circuit diagram of phase shifter, which is used to shift the phase of

carrier signal. This situation will produce a group of orthogonal carrier signal, which

will supply to the balanced modulators of I-channel and Q-channel. The phase angle

( θ ) is related to R i , Ci and the frequency of carrier. The expression is

θ
tan ( )
Ri = 2 (5-7)
2π f C i

Figure 5-11 shows the circuit diagram of linear summer. The objective of the

linear summer is to combine the two groups of the orthogonal BPSK modulation

signals to become a QPSK signal.

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R 12
+12V
1k R13 1k C4
R15 0.01uF
100 100
3.9k
R9 R10
2 3 R16
Data C1 R3 8 6 3.9k
Signal +12V
10 C3
Input
100k 10nF 2.7k R5 10k 12 10nF
R1 10k VR 1 R7 10nF µA741 PSK
MC1496 Output
R17 C5
R2 100k 5.6k
Carrier −12 V
Signal 1
Input 6.8k 4
10k 10k
R6 14 5 R18 R19 10k
R4 R8 R11
VR 2 0.1uF 200
100 100
C2 R 14
500k 10k

−12 V

Figure 5-9 The circuit diagram of balanced modulator.

100k R2

1nF Ci
100k R1
Carrier Carrier
Input 20k R i uA741 Output
Terminal Terminal
C1
Phase
10nF
Adjustment

Figure 5-10 The circuit diagram of phase shifter.

1k

R4
1k R1
I-BPSK
QPSK
uA741
Q-BPSK Output
1k R2
R3
330

Figure 5-11 The circuit diagram of linear summer.

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High Level Digital Communication Systems (ETEK HCS-8000)

III. Experiment Items

Experiment 1: Digital Data Generator and Bit Splitter

1. To implement the clock generator, digital data generator, bit splitter and 2 to 4
voltage level converter as shown in figure 5-4, figure 5-5, figure 5-6 and figure
5-7, respectively or refer to figure 5-1 on ETEK HCS-8000-03 module.

2. By using oscilloscope, observe on the output signals of clock generator (TP4)

and pseudo random data generator (TP1). Adjust the variable resistor (Clock
Adjuster) anti clock wise to the end, then record the measured results in table 5-1.
After that adjust the variable resistor (Clock Adjuster) clock wise to the end, then
record the measured results in table 5-1. During the rotation of the variable
resistor, is there any variation for the LED of the Clock Indicator and the LED of
the Random Data Indicator?

3. By using dual channel oscilloscope, observe on the output signal waveforms of

TP1 and TP2, TP1 and TP3, TP1 and TP5. Then record the measured results in
table 5-3.

4. By using oscilloscope, observe on the output signal waveforms of TP6 and TP7.
Adjust variable resistor VR1 so that the output signal is a second order ladder
wave signal. Then record the measured results in table 5-3.

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Experiment 2: QAM Modulator

1. To implement the level adjuster, phase shifter, balanced modulator and linear
summer as shown in figure 5-8, figure 5-10, figure 5-9 and figure 5-11,
respectively or refer to figure 5-1 on ETEK HCS-8000-03 module.

2. By using oscilloscope, observe on the signal waveforms of TP8 and adjust VR2,
TP9 and adjust VR3, so that both the ladder waves occur bipolar status, then
record the measured results in table 5-4.

3. At the carrier input port (Carrier I/P), input 500 mVp-p and 20 kHz sine wave
frequency. Then by using dual channel oscilloscope, observe on the output signal
waveforms of TP10 and TP11. Adjust the variable resistor (Phase Adjuster) so
that the phase difference between these two signals is 90 degree. Then record the
measured results in table 5-4.

4. By using oscilloscope, observe on the output signal waveforms of balanced

modulator (TP12). Adjust variable resistors VR4 and VR6 so that the output
signal becomes the variations of amplitude and phase. Then, by using
oscilloscope, observe on the output signal waveforms of balanced modulator
(TP13). Adjust variable resistors VR5 and VR7 so that the output signal becomes
the variations of amplitude and phase. Finally, record the measured results in
table 5-4.

5. By using oscilloscope, observe on the output signal waveform of QAM O/P, then
record the measured results in table 5-4.

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IV. Experiment Results

Table 5-3 Measured results of digital data generator.

Test Test
Measured Results Measured Results
Points Points

TP4 TP1

Clock
Clock
Adjuster
Adjuster
Anti
Clock
Clock
Wise to
Wise to
the end
the end

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Table 5-3 Measured results of digital data generator. (Continue)

Test Test
Measured Results Measured Results
Points Points

TP1 TP1
and and
TP2 TP3

TP1
and TP6
TP5

TP7

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Table 5-4 Measured results of QAM modulator.

Test Test
Measured Results Measured Results
Points Points

TP8 TP9

TP10
and TP12
TP11

QAM
TP13
O/P

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V. Problems Discussion
1. Explain what are the differences between the QPSK modulation and
8-QAM modulation.

2. Describe the circuits, which comprised the 8-QAM modulator.

3. Describe the functions of pseudo random generator in 8-QAM

modulator.

4. Describe the functions of phase shifter in 8-QAM modulator.

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Appendix

Expected Results

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Chapter 5: Expected Measured Results

Table 5-3 Measured results of digital data generator.

Test Test
Measured Results Measured Results
Points Points

TP4 TP1

Clock
Clock
Adjuster
Adjuster
Anti
Clock
Clock
Wise to
Wise to
the end
the end

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Table 5-3 Measured results of digital data generator. (Continue)

Test Test
Measured Results Measured Results
Points Points

TP1 TP1
and and
TP2 TP3

TP1
and TP6
TP5

TP7

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Table 5-4 Measured results of QAM modulator.

Test Test
Measured Results Measured Results
Points Points

TP8 TP9

TP10
and TP12
TP11

QAM
TP13
O/P

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