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I2C (Inter Integrated Circuit) : Features

I2C is an embedded communication interface that allows easy communication between components on the same circuit board. It uses only two bidirectional lines (serial data line and serial clock line) and can connect a microcontroller to sensors, ADCs, DACs, and other devices. I2C follows a master-slave architecture with simple addressing of up to 112 unique slave devices and supports asynchronous data transfer between components.

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83 views7 pages

I2C (Inter Integrated Circuit) : Features

I2C is an embedded communication interface that allows easy communication between components on the same circuit board. It uses only two bidirectional lines (serial data line and serial clock line) and can connect a microcontroller to sensors, ADCs, DACs, and other devices. I2C follows a master-slave architecture with simple addressing of up to 112 unique slave devices and supports asynchronous data transfer between components.

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vamsikrishna gollapudi
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© © All Rights Reserved
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I2C (Inter Integrated circuit)

 I2C is one of the best embedded communication interfaces.

 It is allow easy communication between components which reside on the same


circuit board. To connect two ICs on circuit board and also used for connect
microcontroller to A/D (Analog to Digital converter), D/A (Digital to Analog
converter) or sensors.
e.g.: Temperature sensors.

 It also used to connect components which are linked via cable.

 Simplicity and flexibility are the key characteristics that make this bus especially
attractive for consumer and automotive electronics.

 It is a simple Master-Slave flip-flop, half duplex (data transmitted one way at a


time), and serial bus architecture with ACK (Acknowledgement signal) and
asynchronous transmission (transfers a single byte at a time).

 Many Slaves under one Master, with a 7/10 bit addressing.

 The I2C-bus has 2-wire interface architecture. Those are SDL (Serial Data Line)
and SCL (Serial Clock Line).

 SDL is responsible for transmission and reception of data. Master only gives the
clock pulses those clock pulses are nothing but SCL.

Features:

 Only two bus lines are required (SDL, SCL) two are bidirectional.

 No strict baud rate requirements like for instance with RS-232, the Master
generates a bus clock.
 Simple Master/Slave relationships exist between all components. Each device
connected to the bus soft ware addressable by a unique address.

 I2C is a true multi master bus providing arbitration and collision detection.

Design of I2C:

Devices to interface:
 LCD/LED drivers
 EPROM’s

 DACs, ADCs and IO expanders


 capacitive sensors
 real-time clocks
 digital temperature ICs
 accelerometers
 compass
 third party sensors with an I2C interface (sonar’s, IR range finders, NXT I2C
sensors)

 The device initiating data transfers and providing the clock signal on the bus is
called a “Master”, a device being addressed by the Master is called a “Slave”.

 Slave devices going to limit the transfer speed.


 ACK (Acknowledgement) is provided for we knowing the data is received the
destination or not, if not then we can retransmit the data.

 I2C has transmitter and receiver, follows asynchronous transmission of data.

 It can accept request from other devices.

Master and Slave those are having I2C Rx (Receiver) and I2C Tx (Transmitter), so both
sides we can sends data and receives data.

Timing diagram:

Frame format:
 The first byte of an I2C transfer contains slave address and data direction. The
address is 7-bit long. Direction bit is 1-bit long.

 112 Slave addresses are available from the 127 possible ones (7-bit) as some
address are reserved for special purposes. 10 bit addressing has been defined as
well.

 Master can stop the transfer. That is RD/WR (Read/Write) the data depends on
Master.

 I2C can be either single Master or a multi Master bus.

 Each device is of 10-bit or 7-bit address.

 A bit in the frame is used in the address either to read or write.

 No error checking mechanism in I2C.

 In multi Master system, sending data at a same time but the data will not be
disturbed or collisions will not occur.

 I2C can only responsible for resolving those collisions.


I2C basic command sequence:

 1. Send the START bit (S).


 2. Send the slave address (ADDR).
 3. Send the Read(R)-1 / Write (W)-0 bit.
 4. Wait for/Send an acknowledge bit (A).
 5. Send/Receive the data byte (8 bits) (DATA).
 6. Expect/Send acknowledge bit (A).
 7. Send the STOP bit (P).

I2C arbitration:

 Several I2C Masters can be connected to the same lines at the same time. To
prevent collisions all Masters prior to transmission have to:

-Constantly monitor SDA and SCL from start and stop conditions.
-Determine whether the bus is idle or not.
-Delay the transmission until the bus is free.
-Monitor SDA and SCL during transmission as two Masters might start the
transmission at the same time. In case of detection SDA being low while
transmitting high the transmitter has to stop the transmission. This is called bus
arbitration.

I2C interface:

 By the AND operation I2C detects the clocks of all Masters are given as HIGH.

 Low high Tran session, it can transmits data i.e. SCL=1.


 Bidirectional SDA and SCL lines. SDA and SCL don’t have pull up registers,
always connect to P0. We can connect SDA, SCL to pull up registers to drive the
Slave devices.

 When, SDA = 0
SCL = 1
It indicates that, now we can start of transfer

 When, SDA = 1
SCL = 0
It indicates that, end of transfer of data.

 SDA and SCL always driven by Master only.

 We have ACK/NACK. NACK (Non acknowledgement) is used, when data can’t


be received, request to retransmit the data.

Performance of I2C:

Three basic modes are there.

Standard mode:
Speed is 100 Kbits/sec. It is the default mode.
Control limitations are done on the speed of the Slave device.
It is having a 7-bit address.

Fast mode:
Speed is 400 Kbits/sec.
It is having a 7-bit/10-bit address.

High speed mode:


Speed is 3, 4 Mbits/sec.
This mode is compatible with above two modes.
Applications:

 Reading configuration data from SPD EPROM’s on SDRAM, DDR SDRAM,


DDR2 SDRAM memory sticks (DIMM) and other stacked PC boards.
 Supporting systems management for PCI cards, through a SMBus 2.0 connection.
 Accessing NVRAM chips that keep user settings.
 Accessing low speed DACs.
 Accessing low speed ADCs.
 Changing contrast, hue, and color balance settings in monitors (Display Data
Channel).
 Changing sound volume in intelligent speakers.
 Controlling OLED/LCD displays, like in a cell phone.
 Reading hardware monitors and diagnostic sensors, like a CPU thermostat and fan
speed.
 Reading real time clocks.
 Turning on and turning off the power supply of system components.

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