SINUSOIDAL INPUTS; HALF-WAVE RECTIFICATION

The diode analysis will now be expanded to include time-varying functions such as the sinusoidal waveform
and the square wave. There is no question that the degree of difficulty will increase, but once a few
fundamental maneuvers are understood, the analysis will be fairly direct and follow a common thread. The
simplest of networks to examine with a time-varying signal appears in Fig. 2.44 . For the moment we will
use the ideal model (note the absence of the Si, Ge, or GaAs label) to ensure that the approach is not clouded
by additional mathematical complexity.

Over one full cycle, defined by the period T of Fig. 2.44 , the average value (the algebraic sum of the areas
above and below the axis) is zero. The circuit of Fig. 2.44, called a half-wave rectifier, will generate a
waveform vo that will have an average value of particular use in the ac-to-dc conversion process. When
employed in the rectification process, a diode is typically referred to as a rectifier. Its power and current
ratings are typically much higher than those of diodes employed in other applications, such as computers
and communication systems. During the interval t = 0 T>2 in Fig. 2.44 the polarity of the applied
voltage vi is such as to establish “pressure” in the direction indicated and turn on the diode with the polarity
appearing above the diode. Substituting the short-circuit equivalence for the ideal diode will result in the
equivalent circuit of Fig. 2.45 , where it is fairly obvious that the output signal is an exact replica of the
applied signal. The two terminals defining the output voltage are connected directly to the applied signal
via the short-circuit equivalence of the diode. For the period T>2 T, the polarity of the input vi is as
shown in Fig. 2.46 , and the resulting polarity across the ideal diode produces an “off” state with an open-
circuit equivalent. The result is the absence of a path for charge to flow, and vo = iR = (0)R = 0 V for the
period T>2 T. The input vi and the output vo are sketched together in Fig. 2.47 for comparison
purposes. The output signal vo now has a net positive area above the axis over a full period and an average
value determined by

The process of removing one-half the input signal to establish a dc level is called halfwave rectification.
The effect of using a silicon diode with VK = 0.7 V is demonstrated in Fig. 2.48 for the forward-bias region.
The applied signal must now be at least 0.7 V before the diode can turn “on.” For levels of vi less than 0.7
V, the diode is still in an open-circuit state and vo = 0 V, as shown in the same figure. When conducting,

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the difference between vo and vi is a fixed level of VK = 0.7 V and vo = vi - VK, as shown in the figure. The

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net effect is a reduction in area above the axis, which reduces the resulting dc voltage level. For situations
where Vm >> VK, the following equation can be applied to determine the average value with a relatively
high level of accuracy.

In fact, if Vm is sufficiently greater than VK, Eq. (2.7) is often applied as a first approximation for Vdc.
Example 2.16 (in reference book)

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PIV (PRV)
The peak inverse voltage (PIV) [or PRV (peak reverse voltage)] rating of the diode is of
primary importance in the design of rectification systems. Recall that it is the voltage rat
ing that must not be exceeded in the reverse-bias region or the diode will enter the Zener
avalanche region. The required PIV rating for the half-wave rectifier can be determined
from Fig. 2.52, which displays the reverse-biased diode of Fig. 2.44 with maximum applied
voltage. Applying Kirchhoff’s voltage law, it is fairly obvious that the PIV rating of the
diode must equal or exceed the peak value of the applied voltage. Therefore,

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FULL-WAVE RECTIFICATION

Bridge Network
The dc level obtained from a sinusoidal input can be improved 100% using a process
called full-wave rectification. The most familiar network for performing such a function
appears in Fig. 2.53 with its four diodes in a bridge configuration. During the period t=0 to T>2 the polarity
of the input is as shown in Fig. 2.54 . The resulting polarities across the ideal diodes are also shown in Fig.
2.54 to reveal that D2 and D3 are conducting, whereas D1 and D4 are in the “off” state. The net result is the
configuration of Fig. 2.55 , with its indicated current and polarity across R. Since the diodes are ideal, the
load voltage is vo = vi, as shown in the same figure.

For the negative region of the input the conducting diodes are D1 and D4, resulting in the
configuration of Fig. 2.56 . The important result is that the polarity across the load resistor R
is the same as in Fig. 2.54 , establishing a second positive pulse, as shown in Fig. 2.56 . Over
one full cycle the input and output voltages will appear as shown in Fig. 2.57

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Since the area above the axis for one full cycle is now twice that obtained for a half-wave
system, the dc level has also been doubled and

If silicon rather than ideal diodes are employed as shown in Fig. 2.58 , the application of
Kirchhoff’s voltage law around the conduction path results in

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The peak value of the output voltage vo is therefore
Vo max = Vm - 2VK
For situations where Vm >>2VK, the following equation can be applied for the average value with a
relatively high level of accuracy:

Then again, if Vm is sufficiently greater than 2VK, then Eq. (2.10) is often applied as a first
approximation for Vdc.

PIV The required PIV of each diode (ideal) can be determined from Fig. 2.59 obtained at
the peak of the positive region of the input signal. For the indicated loop the maximum
voltage across R is Vm and the PIV rating is defined by

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Center-Tapped Transformer
A second popular full-wave rectifier appears in Fig. 2.60 with only two diodes but requiring a center-tapped
(CT) transformer to establish the input signal across each section of the secondary of the transformer.
During the positive portion of vi applied to the primary of the transformer, the network will appear as shown
in Fig. 2.61 with a positive pulse across each section of the secondary coil. D1 assumes the short-circuit
equivalent and D2 the open-circuit equivalent, as determined by the secondary voltages and the resulting
current directions. The output voltage appears as shown in Fig. 2.61

During the negative portion of the input the network appears as shown in Fig. 2.62 , reversing the roles of
the diodes but maintaining the same polarity for the voltage across the load resistor R. The net effect is the
same output as that appearing in Fig. 2.57 with the same dc levels.

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AND/OR GATES

The tools of analysis are now at our disposal, and the opportunity to investigate a computer
configuration is one that will demonstrate the range of applications of this relatively simple device. Our
analysis will be limited to determining the voltage levels and will not include a detailed discussion of
Boolean algebra or positive and negative logic. The network to be analyzed below is an OR gate for positive
logic. That is, the 10-V level of the figure is assigned a “1” for Boolean algebra and the 0-V input is assigned
a “0.” An OR gate is such that the output voltage level will be a 1 if either or both inputs is a 1. The output
is a 0 if both inputs are at the 0 level. The analysis of AND/OR gates is made easier by using the approximate
equivalent for a diode rather than the ideal because we can stipulate that the voltage across the diode must
be 0.7 V positive for the silicon diode to switch to the “on” state. In general, the best approach is simply to
establish a “gut” feeling for the state of the diodes by noting the direction and the “pressure” established by
the applied potentials. The analysis will then verify or negate your initial assumptions.

OR GATE. Determine Vo for this network.

Solution: First note that there is only one applied potential; 10

V at terminal 1. Terminal 2 with a 0-V input is essentially at
ground potential, as shown in the redrawn network. It
“suggests” that D1 is probably in the “on” state due to the
applied 10 V, whereas D2 with its “positive” side at 0 V is
probably “off.” Assuming these states will result in the other
configuration. The next step is simply to check that there is no
contradiction in our assumptions. That is,
note that the polarity across D1 is such as to turn it on and the
polarity across D2 is such as to turn it off.

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For D1 the “on” state establishes Vo at Vo = E - VD = 10 V - 0.7 V = 9.3 V. With 9.3 V at the cathode (-)
side of D2 and 0 V at the anode (+) side, D2 is definitely in the “off” state. The current direction and the
resulting continuous path for conduction further confirm our assumption that D1 is conducting. Our
assumptions seem confirmed by the resulting voltages and current, and our initial analysis can be assumed
to be correct. The output voltage level is not 10 V as defined for an input of 1, but the 9.3 V is sufficiently
large to be considered a 1 level. The output is therefore at a 1 level with only one input, which suggests that
the gate is an OR gate. An analysis of the same network with two 10-V inputs will result in both diodes
being in the “on” state and an output of 9.3 V. A 0-V input at both inputs will not provide the 0.7 V required
to turn the diodes on, and the output will be a 0 due to the 0-V output level. For the network the current
level is determined by

AND GATE. Determine the output level for the positive logic AND gate. An AND gate is one where a 1
output is only obtained when a 1 input appears at each and every input.
Solution: Note in this case that an independent source appears in the grounded leg of the network. For
reasons soon to become obvious, it is chosen at the same level as the input logic level. The network is
redrawn with our initial assumptions regarding the state of the diodes. With 10 V at the cathode side of D1
it is assumed that D1 is in the “off” state even though there is a 10-V source connected to the anode of D1
through the resistor.

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However, recall that we mentioned in the introduction to this section that the use of the
approximate model will be an aid to the analysis. For D1, where will the 0.7 V come from
if the input and source voltages are at the same level and creating opposing “pressures”? D2 is assumed to
be in the “on” state due to the low voltage at the cathode side and the availability of the 10-V source through
the 1-k resistor. For the network, the voltage at Vo is 0.7 V due to the forward-biased diode
D2. With 0.7 V at the anode of D1 and 10 V at the cathode, D1 is definitely in the “off”
state. The current I will have the direction indicated in Figure and a magnitude equal to

The state of the diodes is therefore confirmed and our earlier analysis was correct. Although not 0 V as
earlier defined for the 0 level, the output voltage is sufficiently small to be considered a 0 level. For the
AND gate, therefore, a single input will result in a 0-level output.

CLIPPERS

The previous section on rectification gives clear evidence that diodes can be used to change
the appearance of an applied waveform.

Clippers are networks that employ diodes to “clip” away a portion of an input signal
without distorting the remaining part of the applied waveform.

The half-wave rectifier of Section 2.6 is an example of the simplest form of diode clipper one resistor and
a diode. Depending on the orientation of the diode, the positive or negative region of the applied signal is
“clipped” off. There are two general categories of clippers: series and parallel. The series configuration is
defined as one where the diode is in series with the load, whereas the parallel variety has the diode in a
branch parallel to the load.

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SERIES

The response of the series configuration of Fig. 2.68a to a variety of alternating waveforms
is provided in Fig. 2.68b . Although first introduced as a half-wave rectifier (for sinusoidal
waveforms), there are no boundaries on the type of signals that can be applied to a clipper.

The addition of a dc supply to the network as shown in Fig. 2.69 can have a pronounced
effect on the analysis of the series clipper configuration. The response is not as obvious
because the dc supply can aid or work against the source voltage, and the dc supply can be
in the leg between the supply and output or in the branch parallel to the output.
There is no general procedure for analyzing networks such as the type in Fig. 2.69 , but
there are some things one can do to give the analysis some direction. First and most important:

1. Take careful note of where the output voltage is defined.

In Fig. 2.69 it is directly across the resistor R. In some cases it may be across a combination of series
elements. Next:

2. Try to develop an overall sense of the response by simply noting the “pressure”
established by each supply and the effect it will have on the conventional current
direction through the diode.
In Fig. 2.69 , for instance, any positive voltage of the supply will try to turn the diode on
by establishing a conventional current through the diode that matches the arrow in the

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diode symbol. However, the added dc supply V will oppose that applied voltage and try to
keep the diode in the “off” state. The result is that any supply voltage greater than V volts
will turn the diode on and conduction can be established through the load resistor. Keep in
mind that we are dealing with an ideal diode for the moment, so the turn-on voltage is
simply 0 V. In general, therefore, for the network of Fig. 2.69 we can conclude that the
diode will be on for any voltage vi that is greater than V volts and off for any lesser voltage.
For the “off” condition, the output would be 0 V due to the lack of current, and for the “on”
condition it would simply be vo = vi - V as determined by Kirchhoff’s voltage law.

3. Determine the applied voltage (transition voltage) that will result in a change of
state for the diode from the “off” to the “on” state.
This step will help to define a region of the applied voltage when the diode is on and
when it is off. On the characteristics of an ideal diode this will occur when VD 0 V and
ID 0 mA. For the approximate equivalent this is determined by finding the applied voltage when the diode
has a drop of 0.7 V across it (for silicon) and ID 0 mA. This exercise was applied to the network of Fig.
2.69 as shown in Fig. 2.70 . Note the substitution of the short-circuit equivalent for the diode and the fact
that the voltage across the resistor is 0 V because the diode current is 0 mA. The result is vi V 0, and so
the transition voltage is

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EXAMPLE 2.19 Find the output voltage for the network examined in
Example 2.18 if the applied signal is the square wave of Fig. 2.77 .
Solution: For vi = 20 V (0 S T>2) the network of Fig. 2.78 results. The diode
is in the short-circuit state, and vo = 20 V + 5 V = 25 V. For vi = -10 V the
network of Fig. 2.79 results, placing the diode in the “off” state, and vo = iR R
= (0) R = 0 V. The resulting output voltage appears in Fig. 2.80 .

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PARALLEL

The network of Fig. 2.81 is the simplest of parallel diode configurations with the output for
the same inputs of Fig. 2.68. The analysis of parallel configurations is very similar to that
applied to series configurations, as demonstrated in the next example.

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CLAMPERS

A clamper is a network constructed of a diode, a resistor, and a capacitor that shifts a waveform to a different
dc level without changing the appearance of the applied signal. Additional shifts can also be obtained by
introducing a dc supply to the basic structure. The chosen resistor and capacitor of the network must be
chosen such that the time constant determined by t RC is sufficiently large to ensure that the voltage across
the capacitor does not discharge significantly during the interval the diode is nonconducting. Throughout
the analysis we assume that for all practical purposes the capacitor fully charges or discharges in five time
constants. The simplest of clamper networks is provided in Fig. 2.89 . It is important to note that the
capacitor is connected directly between input and output signals and the resistor and the diode are connected
in parallel with the output signal. Clamping networks have a capacitor connected directly from input to
output with a resistive element in parallel with the output signal. The diode is also in parallel with the output
signal but may or may not have a series dc supply as an added element.

There is a sequence of steps that can be applied to help make the analysis straightforward. It is not the only
approach to examining clampers, but it does offer an option if difficulties surface.
Step 1: Start the analysis by examining the response of the portion of the input signal
that will forward bias the diode.

Step 2: During the period that the diode is in the “on” state, assume that the capacitor will charge up
instantaneously to a voltage level determined by the surrounding network.
For the network of Fig. 2.89 the diode will be forward biased for the positive portion of
the applied signal. For the interval 0 to T>2 the network will appear as shown in Fig. 2.90.
The short-circuit equivalent for the diode will result in vo=0 V for this time interval, as
shown in the sketch of vo in Fig. 2.92 . During this same interval of time, the time constant
determined by 𝜏 = RC is very small because the resistor R has been effectively “shorted
out” by the conducting diode and the only resistance present is the inherent (contact, wire)
resistance of the network. The result is that the capacitor will quickly charge to the peak
value of V volts as shown in Fig. 2.90 with the polarity indicated.

Step 3: Assume that during the period when the diode is in the “off” state the capacitor holds on to
its established voltage level.

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Important Conclusions and Concepts
1. The characteristics of a diode are unaltered by the network in which it is employed. The network simply
determines the point of operation of the device.
2. The operating point of a network is determined by the intersection of the network equation and an
equation defining the characteristics of the device.
3. For most applications, the characteristics of a diode can be defined simply by the threshold voltage in
the forward-bias region and an open circuit for applied voltages less than the threshold value.
4. To determine the state of a diode, simply think of it initially as a resistor, and find the polarity of the
voltage across it and the direction of conventional current through it. If the voltage across it has a forward-
bias polarity and the current has a direction that matches the arrow in the symbol, the diode is
conducting.
5. To determine the state of diodes used in a logic gate, first make an educated guess about the state of the
diodes, and then test your assumptions. If your estimate is incorrect, refine your guess and try again until
the analysis verifies the conclusions.
6. Rectification is a process whereby an applied waveform of zero average value is changed to one that
has a dc level. For applied signals of more than a few volts, the ideal diode approximations can normally
be applied.
7. It is very important that the PIV rating of a diode be checked when choosing a diode for a particular
application. Simply determine the maximum voltage across the diode under reverse-bias conditions, and
compare it to the nameplate rating. For the typical half-wave and full-wave bridge rectifiers, it is the peak
value of the applied signal. For the CT transformer full-wave rectifier, it is twice the peak value (which can
get quite high).
8. Clippers are networks that “clip” away part of the applied signal either to create a specific type of signal
or to limit the voltage that can be applied to a network.
9. Clampers are networks that “clamp” the input signal to a different dc level. In any event, the peak-to-
peak swing of the applied signal will remain the same.

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