dce 2017

dce 2017 Chapter 3 Objectives

• Selected areas covered in this chapter:
– Operation of truth tables for AND, NAND, OR, and
NOR gates, and the NOT (INVERTER) circuit.
– Boolean expression for logic gates.

Digital Systems – DeMorgan’s theorems to simplify logic expressions.

– Universal gates (NAND or NOR) to implement a circuit
represented by a Boolean expression.
– Concepts of active-LOW & active-HIGH logic signals.
Nguyễn Trần Hữu Nguyên
BK
TP.HCM
– Describing and measuring propagation delay time.
D: Computer Engineering – Differences between an HDL and a computer
E: [email protected] programming language.

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dce dce 3-2 Truth Tables

2017
3-1 Boolean Constants and Variables 2017

• Boolean algebra allows only two values—0 and 1. • A truth table describes the relationship between
– Logic 0 can be: false, off, low, no, open switch.
the input and output of a logic circuit.
– Logic 1 can be: true, on, high, yes, closed switch.
• The number of entries corresponds to the
number of inputs.
– A 2-input table would have 22 = 4 entries.
– A 3-input table would have 23 = 8 entries.

• The three basic logic operations:

– OR, AND, and NOT.

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dce 3-2 Truth Tables dce
2017 2017 3-3 OR Operation With OR Gates
Examples of truth tables with 2, 3, and 4 inputs. • The Boolean expression for the OR operation is:
X = A + B — Read as “X equals A OR B”

The + sign does not stand for ordinary

addition—it stands for the OR operation

• The OR operation is similar to addition, but when

A = 1 and B = 1, the OR operation produces:

1 + 1 = 1 not 1 + 1 = 2

In the Boolean expression x = 1 + 1 + 1 = 1…

x is true (1) when A is true (1) OR B is true (1) OR C is true (1)

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dce dce
2017 3-3 OR Operation With OR Gates 2017 3-3 OR Operation With OR Gates
• An OR gate is a circuit with two or more inputs, • An OR gate is a circuit with two or more inputs,
whose output is equal to the OR combination whose output is equal to the OR combination
of the inputs. of the inputs.

Truth table/circuit symbol for a two input OR gate. Truth table/circuit symbol for a three input OR gate.

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dce 3-3 OR Operation With OR Gates
2017
dce 3-4 AND Operations with AND gates
2017

Example of the use of an OR • The AND operation is similar to multiplication:

gate in an alarm system.
X = A • B • C — Read as “X equals A AND B AND C”
The + sign does not stand for ordinary
multiplication—it stands for the AND operation.
x is true (1) when A AND B AND C are true (1)

Truth table — Gate symbol.

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dce 3-4 AND Operations with AND gates

2017
dce AND / OR
2017

Truth table/circuit symbol for a three input AND gate.

The AND symbol on a logic-
circuit diagram tells you
output will go HIGH only
when all inputs are HIGH.

The OR symbol means the

output will go HIGH when
any input is HIGH.

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dce 3-5 NOT Operation
2017
dce 3-5 NOT Operation
2017

• The Boolean expression for the NOT operation:

A NOT circuit—commonly called an INVERTER.
X = A — Read as: “X equals NOT A”
The overbar represents “X equals the inverse of A”
the NOT operation.
“X equals the complement of A”

A' = A
Another indicator for
inversion is the
prime symbol (').

This circuit always has only a single input, and the out-put
logic level is always opposite to the logic level of this input.
NOT Truth Table

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dce 3-5 NOT Operation

2017
dce 3-5 NOT Operation
2017

The INVERTER inverts (complements) the Typical application of the NOT gate.
input signal at all points on the waveform.

Whenever the input = 0, output = 1, and vice versa. This circuit provides an expression that
is true when the button is not pressed.

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Digital Logic Design 1 4

dce Boolean Operations
2017
dce 3-6 Describing Logic Circuits Algebraically
2017

• If an expression contains both AND and OR

Summarized rules for OR, AND and NOT
gates, the AND operation will be performed first.

• Unless there is a parenthesis in the expression.

These three basic Boolean operations

can describe any logic circuit.
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dce dce 3-6 Describing Logic Circuits Algebraically

2017
3-6 Describing Logic Circuits Algebraically 2017

• Whenever an INVERTER is present, output is • Further examples…

equivalent to input, with a bar over it.
– Input A through an inverter equals A.

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dce 3-6
2017 Describing Logic Circuits Algebraically dce 3-7 Evaluating Logic Circuit Outputs
2017

• Further examples… • Rules for evaluating a Boolean expression:

– Perform all inversions of single terms.
– Perform all operations within parenthesis.
– Perform AND operation before an OR operation unless
parenthesis indicate otherwise.
– If an expression has a bar over it, perform operations
inside the expression, and then invert the result.

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dce 3-7 Evaluating Logic Circuit Outputs

2017
dce 3-7 Evaluating Logic Circuit Outputs
2017

• The best way to analyze a circuit made up of • The first step after listing all input combinations
multiple logic gates is to use a truth table. is to create a column in the truth table for each
– It allows you to analyze one gate or logic intermediate signal (node).
combination at a time.
– It allows you to easily double-check your work.
– When you are done, you have a table of tremendous
benefit in troubleshooting the logic circuit.

Node u has been filled as the complement of A

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Digital Logic Design 1 6

dce 3-7 Evaluating Logic Circuit Outputs
2017
dce 3-7 Evaluating Logic Circuit Outputs
2017

• The next step is to fill in the values for column v. • The third step is to predict the values at node w
which is the logical product of BC.

v =AB — Node v should be HIGH

when A (node u) is HIGH AND B is HIGH This column is HIGH whenever B is HIGH AND C is HIGH

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dce 3-7 Evaluating Logic Circuit Outputs

2017
dce 3-7 Evaluating Logic Circuit Outputs
2017

• The final step is to logically combine columns v • Output logic levels can be determined directly
and w to predict the output x. from a circuit diagram.
– Output of each gate is noted until final output is found.
• Technicians frequently use this method.

Since x = v + w, the x output will be HIGH when v OR w is HIGH

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Digital Logic Design 1 7

dce dce 3-8 Implementing Circuits From Boolean Expressions
2017
3-7 Evaluating Logic Circuit Outputs 2017

• It is important to be able to draw a logic circuit

from a Boolean expression.
– The expression X = A • B • C, could be drawn
as a three input AND gate.
– A circuit defined by X = A + B, would use a two-
input OR gate with an INVERTER on one of
the inputs.

Table of logic state

at each node of the
circuit shown.

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dce 3-8 Implementing Circuits From Boolean Expressions

2017
dce 3-8 Implementing Circuits From Boolean Expressions
2017

• Each OR gate input is an AND product term,

– An AND gate with appropriate inputs can be
used to generate each of these terms.
A circuit with output y = AC + BC + ABC
contains three terms which are ORed together.

…and requires a three-input OR gate.

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dce 3-8 Implementing Circuits From Boolean Expressions
2017
dce 3-9 NOR Gates and NAND Gates
2017

• Combine basic AND, OR, and NOT operations.

– Simplifying the writing of Boolean expressions
• Output of NAND and NOR gates may be found
Circuit diagram to implement x = (A + B) (B + C) by determining the output of an AND or OR
gate, and inverting it.
– The truth tables for NOR and NAND gates show the
complement of truth tables for OR and AND gates.

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dce 3-9 NOR Gates and NAND Gates

2017
dce 3-9 NOR Gates and NAND Gates
2017

• The NOR gate is an inverted OR gate. Output waveform of a NOR gate for
– An inversion “bubble” is placed at the output the input waveforms shown here.
of the OR gate, making the Boolean output
expression x = A + B

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Digital Logic Design 1 9

dce 3-9 NOR Gates and NAND Gates
2017
dce 3-9 NOR Gates and NAND Gates
2017

• The NAND gate is an inverted AND gate. Output waveform of a NAND gate for
– An inversion “bubble” is placed at the output the input waveforms shown here.
of the AND gate, making the Boolean output
expression x = AB

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dce 3-9 NOR Gates and NAND Gates

2017
dce 3-10 Boolean Theorems
2017

The theorems or laws that follow may represent an

expression containing more than one variable.
Logic circuit with the expression x = AB • (C + D)
using only NOR and NAND gates.

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dce 3-10 Boolean Theorems
2017
dce 3-10 Boolean Theorems
2017

Theorem (5) is straightforward,

Theorem (1) states that if any variable as 0 added to anything does not
is ANDed with 0, the result must be 0. affect value, either in regular
addition or in OR addition.

Theorem (2) is also obvious Theorem (6) states that if any variable
by comparison with ordinary is ORed with 1, the is always 1.
multiplication. Check values: 0 + 1 = 1 and 1 + 1 = 1.

Prove Theorem (3) by trying each case.

Theorem (7) can be proved by
If x = 0, then 0 • 0 = 0
checking for both values of x:
If x = 1, then 1 • 1 = 1
0 + 0 = 0 and 1 + 1 = 1.
Thus, x • x = x

Theorem (4) can be proved

in the same manner. Theorem (8) can be proved similarly.

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dce dce
2017
3-10 Boolean Theorems 2017
3-10 Boolean Theorems
Multivariable Theorems Multivariable Theorems
Commutative laws Theorems (14) and (15) do not have counterparts
in ordinary algebra. Each can be proved by
trying all possible cases for x and y.
Analysis table & factoring
Associative laws for Theorem (14)

Distributive law

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Digital Logic Design 1 11

dce 3-11 DeMorgan’s Theorems
2017
dce 3-11 DeMorgan’s Theorems
2017

• DeMorgan’s theorems are extremely useful in Equivalent circuits implied by Theorem (16)
simplifying expressions in which a product or
sum of variables is inverted.

Theorem (16) says inverting the OR sum of two variables is the same as
inverting each variable individually, then ANDing the inverted variables.

Theorem (17) says inverting the AND product of two variables is the
same as inverting each variable individually and then ORing them. The alternative symbol
for the NOR function.

Each of DeMorgan’s theorems can readily be proven

by checking for all possible combinations of x and y.

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dce 3-11 DeMorgan’s Theorems

2017
dce 3-12 Universality of NAND and NOR Gates
2017

Equivalent circuits implied by Theorem (17) • NAND or NOR gates can be used to create the
three basic logic expressions.
– OR, AND, and INVERT.
• Provides flexibility—very useful in logic circuit design.

The alternative symbol

for the NAND function.

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Digital Logic Design 1 12

dce 3-12 Universality of NAND and NOR Gates
2017
dce 3-12 Universality of NAND and NOR Gates
2017

How combinations of NANDs or NORs are How combinations of NANDs or NORs are
used to create the three logic functions. used to create the three logic functions.

It is possible, however, to implement any logic expression using NOR gates can be arranged to implement
only NAND gates and no other type of gate, as shown. any of the Boolean operations, as shown.

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dce 3-12 Universality of NAND and NOR Gates

2017
dce 3-12 Universality of NAND and NOR Gates
2017

A logic circuit to generate a signal x, that will go HIGH Possible Implementations # 1

whenever conditions A and B exist simultaneously, or
whenever conditions C and D exist simultaneously.

The logic expression will be x = AB + CD.

Each of the TTL ICs shown here will

fulfill the function. Each IC is a quad,
with four identical gates on one chip

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dce 3-12 Universality of NAND and NOR Gates
2017
dce 3-13 Alternate Logic-Gate Representations
2017

Possible Implementations #2 • To convert a standard symbol to an alternate:

– Invert each input and output in standard symbols.
• Add an inversion bubble where there are none.
• Remove bubbles where they exist.

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dce 3-13 Alternate Logic-Gate Representations

2017
dce 3-13 Alternate Logic-Gate Representations
2017

• Points regarding logic symbol equivalences: • Active-HIGH – an input/output has no inversion

– The equivalences can be extended to gates with bubble.
any number of inputs. • Active-LOW – an input or output has an inversion
– None of the standard symbols have bubbles on bubble.
their inputs, and all the alternate symbols do.
– Standard & alternate symbols for each gate represent
the same physical circuit.
– NAND and NOR gates are inverting gates.
• Both the standard and the alternate symbols for each will have
a bubble on either the input or the output.
– AND and OR gates are noninverting gates.
• The alternate symbols for each will have bubbles
on both inputs and output.

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Digital Logic Design 1 14

dce 3-13 Alternate Logic-Gate Representations
2017
dce 3-13 Alternate Logic-Gate Representations
2017

Interpretation of the two NAND gate symbols. Interpretation of the two OR gate symbols.

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dce 3-14 Which Gate Representation to Use

2017
dce 3-14 Which Gate Representation to Use
2017

Proper use of alternate gate symbols in the circuit diagram • When a logic signal is in the active state (HIGH or
can make circuit operation much clearer. LOW) it is said to be asserted.
• When a logic signal is in the inactive state (HIGH
Original circuit using or LOW) it is said to be unasserted.
standard NAND
symbols.
A bar over a signal Absence of a bar

Equivalent representation
means asserted
(active) LOW.
RD means asserted
(active) HIGH
RD
where output Z is
active-HIGH.

Equivalent representation
where output Z is
active-LOW.

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Digital Logic Design 1 15

dce 3-14 Which Gate Representation to Use
2017
dce 3-14 Which Gate Representation to Use
2017

• An output signal can have two active states, • When possible, choose gate symbols so bubble
with an important function in the HIGH state, outputs are connected to bubble input.
and another in the LOW state. – Nonbubble outputs connected to nonbubble inputs.
– It is customary to label such signals so both
active states are apparent.

A common example is the read/write signal.

RD/WR
When this signal is HIGH, the read operation (RD) is performed;
when it is LOW, the write operation (WR) is performed.

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dce 3-14 Which Gate Representation to Use

2017
dce 3-15 Propogation Delay
2017

The logic circuit shown activates an • Propagation delay is the time it takes for a system
alarm when output Z goes HIGH. to produce output after it receives an input.
– Speed of a logic circuit is related to propagation delay.
Modify the circuit diagram • Parts to implement logic circuits have a data
so it represents the circuit
operation more effectively.
sheet that states the value of propagation delay.
– Used to assure that the circuit can operate fast enough
for the application.
The NOR gate symbol should be
changed to the alternate symbol with a
nonbubble (active-HIGH) output to
match the nonbubble input of AND
gate 2.
The circuit now has nonbubble outputs
connected to nonbubble inputs of gate 2.

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Digital Logic Design 1 16

dce dce A typical CAD flow
2017
Summary so far 2017

for logic design

• Boolean Algebra: a mathematical tool used in the analysis
and design of digital circuits
• OR, AND, NOT: basic Boolean operations
• OR: HIGH output when any input is HIGH
• AND: HIGH output only when all inputs are HIGH
• NOT: output is the opposite logic level as the input
• NOR: OR with its output connected to an INVERTER
• NAND: AND with its output connected to an INVERTER
• Boolean theorems and rules: to simplify the expression of
a logic circuit and can lead to a simpler way of
implementing the circuit
• NAND, NOR: can be used to implement any of the basic
Boolean operations
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dce dce
2017
A simple logic fn and its Verilog module 2017
A simple logic fn and its Verilog module

The module of a Verilog design unit describes what the design “looks
like” on the inside i.e. what its behaviour and/or structure is

Sensitivity list

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dce dce
2017
A simple logic fn and its Verilog module 2017
Verilog syntax

• The names of modules and signals in Verilog

code follow two simple rules:
– the name must start with a letter, and
Sensitivity list
– it can contain any letter or number plus the “_”
underscore and “$” characters.
• Verilog is case sensitive.
– Thus, the name k is not the same as K and
– Example1 is not the same as example1.
• The Verilog syntax does not enforce a particular
style of code.
– For example, multiple statements can appear on a
single line.

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dce dce
2017
Verilog syntax 2017
Four input example

• White space characters, such as SPACE and

TAB, and blank lines are ignored.
• As a matter of good style, code should be
formatted in such a way that it is easy to read.
• Indentation and blank lines can be used to make
separate parts of the code easily recognizable.
• Comments may be included in the code to
improve its readability.
• A comment begins with the double slash “//” and
continues to the end of the line.

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dce dce
2017
Hierarchical Verilog Code 2017
Hierarchical Verilog Code

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dce
2017
Hierarchical Verilog Code

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Digital Logic Design 1 19