International Journal of Innovative Technology and Exploring Engineering (IJITEE)

ISSN: 2278-3075, Volume-X, Issue-X, don’t delete Top & Bottom Header, & Fill up Manuscript details (Ist Page, Bottom, Left Side)

Design of a combinational circuit by optimizing

Jahnavi. Ratnam, E. Raghuveera

EX-OR gate


Abstract: In this paper a full adder is designed by optimizing the

Full Adder is one of the effective structural blocks and basic EXOR gate. The EXOR plays a major role in the
elements in many of the architectures available in VLSI and generation of sum in any full adder; optimization of EXOR
DSP domains. Adder is an adaptable element and it is mainly gate makes significant variations in power, delay and
known for addition and multiplication as its principal transistor count. The design is verified for its functionality
functioning element. In VLSI it is used in ALU design, Address in mentor graphics 180nm technology. Power and delay
generation in processors, Multipliers etc... In DSP it is used for
analysis is carried out in the simulation environment. The
conversion, Signed addition and Signed multiplication,
Transformations and Signal processing applications. So, results are compared with the existing adders like hybrid
designing of an adder in an effective manner is an essential full adder and CMOS full adder[9][10]. Initially the full
factor. The recent circuit designing in VLSI is mainly to adder was designed with 28T using CMOS technology as
concentrate on power and delay reduction. In this paper a full shown in below figure.
adder is designed by optimizing XOR gate in mentor graphics
130nm and 45nm technology. Transistor count, power, delay
are compared with the existing adder.

Index Terms: Full adder, Mentor graphics, Hybrid full adder,

CMOS full adder, Novel full adder, Transistor count, Power,
Delay.

I.INTRODUCTION
Digital electronics has become an essential
part in everyone’s life in the form of mobile phones,
Laptops, sensor nodes and major portable devices. The
circuit delay is scaled down by 30% while performance and
transistor density are increased by two times with a
threshold voltage reduction of almost 15% roughly for
every two years. The increase in resources is directly
proportional to rise in IC temperature and affects battery
life. So, the battery life of these devices has to be improved
by reducing the power consumption and area. This can be
done by designing optimized low power[1][6][8] VLSI
circuits such as adders, multipliers etc… As full adders are
very important because they are the basic building blocks of
many signal and image processing algorithms[6], it is
required to design adders that occupy minimum area and
consume minimum power.

The effectiveness of digital applications relate to the

performance of the arithmetic circuits such as adders,
multipliers, and dividers. Because of the basal role of Figure 1. Conventional CMOS full adder
addition in all the arithmetic operations, number of efforts
has been made to explore efficient adder structures, for
example carry select, carry skip, conditional sum, and carry
look-ahead adders. In all these adders full adder is at the
centre of attention.
The arrangement of the paper is as follows. In section II,
Full adders are mainly made of two modules, including 2- design work for the proposed work is elaborated. The
input XOR 2-to-1 multiplexer (2-1-MUX) gate. The discussion of results is presented in section III. The
XOR/XNOR [5] gate is the major consumer of conclusion of the paper is in section IV.
power in the FA cell. Therefore, the power
consumption of the FA cell can be reduced by
optimum designing of the XOR/XNOR gate. The II. DESIGN APPROACH
XOR/XNOR gate has also many applications in
digital circuits design. The implementation started with the basic CMOS full

Revised Manuscript Received on December 22, 2018.
adder[9] which consists of 28 transistors.
Jahnavi. Ratnam, Department of ECE, Koneru Lakshmaiah Educational
Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
E. Raghuveera, Department of ECE, Koneru Lakshmaiah Educational
Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.

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 Design of a combinational circuit by optimizing EX-OR gate

Figure 2. Designed Full Adder Figure 3. An Ex-Or Gate

A multiplexer is a combinational logic circuit which selects
The designed full adder consists of 10 transistors shown in no. of analog or digital signals and gives the selected input
the figure 1. It consists of two XOR gates and a 2:1 MUX. signal to a single output line. The required input signal is
The first gate performs two input XOR operation and the selected using a select channel S.
result is again XORed with the third input to generate the
output sum. The XOR gate was designed using two NMOS CARRY = (CinS + AS) (4)
and two PMOS transistors. The 2:1 MUX has two inputs
with a select line S which generates output carry.

SUM = A ⊕ B ⊕ Cin (1)

CARRY = A.B + B.Cin + Cin.A (2)

The digital logic gate XOR in figure 3 performs the

‘exclusive OR’ function. If both the inputs are HIGH (1) or
LOW (0) then the output of the gate is LOW (0). If one of Figure 4. A Multiplexer
the inputs is HIGH (1) then the output is HIGH (1).

III. RESULTS AND DISCUSSION

A ⊕ B = AB + AB (3)
The basic CMOS 28[10] transistor full adder is compared
with the designed full adder in terms of power, delay and
transistor count. The circuit schematics are designed and
simulated in mentor graphics 45nm technology using pyxis
schematic.
The output of the full adder varies for different patterns. For
all possible input patters the simulation has been
performed. The delay for 28 transistor full adder is
0.1759us. The delay for the designed full adder is 4.81ns.

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 International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075, Volume-X, Issue-X, don’t delete Top & Bottom Header, & Fill up Manuscript details (Ist Page, Bottom, Left Side)

Table 1: Comparison of simulation results (No. of

transistors, Power (uW), Delay (ns), PDP (e-12)) with 0.6-V
Figure 5. Schematic of designed Full Adder power supply voltage at 100MHz.

The power dissipation for 28 transistor full adder is

26.497nW. The power dissipation for the designed full
adder is 103.2nW.

Figure 7. Comparison graph for Power, Delay and PDP.

IV. CONCLUSION
The design and simulation of basic CMOS full adder with
28T, hybrid full adder with 22T is performed initially in
mentor graphics. The power, delay and PDP of the two
designs are analyzed. The designed structure which consists
of 10T is also simulated in mentor graphics 45nm
technology with a supply voltage of 0.6V at 100MHz
frequency. It is observed that the delay and power
consumption is reduced when compared to the 28 and 22
transistor design. As the no. of transistors decreases the
Figure 6: Simulation Result of Proposed Full adder. area consumed also decreases. But always there will be a
trade-off between power and delay as delay decreases power
The reduction in power consumption for the designed full increases and if delay increases power decreases. The
adder enables building large systems which depends on full proposed design can be used in DSP applications in the
adder whose performance in terms of battery life can be optimization of area, power and delay.
extended for portable devices. Miniaturization of the system
is also possible due to the reduction in area as the transistor
count is also reduced.
REFERENCES
[1] Hamed Naseri et.al., “Low-Power and Fast Full Adder by Exploring
New XOR and XNOR Gates”, IEEE Tranactions Very Large Scale
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[4] R. K. Sharma et.al., “Low voltage high performance hybrid full adder,”
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 Design of a combinational circuit by optimizing EX-OR gate

[5] W.-S. Feng et.al., “New efficient designs for XOR and XNOR functions on
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AUTHORS PROFILE

Jahnavi Ratnam is pursuing M. Tech (VLSI),

Department of Electronics and Communication Engineering
from Koneru Lakshmaiah Educational Foundation (Deemed
to be university), Guntur, Andhra Pradesh, India.

E. Raghuveera received the M. Tech. In

VLSI System Design of Electronics and
Communication Engineering from
VNT VJIET, Hyderabad, Telangana India, in 2012
and B. Tech. in Electronics and Communication
Engineering, from RGMCET, Nandyal, Andhra
Pradesh, India, in 2006. He was a Faculty Member with the Department of
Electronics and communication Engineering, JNT University,
Ananthapuramu, Andhra Pradesh, India, He joined in the Department of
Electronics & Communication Engineering KLEF(Deemed to be University),
Green Fields, Veddeswaram, Guntur, Andhra Pradesh, India. In 2016, where
he is currently a Asst. Professor. His current research interests include VLSI
designs, video/image signal processing, and low-power VLSI circuit designs.

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