General assembler design

• Let us pretend that we are the assembler trying to translate the

program given here
Source program Output program
St. No Label Opcode Operand Rel. add. Object code
1 JOHN START 0
2 USING *, 15
3 L 1, FlVE 0 L 3, 12 (0,12)
4 A 1,FOUR 4 A 1,16(0,15)
5 ST 1,TEMP 8 ST 1,2O(0,15)
6 FIVE DC F’5’ 12 5
7 FOUR DC F’4’ 16 4
8 TEMP DC 1F 20
9 END
MOT
Mnemonic Op code Type Format Length
L 58 RX OP R1, D2 (X2,R2) 4
A 5A RX OP R1, D2 (X2,R2) 4
ST 50 RX OP R1, D2 (X2,R2) 4

POT
PSEUDO OP TASKS
START Start the program and initialize the LC with the value of the operand or zero as appropriate. Label
part indicates the name of the program
USING Set the base register with the content of the operand. If *, then current value of LC
DC Define a constant with the storage requirement and update the LC value
DS Define a storage with reserve space for future requirements. Update LC
END End indicates the physical end of the program. It also enables the allocation of addresses to literals
(if unallocated). The control for translation process is sent to 2nd pass
Statement no 1 Pass 1
JOHN START 0
• Pseudo op START, so get info from POT.
• JOHN is a symbol and is the name of the program to be stored in
symbol table
• Set LC 0
Symbol Address (Value of LC)
JOHN 0
Statement no 2
USING *, 15
• Pseudo op USING, so get info from POT.
• Base register is 12 and its content is the current value of the location
counter
• Set R12 0
Statement no 3
L 1, FlVE
• Machine op L, so get info from MOT.
• Mnemonic instruction looks like
L 1, D2 (X2, R2)
• Assume index register X2=0.
• Base register R2=R12
• The address D2 (X2, R2) is the address for FIVE.
• Till now, we do not know this address
• For time being, we keep this blank
• L 1, FIVE is translated to L 1, …(0, 12)
• Update the LC
LC LC + Length of instruction LC + 4 0+4 4
Statement no 4
A 1,FOUR
• Machine op A, so get info from MOT.
• Mnemonic instruction looks like
A 1, D2 (X2, R2)
• Assume index register X2=0.
• Base register R2=R12
• The address D2 (X2, R2) is the address for FOUR.
• Till now, we do not know this address
• For time being, we keep this blank
• A 1, FOUR is translated to A 1, …(0, 12)
• Update the LC
LC LC + Length of instruction LC + 4 4+4 8
Statement no 5
ST 1,TEMP
• Machine op ST, so get info from MOT.
• Mnemonic instruction looks like
ST 1, D2 (X2, R2)
• Assume index register X2=0.
• Base register R2=R12
• The address D2 (X2, R2) is the address for TEMP.
• Till now, we do not know this address
• For time being, we keep this blank
• ST 1, TEMP is translated to ST 1, …(0, 12)
• Update the LC
LC LC + Length of instruction LC + 4 8+4 12
Statement no 6
FIVE DC F’5’
• Pseudo op DC, so get info from POT.
• It allocates a full word space (denoted by F) for decimal 5 for symbol
FIVE
• Put this symbol into ST with current value of LC i.e 12
• Update LC
LC LC + Length of instruction LC + 4 12 + 4 16
Symbol Address (Value of LC)
JOHN 0
FIVE 12
Statement no 7
FOUR DC F’4’
• Pseudo op DC, so get info from POT.
• It allocates a full word space (denoted by F) for decimal 4 for symbol
FOUR
• Put this symbol into ST with current value of LC i.e 16
• Update LC
LC LC + Length of instruction LC + 4 16 + 4 20
Symbol Address (Value of LC)
JOHN 0
FIVE 12
FOUR 16
Statement no 8
TEMP DS 1F
• Pseudo op DS, so get info from POT.
• It allocates a full word space (denoted by F) for symbol TEMP
• Put this symbol into ST with current value of LC i.e 20
• Update LC
LC LC + Length of instruction LC + 4 20 + 4 24
Symbol Address (Value of LC)
JOHN 0
FIVE 12
FOUR 16
TEMP 20
Statement no 9
END
• Pseudo op END, so get info from POT.
• It indicates the end of program
• No action for LT, as no literals
• Move to pass 2
Intermediate mnemonic program
Rel. Addr Mnemonic code
0 L 1, ….(0,12)
4 A 1, ….(0,12)
8 ST 1, ….(0,12)
12 5
16 4
20 ….
Statement no 1 Pass 2
JOHN START 0
• Pseudo op START, so get info from POT.
• It performs same task as of pass 1
• JOHN is a symbol and is the name of the program to be stored in
symbol table
• Set LC 0
Symbol Address (Value of LC)
JOHN 0
Statement no 2
USING *, 15
• Pseudo op USING, so get info from POT.
• Base register is 12 and its content is the current value of the location
counter
• Set R12 0
• There will be an entry on to the base register table (BRT)
 BASE REGISTER TABLE

After statement Base register Content of base

2 12 0
Statement no 3
L 1, FlVE
• Machine op L, so get info from MOT.
• Mnemonic instruction looks like
L 1, D2 (X2, R2)
• Assume index register X2=0.
• Base register R2=R12
• The address D2 (X2, R2) is the address for FIVE.
• From ST, the address of FIVE is 12
• L 1, FIVE is translated to L 1,12(0, 12)
• Update the LC
LC LC + Length of instruction LC + 4 0+4 4
Statement no 4
A 1,FOUR
• Machine op A, so get info from MOT.
• Mnemonic instruction looks like
A 1, D2 (X2, R2)
• Assume index register X2=0.
• Base register R2=R12
• The address D2 (X2, R2) is the address for FOUR.
• From ST, the address of FOUR is 16
• A 1, FOUR is translated to A 1,16 (0, 12)
• Update the LC
LC LC + Length of instruction LC + 4 4+4 8
Statement no 5
ST 1,TEMP
• Machine op ST, so get info from MOT.
• Mnemonic instruction looks like
ST 1, D2 (X2, R2)
• Assume index register X2=0.
• Base register R2=R12
• The address D2 (X2, R2) is the address for TEMP.
• From ST, the address of TEMP is 20
• ST 1, TEMP is translated to ST 1, 20 , 12)
• Update the LC
LC LC + Length of instruction LC + 4 8+4 12
Statement no 6
FIVE DC F’5’
• Pseudo op DC, so get info from POT.

• Update LC
LC LC + Length of instruction LC + 4 12 + 4 16
Statement no 7
FOUR DC F’4’
• Pseudo op DC, so get info from POT.

• Update LC
LC LC + Length of instruction LC + 4 16 + 4 20
Statement no 8
TEMP DS 1F
• Pseudo op DS, so get info from POT.

• Update LC
LC LC + Length of instruction LC + 4 20 + 4 24
Statement no 9
END
• Pseudo op END, so get info from POT.
• It indicates the end of program
• No action for LT, as no literals