International Journal of Environment 4(1): 18-24 (2014) ORIGINAL ARTICLE

Proficient FPGA Execution of Secured and Apparent Electronic

Voting Machine Using Verilog HDL
Tabia Hossain, Syed Syed Shihab Uddin, Iqbalur Rahman Rokon, K.M.A Salam, M. Abdul
Awal

Abstract
Electronic Voting Machine is an electronic voting device used for
conducting the parliamentary elections electronically. It consists of two
units that can be inter-linked; a ballot unit which a voter uses to
ISSN: 2186- 6872 (print) exercise his vote and a control unit which used by the polling officials.
ISSN: 2186-0009 (online) As there is no available design of Electronic Voting Machine using
http://www.BENJapan.org/IJE Verilog FPGA, in this paper, we introduce an efficient, transparent and
secured FPGA implementation of EVM using Verilog HDL. The design is
ARTICLE HISTORY coded in Verilog hardware description language at Register Transfer
Level (RTL), simulated in ModelSim, synthesized in Quartus II and
Received: 10 November 2013
implemented in Cyclone II FPGA using the AlteraDE1 board.
Revised: 3 May 2014
Accepted: 5 June 2014

Published online: 14 June 2014 Key words: EVM, RTL, Verilog HDL, FPGA, VLSI, FSM

 2014, International Journal of Environment. All rights reserved.

I. INTRODUCTION1 reliable, accurate and it must be transparent.

Bangladesh has always been able to keep The voting system of Bangladesh is still paper
pace with the technology advancements in all ballot based, a very outdated process. The
sectors worldwide. Compared to the other whole world is looking forward to E-voting
developed, even to some of the developing rather than using paper ballots in voting.
countries, Bangladesh lags far behind in the Today Electronic Voting Machines has become
system of national parliamentary voting in a major concern in electoral mechanisms in
technological perspective. For a democratic general elections. Considering these points, we
country, public opinion is the most important made the design for an Electronic Voting
to establish a government. Voting is the Machine using Verilog FPGA, which absolutely
process through which people display their is an original design of our own where with the
opinion and help to setup a democratic advantages of VLSI design methodology and
government. So the voting system should be Verilog codes; we focused on implementing
proficient, secured and apparent satisfactorily
error free electronic voting device.
AUTHORS INFO
The rest of this paper is organized as follows.
Tabia Hossain* Section II present design specification. Section
e-mail: [email protected] III shows design hierarchy and section IV
Address: Department of Electrical Engineering shows top view of our design. Section V
and Computer Science, North South University
describes entire block design. Section VI
Plot 15, Block B, Bashundhara Dhaka 1229,
Bangladesh describes methodology and hardware part and
section VII describe the result of our design.
Syed Shihab Uddin
e-mail: [email protected]
Advantages and conclusions are given in
Address: North South University, Bangladesh Section VII and IX respectively.
Iqbalur Rahman Rokon
e-mail: [email protected]
Address: North South University,Bangladesh II. DESIGN DESCRIPTION
K.M.A. Salam This section should provide the reader with
e-mail: [email protected] all the information necessary to repeat the
Address: North South University, Bangladesh work. Our voting machine works as same as
M.Abdul Awal electronic voting device. But there is a little bit
e-mail: [email protected] change we made on our voting machine. Our
Address: North South University,Bangladesh voting machine does not totally depend on
*Tabia Hossain electronic system. We also include a punch
e-mail: [email protected] system which performs quite similar operation
Tel:+8801777682314 like paper ballot system does. Voting contains
Tabia Hossain et al.

the instantiations of the other 5 modules, party’s logo. Individual party counts and the
which are 5 separate source files of the 5 total counts will be monitored and recorded
different operations. Inside Ballot module and successfully after each successive voting
Control module, there are another two process is done. Our design of the EVM is a
modules separately instantiated.We use five Finite State Machine (FSM) approach. A finite-
different steps for our design. Firstly we have state machine (FSM) or finite-state automaton
to prepare our design specification. From our is a mathematical model of computation used
design specification we write RTL Description. to sequential logic circuits and computer
Then we convert our RTL description to Gate programs [9]. It is conceived as an abstract
level design. From gate level design we go to machine that can be in one of a finite number
physical layout of our design. Finally we of states. The state diagram of our design is
implement our design. These five steps work shown in Fig.2.
individually but finally full work depends on
each of the state. If we fail to fulfil one step,
next step does not work. Though they are five
different steps and work individually, they
fully depend on each other. Without any of
these we cannot complete our design as we
want. Design flow diagram is given below:

Fig.1. Design Flow Diagram

Our Electronic Voting Machine (EVM) works
in two major units: Control Unit and Ballot
Fig.2. State Diagram of EVM
Unit. The control unit counts the individual
party results as well as the total vote counts.
III. DESIGN HIERARCHY
The ballot unit makes a beep sound and gives
a green signal when a cast vote is accepted. It
will also give out a punched paper for the
appropriate party. If any error occurs, the
ballot unit will give a red signal indication an Voting
error and hence, it will display an error
message. Validity of a voter for a certain vote
centre will be checked at fist. Only a valid Idcheck Combine Ballot Control Adder
voter with a valid NID can access the machine
to cast a vote. Error can occur in three ways:
firstly wrong ID encounter; secondly repetition Counter Decoder
of the same voter and thirdly, if more than one
party is pressed simultaneously. When a vote
is successfully accepted, along with the sound
and the green signal, a punched paper will
come out putting a seal on the appropriate Fig.3. Design Hierarchy of EVM

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EVM

IV. TOP VIEW OF EVM C. Ballot

It consists of clk, gl, rl, sound, and state.
This module also consists of a decoder module
which is instantiated inside the ballot module.
Whenever a vote is properly accepted this unit
gives beep sound and green signal which
indicate the vote is accepted. If the vote was
not accepted or any error occurs during the
voting process, this module gives a red signal
which indicates the process is wrong and
turns the voter back to the second state.

Fig.4. Top View of EVM

V. BLOCK DESCRIPTION
A. Idcheck
It consists of clk, sz, voter and xx. This
module checks whether the voter id valid or
not. Whenever voter id matches with the
stored data it makes xx high and allows the
voter for the next state.

B. Combine
It consists of con and party. Whenever id
check unit makes xx high this unit allows Fig.6. Timing Diagram of Ballot
voter to access his/her vote to any of the
D. Control
party (par1, par2, par3, par4) specified by the
machine. Whenever con becomes binary It consists of the result of four individual
0001, vote is accepted for the party1, binary party (c0, c1, c2, c3), punch (vv), clk, clr, con
0010 indicates vote for party2, binary 0100 and sound. It also consists of a counter
for party3 and binary 1000 for party4. module which is instantiated inside it. In this
unit machine gets the beep sound from the
ballot unit and the counter starts to count the
particular party’s vote and punches the
specific party’s logo on a ballot paper. This
module gives individual result of the
individual party and punches out the sealed
hard paper which can be stored outside the
machine.

Fig.5.Block Diagram of EVM Fig.7. Timing Diagram of Control

Tabia Hossain et al.

E. Adder
It consists of individual results of the
parties (co, c1, c2, c3) and total result. This
unit adds individual results of the parties and
gives the total number of vote accepted by the
machine.

Fig.9. Implementation Flow Diagram

Fig.8. Timing Diagram of Adder VII. RESULT

We simulate our design by using Modelsim
VI. METHODOLOGY AND HARDWARE ARCHITECTURE 6.5b software from which we get output web
form of our design.
In this section, the design procedure and the Fig.10. Shows the Simulation result of EVM:
architecture of EVM has been described. Fig.9.
shows the different stages of the design. [2]
The Verilog Codes were at first simulated with
ModelSim and then synthesized with Xillinx
and Quartus II Software targeted for Cyclone II
(EP2C20F484C7) device [1]. FPGA technology
is chosen because it provides some important
advantages over general purpose processors
and application specific integrated circuits
(ASICs). To simulate the design, the design
under test (DUT) and the stimulus provided by
the test bench were required. The test bench
was an HDL code that allowed providing a
documented, repeatable set of stimuli that was
portable across different simulators. The test
bench used for this design was a more
complicated file that included error checking,
file input and output and conditional testing.
After simulating the design, synthesis was
performed. The Quartus II 11.1 Synthesis tool
and the Xilinx Synthesis Technology (XST) of
Xilinx ISE 9.2i tool software both synthesized
the Verilog codes to create Xilinx / Quartus-
specific net-list files.

21
EVM

Fig.10. Simulation result of EVM Fig.12. Shows the internal block diagram of
After simulating the design, synthesis was EVM:
performed. The Quartus II 11.1 Synthesis tool
and the Xilinx Synthesis Technology (XST) of
Xilinx ISE 9.2i tool software both synthesized
the Verilog codes to create Xilinx / Quartus-
specific net-list files. Xilinx and Quartus II
generated the following files as output.
RTL Schematic: This representation is in
terms of generic symbols and was generated
after the HDL synthesis phase of the synthesis
process.
Fig.11. Shows the RTL Schematic diagram of
EVM:

Fig.12. Internal RTL Schematic Diagram of EVM

Fig.13. Shows the Synthesis Summary of EVM

Fig.11. RTL Schematic Diagram of EVM

Technology schematic: This is a schematic

representation shown in terms of logic
elements which is optimized to the target
architecture or "technology". It was generated Fig.13. Device Summary from Quartus II Tool
after the optimization and technology targeting
phase of the synthesis process.
Tabia Hossain et al.

Fig.14. Shows the data sheet report from Fig.15. Timing Report from Quartus II Tool
Quartus II synthesis tool:
For the implementation of the design, the
Altera DE1 Development and Education Board
is used. The purpose of the Altera DE1
Development and Education Board is to
provide the ideal vehicle for advanced design
prototyping in the multimedia, storage and
networking. This board uses the state-of-the-
art technology in both the hardware and
software CAD tools to expose designers to a
wide range of topics. The board offers a rich
set of features that makes it suitable for use in
a laboratory environment for the university
and college courses, for a variety of design
projects, as well as for the development of the
sophisticated digital systems. Altera provides a
suite of supporting materials for the DE1
board.
Fig.16. Shows the FPGA implementation on
Altera DE1 board:

Fig.14. Data Sheet Report from Quartus II Tool

Fig.15. shows the timing report from Quartus

II synthesis tool:

Fig.16. FPGA Implementation on Altera DE1 Board

VIII. ADVANTAGES
By using simple Verilog simulations, we can
easily hardware implement the design in our
real life environment satisfying the issues of
efficiency, cost and the transparency. So by
using FPGA based EVM, we can save around
1100 corers of taka in the 5 years of electro
cycle [4].
23
EVM

We also have FPGA based design advantages [5]VerilogHardware Description Language Reference,
on our design. Manual, Version 2.09, Los Gatos, CA, Open Verilog
We can also save huge amount of power by International, March 1993.
using this voting system as the battery is [6] Altera DE1 board. (n.d.). Retrieved December 10,
required only to activate the EVMs at the time 2010, from terasic: http://www.terasic.com.tw/cgi-
of polling and counting. As soon as the polling bin/page/archive.p1?Language=English&No=83
is over, the battery can be switched off and [7] Barlow L.(2003, November), An Introduction to
this will be required to be switched on only at Electronic Voting, Retrieved from
the time of counting. http://brahms.emu.edu.tr/rza/Electronic%20
For each national election alone it is Voting.pdf
estimated that about 10,000 tons of ballot [8] Indian Voting Machine, Wikipedia the free
paper (roughly 200,000 trees) would be saved encyclopedia. Retrieved from March 28, 2010, from
by using Electronic Voting Machine. There is http://en.wikipedia.org/wiki/Indianvoting machine.
of course many more state and city/village [9] Finite State Machine, Wikipedia the free
level elections and the cost of printing those encyclopedia.https://en.wikipedia.org/wiki/Finite-
ballot papers would be also enormous [8]. state_machine.
The vote-counting is very fast and the result [10] Verilog. Wikipedia, the free encyclopedia.
can be declared within 2 to 3 hours as Retrieved March 23, 2012 from
compared to 30–40 hours, on an average, http://en.wikipedia.org/wiki/Verilog_HDL
under the ballot-paper system. [11] Elections in Bangladesh 2006-2009:
Transforming Failure into Success. Retrieved from
IX. CONCLUSION http://sembec.org.bd/content/elections-
Considering the fact of the uncompromising bangladesh-2006-2009-transforming-failure-
advancement of VLSI technology, we have success
successfully implemented an efficient [12] Electronic Voting Machines. Retrieved from
Electronic Voting Machine on FPGA by http://www.gktoday.in/quiz-597-current-general-
satisfactorily meeting the related issues of knowledge
security and transparency for an EVM. Our
EVM deals with the sensitive cases in voting
processes like restriction of an invalid voter,
prohibition of same voter and simultaneous
vote cast for more than one candidate. Along
with that, if the punched paper results
matches with the software results then we can
say the machine result is also transparent. We
can use this efficient, secured and transparent
voting machine successfully for electoral
voting process in Bangladesh and worldwide.

ACKNOWLEDGEMENT
At first the authors would like to thank Allah
forgiving them the opportunity to do this work.
Then they would want to mention their
parents who supported them with mental and
financial support.

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