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EEE598 Project 2

1) The document describes a 3 part project assignment for an EEE598 VLSI circuits class. Part 1 involves creating and simulating a VerilogA model of a full adder circuit and an 8-bit ripple carry adder in Cadence. Part 2 involves characterizing the jitter of an output clock signal from a given CMOS buffer circuit simulation. Part 3 involves finding the voltage signals VA(t), VB(t), and VC(t) for a given step input voltage Vs(t) using circuit simulation.

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103 views

EEE598 Project 2

1) The document describes a 3 part project assignment for an EEE598 VLSI circuits class. Part 1 involves creating and simulating a VerilogA model of a full adder circuit and an 8-bit ripple carry adder in Cadence. Part 2 involves characterizing the jitter of an output clock signal from a given CMOS buffer circuit simulation. Part 3 involves finding the voltage signals VA(t), VB(t), and VC(t) for a given step input voltage Vs(t) using circuit simulation.

Uploaded by

Giser Ali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Subject: EEE598 Project #2, “VLSI High-Speed I/O Circuits” Fall2010, ASU

From: Dr. Hongjiang Song


Due Date: Sept. 23, 2010 (end of class)

Problem 1: VerilogA coding and simulation on Cadence.

Instruction: This project is designed for you to setup your simulation environment in
Cadence and to learn basic coding technique of VerilogA for simple circuits, such as
digital gates.
The easiest way to do this is to copy an existing digital gate to the component name you
would like create. Then modify the symbol and the VerilogA code (text format) to match
your component. An EEE598Lib is posted for you to start with your project. You may
download the file to you unix/lynix fold, un-zip it and then un-tar it.

Here is the project assignment:

1) Create the VerilogA view and symbol view for the digital Full Adder circuit.
Simulate it into Cadence (Spectre) to prove your design.
2) Using the Full Adder circuit to create an 8-bit binary Carry propagation adder by
connecting 8 Full Adder schematic. And simulate it in Spectre to prove your
design.

A Co
S
A Co B
Ci
S
B
Ci
A Co
S
B
Ci

A Co
S
B
Ci
Problem 2: For the CMOS buffer circuit below, find based on the simulation the Mean,
the Standard Deviation of the Absolute Jitter (or TIE), the Period Jitter, and the Cycle-to-
Cycle Jitter of the output clock signal. (Assuming TSMC0.18 process technology)

[1.5 + 0.1xSin(t)]V  = 2 x10Mhz

1.5V 1.5V

1.5V
…
0 A A A A Do

T =2ns
Rise time = fall time = 50ps P: 1.8u/0.18u
N: 1.2u/0.18u

Problem 3. For step function Vs(t) find the voltage signal at VA(t), VB(t), and VC(t). Verify
your result using circuit simulation (Hint: use T-line model in Cadence/spice).

Delay = 1s
Delay = 9s

- + VB
Vs(t) 25 VA 50 VC

ZL >> 50

1V

Vs(t)
`include "discipline.h"
`include "constants.h"

module full_adder(vin1, vin2, vin_carry, vout_sum, vout_carry);


input vin1, vin2, vin_carry;
output vout_sum, vout_carry;
electrical vin1, vin2, vin_carry, vout_sum, vout_carry;
parameter real vlogic_high = 5;
parameter real vlogic_low = 0;
parameter real vtrans = 1.4;
parameter real tdel = 3u from [0:inf);
parameter real trise = 1u from (0:inf);
parameter real tfall = 1u from (0:inf);

integer a, b, c;
real vout_sum_val;
real vout_carry_val;

analog begin

@ ( initial_step ) begin
if (vlogic_high < vlogic_low) begin
$display("Range specification error. vlogic_high = (%E) less than vlogic_low = (%E).\n",
vlogic_high, vlogic_low );
$finish;
end
if (vtrans > vlogic_high || vtrans < vlogic_low) begin
$display("Inconsistent $threshold specification w/logic family.\n");
end
end

a = V(vin1) > vtrans;


b = V(vin2) > vtrans;
c = V(vin_carry) > vtrans;

@ (cross(V(vin1) - vtrans, 1)) a = 1;


@ (cross(V(vin1) - vtrans, -1)) a = 0;

@ (cross(V(vin2) - vtrans, 1)) b = 1;


@ (cross(V(vin2) - vtrans, -1)) b = 0;

@ (cross(V(vin_carry) - vtrans, 1)) c = 1;


@ (cross(V(vin_carry) - vtrans, -1)) c = 0;

vout_sum_val = (c ^ a ^ b) ? vlogic_high : vlogic_low;


vout_carry_val = ((c && (a || b)) || (a && b))
? vlogic_high : vlogic_low;

V(vout_sum) <+ transition( vout_sum_val, tdel, trise, tfall);


V(vout_carry) <+ transition( vout_carry_val, tdel, trise, tfall);
end
endmodule

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