VHDL PROJECT

Submitted to – Vipin Kamble Sir

Submitted by –
• Praneeth Inumula(bt17ece046)
• Ashok Kumar Varasala(bt17ece069)
• Anirudh Senani(bt17ece073)
 Finite State Machine based Vending
Machine Controller
ABSTRACT

Nowadays, Vending Machines are well known among Japan, Malaysia and Singapore.
The quantity of machines in these countries is on the top worldwide. This is due to the
modern lifestyles which require fast food processing with high quality.

Vending machines are used to dispense small different products, when a coin is
inserted. FPGA based vending machine give fast response and uses less power than the
microcontroller based vending machine. The FPGA based vending machine supports
four products and three coins. The vending machine accepts coins as inputs in any
sequence and delivers products when required amount is deposited and gives back the
change if entered amount is greater than the price of product. It also supports cancel
feature means a user can withdraw the request any time and entered money will be
returned without any product. The proposed algorithm is implemented in Verilog HDL
and simulated using Xilinx ISE simulator tool

PROBLEM STATEMENT

Suppose we have a vending machine that sells soda cans that costs a 2$ each.
Moreover, we have only 3 types of coins: 1$, 2$ and 5$.
Our objective is to design a state machine that determines when to dispense a can, how to
return the change.
Note: in this design we will ignore the capacity of the stock, which means, we’ll assume that
there will always be can in the vending machine.
Also, we can assume that only one action could be made in every “clock cycle” or state
RULES:
first give back the change then dispense the can
KEYWORDS

FSM; VHDL; Vending Machine; FPGA Spartan 3 development board;

INTRODUCTION

A vending machine is a machine that provides items such as four different products even
diamonds and platinum jewellery to customers, after the vendee inserts currency or credit
into the machine using extremely simple steps. These steps would not be time consuming at
all. The vendee would get all the details on the screen which he/she should follow. Previous
microcontroller or microprocessor based vending machines were inefficient as compared to
FPGA based vending machine. So, it is necessary to make it more reliable with efficient
algorithm that will be fully commanded by FPGA based solution. The main purpose of this
project was to create a vending machine which could provide four different snacks products
to the people using extremely simple steps. We have tried to vend four products of different
prices in the same machine. The machine will also provide the change to the vendee
depending on the amount of money he/she has inserted. It is also possible to withdraw the
deposited money in between, if consumer wishes by pressing a cancel button.

DESIGN OBJECTIVES

To Design a powerful vending machine containing the following features:

1. Sell a can and accept three types of coins (Rs1, Rs2, Rs5)
2. Give change after successful trade
3. If amount is less then it reminds the remaining amount
4. Small size and acceptable power consumption

OPERATION OF VENDING MACHINE

I. When the user puts in money, money counter tells the control unit, the amount of
money inserted in the Vending Machine.
II. When the user presses the button to purchase the item that he wants, the control
unit turn on the motor and dispenses the product if correct amount is inserted.
III. If there is any change; machine will return it to the user.
IV. The machine will demand for servicing when the products are not available inside
the machine.
FSM (Finite State Machine)
In a Finite State Machine, the circuit’s output is defined in a different set of states i.e. each
output is a state. A State Register to hold the state of the machine and a next state logic to
decode the next state. An output register defines the output of the machine. In FSM based
machines the hardware gets reduced as in this the whole algorithm can be explained in one
process.

UNDERSTANDING THE POSSIBILTIES:

There are quite few options:
1) entering no money
2)putting 1$ followed by another 1$ => getting the can
3)putting 1$ followed by 2$ => receiving change => getting a can
4)putting 1$ followed by 5$ => receiving change => getting a can
5)putting 2$ and getting the can
6)putting 5$ => receiving change => getting a can.

Above, is the “big picture” of the options or states of the machine, note that if you put a
sum of money which is more or equal to 2$, you can’t put more money (since it would be
meaningless, no?!)

THE VENDING MACHINE HAS THREE INPUTS:

QUATER: a signal that goes high and then low when a quarter has been deposited
CLOCK: a clock that will drive the FSM
RESET: a signal that will reset the FSM to its initial state

THE VENDING MACHINE HAS OUTPUTS:

COUNT: a signal that goes high when a single quarter has been accepted. This signal should
remain high for one clock cycle.
DISPENSE: a signal that goes high when the soda has been dispensed
Part I
Create a clock divider module to divide the master clock (at 50MHz) to a 1Hz clock. You may
also need to create a switch debouncer for the QUARTER input to avoid confusing the FSM.
Part 2
Create your state diagram that you will use to implement the FSM VHDL module. The
vending machine behaves as follows:
• If the RESET input is asserted, the FSM will go to the initialization state (S_init)
immediately. All the outputs should be zero in this state.
• From the initialization state (S_init), the FSM will unconditionally go to the wait state
(S_wait)
• From the wait state (S_wait), the FSM waits for the QUARTER switch to be activated.
• If QUARTER is asserted, the FSM goes to state S_Q1. In this state, the COUNT output
is set to 1, indicating that a quarter has been accepted. The FSM will stay in this state until
the QUARTER input is de-asserted. When this occurs, the FSM goes to state S_QW1, then
unconditionally to state S_QW2 and the COUNT output is set to 0. The FSM waits for the
QUARTER switch to be activated.
• If QUARTER is asserted while the FSM is in S_QW2, then the state machine goes to
state S_Q2. In this state, the COUNT output is again set to 1. The FSM will stay in this state
until the QUARTER input is de-asserted. When this occurs, the FSM goes to S_QW3, and
then unconditionally to state S_dispense, the COUNT output is set to 0, and the DISPENSE
output is set to 1.
• From state S_dispense, the FSM unconditionally goes to state S_init.
CODE:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity soda_vending_machine is
Port (clk: in STD_LOGIC; --Clock, active high
rstn: in STD_LOGIC; --Async. Reset, active low
coinIn: in STD_LOGIC_VECTOR (1 downto 0); --Which coin was inserted?
soda: out STD_LOGIC;
coinOut: out STD_LOGIC_VECTOR (1 downto 0)); --Which coin is dispensed?
end soda_vending_machine;

architecture Behavioral of soda_vending_machine is

type state_type is (idle, --start state/reset

put_money, --waiting to enter money
in_1, in_3, in_6, in_5, --represent the current sum of money after returning change
change_1, --should return change of 1$
soda_out --dispence soda can.
); --type of state machine.

signal current_s, next_s: state_type; --current and next state declaration.

begin

process (CLK, RSTn)

begin
if (RSTn = '0') then
current_s <= idle; --default state is on RESET
elsif (clk'event and clk = '1') then
current_s <= next_s;
end if;
end process;
--------------------
--FSM process:
Process (current_s, CoinIn)
begin
case current_s is
when idle => --state reset or idle
Soda <= '0';
CoinOut <= "00";
next_s <= put_money;
------------------------------------------------------
when put_money => --wait for money to be entered
if (CoinIn = "00") then
Soda <= '0';
CoinOut <= "00";
next_s <= put_money;
elsif (CoinIn = "01") then --insert 1$
Soda <= '0';
CoinOut <= "00";
next_s <= in_1;
elsif (CoinIn = "10") then --insert 2$
Soda <= '0';
CoinOut <= "00";
next_s <= soda_out;
elsif (CoinIn = "11") then --insert 5$
Soda <= '0';
CoinOut <= "00";
next_s <= in_5;
end if;
------------------------------------------------------
when in_1 =>
if (CoinIn = "00") then--stay on the same state
Soda <= '0';
CoinOut <= "00";
next_s <= in_1;
elsif (CoinIn = "01") then--inserted another 1$
Soda <= '0';
CoinOut <= "00";
next_s <= soda_out;
elsif (CoinIn = "10") then--inserted another 2$
Soda <= '0';
CoinOut <= "00";
next_s <= in_3;
elsif (CoinIn = "11") then
Soda <= '0';
CoinOut <= "10";
next_s <= in_6;
end if;
------------------------------------------------------
when in_3 =>
Soda <= '0';
CoinOut <= "01";
next_s <= soda_out;
------------------------------------------------------
when in_6 =>
Soda <= '0';
CoinOut <= "01";
next_s <= in_5;
------------------------------------------------------
when in_5 => -- input = 5 coin
Soda <= '0';
CoinOut <= "10";
next_s <= change_1;
------------------------------------------------------
when change_1 => -- input = 5 coin
Soda <= '0';
CoinOut <= "01";
next_s <= soda_out;
------------------------------------------------------
when soda_out =>
Soda <= '1';
CoinOut <= "00";
next_s <= put_money;
end case;
end process;
end Behavioral;

WAVEFORM OF VENDING MACHINE:

OUTPUT for 00:

OUTPUT for 01:

OUTPUT for 10:

OUTPUT for 11:

CONCLUSION:

The present FPGA based vending machine controller is implemented using FSMs with the
help of Xilinx ISE Design Suite 14.1. The design can be verified on the FPGA Spartan 3
development Board. State machines based vending Systems enhances productivity, reduces
system development cost, and accelerates time to market. Also, FPGA based vending
machine give fast response and easy to use by an ordinary person. The designed machine
can be used for many applications and we can easily enhance the number of selections. The
next stage of this study is to convert this model into hardware and to calculate the total
power consumption of the machine.