Gate-Level Timing Analysis

Smith Chapter 13
Outline
 Gate-delay models
 Circuit timing constraints
 VITAL models for gate-level simulation
 VHDL netlist simulation with VITAL models and Standard
Delay Format (SDF) files
 Logic cell delay models

 “Delay” = time from the occurrence of an event until the

occurrence time of a 2nd event caused by the first
 depends on circuit structure & technology
 may also depend on cell interconnects
 model delays with different levels of detail/accuracy
 may have a range of possible values (process/condition dependent)

Event Event
Delay
Primitive device delay models

 A primitive logic gate has an intrinsic delay.

 model as an ideal (zero-delay) gate and a “transport delay”
element.
 transport delay models:
 unit/nominal delay
 rise/fall delay a c*
t c
 ambiguous or min/max delay b
Ideal Time
gate delay
Unit/nominal delay
 Unit delay: each gate has delay of one “unit” of time.
 Nominal delay: delays determined separately for each type of
gate
(e.g., on time unit for NOR and two time units for XOR).

t t
Rise/fall delay
 Delays for 0 to 1 and 1 to 0 transitions.
 tPLH (rise time): propagation delay for signal changing from
low to high.
 tPHL (fall time): propagation delay from high to low.

tPLH tPHL
(rise time) (fall time)
Example: ADK tsmc035 technology

 nand02 cell:
 tP=0.537466 (ns) INV on A0(RI) to Y(FA)
 tP=0.810693 (ns) INV on A0(FA) to Y(RI)
 tP=0.421754 (ns) INV on A1(RI) to Y(FA)
 tP=0.868593 (ns) INV on A1(FA) to Y(RI)
 and02 cell:
 tP=0.726188 (ns) INV on A0(RI) to Y(FA)
 tP=0.828392 (ns) INV on A0(FA) to Y(RI)
 tP=0.679021 (ns) INV on A1(RI) to Y(FA)
 tP=0.921874 (ns) INV on A1(FA) to Y(RI)
Ambiguous or Min/Max Delay
 Difficult to predict exact rise or fall time of a signal.
 For worst-case performance analysis, {tmin, tmax} is specified for
each timing parameter.

c
tmin

ambiguity regions
tmax
Accumulated min/max delays

 Simulation producing min/max delay results tend to be

pessimistic.
 ambiguity region larger at each level

d
a f
b e
h
g
c
d g h
e
15
101214 16 20 25
Inertial Delay
 An input value must persist for some minimum duration of
time to provide the output with the needed inertia to change.
 The minimum duration is called inertial delay.

a a

b b

c c
(a) Transport delay model (b) Inertial delay model

t a*
a
c* t
Model with both inertial c
b t Transport
and transport delays: b* Ideal delay
Inertial gate
delay
 VHDL transport/inertial delays

 Default is “inertial” - reject pulses shorter than circuit

switching time (cancel pending “events”)
 Op <= Ip after 10 ns;
 Op <= inertial Ip after 10 ns;
 Op <= reject 10 ns inertial Ip after 10 ns;
 “Transport” delay – transmit all pulses, of any duration
 Op <= transport Ip after 10 ns;
 Op <= transport Ip after 10 ns, not Ip after 20 ns
Equivalent:
 Op <= reject 0 ns inertial Ip after 10 ns;
 Op <= reject 0 ns inertial Ip after 10 ns, not Ip after 20 ns
 Path delays of interest
1. Combinational: primary input to primary output: in2->out2
2. Primary input to register input: in1 -> FF1/D1
3. Clock/register output to primary output: clk -> Q2 -> out1
4. Clock/register output to register input: clk -> Q1 -> D2

2 4 3

1
Timing Constraints:
Flip flop setup, hold & clock times
 Constrain signal transitions to ensure reliable
operation
 tSU (setup time) of signal X with respect to signal Y = time
prior to active change on Y by which X must be stable
 tH (hold time) of signal X with respect to signal Y = time
following active change on Y during which X must be stable
 tPW, tH, tL = clock signal minimum pulse width, high time,
low time T
tSU tH
Signal X T = time of clock transition
tSU = flip flop setup time
tH = flip flop hold time

No changes at
flip flop inputs
SN74LS74A (D flip flop) parameters

Source:http://focus.ti.com/lit/ds/symlink/sn74ls74a.pdf
 ADK tsmc035 technology D flip flop
Report Timing Info for Instance /DFFR1 of TYPE QPT
tP = 0.637972 (ns) NONINV ON CLK(RI) TO Q(RI) --delays from CLK rise
tP = 0.746466 (ns) INV ON CLK(RI) TO QB(FA)
tP = 0.752151 (ns) INV ON CLK(RI) TO Q(FA)
tP = 0.896604 (ns) NONINV ON CLK(RI) TO QB(RI)
tP = 0.828865 (ns) INV ON R(RI) TO Q(FA) --delays from Reset active
tP = 0.973914 (ns) NONINV ON R(RI) TO QB(RI)

tS = 0.688299 (ns) ON D(H) TO CLK(RI) -- setup times

tS = 0.583595 (ns) ON D(L) TO CLK(RI)
taS = 0.579838 (ns) ON R(FA) TO CLK(RI)

tH = -0.0942826 (ns) ON D(H) TO CLK(RI) -- hold times

tH = -0.052878 (ns) ON D(L) TO CLK(RI)
taH = 0.330582 (ns) ON R(FA) TO CLK(RI)
Methods for timing anaysis
 Timing simulation
 Primitive element models include delay and constraint
parameters
 Gate and/or transistor level
 Delays and constraint violations detected in simulation
results

 Static timing analysis

 Path delays calculated from primitive models
 Determine max operating frequency by finding “critical path”
= longest delay between successive flip flops
Detection of static hazards
 A glitch in g at time t3 can be detected from the
output waveforms.
 This occurs because both e and f become 0
momentarily between t2 and t3.
a

c
a e
b d
g
e
d

c f
f
g

Time t t t
t1 t2 t3 t4
Circuit-level timing constraints
tPCL (propagation delay)

Inputs Outputs
Combinational
Logic

tPFF (prop. delay) Next

State State
Flip
flops

Clock
Minimum clock period
TCLK

TCLK min t PFF t PCL t su

Flip flop
Combinational Flip flop
propagation setup time
delay (max) logic propagation
delay (max)
External input setup/hold times
t T
tPCL tSU tH tPCL = max, propagation delay from
ext. signal to FF inputs
tSU = flip flop setup time
tH = flip flop hold time
T = time of clock transition
Input No changes at t = time of input change (Δx)
change flip flop inputs

For reliable operation, constrain time t of external input

changes, relative to the time T of the active clock transition:
x:t T t PCL t su Satisfy setup time constraint

x:t T tH t PCL Satisfy hold time constraint

Timing simulation with VHDL models
 Synthesized structural models comprise cells from a
library (ADK library, for example)
 Each library cell has been characterized to determine delays,
constraints, etc.
 Most current libraries represent timing information using
the VITAL standard
 VHDL Initiative Toward ASIC Libraries
 IEEE Standard 1076.4
 Synthesis tools create a Standard Delay Format (SDF)
file of timing data for each cell in the design for use
with VITAL models
 SDF = IEEE Standard 1497
Example
 The modulo 7 counter was synthesized using one of the
technologies in the ADK
 The next slides show a VITAL model of a D flip flop from
the library.
 The following slides contain a partial SDF file, showing the
timing parameters extracted for a couple of gates in the
synthesized design
VITAL model of a D flip flop
library IEEE; use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Primitives.all; -- Primitive logic functions
use IEEE.VITAL_Timing.all; -- Delay/Constraint calculation func’s

entity dff is
generic (
tipd_CLK : VitalDelayType01Z := VitalZeroDelay01Z;
tipd_D : VitalDelayType01Z := VitalZeroDelay01Z;
tpd_CLK_Q : VitalDelayType01Z := VitalZeroDelay01Z;
tpd_CLK_QB : VitalDelayType01Z := VitalZeroDelay01Z;
tsetup_D_CLK_noedge_posedge : VitalDelayType := 0 ns;
thold_D_CLK_noedge_posedge : VitalDelayType := 0 ns;
tpw_CLK_posedge : VitalDelayType := 0 ns;
tpw_CLK_negedge : VitalDelayType := 0 ns;
TimingChecksOn : BOOLEAN := TRUE;
InstancePath : STRING := "*“
);
-- VitalDelayType01Z = delays for 0-1,1-0,0-Z,1-Z,Z-0,Z-1 changes
Continued
DFF model (continued)
port (
D : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC;
QB : out STD_LOGIC
);
attribute VITAL_LEVEL0 of dff : entity is TRUE;
end dff;

architecture dff_arch of dff is

attribute VITAL_LEVEL1 of dff_arch : architecture is TRUE;
signal CLK_ipd : STD_LOGIC := 'X';
signal D_ipd : STD_LOGIC := 'X';

Continued
 DFF model (continued)
begin
WireDelay : Block begin -- Input wire delays
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (D_ipd, D, tipd_D);
end Block;

VitalBehavior : Process (CLK_ipd, D_ipd)

VARIABLE Tviol_0 : X01 := '0';
VARIABLE SetupHoldInfo_0 : VitalTimingDataType :=
VitalTimingDataInit;
VARIABLE Pviol_0 : X01 := '0';
VARIABLE PeriodDataInfo_0 : VitalPeriodDataType :=
VitalPeriodDataInit;
VARIABLE Violation_0 : X01 := '0';
VARIABLE PrevData_0 : STD_LOGIC_VECTOR(0 to 2);
VARIABLE Results_0 : STD_LOGIC_VECTOR(0 to 2);

Continued
DFF model (continued)
CONSTANT DFF_table : VitalStateTableType := (
('X','-','-','-','-','X','X','X'), ('-','^','0','0','-','X','0','1'),
('-','^','1','0','-','X','1','0'), ('-','^','0','1','0','X','0','1'),
('-','^','1','1','1','X','1','0'), ('-','f','0','-','0','1','S','S'),
('-','f','0','-','1','1','X','X'), ('-','f','1','-','1','1','S','S'),
('-','f','1','-','0','1','X','X'), ('-','v','B','B','-','X','S','S'),
('-','r','0','-','0','0','S','S'), ('-','r','0','-','-','0','X','X'),
('-','r','1','-','1','0','S','S'), ('-','r','1','-','-','0','X','X'),
('-','/','0','-','-','X','0','1'), ('-','/','1','-','-','X','1','0'),
('-','\','-','-','-','X','S','S'), ('-','*','-','-','-','X','X','X'),
('-','B','*','-','-','X','S','S'), ('-','-','*','-','-','X','S','S'),
('-','-','-','-','-','S','S','S')
);

ALIAS INT_RES_0 : STD_LOGIC is Results_0(1);

ALIAS INT_RES_1 : STD_LOGIC is Results_0(2);
VARIABLE GlitchData_Q : VitalGlitchDataType;
VARIABLE GlitchData_QB : VitalGlitchDataType;
Continued
DFF model (continued)
begin -- process begin
------------------------------------
-- TIMING SECTION --
------------------------------------
if (TimingChecksOn) then --check constraint violations
VitalSetupHoldCheck (
TestSignal => D_ipd, TestSignalName => "D",
RefSignal => CLK_ipd, RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TRUE,
RefTransition => 'R',
TimingData => SetupHoldInfo_0,
MsgOn => TRUE, XOn => TRUE,
HeaderMsg => InstancePath & "/dff",
Violation => Tviol_0,
MsgSeverity => ERROR ); Continued
DFF model (continued)
VitalPeriodPulseCheck (
TestSignal => CLK_ipd, TestSignalName => "CLK",
Period => 0 ns,
PulseWidthHigh => tpw_CLK_posedge,
PulseWidthLow => tpw_CLK_negedge,
CheckEnabled => TRUE,
PeriodData => PeriodDataInfo_0,
MsgOn => TRUE, XOn => TRUE,
HeaderMsg => InstancePath & "/dff",
Violation => Pviol_0,
MsgSeverity => ERROR
);
end if;

Continued
DFF model (continued)
------------------------------------
-- FUNCTIONALITY SECTION --
------------------------------------
-- Functional behavior of D flip flop
Violation_0 := Tviol_0 or Pviol_0;
VitalStateTable (
StateTable => DFF_table,
DataIn => STD_LOGIC_VECTOR'(
Violation_0, CLK_ipd, D_ipd
),
NumStates => 2,
Result => Results_0,
PreviousDataIn => PrevData_0
);

Continued
DFF model (continued)
------------------------------------
-- PATH DELAY SECTION --
------------------------------------

VitalPathDelay01Z ( -- delay to output Q

OutSignal => Q,
OutSignalName => "Q",
OutTemp => INT_RES_0,
Paths => (
0 => (
InputChangeTime => CLK_ipd'LAST_EVENT,
PathDelay => tpd_CLK_Q,
PathCondition => TRUE
)
),
GlitchData => GlitchData_Q,
Mode => OnDetect,
MsgOn => TRUE, Xon => TRUE,
MsgSeverity => WARNING ); Continued
DFF model (continued)
VitalPathDelay01Z ( -- delay to output QB
OutSignal => QB,
OutSignalName => "QB",
OutTemp => INT_RES_1,
Paths => (
0 => (
InputChangeTime => CLK_ipd'LAST_EVENT,
PathDelay => tpd_CLK_QB,
PathCondition => TRUE
)
),
GlitchData => GlitchData_QB,
Mode => OnDetect,
MsgOn => TRUE, Xon => TRUE,
MsgSeverity => WARNING
);
end Process VitalBehavior;
end dff_arch;
Standard Delay File (SDF)
 Produced by synthesis tool (Leonardo)
 Contains VITAL data values for all cells in the netlist
 Example (for synthesized counter and ADK library):
SDF Header – common to all cells in this synthesized netlist
(DELAYFILE
(SDFVERSION "2.0")
(DESIGN "count4")
(DATE "Thu Feb 09 15:49:13 2006")
(VENDOR "Exemplar Logic, Inc., Alameda")
(PROGRAM "LeonardoSpectrum Level 3")
(VERSION "2005a.82")
(DIVIDER /)
(VOLTAGE)
(PROCESS)
(TEMPERATURE)
(TIMESCALE 1 ns)
SDF data for DFFR instance Q_0
- path delays and constraints
- one for each cell instance in the circuit
(CELL
(CELLTYPE "dffr")
(INSTANCE Q_0) Select at
(Min: Typical: Max)
(DELAY simulation setup
(ABSOLUTE
(PORT D (::0.00) (::0.00))
(PORT CLK (::0.00) (::0.00)) Input pin delays
(PORT R (::0.00) (::0.00))
(IOPATH CLK Q (::0.51) (::0.55))
(IOPATH R Q (::0.00) (::0.60)) Path delays from
(IOPATH CLK QB (::0.39) (::0.30)) reset/clock to outputs
(IOPATH R QB (::0.44) (::0.00))))
(TIMINGCHECK
(SETUP D (posedge CLK) (0.47))
(HOLD D (posedge CLK) (-0.06)))) Constraints
SDF data for NAND instance ix170
-- path delays only (no constraints)

(CELL
(CELLTYPE "nand02")
(INSTANCE ix170)
(DELAY
(ABSOLUTE
(PORT A0 (::0.00) (::0.00))
(PORT A1 (::0.00) (::0.00))
(IOPATH A0 Y (::0.09) (::0.08))
(IOPATH A1 Y (::0.12) (::0.10)))))
Timing simulation in Modelsim
Select SDF tab
when starting
simulation.

Click Add to
select SDF file

Select
min, typ
or max
delay

Reduce error to warning

to permit simulation to
continue after error
Simulating with SDF & do file
vsim modulo7 –sdftyp modulo7_0.sdf –sdfnoerror -L adk –t ps

Compile options
-sdftyp modulo7_0.sdf
-Apply delays from SDF file modulo7_0.sdf
-Can also use –sdfmin or –sdfmax.
-sdfnoerror -Reduce SDF errors to warnings to enable
simulation with missing hold times, etc.
-L adk -Library of gate-level VITAL models.
-t ps -Timing resolution consistent with SDF.
Simulating with SDF & testbench

vsim -sdftyp /modulo7_bench/UUT=modulo7_0.sdf

-sdfnoerror -L adk -t ps modulo7_bench

Compile options
-sdftyp /modulo7_bench/UUT=modulo7_1.sdf
-Apply delays only to design instance (UUT).
-Can also use –sdfmin or –sdfmax.
-sdfnoerror -Reduce SDF errors to warnings to enable
simulation with missing hold times, etc.
-L adk -Library of gate-level VITAL models.
-t ps -Timing resolution consistent with SDF.
Testbench: modulo7_bench.vhd
LIBRARY ieee; USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
Alternative
ENTITY modulo7_bench is end modulo7_bench;
to “do” file
ARCHITECTURE test of modulo7_bench is
component modulo7
PORT (reset,count,load,clk: in std_logic;
I: in std_logic_vector(2 downto 0);
Q: out std_logic_vector(2 downto 0));
end component;
for all: modulo7 use entity work.modulo7(Behave);
signal clk : STD_LOGIC := '0';
signal res, cnt, ld: STD_LOGIC;
signal din, qout: std_logic_vector(2 downto 0);

begin
-- instantiate the component to be tested Continue on
UUT: modulo7 port map(res,cnt,ld,clk,din,qout); next slide
 Testbench: modulo7_bench.vhd
qint = expected outputs of UUT
clk <= not clk after 10 ns;

P1: process qint := UNSIGNED(din); --loaded value

variable qint: UNSIGNED(2 downto 0); wait for 5 ns; --hold after load
variable i: integer; ld <= '0'; --disable load
begin cnt <= '1'; --enable count
qint := "000"; for i in 0 to 20 loop
din <= "101"; res <= '1'; wait until clk'event and clk = '1';
cnt <= '0'; ld <= '0'; assert UNSIGNED(qout) = qint
wait for 10 ns; report "ERROR Q not Q+1"
res <= '0'; --activate reset for 10ns severity WARNING;
wait for 10 ns; if (qint = "110") then
assert UNSIGNED(qout) = qint qint := "000"; --roll over
report "ERROR Q not 000" else
severity WARNING; qint := qint + "001"; --increment
res <= '1'; --deactivate reset end if;
wait for 5 ns; --hold after reset end loop;
ld <= '1'; --enable load end process;
wait until clk'event and clk = '1';
Print message if incorrect result
 Simulation without SDF

Note “delta”
delays for
behavioral
model.
Simulation using SDF file

Note actual
delays within
test circuit.

Delta delays at
testbench level. load

count