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Synthesis Script

This document outlines the steps for a synthesis flow, including reading Verilog files, elaborating the design, reading constraints, optimizing for timing, writing out gate-level netlists and reports. It specifies libraries, turns off certain optimizations, and sets attributes like preserving clock signals before running the actual synthesis step to generate a mapped netlist and various reports on area, timing, power and runtime.

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poojabadiger
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97 views

Synthesis Script

This document outlines the steps for a synthesis flow, including reading Verilog files, elaborating the design, reading constraints, optimizing for timing, writing out gate-level netlists and reports. It specifies libraries, turns off certain optimizations, and sets attributes like preserving clock signals before running the actual synthesis step to generate a mapped netlist and various reports on area, timing, power and runtime.

Uploaded by

poojabadiger
Copyright
© © All Rights Reserved
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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# Atharva Wazurkar

set design demo_comp

######-------Specifying the target library (tt or ss or ff).

set_attribute library
{/home/atharva/ASIC_flow/Frontend_Flow/fsf0l_ers/2013Q1v1.0/GENERIC_CORE/FrontEnd/s
ynopsys/synthesis/fsf0l_ers_generic_core_ss1p08v125c.lib}

######-------Capacitance table is included after the parasitic extraction of the


layout.

##set_attribute cap_table_file file_name.cap

######-------Reads the Verilog-hdl file and checks for the syntax error and
elaborates the design.

read_hdl /home/atharva/ASIC_flow/Frontend_Flow/hdl_codes/$design.v

######-------Buids data structure, infers registers, performs high-level HDL


optimization and checks semantics.

elaborate

######-----Reading design constraint file (in .sdc format)..

read_sdc ./rc_script/$design.sdc

######-----set don't touch the clk signal---------

set_attribute preserve true clk

######-----preserve the sequential block which do not fannout while


synthesizing---------

set_attribute delete_unloaded_seqs false

######------Prevents constant propagation via latches in the design------

set_attribute optimize_constant_latches false

######-------Instructs RTL compiler to optimize all the paths with negative slack
apart from the path with worst case negative slack.

set_attribute tns_opto true

#####------Proceeding with synthesis consideering the constraints..

synthesize -to_mapped

######---------Generate gate-level netlist to a specific file..

write_hdl > ./GateLevel_netlist/$design.v


#######---------write SDC file..

write_sdc > ./sdc_file/$design.sdc

set_attribute information_level 9

######----Generating the synthesis report..

report area > ./Synthesis_reports/area.rep

report gates > ./Synthesis_reports/gate_count.rep

#report timing -lint > ./Sythesis_reports/timing.rep

report timing > ./Synthesis_reports/timing.rep

report power > ./Synthesis_reports/summary_power.txt

report messages > ./Synthesis_reports/summary_error_warning_info.rep

#####---------------CPU-runtime and memory usage..

get_attribute runtime

get_attribute memory_usage

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