STLD Question Bank
STLD Question Bank
2 MARK QUESTIONS:
1. Draw the logic symbols and truth table of NAND and NOR gates
2. What is the BCD equivalent of 45610
3. If 1435 = X6, then X is
4. Minimum number of two input NAND gates required to implement Y = A + B C
5. State and prove De-Morgan’s theorem
6. What do you understand by universal gate
7. Convert the given equation Y=AB+AC’+BC into standard SOP form
8. Reduce A'B'C' + A'BC' + A'BC
9. Simplify the following expression Y = (A + B) (A + C’) (B' + C’)
10. Define duality property
11. Find the complement of the functions F1 = x'yz' + x'y'z and F2 = x (y'z' + yz).By
applying De-Morgan's theorem.
12. What is a Logic gate?
13. State the associative property of boolean algebra
14. Reduce AB + (AC)' + AB’C (AB + C)
15. Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC
16. Convert the given expression in canonical SOP form Y = AC + AB + BC.
17. Simplify the following expression Y = (A + B) (A + C’) (B' + C’)
18. What is the Hexadecimal equivalent of 11100101102
19. Draw the logic symbols of EX-NOR and EX-OR gates and its truth table.
20. Prove A(A'+B)=AB
10 MARK QUESTIONS
1. Convert the given decimal number 234 to binary, quaternary, octal, hexadecimal and BCD
equivalent
2. Perform the following
(i) Subtraction by using 10’s complement for the given 3456 - 245.
(ii) Subtraction by using 2’s complement for the given 111001-1010.
3. A) Convert the following to Decimal and then to Octal. (i) 423416 (ii) 100100112
B) Convert the following to Decimal and then to Hexadecimal. ( i) 12348 (ii) 110011112
4. Simplify the following Boolean expression: (i) F = (A+B)(A’+C)(B+C). (ii) F =
A+B+C’+D(E+F)’
5. A) Obtain the truth table of the following Boolean function and express the function
as sum of minterms and product of maxterms F = (A+B) (B+C).
B) Simplify the following Boolean functions to minimum number of literals.
(i)xyz + x’y + xyz’.
(ii)xz + x’yz.
6. Convert the following to Decimal and then to Octal.
(a) 123416
(b) 12EF16
(c) 101100112
(d) 100011112
(e) 35210
(f) 99910
7. (a) Simplify the following Boolean expressions to minimum no. of literals.
i. ABC+A’B+ABC’
ii. (BC’+A’D)(AB’+CD’)
iii. x’yz+xz
iv. xy+x(wz+wz’)
(b) Obtain the Dual of the following Boolean expressions.
i. AB+A(B+C)+B’(B+D)
ii. A+B+A‘B’C
iii. A’B+A’BC’+A’BCD+A’BC’D’E
iv. ABEF+ABE’F’+A’B’EF
8. (a) State Duality theorem. List Boolean laws and their Duals.
(b) Simplify the following Boolean functions to minimum number of literals:
i. F = ABC + ABC’ + A’B
ii. F = (A+B)’ (A’+B’)
9. (a) Convert the following
(i) (BC)16 = ( )10 (ii)(2314)8= ( )10 (iii) (1000011)2 = ( )10 (iv) (647)10=( )16
(b) Perform the following using BCD arithmetic
(i) (79)10 + (177)10 (ii) (481)10 + (178)10
10. Convert the following to binary and then to gray code.
(a) (1111)16 (b) (BC54)16 (c) (237)8 (d) (164)10 (e) (323)8
BITS
1. Indicate which of the following logic gates can be used to realized all possible
combinational logic functions. GATE 1989 [ ]
A. OR gate B.NAND gates only C. EX-OR gate D. NOR & NAND gates
2. Boolean expression for the output of XNOR logic gate with inputs A and B is
GATE 1993 [ ]
A. AB’ + A’B B. (AB)’ + AB C. (A’ + B)(A + B’) D. (A’ + B’)(A + B)
3. The output of a logic gate is ‘1’ when all its inputs are at logic ‘0’. The gate is either
GATE 1994 [ ]
A. a NAND or an EX-OR gate B. a NOT or an EX-NOR gate
C. an OR r an EX-NOR gate D. an AND or an EX-OR gate
4. The output of the logic gate shown is GATE 1997 [ ]
A. 0 B. 1 C. A D. A’
5. 2’s complement representation of a 16 bit number (one sign bit and 15 magnitude
bits) is FFFF. Its magnitude in decimal representation is GATE 1993 [ ]
A. 0 B. 1 C. 32,767 D. 65,535
6. Two 2’s complement numbers having sign bits x and y are added and the sign bit of
the result is z. Then, the occurrence of overflow is indicated by the Boolean function.
GATE 1998 [ ]
A) xyz B) x y z C) x y z xy z D. xy + yz + zx
7. 4 – bit 2’s complement representation of a decimal number is 1000. The number is
GATE 2002 [ ]
A. +8 B. 0 C. -7 D. -8
8. The number of bytes required to represent the decimal number 1856357 in packed
BCD (Binary Coded Decimal) form is _______. GATE 2014 [ ]
A. 4 B. 3 C. 2 D. 8
9. The two numbers represented in signed 2’s compliment form are P = 11101101 and Q
= 11100110. If Q is subtracted from P, the value obtained in signed 2’s compliment
form is___. GATE 2008 [ ]
A. 100000111 B. 00000111 C. 11111001 D. 111111001
10. A new Binary Coded Pentary (BCP) number system is proposed in which every digit
of a base-5 number is represented by its corresponding 3-bit binary code. For
example, the base-5 number 24 will be represented by its BCP code 010100. In this
number system, the BCP code 100010011001 corresponds to the following number in
base-5 system. GATE 200 [ ]
A. 423 B. 1324 C. 2201 D. 4231
11. Boolean expression for the output of XNOR logic gate with inputs A and B is
GATE 1993 [ ]
A. AB’ + A’B B. (AB)’ + AB C. (A’ + B)(A + B’)
D. (A’ + B’)(A + B)
12. The 2’s complement representation of – 17 is GATE 2001 [ ]
A. 01110 B. 101111 C. 11110 D. 10001
13. The range of signed decimal numbers that can be represented by 6 bit 1’s complement
form is GATE 2004 [ ]
A. -31 to +31 B. -63 to +64 C. -64 to +63 D. -32 to +31
14. Decimal 43 in Hexadecimal and BCD number system is respectively.GATE 2005 [ ]
A. B2, 0100 0011 B. 2B, 0100 0011 C. 2B, 0011 0100 D. B2, 0100 0100
15. X = 01110 and Y = 11001 are two 5 bit binary numbers represented in 2’s
compliement format. The sum of X and Y represented in 2’s compliment format using
6 bits is GATE 2004 [ ]
A. 100111 B. 001000 C. 000111 D. 101001
16. The number of bytes required to represent the decimal number 1856357 in packed
BCD (Binary Coded Decimal) form is ___. GATE 2014 [ ]
A. 1 B. 2 C. 4 D. 8
17. The Boolean function A + BC is a reduced form of GATE 1997 [ ]
A. AB + BC B. (A + B)(A + C) C. A’B + AB’C D. (A + C)B
18. The logical expression Y = A + A’B is equivalent to GATE 1999 [ ]
A. AB B. A’B C. A’ + B D. A+B
19. The minimized form of the logical expression ABC ABC ABC ABC is
GATE 1999 [ ]
A. AC BC AB B. AC C B AB C. C A C B AB D. None
20. The Boolean expression AC + BC’ is equivalent to GATE 2004 [ ]
21. The following Boolean expression Y = A’B’C’D + A’BCD’ + AB’C’D + ABC’D’
can be minimized to GATE 2007 [ ]
A. ABCD ABC ACD B. ABCD BC D ABCD
C. ABC D BCD ABC D D. None
22. The number of Boolean functions that can be generated by n variables is equal to
GATE 1990 [ ]
2 n 1 2n n 1 n
A. 2 B. 2 C. 2 D. 2
23. The hexadecimal representation of 7568 is _____. [ ]
(A). 1EEH (B). 178H (C). EE1H (D). 436H
24. A group of 16 bits is known as ____ [ ]
(A). Bit (B). Byte (C). Word (D). Nibble
25. A 15-bit hamming code requires _____. [ ]
(A). 4 parity bits (B). 5 parity bits (C). 10 parity bits (D). 7 parity bits
26. Applying Canonical theorem to the expression, A B C D , we get ____. [ ]
̅ ̅ ̅ ̅ ̅ ̅
(A). ABCD (B). A + B + C + D ̅ ̅ ̅ ̅
(C). A + B + C + D ̅
(D). A + B + C + D ̅
31. Hexadecimal letters A through F are used for decimal equivalent values from___. [ ]
(A). 1 through 6 (B). 9 through 15 (C). 10 through 15 (D). 11 through 16
38. The minimum number of NAND gates required to implement the Boolean function A
+ AB’ + AB’C is equal to GATE 1995 [ ]
A. Zero B. 1 C. 4 D. 7
39. The subtraction of a binary number Y from another binary number X, done by adding
2’s compliment of Y to X, results in a binary number without overflow. This implies
that the result is GATE 1987 [ ]
A. Negative and is in normal form B. Negative an is in 2’s compliment form
C. Positive and is in normal form D. Positive and is in 2’s compliment form
40. 2’s complement representation of a 16 bit number (one sign bit and 15 magnitude
bits) is FFFF. Its magnitude in decimal representation is GATE 1993 [ ]
A. 0 B. 1 C. 32,767 D. 65,535
UNIT-II
2 MARK QUESTIONS:
10 MARK QUESTIONS:
1. Minimize the following Boolean function using k-map and realize using NAND Gates
F(A, B, C, D)= Σm(0, 2, 4, 6, 8, 10, 12, 14).
2. Minimize the given Boolean function F(A,B,C,D) = Σ m(0,1,2,3,6,7,13,15) using tabulation
method and implement using basic gates
3. Simplify the following Boolean expressions using K-map and implement them using
NAND gates
F(W,X,Y,Z)= XZ+W’XY’+WXY+W’YZ+WY’Z
4. Simplifying the following expression using tabulation technique
F=Σm(0,1,2,8,9,15,17,21,24,25,27,31)
5. Simplify the following expression using the K-map for the 4-variable
Y = AB’C+A’BC+A’B’C+A’B’C’+AB’C’
6. Implement the following Boolean function using NOR gates
Y=(AB’+A’B)(C+D’).
7. Simplify the Boolean function by using tabulation method
F(a,b,c,d)=Σm(0,1,2,5,6,7,8,9,10,14)
8. Simplify the following Boolean function for minimal SOP form using K-map
F(A,B,C,D) = Σ(0,1,2,4,5,6,8,9,12,13,14)
9. Simplify the following Boolean function using Tabulation method
Y(A,B,C,D) = Σ(1,3,5,8,9,11,15)
10. Simplify the following Boolean function for minimal POS form using K-map
F(X,Y,Z) = X’YZ + XY’Z’ + XYZ + XYZ’
BITS
1. The number of product terms in the minimized sum of product expression obtained
through the following K-map (where “d” denotes don’t care states) GATE 2006[ ]
1 0 0 1
0 d 0 0
0 0 d 1
1 0 0 1
A). 2 B). 3 C. 4 D. 5
2. A Boolean function, F is given as sum of product (SOP) terms as P = ∑m (3, 4, 5, 6)
with A, B and C as inputs. The function, F can be expressed on the karnaugh’s map
shown below. What will be the minimized SOP expression for F GATE 1994 [ ]
A). 6 B). 5 C. 4 D. 8
4. In the sum of products function f(X,Y,Z ) =Σ(2,3,4,5), the prime implicates are
GATE 2012 [ ]
A. X Y , X Y B. X Y , X Y Z C. X YZ , X Y D. X YZ , X Y , XYZ
5. When grouping cells within a K-map, the cells must be combined in groups of____.[ ]
(A). 1,2,3,4,etc (B). 1,2,4,8, etc, (C). 1,3,5,7 (D). 1,10,20
6. The adjacent cells/squares of minterm 5 in a 4 – variable K-map is [ ]
(A). 1,4,7,13 (B). 0,1,3,2 (C). 8,9,10,11 (D). 12,13,4,7
UNIT-3
2 MARK QUESTIONS:
10 MARK QUESTIONS:
BITS
2 MARK QUESTIONS:
10 MARK QUESTIONS:
1. a) Design D Flip Flop by using SR Flip Flop and draw the timing diagram
b) Write the differences between combinational and sequential circuits
2. a) Draw the logic symbol, characteristics table and derive characteristics equation of JK flip
flop
b) Design T Flip Flop by using JK Flip Flop and draw the timing diagram
3. a) Draw the circuit of JK flip flop using NAND gates and explain its operation
b) Design a 2-input 2-output detector which produces an output 1 every time the sequence
0101 is detected. Implement the sequence detector using JK flip-flops.
4. a) Convert S-R flip flop into JK-flip flop. Draw and explain the logic diagram
b) A clocked sequential circuit with single input x and single output z produces an output
z=1 whenever the input x compares the sequence 1011 and overlapping is allowed.
Obtain the state diagram, state table and design the circuit with D flip-flops.
5. A sequential circuit with two D-flip flops A and B, two inputs ‘x’ and ‘y’ and one output ‘z’ is
specified by the following next state and output equation.
A(t+1) = x’y+xA, B(t+1) = x’B+xA and Z = B
(i) Draw the logic diagram of the circuit. (ii) List the state table and draw the corresponding
state diagram
6. Design and implement 3-bit ripple counter using J-K flip flop. Draw the state diagram, logic
diagram and timing diagram for the same.
7. What is a critical and non-critical race in asynchronous circuits? How to avoid races?
Illustrate with one example.
8. With a neat sketch explain MOD 6 Johnson counter using D FF. IES 2015
9. Implement 6-bit ring counter using suitable shift register. Briefly describe its
operation. National Exam May 2012
10. Design a binary counter having repeated binary sequence using JK flip flops :
0,1,2,4,5,6. IES 2016(CONVENTIONAL)
BITS
1. The output Y of a 2-bit comparator is logic 1 whenever the 2 bit input A is greater
than the 2 bit input B. The number of combinations for which the output is logic 1, is
A. 4 B. 6 C. 8 D. 10
GATE 2012 [ ]
2. A switch-tail ring counter is made by using a single D flip flop. The resulting circuit
is a GATE 1995 [ ]
A. SR flip flop B. JK flip flop C. D flip flop D. T flip flop
3. An SR latch is a GATE 1995 [ ]
A. Combinational circuit B. Synchronous sequential circuit
C. One bit memory element D. One clock delay element
4. The present output Qn of an edge triggered JK flip-flop is logic ‘0’. If j = 1, then Qn+1
is GATE 2005 [ ]
A. Cannot be determined B. Will be logic ‘0’
C. Will be logic ‘1’ D. Will race around
5. A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each
flip-flop is 50 nsec, the maximum clock frequency that can be used is equal to ____.
GATE 1990 [ ]
A. 20 MHz B. 10 MHz C. 5 MHz D. 4 MHz
6. Synchronous counters are ________ than the ripple counters. GATE1994 [ ]
A. Slower B. Faster C. Moderate D. None
7. A 4 bit ripple counter and a 4 bit synchronous counter are made using flip flops
having a propagation delay of 10 ns each. If the worst case delay in the ripple counter
and the synchronous counter be R and S respectively, then GATE 2003 [ ]
A. R = 10 ns, S = 40 ns B. R = 40 ns, S = 10 ns
C. R = 10 ns, S = 30 ns D. R = 30 ns, S = 10 ns
8. In sequential Circuits, the output variable depends on ______of the input variable. [ ]
A. Present State B. Past State C. Both D. None
9. The Serial adder is a _______Circuit. [ ]
A. Combinational B. Sequential C. Both D. None
10. The outputs of any sequential circuit are always ______to each other.
A. Complementary B. Independent C. Pearson D. None
11. In S-R latch, if S=R=1, the present state of the latch is. [ ]
A. 1 B. 0 C. Undetermined D. None
12. The D- latch sometimes called as _____ Latch. [ ]
A. Flipflop B. Buffer C. Transperant D. None
13. _____ and ______are building blocks of Sequential Circuits. [ ]
A. Flipflop B. Latches C. Both D. None
14. In ______Triggering, the output of Flipflop responds to the input changes only when
its enable input is Low. [ ]
A. Negative Level B. Positive Level C. Edge D. None
15. If S=0, R=1 and CP = 0 to which Qn = 0\1, the S-R Flipflop will be in __State. [ ]
A. No change B. 1 C. 0 D. Undetermined
16. The Basic building block of D- flipflop is ____Flipflop. [ ]
A. J-K B. Master-Slave C. S-R D. None
17. The output Qn+1 is delayed by one clock period for an D- Flipflop to which it is called
as ____Flipflop. [ ]
A. J-K B. Master-Slave C.S-R D. Delay
18. For the Inputs J=0, K=0, the output Q will be in ____state. [ ]
A. Reset B. Undertermined C.Nochange D. Delay
19. In JK flipflop, when J = K = 1, the output the Flipflop will be in ____state. [ ]
A. Reset B. Undertermined C. Toggling D. Delay
20. _____will not be an clock input of the Master-slave Flipflop. [ ]
A. Edge Triggered B. Level Triggered C. Both D. None
21. The ____ Flipflop is a modification of JK Flipflop. [ ]
A. J-K B. Master-Slave C.S-R D. T
22. If P = C = 0, the flipflop will be in _____ State. [ ]
A. Reset B. Uncertan C.Nochange D. Delay
23. For Moore Sequential Circuit, the output depends on ____ State. [ ]
A. Reset B. Present C. Previous D. Delay
24. The state reduction technique avoids ______states. [ ]
A. Reset B. Present C. Previous D. Redundant
25. The Input and Output of a register can be controlled by connecting ____. [ ]
A. Buffer B. Flipflop C. Tristate Buffers D. None
26. The _____ are used to transfer and storage of data in the registers. [ ]
A. Barrel Registers B. Shift Registers C. Tristate Buffers D. None
27. The acronym of SIPO is______. [ ]
A. Serial In Parallel Out B. Serial In Page Out
C.Series In Parallel Out D. None
28. The _____ register has capability of both shifts and parallel load. [ ]
A. Barrel Registers B. Universal Shift Registers C. Tristate Buffers D. None
29. The______ counters are simple in construction for more no. of states. [ ]
A. Synchronous B. Asynchronous C. Both D. None
30. The Major limitation of Ripple counter is_____. [ ]
A. Glitch Problem B. Asynchronous C. Both D. None
31. For n no. of Flipflops, the counter has ____no. of states. [ ]
A. n B. 2n C. 2n D. None
32. The twisted counter is also called as ______Counter. [ ]
A. Ring B. Johnson C. Road D. None
33. The _____ Counter requires only half the no. of Flipflops compared to Standard
counter. [ ]
A. Ring B. Johnson C. J-K D. None
34. For a counter of five-bit sequence, there are ____ states. [ ]
A. 10 B. 8 C. 4 D. 2
35. If all the Fliflops are triggered at the same time in an counter, then the counter is
referred to as ______ Counter. [ ]
A. Synchronous B. Asynchronous C. Both D. None
36. An eight stage ripple counter uses a flip-flop with propagation delay of 75
nanoseconds. The pulse width of the strobe is 50ns. The frequency of the input signal
which can be used for proper operation of the counter is approximately. [ ]
A. 1MHz B. 500 MHz C. 4 MHz D. 2 MHz
37. The output of a JK flipflop with asynchronous preset and clear inputs is ‘1’. The
output can be changed to ‘0’ with one of the following conditions [ ]
A. By applying J = 0, K = 0 and using a clock
B. By applying J = 1, K = 0 and using the clock
C. By applying J = 1, K = 1 and using the clock
D. By applying a synchronous preset input
38. Two D flip-flops are connected as a synchronous counter that goes through the
following QB QA sequence 00 -> 11 -> 01 -> 10 -> 00-> ………. The connections of
the inputs DA and DB are GATE 2011 [ ]
l l
A. DA= QB, DB= QA B. DA= QB , DB= QA
C.DA= QA QB + QAl,QBl, DB= QBl D.None
39. For the ring oscillator shown in teh figure, the propagation delay of each inverter is
100 pico sec. What is the fundamental frequency of the oscillator output?
GATE 2001 [ ]
2 MARK QUESTIONS:
10 MARK QUESTIONS:
BITS