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Case12d Observation

The document discusses observations from a scan insertion lab experiment. It provides a block diagram showing the inputs and outputs to the top design, including 4 scan chains connected to a single test clock. It notes there was initially an S1 violation that was resolved by using commands to insert the scan chains and set the test clock signal. The observations section details aspects of the scan-inserted netlist such as the number of scan flops, non-scan elements, chain lengths, and violations detected.

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125 views

Case12d Observation

The document discusses observations from a scan insertion lab experiment. It provides a block diagram showing the inputs and outputs to the top design, including 4 scan chains connected to a single test clock. It notes there was initially an S1 violation that was resolved by using commands to insert the scan chains and set the test clock signal. The observations section details aspects of the scan-inserted netlist such as the number of scan flops, non-scan elements, chain lengths, and violations detected.

Uploaded by

senthilkumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

SCAN INSERTION LAB OBSERVATIONS


Test Case 12d: -
Problem Definition: -
Design has 3 clocks (one +ve , one -ve, one using both edges)
d) use a single test clock and insert 4 scan chains
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def
Q. What is issue?
Ans: we have to insert 4 scan chain with single test clock and also 80, S1 violation is coming
Q. How issue resolved
Ans : by using this 2 command insert 4 scan chain with single test clock
We have to take one clock out of 3 clock
set_scan_signal -tclk ProcClk
Insert test logic -chain 4
S1 Violation is fixed by set test logic -on clock

Vlsiguru Confidential 1
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Observations: -

1) Write block diagram with all DFT inputs?

ProcClk

Test_en

Input Scan channel Output Scan channel


Top Design: Idma
Scan_en
Scan_chain Input1 sca
Scan_out1
Scan_chain Input2 Scan_out2
Scan_out3
Scan_chain input3
Sacn_out4
Scan_chain input4

2) How many clock domains? ProcClk


3) How many resets? Reset
4) Number of scan chains 4 scan chains
5) Clock mixing or not clock mixing? No clockmixing
6) How many Lockup-latches are added during scan insertion? 0
7) Is it top-down or bottom up approach? Top Down approach
8) How many terminal lockup latches are added? 0
9) Number of scan flops and non-scan flops in the design? 128 scanable flops and 2 non-
scan elements
10) Chain length? 2 (total 128 memory elements)
#chains: 1 , 7
#chain 2, 41
#chain 3,40
#chain 4,40

11)Number of DRC violations? C8,C9,D5,D7,S1

Vlsiguru Confidential 2
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

11) Write diagram with issue

Q.12) write solve issue

Q.13 Log file: - please note your observations from the log file
Top module is Idma
Number of shift registers =0
Number of INV inserted =0
Number of lockup latch =0
Number of MUX inserted =2
Number of terminal Lockup latch added =0
No of scan memory element =130
No of non scan memory element converted to scanable =128
Number of new Pins inserted= 10 ( 4 scan inputs,4 scan_output, test_en,scan_en )

Vlsiguru Confidential 3

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