Microcontrollers for Embedded Systems

3rd Year 2nd Semester

Open Elective

Dr. V. VIJAYARAGHAVAN, M.E., Ph.D.,

Assistant Professor - ECE, VFSTR, Guntur, AP.

 UNIT - IV
COMPANY
LOGO

ARM Cortex - M3 Processor

ARM Cortex-M3: ARM Cortex-M3 Processor

ARM Cortex-M3 Architecture

Instruction Set Development

The Thumb-2 Technology

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3 Basics
The Cortex-M3 addresses the requirements for the 32-bit embedded processor
market in the following ways:
 Greater performance efficiency: allowing more work to be done without increasing the
frequency or power requirements
 Low power consumption: enabling longer battery life, especially critical in portable
products including wireless networking applications
 Enhanced determinism: guaranteeing that critical tasks and interrupts are serviced as
quickly as possible and in a known number of cycles
 Improved code density: ensuring that code fits in even the smallest memory footprints
 Ease of use: providing easier programmability and debugging for the growing number
of 8-bit and 16-bit users migrating to 32 bits
 Lower cost solutions: reducing 32-bit-based system costs close to those of legacy 8-bit
and 16-bit devices and enabling low-end, 32-bit microcontrollers to be priced at less
than US$1 for the first time
 Wide choice of development tools: from low-cost or free compilers to full-featured
development suites from many development tool vendors

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

ARM Cortex-M3 Basics…..
ARM version 7 or v7 architecture design is divided into three profiles:
 A Profile (ARMv7-A): Application processors which are designed to handle
complex applications such as high-end embedded operating systems (OSs)
(e.g., Symbian, Linux, and Windows Embedded). These processors requiring the
highest processing power, virtual memory system support with memory
management units (MMUs), and, optionally, enhanced Java support and a secure
program execution environment. Example products include high-end mobile phones
and electronic wallets for financial transactions.
 R Profile (ARMv7-R): Real-time, high-performance processors targeted primarily at
the higher end of the real-time market—those applications, such as high-end
breaking systems and hard drive controllers, in which high processing power and
high reliability are essential and for which low latency is important.
 M Profile (ARMv7-M): Processors targeting low-cost applications in which
processing efficiency is important and cost, power consumption, low interrupt
latency, and ease of use are critical, as well as industrial control applications,
including real-time control systems.

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3
The Cortex-M3 is a low-power processor that features low gate count,
low interrupt latency, and low cost debug. It is intended for deeply
embedded applications that require optimal interrupt response features.

Features:
 A Nested Vectored Interrupt Controller (NVIC) closely integrated
with the processor core to achieve low latency interrupt processing.
 Multiple high-performance bus interfaces.
 A low-cost debug solution with the optional ability to:
o Implement breakpoints and code patches.
o Implement watchpoints, tracing, and system profiling.
o Support printf() style debugging.
o Bridge to a Trace Port Analyzer (TPA).
 An optional Memory Protection Unit (MPU).

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

ARM Cortex-M3…..
Key features of the Cortex-M3 core are:
 ARMv7-M architecture
 3-stage pipeline with branch speculation.
 Instruction sets:
o Thumb-1 (entire).
o Thumb-2 (entire).
o 32-bit hardware integer multiply with 32-bit or 64-bit result, signed or unsigned,
add or subtract after the multiply. (32-bit multiply is 1 cycle, but 64-bit multiply
and MAC instructions require extra cycles).
o 32-bit hardware integer divide (2–12 cycles).
o saturation arithmetic support.
 1 to 240 interrupts, plus NMI.
 12 cycle interrupt latency.
 Integrated sleep modes.
 Optional Memory Protection Unit (MPU): 0 or 8 regions.

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

ARM Cortex-M Series Comparision

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

ARM Cortex-M3 Block Diagram

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

ARM Cortex-M3 Architecture

Vijaya Raghavan.V, Asst. Prof - ECE, VFSTR

ARM Cortex-M3 Architecture…..
Fundamentals:
 The Cortex-M3 is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit
register bank, and 32-bit memory interfaces.
 The processor has a Harvard architecture, which means that it has a separate
instruction bus and data bus. This allows instructions and data accesses to take
place at the same time, and as a result of this, the performance of the processor
increases because data accesses do not affect the instruction pipeline. This
feature results in multiple bus interfaces on Cortex-M3, each with optimized
usage and the ability to be used simultaneously.
 For complex applications that require more memory system features, the
Cortex-M3 processor has an optional Memory Protection Unit (MPU), and it is
possible to use an external cache if it’s required.
 Both little endian and big endian memory systems are supported.
 The Cortex-M3 processor includes a number of fixed internal debugging
components. These components provide debugging operation supports and
features, such as breakpoints and watchpoints.
 In addition, optional components provide debugging features, such as
instruction trace, and various types of debugging interfaces.
V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur
ARM Cortex-M3 Architecture….. Registers
The Cortex-M3 processor has registers R0 through R15. R13 (the stack pointer)
is banked, with only one copy of the R13 visible at a time.
General-Purpose Registers: R0–R12
R0-R12 are 32-bit general-purpose registers for data operations. Some 16-bit
Thumb instructions can only access a subset of these registers (R0-R7).
Stack Pointers: R13
The Cortex-M3 contains two stack pointers (R13). They are banked so that
only one is visible at a time. The two stack pointers are as follows:
 Main Stack Pointer (MSP): The default stack pointer, used by the
operating system (OS) kernel and exception handlers
 Process Stack Pointer (PSP): Used by user application code
The lowest 2 bits of the stack pointers are always 0, which means they are
always word aligned.
The Link Register: R14
When a subroutine is called, the return address is stored in the link register.
The Program Counter: R15
The program counter is the current program address. This register can be written
to control the program flow.
V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur
ARM Cortex-M3 Architecture….. Registers

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

ARM Cortex-M3 Architecture….. Registers
Special Registers
The Cortex-M3 processor also has a number of special registers.
 Program Status registers (PSRs)
 Interrupt Mask registers (PRIMASK, FAULTMASK, and BASEPRI)
 Control register (CONTROL)
These registers have special functions and can be accessed only by special instructions.
They cannot be used for normal data processing.

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

ARM Cortex-M3 Architecture….. Registers

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. Operation Modes
The Cortex-M3 processor has two modes and two privilege levels. The operation
modes (thread mode and handler mode) determine whether the processor is
running a normal program or running an exception handler like an interrupt
handler or system exception handler. The privilege levels (privileged level and
user level) provide a mechanism for safeguarding memory accesses to critical
regions as well as providing a basic security model.
When the processor is running a main program (thread mode), it can be either in a
privileged state or a user state, but exception handlers can only be in a privileged
state. When the processor exits reset, it is in thread mode, with privileged access
rights. In the privileged state, a program has access to all memory ranges (except
when prohibited by MPU settings) and can use all supported instructions.

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. Operation Modes…
Software in the privileged access level can switch the program into the user access level
using the control register. When an exception takes place, the processor will always switch
back to the privileged state and return to the previous state when exiting the exception
handler. A user program cannot change back to the privileged state by writing to the control
register. It has to go through an exception handler that programs the control register to
switch the processor back into the privileged access level when returning to thread mode.
The separation of privilege and user levels improves system reliability by preventing
system configuration registers from being accessed or changed by some untrusted
programs. If an MPU is available, it can be used in conjunction with privilege levels to
protect critical memory locations, such as programs and data for OSs.

For example, with privileged accesses,

usually used by the OS kernel, all
memory locations can be accessed
(unless prohibited by MPU setup).
When the OS launches a user
application, it is likely to be executed
in the user access level to protect the
system from failing due to a crash of
untrusted user programs.

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

ARM Cortex-M3….. Memory Map

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. Bus Interface
There are several bus interfaces on the Cortex-M3 processor. They allow the
Cortex-M3 to carry instruction fetches and data accesses at the same time.
The main bus interfaces are as follows:
 Code memory buses
 System bus
 Private peripheral bus
The code memory region access is carried out on the code memory buses,
which physically consist of two buses, one called I-Code and other called
D-Code.
 ICode bus: This is for instruction and vector fetches from code space.
 DCode bus: This is for data load/stores and debug accesses to code space.
The system bus is used to access memory and peripherals. This provides access
to the Static Random Access Memory (SRAM), peripherals, external RAM,
external devices, and part of the system level memory regions.
The private peripheral bus provides access to a part of the system-level memory
dedicated to private peripherals, such as debugging components.

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. NVIC
The Cortex-M3 processor includes an interrupt controller called the Nested
Vectored Interrupt Controller (NVIC). It is closely coupled to the processor core
and provides a number of features as follows:
 Nested interrupt support
 Vectored interrupt support
 Dynamic priority changes support
 Reduction of interrupt latency
 Interrupt masking

Nested Interrupt Support

The NVIC provides nested interrupt support. All the external interrupts and
most of the system exceptions can be programmed to different priority levels.
When an interrupt occurs, the NVIC compares the priority of this interrupt to
the current running priority level. If the priority of the new interrupt is higher
than the current level, the interrupt handler of the new interrupt will override the
current running task.

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. NVIC
Vectored Interrupt Support
The Cortex-M3 processor has vectored interrupt support. When an interrupt is accepted,
the starting address of the interrupt service routine (ISR) is located from a vector table in
memory. There is no need to use software to determine and branch to the starting address
of the ISR. Thus, it takes less time to process the interrupt request.
Dynamic Priority Changes Support
Priority levels of interrupts can be changed by software during run time. Interrupts that
are being serviced are blocked from further activation until the ISR is completed, so their
priority can be changed without risk of accidental reentry.
Reduction of Interrupt Latency
The Cortex-M3 processor also includes a number of advanced features to lower the
interrupt latency. These include automatic saving and restoring some register contents,
reducing delay in switching from one ISR to another, and handling of late arrival
interrupts.
Interrupt Masking
Interrupts and system exceptions can be masked based on their priority level or masked
completely using the interrupt masking registers BASEPRI, PRIMASK, and
FAULTMASK. They can be used to ensure that time-critical tasks can be finished on
time without being interrupted.

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. Interrupts and Exceptions
It has a number of system exceptions plus a number of external Interrupt Request (IRQs).
There is no fast interrupt (FIQ) in the Cortex-M3; however, interrupt priority handling
and nested interrupt support are now included in the interrupt architecture.

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. IPR Register

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. Debugging Support
The Cortex-M3 processor includes a number of debugging features, such as
program execution controls, including halting and stepping, instruction
breakpoints, data watchpoints, registers and memory accesses, profiling, and
traces.
The debugging hardware of the Cortex-M3 processor is based on the CoreSight
architecture. Unlike traditional ARM processors, the CPU core itself does not
have a Joint Test Action Group (JTAG) interface. Instead, a debug interface
module is decoupled from the core, and a bus interface called the Debug Access
Port (DAP) is provided at the core level. Through this bus interface, external
debuggers can access control registers to debug hardware as well as system
memory, even when the processor is running.
The control of this bus interface is carried out by a Debug Port (DP) device. The
DPs currently available are the Serial-Wire JTAG Debug Port (SWJ-DP) or the
SW-DP (supports the Serial-Wire protocol only). A JTAG-DP module from the
ARM CoreSight product family can also be used. Chip manufacturers can
choose to attach one of these DP modules to provide the debug interface.

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. Debugging Support
Chip manufacturers can also include an Embedded Trace Macrocell (ETM) to allow instruction
trace. Trace information is output via the Trace Port Interface Unit (TPIU), and the debug host
[PC] can then collect the executed instruction information via external tracecapturing hardware.
Within the Cortex-M3 processor, a number of events can be used to trigger debug actions.
Debug events can be breakpoints, watchpoints, fault conditions, or external debugging
request input signals. When a debug event takes place, the Cortex-M3 processor can either
enter halt mode or execute the debug monitor exception handler.
The data watchpoint function is provided by a Data Watchpoint and Trace (DWT) unit in the
Cortex-M3 processor. This can be used to stop the processor (or trigger the debug monitor
exception routine) or to generate data trace information. When data trace is used, the traced data
can be output via the TPIU.
In addition to these basic debugging features, the Cortex-M3 processor also provides a
Flash Patch and Breakpoint (FPB) unit that can provide a simple breakpoint function or remap
an instruction access from Flash to a different location in SRAM.
An Instrumentation Trace Macrocell (ITM) provides a new way for developers to output data to
a debugger. By writing data to register memory in the ITM, a debugger can collect the data via a
trace interface and display or process them. This method is easy to use and faster than JTAG
output.
All these debugging components are controlled via the DAP interface bus on the Cortex-M3 or
by a program running on the processor core, and all trace information is accessible from the
TPIU.
V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur
ARM Cortex-M3….. Thumb-2 Instruction Set
With the introduction of the Thumb-2 instruction set, it is now
possible to handle all processing requirements in one operation
state. Even interrupts are now handled with the Thumb state.
Since there is no need to switch between states, the Cortex-M3
processor has a number of advantages over traditional ARM
processors, such as:
 No state switching overhead, saving both execution time and instruction
space
 No need to separate ARM code and Thumb code source files, making
software development and maintenance easier
 It’s easier to get the best efficiency and performance, in turn making it
easier to write software, because there is no need to worry about switching
code between ARM and Thumb to try to get the best density/performance

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

ARM Cortex-M3….. Instruction Set

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

ARM Cortex-M3….. Instruction Set

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. Instruction Set

Memory
Access
Instructions

Offset,
Pre-Index,
and
Post-Index

IA, IB,
DA, DB
!

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. Instruction Set

General
Data
Processing
Instructions

If S is
specified,
these
instructions
update the
N, Z, C & V
flags
according to
the result.
V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur
 ARM Cortex-M3….. Instruction Set
Multiply and Divide Instructions

Saturating Instructions

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 ARM Cortex-M3….. Instruction Set
Bitfield Instructions

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 ARM Cortex-M3….. Instruction Set
Branch and Control Instructions

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. Instruction Set
Miscellaneous Instructions

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. Instruction Set
The Cortex-M3 processor has a number of interesting and powerful
instructions. Here are a few examples:
• UFBX, BFI, and BFC: Bit field extract, insert, and clear instructions
• UDIV and SDIV: Unsigned and signed divide instructions
• WFE, WFI, and SEV: Wait-For-Event, Wait-For-Interrupts, and Send-Event;
these allow the processor to enter sleep mode and to handle task
synchronization on multiprocessor systems
• MSR and MRS: Move to special register from general-purpose register and
move special register to general-purpose register; for access to the special
registers
Coprocessor instructions are not supported on the Cortex-M3 (external data
processing engines can be added), and Single Instruction–Multiple Data
(SIMD) is not implemented on the Cortex-M3. In addition, a few Thumb
instructions are not supported, such as Branch with Link and Exchange (BLX)
with immediate (used to switch processor state from Thumb to ARM), a couple
of change process state (CPS) instructions, and the SETEND (Set Endian)
instructions, which were introduced in architecture v6.
V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur
ARM Cortex-M3….. saturating arithmetic
For example, if the valid range of values is from −100 to 100, the following
saturating arithmetic operations produce the following values:

 60 + 30 → 90.
 60 + 43 → 100. (not the expected 103.)
 (60 + 43) − (75 + 75) → 0. (not the expected −47.) (100 − 100 → 0.)
 10 × 11 → 100. (not the expected 110.)
 99 × 99 → 100. (not the expected 9801.)
 30 × (5 − 1) → 100. (not the expected 120.) (30 × 4 → 100.)
 (30 × 5) − (30 × 1) → 70. (not the expected 120. not the previous 100.) (100
− 30 → 70.)

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. 16-bit Thumb
Some of the changes used to reduce the length of the
instructions from 32 bits to 16 bits:
 reduce the number of bits used to identify the register
o less number of registers can be used
 reduce the number of bits used for the immediate value
o smaller number range
 remove options such as ‘S’
o make it default for some instructions
 remove conditional fields (N, Z, V, C)
 no conditional executions (except branch)
 remove the optional shift (and no barrel shifter operation
o introduce dedicated shift instructions
 remove some of the instructions
o more restricted coding

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. 16-bit Instruction Set
ASSEMBLER OPERATION

LDR <Rd>, [<Rn>, <Rm>] Load memory word from base register address + register offset

LDRB <Rd>, [<Rn>, <Rm>] Load memory byte [7:0] from register address + register offset

LDRH <Rd>, [<Rn>, <Rm>] Load halfword [15:0] from register address + register offset

LDRSB <Rd>, [<Rn>, <Rm>] Load signed byte [7:0] from register address + register offset

LDRSH <Rd>, [<Rn>, <Rm>] Load signed halfword [15:0] from register address + register offset

STR <Rd>, [<Rn>, <Rm>] Store register word to register address

STRB <Rd>, [<Rn>, <Rm>] Store register byte [7:0] to register address

STRH <Rd>, [<Rn>, <Rm>] Store register halfword [15:0] to register address + register offset

LDMIA <Rn>!, <registers> Multiple sequential memory word loads

STMIA <Rn>!, <registers> Store multiple register words to sequential memory locations

PUSH <registers> Push registers onto stack

POP <registers> Pop registers from stack

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. 16-bit Instruction Set
ASSEMBLER OPERATION

ADD <Rd>, <Rm> Add register value to register value

ADD <Rd>, #<immed_8> Add immediate 8-bit value to register

ADC <Rd>, <Rm> Add register value and C flag to register value

ADD <Rd>, PC, #<im_8> * 4 Add 4* (immediate 8-bit value) with PC to register

ADD <Rd>, SP, #<im_8> * 4 Add 4* (immediate 8-bit value) with SP to register

SUB <Rd>, <Rn>, <Rm> Subtract register values

SUB <Rd>, #<immed_8> Subtract immediate 8-bit value from register value

SBC <Rd>, <Rm> Subtract register value and C flag from register value

MUL <Rd>, <Rm> Multiply register values

MOV <Rd>, #<immed_8> Move immediate 8-bit value to register

MOV <Rd>, <Rm> Move high or low register value to high or low register

MVN <Rd>, <Rm> Move complement of register value to register

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 ARM Cortex-M3….. 16-bit Instruction Set
ASSEMBLER OPERATION
AND <Rd>, <Rm> Bitwise AND register values
ORR <Rd>, <Rm> Bitwise logical OR register values
EOR <Rd>, <Rm> Bitwise exclusive OR register values
NEG <Rd>, <Rm> Negate register value and store in register
CMP <Rn>, <Rm> Compare registers
CMP <Rn>, #<immed_8> Compare immediate 8-bit value
CMN <Rn>, <Rm> Compare negation of reg. value with another reg. value
REV <Rd>, <Rn> Reverse bytes in word and copy to register
BIC <Rd>, <Rm> Bit clear
ASR <Rd>, <Rs> Arithmetic shift right by number in register
ASR <Rd>, <Rm>, #<im_5> Arithmetic shift right by immediate number
LSL <Rd>, <Rs> Logical shift left by number in register
LSL <Rd>, <Rm>, #<im_5> Logical shift left by immediate number
LSR <Rd>, <Rs> Logical shift right by number in register
LSR <Rd>, <Rm>, #<im_5> Logical shift right by immediate number
ROR <Rd>, <Rs> Rotate right by amount in register
V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur
 ARM Cortex-M3….. 16-bit Instruction Set
ASSEMBLER OPERATION
B <target_address> Branch unconditional
B<cond> <target address> Branch conditional
BL <Rm> Branch with link
BLX <Rm> Branch with link and exchange
BKPT <immed_8> Software breakpoint
CBZ <Rn>,<label> Compare zero and branch
CBNZ <Rn>,<label> Compare not zero and branch
CPS <effect>, <iflags> Change processor state
CPY <Rd> <Rm> Copy high or low register value to another high or low register
IT <cond> Condition the following instruction,
IT<x> <cond> Condition the following two instructions,
IT<x><y> <cond> Condition the following three instructions,
IT<x><y><z> <cond> Condition the following four instructions
SEV <c> Send event
WFE <c> Wait for event
WFI <c> Wait for interrupt
V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur
 REFERENCE BOOKS
COMPANY
LOGO

 Raj Kamal, Microcontroller, Programming and Design. 2nd Edition,

Pearson, 2012.
 K.V.K.K. Prasad, “Embedded Real-Time Systems: Concepts, Design & Programming”,
Dream Tech Press, 2005.

 Marilyn Wolf, “Computers as Components - Principles of Embedded Computing System

Design”, Third Edition “Morgan Kaufmann Publisher (An imprint from Elsevier), 2012.

 Arnold S. Berger, An introduction to Processes, Tools and Techniques, CMP books, 2005.

 Wang K.C., Embedded and Real-Time Operating Systems, Springer, 2017.

 Frank Vahid and Tony Givargis, Embedded System Design: A Unified Hardware/Software
Introduction, John Wiley & Sons, Student edition, 2006.

V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur

 COMPANY
Microcontrollers for Embedded Systems LOGO

Dr. V.Vijayaraghavan, Assistant Professor-ECE, VFSTR, Guntur