High-Bandwidth Memory White Paper

Start Your HBM/2.5D Design Today

Kevin Tran Executive Summary Avery Design Systems have joined forces
to offer a complete HBM supply chain
High-bandwidth memory (HBM) is a
SK hynix Inc. JEDEC-defined standard, dynamic random
solution that is delivering and supporting
customer HBM designs now.
access memory (DRAM) technology
Paul Silvestri that uses through-silicon vias (TSVs) to In this open supply chain collaboration,
interconnect stacked DRAM die. In its first SK hynix provides the HBM stack.
Amkor Technology, Inc. implementation, it is being integrated with a eSilicon is the application-specific
system-on-chip (SoC) logic die using 2.5D integrated circuit (ASIC) vendor for
silicon interposer technology. the SoC, providing the HBM physical
Bill Isaacson interfaces (PHYs) and associated
In June 2015, AMD introduced its Fiji
services, and is also the overall HBM
eSilicon Corporation processor, the first HBM 2.5D design,
module integrator. Northwest Logic
which comprises a graphics processor
provides the HBM controller intellectual
unit (GPU) connected with four HBM
property (IP) for the SoC. Avery Design
Brian Daellenbach stacks using a silicon-based interconnect.
Systems provides the HBM verification
The Fiji processor is powering AMD’s
Northwest Logic latest generation of Radeon Fury graphics
IP. Amkor integrates the SoC, HBM stack
and interposer into a 2.5D assembly,
cards for high-performance gaming.
and tests, packages and ships it to the
This event was the turning point for
Chris Browy HBM, opening the floodgates for system
customer (Figure 1).

Avery Design Systems integrators to adopt HBM as a memory The five companies recently sponsored
solution for high-bandwidth, low-power a seminar to promote their efforts and
products. In addition to graphics, HBM explain how this supply chain works.
is being used in high-performance Attendee feedback was very positive and
computing (HPC), data center and included the following comments:
networking applications.
• Bringing key players for interposer-
SK hynix Inc., Amkor Technology, Inc., based designs into one room was
eSilicon Corporation, Northwest Logic and strategic and helpful.

Figure 1: HBM Supply Chain

High-Bandwidth Memory White Paper Start Your HBM/2.5D Design Today

• It was very informative. I had a lot of questions answered. bottlenecks. TSVs run interconnects through the die, making
• It was a good assembly of design and manufacturing elements. it possible to stack a higher number of die without needing to
• I learned a lot that I didn’t know. run wire bonds from pads to the package, thereby reducing the
• It’s good to hear that TSVs are ready for HBM. overall package size of the DRAM device.

This white paper explains HBM’s value proposition, and how these HBM overcomes all DRAM bandwidth challenges. Low speed-
five companies make it easy for system and integrated circuit (IC) per-pin and input/output capacitance (Cio) reduce power
designers to access the many benefits this technology offers. consumption and increase efficiency. Usually, power and
bandwidth go hand in hand. However, because HBM is designed
Introduction as an in-package memory that sits next to the processor or ASIC
(SoC) on top of an organic or silicon interposer, driver size and
HBM is a JEDEC-defined standard DRAM stack. It is integrated capacitance is minimized. Bandwidth is now a product of I/O
with an SoC using a fine-pitch interposer. The first HBM-based speed. In fact, HBM provides the highest bandwidth per unit area
product went into production in early 2015. Many companies are when compared with other DRAM memories.
already using HBM to create very-high-bandwidth, low-power
products (Figure 2). To provide 1 Tb/second of memory bandwidth using conventional
DRAM such as DDR4 requires a tremendous amount of space on
Figure 2: HBM Module Construction the printed circuit board (PCB): 160 DDR4 components take up
15,600mm2 of the PCB, versus 4 HBM2 components, which take
up 384mm2 (Figure 3).

Figure 3: HBM Provides Highest Bandwidth Compared with

Other DRAM Memories per Unit Area

HBM was developed by JEDEC and its member companies

to meet the needs of applications in which memory bandwidth
needs exceed the capabilities of traditional memory approaches
like DDR4 and GDDR5. A single HBM stack provides bandwidth
equivalent to 16 DDR 4/3 DIMMs. Multiple HBM stacks can be
connected with a single SoC in an HBM 2.5D package design.

HBM has emerged as the leader in customer adoption over Further, from a raw bandwidth perspective, the 2 Tb/second of
competing technologies due to its low-power capabilities, JEDEC bandwidth that a single HBM provides would require 40 DDR
standardization and availability from multiple sources. SK hynix is PHYs on the ASIC. This takes up 300mm2 of ASIC real estate
the first memory manufacturer to ramp HBM to production. compared with 12mm2 needed to accommodate a single HBM.

In response to this market demand, SK hynix, eSilicon, Northwest To ensure quality and reliability, a programmable built-in self-test
Logic, Avery Design Systems and Amkor Technology have put (BIST) engine to test, detect and correct failures was added.
together an end-to-end supply chain for HBM/2.5D designs. System architects appreciate the ability to do post-package repair
according to the IEEE 1500 standard.
SK hynix The HBM supply chain is ready to support designs. Seven test
SK hynix began to develop HBM technology in 2011 when it vehicles have been taped out. Two production designs being
became clear that memory density and bandwidth scaling would developed by eSilicon for HPC and networking, one at 28nm and
be critical for next-generation architectures. Graphics, HPC, one at 14nm, expect to ramp to volume in 2016. Many additional
networking and data center applications were experiencing a customer designs are underway.
memory bottleneck due to a performance discrepancy between Going forward, SK hynix plans to redesign HBM to accommodate
CMOS logic and DRAM. vertical stacking. The company is also exploring a low-power
TSV technology is the enabling interconnect technology used ARM-based SoC that could theoretically support an HBM stacked
in HBM that allows DRAM memory to overcome existing on top for mobile applications.

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High-Bandwidth Memory White Paper Start Your HBM/2.5D Design Today

eSilicon Northwest Logic

eSilicon has been specializing in 2.5D interposer designs since Northwest Logic provides a high-performance, highly
2011 with its modular Z-axis integrated circuit (MoZAIC™) program. configurable HBM controller core. As shown in Figure 5, this core
The MoZAIC program focuses on enabling the IP, design capability, consists of a base HBM controller plus a variety of add-on cores.
packaging/test methodologies and supply chain needed to ensure
the lowest-risk, highest-performance device development. The base HBM controller uses all of the available HBM features
including pseudo channels, look-ahead activates/pre-charges,
Seeing the need for an ecosystem to support HBM integration, single-bank refreshes, etc., to ensure that the maximum possible
SK hynix first came to eSilicon as an ASIC vendor. eSilicon bandwidth can be achieved in a targeted user application. The
then invited Northwest Logic, Avery Design Systems and Amkor HBM controller can be configured in a variety of ways, including
Technology to become part of this dedicated supply chain, a single/dual user interface, half/full-rate operation, etc. This
because each brought a different element to the table, without enables the user to select the configuration that best meets their
any conflicts or overlap. design needs.

eSilicon developed its first 2.5D device using first-generation The base HBM controller can be optionally used with a variety
HBM in 2012. Since then, eSilicon has been actively developing of add-on cores. These add-on cores extend the functionality of
and offering organic and silicon interposers and other IP and the controller to support multiple ports, transaction reordering to
technologies needed in this space. This includes HBM PHYs as maximize bandwidth, ECC and advanced test capabilities. Only
well as delay-locked loops (DLLs) and I/O libraries, catering to the add-on cores needed by the customer are included in the
a wide variety of customers and market segments from 28nm to delivery, minimizing the size and complexity of the controller.
14nm/16nm (Figure 4).
The advanced test capabilities allow the HBM controller to
As the ASIC vendor and system integrator, eSilicon works with perform a complete set of write-then-read transactions to the
major computing and network vendors to support ASIC design HBM stack with predefined, user-defined and random data and
by determining what parts work well together to achieve desired address patterns. This enables comprehensive bring-up and
functionality. eSilicon also designs the interposer and package to production system testing to be performed and easily analyzed.
deliver a turnkey solution.
Northwest Logic delivers the HBM controller fully integrated
and verified with the eSilicon HBM PHY. This includes eight

Figure 4: eSilicon HBM2 PHY IP

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High-Bandwidth Memory White Paper Start Your HBM/2.5D Design Today

Figure 5: Northwest Logic Configurable HBM Controller Core

Tuning a system involves the memory
controller, system interconnect,
custom engines, software on
embedded processor and a memory
interface that describes how fast
information is sent into and out of the
memory. It is important to make sure
the algorithm runs quickly, has the
lowest latency possible and accesses
the memory system correctly.

Avery’s HBM verification IP solutions

support HBM2 and spec revisions
from JEDEC and IEEE 1500 test
ports. The company supports a
instantiations of the HBM controller (one for each HBM behavioral BFM PHY monitor and matches the PHY interfaces
channel). Northwest Logic uses its full-featured verification to ensure it adheres to PHY standards. An optional memory
environment, which includes interface test benches and HBM controller BFM and compliance test suite generate traffic
models from Avery Design Systems and the memory vendors to scenarios to further verify the PHY. The HBM memory model
comprehensively verify each customer delivery over a full range BFM supports all test bench configurations, configurable number
of HBM memory configurations and traffic patterns. of channels, density, banks and operating speeds, and the IEEE
1500 port commands. Additionally, as debugging is important for
As of March 2016, the HBM controller is being used in seven analyzing designs, the HBM model generates protocol analyzer
customer designs and multiple test chips. These designs include logs; performs protocol and timing checks, function coverage,
HPC, design center and networking applications that have a wide and performance analysis including: DQ usage, bandwidth, bank
range of feature requirements and traffic scenarios. These real-world analysis, and command latencies to identify memory subsystem
uses have enabled Northwest Logic to optimize the HBM controller and SoC interconnect performance issues and inefficient memory
so that it achieves the highest application bandwidth possible, and page allocation.
supports the broadest range of customer applications.
Once the system architect decides to select HBM versus other
Avery Design Systems memory alternatives such as DDR4 and Hybrid Memory Cube
(HMC), the register transfer logic (RTL) design and verification
Avery Design Systems develops and delivers verification IP phase begin yielding a complete RTL model of the chip
(VIP) solutions including models, protocol checking, compliance comprising embedded processors, custom functions, engines,
test suites and support services. VIP is a behavioral model that system interconnect, a network on a chip, etc.
implements standard protocol and allows system designers to
simulate a device without having to build prototypes. In the case of an HBM 2.5D design, the RTL designer can rely
on Northwest Logic to provide a synthesizable RTL memory
For example, when designing a high-end system router that uses controller IP; eSilicon provides PHY design including a behavioral
memory to store data packets and run various routing, filtering model of the PHY; and Avery Design Systems provides the HBM
and encryption algorithms, Avery Design Systems’ memory memory model. SoC RTL verification then targets generating
model VIP helps verify that the memory subsystem is functioning system memory traffic through the simulated system to make
correctly and efficiently. Designers run a chip-level simulation sure the algorithm is functioning correctly and providing the right
while connected to the memory model, and can test traffic result with good performance. The HBM model is programmed
through the router chip to see how it operates to the memory chip to inject various errors to make sure the system can log it and
module standards. perform error recovery.
As part of this open supply chain, Avery provides HBM models The implementation and verification teams work in parallel paths.
that enable HBM-based SoC and PHY designs to be robustly Once the verification team is through with its simulations, a gate-
verified and performance-optimized quickly and effectively. level netlist is created. eSilicon then implements the netlist into a
While memory suppliers provide models for free, they offer chip layout and works with the fab to implement place and route,
minimal capabilities. Avery Design Systems offers a more complete testability, and final sign-off and tapeout.
solution that includes robust and flexible bus functional models When the design, simulation and chip fabrication steps are
(BFMs), protocol checking and analyzer trace logs, functional complete, Amkor Technology performs the 2.5D device assembly,
coverage, performance analysis, SoC/IP compliance test suites, an test, packaging and shipment.
intelligent scoreboard, integration with a native system Verilog test
bench, and much more, including full customer service and support.

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High-Bandwidth Memory White Paper Start Your HBM/2.5D Design Today

Amkor Technology SK hynix HBM is qualified with Amkor’s assembly process for
2.5D integration. Lastly, all the major foundries are qualified for
Amkor Technology is an outsourced semiconductor assembly
logic devices using Amkor’s fine-pitch copper pillar bumping.
and test service provider and the leader in advanced system-in-
package (SiP) technology. Amkor has been developing 2.5D and Amkor supports multiple assembly flows to provide flexibility in
3D integration technologies since 2006, resulting in a fully qualified HBM/2.5D designs. These include 2.5D chip-on-substrate (CoS)
production line, middle-end-of-line (MEOL) and assembly for 2.5D assembly, 3D CoS assembly and 2.5D/3D chip-on-wafer (CoW)
and 3D technology. The MEOL process flow includes interposer assembly. Flexible assembly options allow customers to make
bumping on the front side, TSV reveal on the back side, followed by critical architecture decisions that best support their product
redistribution layer, micro-bumping and assembly of the ASIC and requirements, including interim interposer test of interposer and
HBM stack on the interposer. It also performs interim and final test ASIC before committing HBM devices to the assembly flow. 2.5D
as directed by the customer. The MEOL and assembly production and 3D CoS assemblies are production-ready.
lines at Amkor are fully qualified and ramping new HBM/2.5D
products to meet customer forecasts. The CoS approach involves assembling each component one
by one, which allows the logic and interposer to undergo interim
All of the bill of materials content for the HBM/2.5D designs tests before the memory is attached, so yield is assured before
are consigned to Amkor by eSilicon, including: the foundry- committing the memory to the stack. Back-side process steps
manufactured TSV interposer; the memory cube from SK hynix; for the interposer and logic die can take place concurrently, as
and the 300mm ASIC wafer from the foundry. One benefit of both components are processed through parallel production lines
working in partnership with eSilicon and SK hynix is that all before being staged for assembly. After the interposer is attached
parts are qualified as compatible with Amkor processes. Amkor to the substrate, the logic die is attached to the interposer and
performs interposer MEOL, as well as fine-pitch copper pillar prepared for an optional interim test step. Both functional test
bumping of the ASIC wafer to better control compatibility with (FT) and system-level test (SLT) are supported. Next, HBM is
downstream assembly processes. attached to the rest of the subassembly and then final assembly
is completed. Final FT and SLT are performed, and the parts are
Interposers are fabricated at various foundry suppliers, typically
packaged and shipped to the customer (Figure 6).
based on 60nm back-end-of-line technology and via-middle TSV
integration. TSV formation from different suppliers has converged 2.5D CoS is active with many customers. It targets GPU, HPC,
on similar via manufacturing, resulting in consistent TSV quality, networking and server applications. 3D CoS and 2.5D/3D CoW
allowing Amkor to use a single MEOL process flow for multiple are being deployed for memory customers.
TSV suppliers. This promotes low cycle time and reduced cost with
consistent reliability. Amkor continues to partner with foundries to Amkor’s production line will allow more customer penetration into
facilitate new sources and extend cost-reduction initiatives. HBM/2.5D products, which in turn reduces costs and improves

Figure 6. 2.5D Process Flow (click here for a larger view in your browser)

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High-Bandwidth Memory White Paper Start Your HBM/2.5D Design Today

efficiencies. Applications include GPU, networking/communication, eSilicon’s HBM PHY, Northwest Logic’s HBM Controller and
memory systems, and server and HPC platforms. Avery Design Systems’ HBM VIP models are all fully verified.
Additionally, SK hynix’s HBM stack is fully qualified, as are two
Summary and Conclusion interposer suppliers. Amkor’s TSV MEOL line is mature and in
production, with >98% yields and CPKs of over 1.3. Several test
HBM provides memory bandwidth far beyond what is available vehicles have been taped out. Additionally, two HBM production
with traditional memory devices, such as DDR4 and GDDR5, at designs for HPC and networking, one at 28nm and one at 14nm,
attractive power and cost. expect to ramp to volume this year.
The introduction of AMD’s HBM-based Fiji product not only Clearly, the time has come for HBM 2.5D designs, and the
proves the manufacturability of HBM 2.5D designs, but the players are in place to help your company compete in this
marketability of such a product. competitive landscape. Start your HBM 2.5D design today.
In this paper, five leading-edge companies have demonstrated
the capabilities of an open-collaboration HBM/2.5D supply chain
that is fully ready to take on designs for high-volume production.

Amkor Technology, Inc. © 2016 Amkor Technology, Inc., Avery Design Systems, eSilicon
www.amkor.com Corporation, Northwest Logic and SK hynix Inc. All rights reserved. This
publication is protected by copyright and international treaty. No part of
Avery Design Systems this publication may be reproduced in any form by any means without
www.avery-design.com prior written authorization from Amkor, Avery Design Systems, eSilicon
Corporation, Northwest Logic and SK hynix. eSilicon is a registered
eSilicon Corporation
trademark, and MoZAIC and the eSilicon logo are trademarks, of eSilicon
www.esilicon.com
Corporation. All other trademarks mentioned herein are the property of
Northwest Logic their respective owners. 20160329.PDF.
www.nwlogic.com

SK hynix Inc.
www.skhynix.com