Experiment-1

COMBINATIONAL CIRCUITS
AIM: To simulate and synthesize combinational circuits using Verilog HDL.

APPARATUS: Xilinx ISE Design suit 14.7 tool.

THEORY:

Half adder: half adder is a combinational circuit, which performs the addition of two binary numbers A
and B are of single bit. It produces two outputs sum, S & carry, C.

Full Adder: Full adder is a combinational circuit, which performs the addition of three bits A, B and Cin.
Where, A & B are the two parallel significant bits and Cin is the carry bit, which is generated from
previous stage. This Full adder also produces two outputs sum, S & carry, Cout,which are similar to Half
adder.

Multiplexer : Multiplexer is a device that has multiple inputs and a single line output. The select lines
determine which input is connected to the output, and also to increase the amount of data that can be
sent over a network within certain time. It is also called a data selector

Demultiplexer: De-multiplexer is also a device with one input and multiple output lines. It is used to
send a signal to one of the many devices. The main difference between a multiplexer and a de-
multiplexer is that a multiplexer takes two or more signals and encodes them on a wire, whereas a de-
multiplexer does reverse to what the multiplexer does.

TRUTH TABLES:

HALF ADDER FULL ADDER

HALF ADDER:

VERILOG CODE AND TEST BENCH:

CODE TEST BENCH

module ha_329(a,b,s_329,c_329); module tb_ha_329;

output s_329,c_329; reg a;reg b;

input a,b; wire s_329;wire c_329;

assign s_329=a^b; ha_329 uut

(.a(a),.b(b),.s_329(s_329),.c_329(c_329));
assign c_329=a&b;
initial begin
endmodule
$monitor($time,"input a=%b,b=%b,output
s_329=%b,c_329=%b",a,b,s_329,c_329)

Initialize Inputs

a = 0;b = 0;

#10 a=0;b=1;

#10 a=1;b=0;

#10 a=1;b=1;

end

endmodule

SIMULATION&CONSOLE WINDOW:
RTL SCHEMATIC:

FULL ADDER:

VERILOG CODE AND TEST BENCH:

CODE TEST BENCH

module fa_329(s_329,c_329,a,b,c); module tb_fa_329;
output s_329,c_329; reg a; reg b; reg c; wire s_329; wire c_329;
input a,b,c; fa_329 uut (.s_329(s_329), .c_329(c_329), .a(a),
.b(b), .c(c));
assign s_329=a^b^c;
initial begin
assign c_329=a&b|b&c|a&c;
$monitor($time,"input=a=%b,b=%b,c=%b,output
endmodule
s_329=%b,c_329=%b",a,b,c,s_329,c_329);
a=0;b=0;c=0;
#10 a=0;b=0;c=1;
#10 a=0;b=1;c=0;
#10 a=0;b=1;c=1;
#10 a=1;b=0;c=0;
#10 a=1;b=0;c=1;
#10 a=1;b=1;c=0;
#10 a=1;b=1;c=1;
end
endmodule

SIMULATIONA & CONSOLE WINDOW:

RTL Schematic:
FULL ADDER USING HALF ADDER

VERILOG CODE AND TEST FIXTURE:

TESTBENCH
module fa_329usha_329(s_329,c_329,a,b,c); module tb_fa_329usha_329;
Output s_329,c_329; reg a; reg b; reg c;
input a,b,c; wire s_329;wire c_329;
wire s1,c1,c2; fa_329usha_329uut(.s_329(s_329),.c_329(c_329),.a(a),.b(b),.c
(c));
ha_329a1(a,b,s1,c1);
initial begin
ha_329a2(s1,c,s_329,c2);
$monitor($time,"input:a=%b,b=%b,c=%b,output:s_329=%b,c_
ora3(c_329,c1,c2);
329=%b",a,b,c,s_329,c_329);
endmodule
a=0;b=0;c=0;
#10a=0;b=0;c=1;
#10a=0;b=1;c=0;
#10a=0;b=1;c=1;
#10a=1;b=0;c=0;
#10a=1;b=0;c=1;
#10a=1;b=1;c=0;
#10a=1;b=1;c=1;
#10a=1;b=1;c=1;
end
endmodule

SIMULATION AND CONSOLE WINDOW:

RTL SCHEMATIC:
4-BIT FULL ADDER:

CODE TESTBENCH
module b4fa_329(s_329,cout,a,b,cin); module tb_b4fa_329;
output [4:1]s_329; reg [4:1]a;
output cout; reg [4:1]b;
input [4:1]a,b; reg cin;
input cin; wire [4:1]s_329;
wire c0,c1,c2,c3; wire cout;
fa_329 a1(s_329[1],c0,a[1],b[1],cin); b4fa_329uut(.s_329(s_329),.cout(cout),.a(a),.b(b),.cin(cin));
fa_329 a2(s_329[2],c1,a[2],b[2],c0); initial begin
fa_329 a3(s_329[3],c2,a[3],b[3],c1); $monitor($time,"input:a=%d,b=%d,cin=%d,outputs:s_329=
%b,cout=%b",a,b,cin,s_329,cout);
fa_329 a4(s_329[4],cout,a[4],b[4],c2);
a=8;b=6;cin=1;
endmodule
#20a=10;b=9;cin=1;
#20a=8;b=8;cin=0;
#20a=10;b=9;cin=1;
end
endmodule

SIMULATION AND CONSOLE WINDOW:

RTL SCHEMATIC:

MULTIPLEXER:

2X1 MULTIPLEXER:
VERILOG CODE AND TEST FIXTURE:

CODE TESTBENCH

modulemux2x1_329(y_329,s,i0,i moduletb_mux2x1_329;
1);
regs;regi0;regi1;
outputy_329;
wirey_329;
inputs,i0,i1;
mux2x1_329uut(.y_329(y_329),.s(s),.i0(i0),.i1(i1));
assigny_329=((~s)&i0)|(s&i1);
initialbegin
endmodule
$monitor($time,"outputy_329=%b,inputs=%b,i0=%b,i1=%b",y_329,s,
i0,i1);

s=0;i0=0;i1=0;

#10s=0;i0=1;

#10s=1;i1=0;

#10s=1;i1=1;

end

endmodule

SIMULATION OUTPUT & CONSOLE WINDOW:

RTL SCHEMATIC:
B) 4X1 MULTIPLEXER:

VERILOG CODE AND TEST FIXTURE:

CODE TESTBENCH

modulemux4x1_329(y_329,s1,s0,i); moduletb_mux4x1_329;

outputy_329; regs1;regs0;reg[3:0]i;

inputs1,s0; wirey_329;

input[3:0]i; mux4x1_329uut(.y_329(y_329),.s1(s1),.s0(s0),.i(i))
;
assigny_329=(~s1)&(~s0)&i[0]|(~s1)&s0&i[1]|s
1&(~s0)&i[2]|s1&s0&i[3]; initialbegin

endmodule $monitor($time,"outputy_329,inputs1=%b,s0=%b,
i=%b",y_329,s1,s0,i);

s1=0;s0=0;i=4'b0000;

#10s1=0;s0=0;i=4'b0001;

#10s1=0;s0=1;i=4'b0010;

#10s1=1;s0=0;i=4'b0100;

#10s1=1;s0=1;i=4'b1000;

end

endmodule
SIMULATION RESULT AND CONSOLE WINDOW:

RTL SCHEMATIC:

8X1MULTIPLEXER:
VERILOG CODE AND TEST FIXTURE:

CODE TESTBENCH

module mux8x1_329(y_329,s,i); module tb_mux8x1_329;

output reg y_329; reg [2:0]s;
input [2:0]s; reg [7:0]i;
input [7:0]i; wire y_329;
always@(*) mux8x1_329uut(.y_329(y_329),.s(s),.i(i));
begin initial begin
case(s) $monitor($time,"inputs=%b,i=%b,outputy_329=%b",s,i,y_329);
3'b000:y_329=i[0];
3'b001:y_329=i[1]; #10 s=3'b000;i=8'b00000001;
3'b010:y_329=i[2]; #10 s=3'b001;i=8'b00000010;
3'b011:y_329=i[3]; #10 s=3'b010;i=8'b00000100;
3'b100:y_329=i[4]; #10 s=3'b011;i=8'b00001000;
3'b101:y_329=i[5]; #10 s=3'b100;i=8'b00010000;
3'b110:y_329=i[6]; #10 s=3'b101;i=8'b00100000;
3'b111:y_329=i[7]; #10 s=3'b110;i=8'b01000000;
endcase #10 s=3'b111;i=8'b10000000;
end end
endmodule endmodule

SIMULATION OUTPUT & CONSOLE WINDOW:

RTL SCHEMATIC:
16X1 MULTIPLEXER:

VERILOG CODE&TEST FIXTURE:

CODE TESTBENCH

module module tb_mux16x1u4x1_329;

mux16x1u4x1_329(y_329,s3,s2,s1,s0,i);
reg s3; reg s2;reg s1;reg s0;
output y_329;
reg [15:0]i;
input s3,s2,s1,s0;
wire y_329;
input [15:0]i;
mux16x1u4x1_329uut(.y_329(y_329),.s3(s3),.s2(s2),.s1(s1),.s
wire [3:0]w; 0(s0),.i(i));
mux4x1_329m1(w[0],s1,s0,i[3:0]); initial begin
mux4x1_329m2(w[1],s1,s0,i[7:4]); $monitor($time,"outputy_329=%b,inputi=%b,s3=%b,s2=%b,s
1=%b,s0=%b",y_329,i,s3,s2,s1,s0);
mux4x1_329m3(w[2],s1,s0,i[11:8]);
#10 s3=0;s2=0;s1=0;s0=0;i=0;
mux4x1_329m4(w[3],s1,s0,i[15:12]);
#10 s3=0;s2=0;s1=0;s0=0;i[0]=1;
mux4x1_329m5(y_329,s3,s2,w[3:0]);
#10 s3=0;s2=0;s1=0;s0=1;i[1]=0;
#10 s3=0;s2=0;s1=1;s0=0;i[2]=1;
endmodule
#10 s3=0;s2=0;s1=1;s0=1;i[3]=0;
#10 s3=0;s2=1;s1=0;s0=0;i[4]=1;
#10 s3=0;s2=1;s1=0;s0=1;i[5]=0;
#10 s3=0;s2=1;s1=1;s0=0;i[6]=1;
 #10 s3=0;s2=1;s1=1;s0=1;i[7]=0;
#10 s3=1;s2=0;s1=0;s0=0;i[8]=1;
#10 s3=1;s2=0;s1=0;s0=1;i[9]=0;
#10 s3=1;s2=0;s1=1;s0=0;i[10]=1;
#10 s3=1;s2=0;s1=1;s0=1;i[11]=0;
#10 s3=1;s2=1;s1=0;s0=0;i[12]=1;
#10 s3=1;s2=1;s1=0;s0=1;i[13]=0;
#10 s3=1;s2=1;s1=1;s0=0;i[14]=1;
#10 s3=1;s2=1;s1=1;s0=1;i[15]=0;
end
endmodule

SIMULATION OUTPUT&CONSOLE WINDOW:

RTL SCHEMATIC: