Chap 4 The Short-Channel MOSFET

+ VG
Shrinking of MOSFETs
10
+ VD
Min. feature [µm]

1
wC
0.1 forecast wS Source
Drain wD
depletion
shrink of ~ 13% / year depletion
0.01 = 2 / 3 years
= 2 in area shrink / 3 years
1E-3
1950 1960 1970 1980 1990 2000 2010 2020 2030
Year

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 1
 4 The Short-Channel MOSFET

4.1 Shrinking
Advantages
Disadvantages

4.2 Short Channel Effects

Discovery and first analysis
Quantitative analysis
- Charge Sharing Model
- Drain-Induced Barrier-Lowering Model

4.3 Scaling Models

Electrostatic Scaling
Subthreshold Scaling

4.4 Limits of Scaling

Gate dielectrics, high-k
Interconnect Materials: Cu and low-k

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 2
4 The Short-Channel MOSFET
4.1 Shrinking
Historical Trend

History:
Shrinking of MOSFETs 1960: 25 µm
Min. feature [µm] 10

1
2000: 180 nm
0.1 forecast 2005: 90 nm
2008: 65 nm
shrink of ~ 13% / year 2012: 22 nm
2010: 32 nm
2014: 14 nm
0.01 = 2 / 3 years
= 2 in area shrink / 3 years
1E-3
1950 1960 1970 1980 1990 2000 2010 2020 2030
Year

Since the first MOSFET (1960) the feature size is shrinked about 13 % per year for 50 years now

Why ?
(see chap.2
Economics: A shrink of 15 % approximately reduces the fabrication costs by 50% / device and exercise 1)

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 3
4 The Short-Channel MOSFET
4.1 Shrinking
Shrinking - The Advantage

Discretes Integration
Gate

Source L Drain

if: vmax = 107 cm/sec 3 years 3 years

channel length L
every 3 years the number of devices
-> transit time t
on the same area increases by 4
Shrinking dimensions:

increase speed reduce device area

L L  A
  ´ A  w L A´ w  L A´
v  ´ S S S S S2
v

reduce energy consumption

(power-delay)
P
P  U  I  P´ U  I   P´
S S S S3

Shrinking dimensions induces: better dynamic behavior (higher speed, lower power)
+ better economics (more devices per wafer)

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 4
4 The Short-Channel MOSFET
4.1 Shrinking
Shrinking - The Disadvantage

Output chracteristics:

* no saturation -> bad for analog application

* early, weak break-through

Sub-threshold behavior:

* increase in subthreshold slope S

(from ideal value 60mV/dec -> higher values)
* increase of leakage current
-> higher voltage swing needed to turn device on/off

Drain Induced Barrier Lowering (DIBL)

* dynamic lowering of threshold voltage

Shrinking dimensions induces: worse static behavior (higher leakage, lower reliability)

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 5
 4 The Short-Channel MOSFET

4.1 Shrinking
Advantages
Disadvantages

4.2 Short Channel Effects

Discovery and first analysis
Quantitative analysis
- Charge Sharing Model
- Drain-Induced Barrier-Lowering Model

4.3 Scaling Models

Electrostatic Scaling
Subthreshold Scaling

4.4 Limits of Scaling

Gate dielectrics, high-k
Interconnect Materials: Cu and low-k

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 6
 4 The Short-Channel MOSFET
4.2 Short Channel Effects
The Discovery of Short-Channel Effects

S/D/G Diffusion S/D/G Diffusion

S/D Diffusion - 18 V - 15 V + 12 V S/D/G implant +5V
Alu channel implant channel implant channel implant
poly-Si poly-Si poly-Si
2.5µm p+ 25µm p+ 2.0µm n+ n+ < 1µm n+ n+
2.5µm p+ 12µm p+ 8µm 3.5µm

1960 1966 1974 1978

1) hot processes first (Diffusion 1000°C) 1) hot poly-gate first (Diffusion 1000°C) 4k-DRAM, CMOS-logic INTEL HMOS I
2) cold processes (Alu 450°C) 2) channel implant (new!)
1) short channel 1) S/D implant -> shallow junctions
-> gate has to be adjusted -> large channels -> S/D self-adjusted -> short channels 2) large diffusion depth 2) low voltage -> reduce electric fields
-> diffusion -> large depth -> diffusion -> large depth 3) high voltages
3) ebeam-lithography for experimental
-> serious „short channel“ effects short channel studies

discovery study

First scaling rules 1974

1980

Empirical relationship

Brews, Fichtner, Nicollian, Sze: "Generalized Guide for MOSFET Miniaturization",

IEEE Electron Device Letters, 1(1980)2-4

geometry- and voltage dependant parameters must be designed together !

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 7
4 The Short-Channel MOSFET
4.2 Short Channel Effects
Qualitative Look Inside the MOSFET

Result: As early as in 1973 it was recognized by experimental devices, that:

+ VG

+ VD

Gate
Source wC
depletion
Drain
wS
depletion depletion
wD

Short-channel effects appear, if the length of the Source/Drain depletion zone is no longer small compared to the channel length

These, not gate-controlled, depletion charges change the gate-defined threshold voltage

In addition, 2-dim or 3-dim field distributions must be handled

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 8
 4 The Short-Channel MOSFET
4.2 Short Channel Effects
Quantitative Look inside the MOSFET

Geometrical layout: Geometrical parameters:

+ VG
L : channel length limited by technology

L + VD rj : junction depth of S/D doping defined by technology

dox dox : oxide thickness uncritical by technology

rj wC
wS
wD Voltage dependent parameters:

width of depletion layer

(one-sided abrupt junction) built-in voltage:

2 0 Si  Vbi  Vext  Vbi 

kT  N A  N D 
 ln 
w q 2
 ni 

qN dop
dependent on doping

Some calculations for historical MOSFETs: see page 25:

year L rj dox Vdd V wS wD Lmin

rj  d ox  wS  wD 
2
µm µm A µm µm µm Empirical formula:
1
1960 25 2.5 2000 18 0.26 1.1 9248 8.6
  3

L min m  0.41  rj[µm]  d ox [A]  w S [µm]  w D [µm] 

o
1974 8 2 1200 12 0.26 1.0 3810 6.4  2

 
1977 6 1 1000 5 0.26 0.6 740 3.7
 
1979 3.5 0.7 700 5 0.26 0.6 362 2.9
1 Ångstroem = 0.1 nm
2000 0.15 0.04 40 1.5 0.26 0.3 0.6 0.34

ws, wD are calculated using: NA = 1016 cm-3, ND= 1020 cm-3

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 9
4 The Short-Channel MOSFET
4.2 Short Channel Effects Quantitative Look inside the MOSFET

1960
1974
calculated values
from table
1977
1979 8.6µm
6.4µm

2000
Since 1985 the channel length is scaled
more aggressively , short channel behavior
partly suppressed by technological tricks

1
  3

L min µm   0.41  rj[µm]  d ox [A]  w S [µm]  w D [µm] 

o
 2

 
 
There exists no (electrical) lower limit for a short-channel device,
if junction depth rj, oxide thickness dox and doping is properly scaled down

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 10
4 The Short-Channel MOSFET
4.2 Short Channel Effects Overview of Basic Short Channel Models

S Long channel:
* the surface potential S, determined by the gate voltage, is constant all over the channel
gate
Source VDS
* the S/D depletion zones are negligible compared to the gate length
Ec
Gradual Channel Approximation
Drain
xS xD
Short channel: Charge sharing model:
S
gate Assumption: the surface potential S is still constant, but the depletion charge is shared by the Source/Drain
depletion zones and the gate depletion
Source VDS
Ec the threshold voltage is reduced due to already depleted Source/Drain depletion
Drain This model is a good description, as long as a remarkable part of the channel is not occupied by the S/D
xS xD
S Drain-induced Barrier Lowering model (DIBL):
gate DIBL Assumption: the surface potential S varies along the channel due to the S/D potentials
Source VDS
the threshold voltage is reduced due to a Source/Drain induced barrier lowering
Ec
Drain This model is a good description, if the S/D depletion zones occupy a remarkable part of the channel
xS xD
These analytical models result in equations, which may be adjusted for practical use

In contrast, with increasing influence of 2-dim or 3-dim effects, analytical models must be replaced by numerical simulations

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 11
4 The Short-Channel MOSFET
4.2 Short Channel Effects
The Charge Sharing Model (Yau-Model)

Calculations for all channels:

+ VG 1) the charges in the gate capacitor equal to zero: Qgate  Qox  Qinv  Qdep  0
Qdep
2) in voltages: Vgate  VFB  S  with: Qdep  qN A wdep A
small VD ´´
Cox A
L Vth  VFB  2bulk 
Qdep
3) with threshold voltage: with: S  2bulk
A
rj
´´
Long channel Cox
wdep
gate depletion
wS Short channel, but the contribution of S/D depletion is small:
L* (channel not too short and/or VDS = zero/ small

1) the gate controlled charge is approximated by a trapezoid:

shared triangles
 L  L* 
Approach: *
Q
dep  qN A wdep  wgate    wgate = width of gate
Yau: "A simple theory to predict the threshold voltage of short-channel IGFETs",  2 
Solid-State Electronics, 17(1974)1059-1063

2) the shared (S/D symmetrical) triangles can be calculated by trigometric: wdep  L  rj   wdep  rj 
L  L*
L 
2 2 2

2
L  L*  2wdep 
 L  rj   1   1 2 0 Si  2bulk
2  rj  wdep 
  qN A
3) the threshold voltage shift is then:
 L  L* 
qN A w dep   w gate  
qN A w dep  w gate  L   2  qN A w dep  L  L*  qN w  rj  2 w dep 
Vth  VthLC  VthSC     1     A dep  1  1
C gate C gate C´´gate  2L  ´´
2LCgate  rj 
 

the long channel threshold voltage decreases with shrinking channel length L, independent of V DS at low VDS

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 12
4 The Short-Channel MOSFET
4.2 Short Channel Effects
The Charge Sharing Model (Yau-Model)

Let us have a look to the empirical scaling law:

1
 2
3
Lmin  0.41 rj [ µm]  d ox[ A]  wS [ µm]  wD [ µm] 
 

From analytics of Charge-Sharing model:

qN A wdep  rj wdep  rj  tox
Vth   ´´
 const 
2 LC gate L

wdep  rj  tox L  const.  wdep  rj  tox

If we ask for: Vth  10%  const. 
L
which corresponds to the old scaling law

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 13
4 The Short-Channel MOSFET
4.2 Short Channel Effects
The Charge Sharing Model (Yau-Model)

Short channel, but the contribution of S/D depletion is high:

xS xD (very short channel and/or VDS high)
L
1) with high VDS the shared tringles increase to unsymmetrical triangles:
dox
rj 2 0 Si  Vbi  S  2 0 Si  Vbi  2bulk 
wdep xS   at Source using:
wS qN A qN A S = 2 bulk
wD
2 0 Si  Vbi  S  VDS  2 0 Si  Vbi  2bulk  VDS  at Drain
shared triangles xD  
qN A qN A (reverse biased)

2 0 Si  2bulk
keeping S = 2 bulk approximately constant -> wdep~const wdep 
qN A

qN A wdep  rj  2 xS   
   1  2 xD  1
2) the threshold voltage shift is then: Vth  VthLC  VthSC     1   1
   
´´
2 LCgate rj   rj 

+ VG the long channel threshold voltage now decreases with shrinking channel length L and VDS (via S or xD)

+ VD
Short channel, the contribution of S/D depletion dominates:
(very short channel and/or VDS high)
w
wS Source dep 1) the gate controlled charge is assumed to reduce to a triangle:
depletion Drain wD
depletion
L  L
wdep    rj   independent of VDS
2r j  4
Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba
Modul 1254 AdMOS, 4- 14
4 The Short-Channel MOSFET
4.2 Short Channel Effects
The Charge Sharing Model (Yau-Model)

Narrow channel
1) in reality the gate voltage also depletes the regions on both sides of the channel,
which means an unintentionally increase in channel width

The gate charge, which in the long channel case, is enough to induce inversion, is no
longer sufficient, because a part of this gate charge depletes the channel sides.

As a result, a higher gate charge is needed for inversion, this corresponds

to higher threshold voltage

2) assuming, that the additional depletion is approximately cylindrical, the total depletion charge is:

  wdep 
*
Qdep  qN A wdep  wgate   L  
 2 wgate 

2 0 SiqN dop  2bulk   wdep 
3) In consequence, the threshold voltage is increased to: Vth  VFB  2bulk   1   
´´
Cox  
 2 wgate 

4) In reality, the metal gate overlaps the sloped regions:

-> analytical corrections must be done
-> or 2-dim/ 3-dim numerical solutions of the Poisson equation (simulations)

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 15
4 The Short-Channel MOSFET
4.2 Short Channel Effects
Effect of Short-Channel on Threshold and Current

Threshold Voltage

geometry: L or w Substrate voltage

the opposite behavior of threshold voltage shift can not be used for compensation, since both effects are nonlinear connected

in addition, the channel length is fixed and defined by technology, the gate width is needed to be flexibel in circuit design

I-V characteristics:
Since short channel and narrow channel effect can not be separated, the simple approach: V th*=VthLC – VthSC +  VthNC
can not be used in the IV-characteristics:

In practice, complicated analytical models must be assumed to calculate Vth* = f( N, L, w, rj, VDS) or 3-dim simulations

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 16
4 The Short-Channel MOSFET
4.2 Short Channel Effects
The Drain-Induced Barrier-Lowering (DIBL) Model

Long channel:
Channel formation (strong inversion) starts when S = 2 bulk

- S is constant all over the channel

short channel - S determines the value of threshold voltage Vth
Vbi 2 0 SiqN dop  2bulk
barrier Vth  VFB  2bulk  ´´
barrier lowering electron path Short channel:
Cox
just for imagination
long channel - a symmetrical barrier lowering exists
- with additional VDS the barrier maximum is shifted to Source and
Source Drain in addition further lowered.

Due to empirical observations the lowering is approximately linear in V DS:

Approach: Vth,SC  Vth, LC  Apene VDS  Bneigh where Apene is a so-called penetration constant, how effective the VSD penetrates
into the channel
and Bneigh a so-called neighbouring-effect B = f(L, xj, dox, Ndop, ...)
For Apene several approaches exist:
6d ox  nL  Apene = 1/L
Apene   exp  
wdep  4wdep  Apene = L-3 as it is used in SPICE

the long channel threshold voltage decreases with shrinking channel length L and linear decrease in VDS
Characterization of the DIBL-model:
disadvantage: the physical description is nearly lost, mainly empirical trends are used, which are fitted to (a special ?) reality

In principle the 2/3-dim Poisson-equation must be solved. Because solving Poisson´s equation is done in
advantage:
any numerical simulation the DIBL-model is very powerful when strong inhomogenities (e.g. channel doping) exists

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 18
4 The Short-Channel MOSFET
4.2 Short Channel Effects
Comparison of Models vs Experiment

Output characteristics: Transfer characteristics:

Experiment

a) Long-channel, L = 0.73µm b) short-channel, L = 0.23µm

weak inversion = sub-threshold

Simulation

Comparison of experimental MOSFETs and numerical simulations show good agreement

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 20
4 The Short-Channel MOSFET
4.2 Short Channel Effects
The DIBL: - Measurements

The DIBL is characterized as a threshold voltage shift

1) In a single device commonly the gate voltage shift at a given

10-8 drain current ID (mostly at ~10-8 A/µm, which was old industry way for fast
determing VT) is used between the characteristics
of 0.1V (low field) and the supply voltage (or sometimes V DS=1V)

This effect is called: DIBL

2) The design of processes and geometries for shrinking MOSFETs

50 nm L consumes a lot of money. Industry prefers devices, where not much
has to be changed with shrinking.
As a test of robustness of technology for future shrinking, MOSFETs
are fabricated with constant technology, but shorter channels.
Now, the gate voltage shift at a given drain current ID [ ~10-8 A/µm)
300 nm for various channel length´s is used.
shorter L

700nm 1.7 µm
This effect is called: VT roll-off

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 21
4 The Short-Channel MOSFET
4.2 Short Channel Effects
The DIBL: - Measurements

Example of DIBL Example of VT Roll-off

(measured in one single device at different voltages) (measured in different devices at same voltages)

Same device, same technology, but just shorten the channel

1) the Ion - current remains the same, because the

internal barrier vanishes at high gate voltage anyhow
( if there is VDS barrier lowering (DIBL) or not)

2) but if DIBL exist, the threshold voltage decreases

and therefore leakage current Ioff increases.
3) if Ioff increases and Ion remains the same the subthreshold swing S
must increase in addition

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 22
4 The Short-Channel MOSFET
4.2 Short Channel Effects
Summary of High-Field Effects

In addition to the small geometry effects all high-field effects have a serious impact to short channel MOSFETs:

Modification in carrier transport

Mobility degradation due to gate-field

Velocity saturation due to Source-drain field

2-dim field effects

Channel length modulation in saturation

High Electric Fields induce:
Break-through effects

1 Hot electrons -> impact ionization

Avalanche multiplication (Drain break-through)
Parasitic Bipolar Transistor

gate injection

2 gate break-through

3 Punch-through

Parasitics

Source-Drain resistors

High electric fields modify (degrade) the MOSFET performance

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 23
 4 The Short-Channel MOSFET

4.1 Shrinking
Advantages
Disadvantages

4.2 Short Channel Effects

Discovery and first analysis
Quantitative analysis
- Charge Sharing Model
- Drain-Induced Barrier-Lowering Model

4.3 Scaling Models

Electrostatic Scaling
Subthreshold Scaling

4.4 Limits of Scaling

Gate dielectrics, high-k
Interconnect Materials: Cu and low-k

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 24
4 The Short-Channel MOSFET
4.3 Scaling
Scaling

To avoid short-channel effects (2/3-dim geometry, hot electrons (high-field) und transport degradations) scaling laws are investigated

The aim of scaling is to reduce the economically needed device size

and
keep the desired electrical advantages (saturation, power reduction, speed increase)
without the electrical disadvantages (degradation, hot carrier effects, reliability reduction))

Two basic scaling approaches exist

Electrostatic scaling subthreshold scaling

(based on physics, advantage for analog application, but practical limits (empirical, focus for digital ULSI-circuits (leakage, switching)

- ideal (constant field)

- constant voltage
- quasi-constant voltage
- free scaling

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 25
4 The Short-Channel MOSFET
4.3 Scaling
Electrostatic Scaling

Constant Field Scaling

Scaling expression limited by
scaling
lateral dimensions lithography
channel length L
1/S * shrinking all geometrical dimensions and voltages by the same
vertical dimensions breakdown,
Oxide thickness, junction depth
1/S tunneling factor S keeps the electrical fields in the MOSFET ~ constant
voltage V
1/S V´ V /S 1
Doping NA to achieve reduction of depletion regions * because depletion width is scaling with    V
*S * compromising 1 without voltage
N ´dop N *S S N dop
S
* compromising 1 with high voltage
S
the doping N is scaled by S*N to reduce depletion width by w/S
consequences of scaling
area 1/S²
area gate capacity C´´ *S C´´
C´´
d
S
drain current 1/S I DS  S 
VG

VD
C´´ S S
Advantages in dynamic behavior
switching time 1/S
power loss 1 / S²
increasing switching speed
power-delay-product 1 / S³ consuming less power
current density *S
interconnection resistance *S R
l increases !
d b
voltage drop not scaling V  I  R But increasing parasitic effects
RC-time not scaling   RC
contact resistance *S  increases !
Vcont  I
A

not influenced by scaling:

work function difference  MS thermodynamic used in Vth
subthreshold swing S same voltage
Limits by not scaling parameters
swing for ion/ioff

not linear scaling:

bulk Fermi-level, inversion-onset N dop
bulk  f (ln )
ni
2 0 Si  Vbi ln N dop  
width of depletion zone w 1 Vext 
ideal should be:
S  S 
wdep 
qSN A
threshold voltage Qox 2 0 Si qSN A  2b (ln( NA))
Vth   MS   2b (ln( NA)) 
Cox S  Cox
subthreshold current
I D,sub  I 0  
N A , ln( N A)  exp  GS 

V
S 

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 26
4 The Short-Channel MOSFET
4.3 Scaling
Electrostatic Scaling

Due to several restrictions in the past (and future), e.g. keeping voltage levels constant or technological capabilities
the „ideal“ Constant-Field Scaling was modified by keeping Poisson´s equation constant

With the Poisson equation the electrical potentials in a semiconductor device are calculated:

d 2  ( x) qN dop
 
dx 2  0 Si  0 Si

Poisson equation is invariant when transforming: Geometries: x*= x/a with a factor a
potentials: *=  /b with a factor b

doping: N*= N(a²/b) with a factor a²/b

2
d 2 * d b a 2 d 2 a 2 qN dop qN *dop
       
dx*2 d x
a
 
2
b dx 2 b  0 Si  0 Si

Choosing special values of a, b results in special scaling models:

a = b =: S, -> a²/b = S -> E=const, Constant-Field-Scaling

a = S, b = const, -> Constant-Voltage Scaling
a > b, Quasi-Constant-Voltage Scaling
a, b general scaling

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 27
4 The Short-Channel MOSFET
4.3 Scaling
Electrostatic Scaling
Constant-Field Constant-Voltage Quasi-Constant Voltage free Scaling
Scaling: a = b = S Scaling: 1 < b < a Scaling: 1 < b < a 1<b<a
but V = const
Constant-Voltage Scaling
scaling
lateral dimensions 1/S 1/a 1/a 1/a
channel length L * was used to keep the voltage level
vertical dimensions 1/S 1/b 1/a 1/a ( e.g. TTL) constant for circuits
Oxide thickness, junction depth * to avoid high gate fields the vertical
voltage V 1/S const=1 1/b 1/b dimensions are less reduced (b < a)
Doping NA *S *a *a a²/b
consequences of scaling
area 1/S² a²
drain current 1/S b a/b² a/b²
Quasi-Constant-voltage Scaling
switching time 1/S 1/a² a/b² a/b²
power loss 1 / S² b a/b³ a/b³
power-delay-product 1 / S³ a/b² a²/b5 a²/b5 * the voltage is also reduced by b
-> depletion width scales less
-> electric fields increase less
interconnection resistance *S *a *a *a
voltage drop not scaling not scaling not scaling not scaling
RC-time not scaling not scaling not scaling not scaling
contact resistance *S² a² a² a²
Free Scaling
 MS
not influenced by scaling:
work function difference thermodynamic * full use of Poisson-scaling
subthreshold swing S same ion/ioff- -> if special parameters are limited
voltage (e.g. oxide thickness) scaling can
be done nevertheless
not linear scaling:
bulk Fermi-level, inversion-onset
width of depletion zone w
threshold voltage
subthreshold current

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 28
4 The Short-Channel MOSFET
4.3 Scaling
Subthreshold Scaling

Subthreshold scaling:
It was found emirically (1980), that the short-channel behavior can be avoided and the subthreshold characteristics
is not degraded, if the following relationship is fulfilled:
1 + VG
 2
3
Lmin  0.41 rj [ µm]  d ox[ A]  wS [ µm]  wD [ µm]  + VD
 
dox
rj rj
wC
wS Source
Drain wD
depletion
depletion

Brews, Fichtner, Nicollian, Sze: "Generalized Guide for MOSFET Miniaturization",

IEEE Electron Device Letters, 1(1980)2-4

Most flexible scaling, because only the product of parameters must be scaled

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 29
4 The Short-Channel MOSFET
4.3 Scaling
MOSFET Development - Overview

Scaling relevant values of parameters in MOSFET generations:

DRAM-complexity 1k 4k 16k 64k 256k 1M 4M 16M 64M 256M 1G 1G * 4G 16G 64G 256G Scaling S
Year 1970/71 1973 1976/77 1979/80 1982 1985 1988 1993 1995 1997 1999 2001 2003 2006 2009 2012 All 3 years
Process p-chan n-chan n-chan n-chanl forecast: ITRS-roadmap 1997
Si-gate Si-gate 2-poly 2-poly
DRAM cell structure 3T 1T 1T
Min.Feature [µm] 8 - 10 7-8 6-7 3.5 2.0 1.0 0.7 0.5 0.35 0.25 0.18 150 130 100 70 50 S=1/2=0.7
(channel length) 3-4 2-2.5 1.5 0.8 0.5 0.3
junction depth [nm] 2500 2000 1000 700 450 250 150 150 100-50 72-36 60-30 52-26 40-20 30-15 20-10
gate oxide thick [nm] 120 120 100 70, 70 45 30-20 15-10 15-10 5-4 4-3 3-2 3-2 2-1.5 < 1.5 < 1.0
gate width µm 5-7 3-4 2 1.2 0.5 0.5
interconnect width µm 5 4 3 2 1 1
interconnect thick µm 1 1 0.9 0.75 0.6 0.6
cell area [µm²] 3700 900 450 170 30 10 3.9 1.5 0.56 0.22 0.14 0.09 0.036 0.014 0.006 S²/1.3
Chip size [mm²] 13 19 18 21 38 55 80 145 190 280 400 445 560 790 1120 1580 1 / 1.5
Udd [V] 18/12 12 12,5 5, 5 5 5 5-3.3 3.3 2.5- 1.8 1.8-1.5 1.5 1.2 1.2-0.9 0.9-0.6 0.6-0.5
Power dissipation [W] 0.2 70 90 110 130 160 170 175
comments HMOS HMOS HMOS
II

Note:
Usually between experimental prototypes -> industrial prototype -> high volume fabrication (~ 1mill. chips/year) several years are passing.
Dependent on source the data correlation year – properties may be shifted for 1-3 years

Note:
A factor 4 increase in chip complexity is achieved by: - decreasing size by 13% per year -> 2 in 3 years -> factor 2 in area

- reducing functionality area by 1.3 per 3 years

- increasing chip size by 1.5 per 3 years

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 30
4 The Short-Channel MOSFET
4.3 Scaling
Historical Scaling

Shrinking of MOSFETs
junction depth 1970-1976:
(values x10) * shrinking of channel length
U=12 V 100 * no shrink of voltage, oxide thickness
10 -> discovery of short channel effects
oxide thickness U= 5 V -> voltage reduction, increased oxide scaling
(values x 100) voltage
Min. feature [µm]

10
quasiconst
1978-1987:
1 * const. Voltage 5V TTL-level
* more vertical shrink to come back to GCA
channel length 1
! Not const.voltage scaling !
Fit:
channel: S=1.13
0.1 1995 - 2000:
0.1 * variable voltage
* ~ quasi-const. Scaling

> 2000 forecast:

0.01 0.01 * ~ subthreshold scaling
1960 1970 1980 1990 2000 2010
Year
The Law: From economical pressure a lateral shrink (channel length) of 13% / year must be achieved -> area shrink of factor 2 / 3 years

Due to the technological capabilities of various companies short-time deviations from long term S=1.13 are the result
Beside the general Const.-Field scaling the scaling models may change from generation to generation

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 31
 4 The Short-Channel MOSFET

4.1 Shrinking
Advantages
Disadvantages

4.2 Short Channel Effects

Discovery and first analysis
Quantitative analysis
- Charge Sharing Model
- Drain-Induced Barrier-Lowering Model

4.3 Scaling Models

Electrostatic Scaling
Subthreshold Scaling

4.4 Limits of Scaling

Gate dielectrics, high-k
Interconnect Materials: Cu and low-k

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 32
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Historical Scaling

We have seen:
"Scaling" is the theoretical instruction how to avoid SCE (Short Channel Effects) in the I-V characteristics

Reduce minimum feature size by S

-> L/S
-> tox/S
-> rj/S
-> other geometries (e.g. interconnects)/S
-> N*S

but following these instructions new problems arise:

tox < 3nm -> through-diffusion of Boron from poly-Gate in channel causes VT-shift
-> quantum-mechanical tunnel leakage current from channel through gate oxide
possible solutions: -> high-k gate dielectrics
-> and/or metal gate (due to gate depletion in poly-Silicon gate)

rj thinner -> increasing resistance of S/D junctions

possible solutions: -> raised S/D by selective epitaxial growth-> thicker S/D -> lower resistance
-> insert of Ge in S/D results in higher solubility of doping atoms in S/D -> lower resistance
-> realization of vertical S/D

shrinking dimensons of interconnects -> inceasing RC-delay in interconnects

possible solutions: -> Cu and low-k intermetalic dielectrics / or air-gap dielectrics

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 33
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Limits of Gate Dielectrics Scaling

1000C
By using thermal oxidation of silicon Si  O2 ~  SiO2 with SiO2 the first working MOSFETs was possible (1960)

Some properties: high temperature stable very good isolator: bulk resitivity 1015 cm
good adhesion to silicon and metals very high breakthrough field: >10 MV/cm
selectively etching to silicon and metals dielectric constant: 3.9
best interface to silicon: Dit < 108 (eVcm)-1 possible

From scaling theory a continous shrinking of oxide thickness is necessary to avoid short channel effects (SCE)

100 Shrinking of MOSFETs

Oxide Thickness [nm]

10

1970 1980 1990 2000 2010

Year
boron diffusion
But when gate oxide thickness was reduced to 4 nm and above two serious problems arose:
gate leakage current

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 34
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Limits of Gate Dielectrics Scaling

Boron diffusion p-poly Si

A CMOS-inverter consists of an p-MOSFET and an n-MOSFET

The gate metal is poly-Silicon, highly-doped together with Source/Drain doping SiO2

p- Source p- Drain
Boron (due to its high solubility in silicon) is used for the p-MOSFET,
implanted as B+ or BF2+ n- substrate p-MOSFET

But Boron has a higher solubility in SiO2 -> boron from gate poly-Si diffuse into SiO2 and also in the silicon channel
These positive charges within the SiO2 and also within the channel will shift the threshold voltage of the MOSFET and increase scattering
, thus reducing mobility and on-current

This effect, called boron penetration, is observed, when gate oxide thickness was around 4 nm and below (beginning 1990)

As a solution the incorporation of nitrogen

within the oxide was/is used.
C-V characteristics of MOS-Gates
But nitrogen was found to diffuse to the interface
of SiO2 and Si and there increasing surface "roughness",
resulting in lowering of mobility and therefore Ion

Shift of threshold voltage

due to boron penetration from: Wu, Lucovski, Int.Conf. on Characterization and Metrology
for ULSI-Technology, 1998

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 35
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Limits of Gate Dielectrics Scaling

Gate leakage current de Broglie 1923:

Based on the dualism of light, that light in some experiments behave like an electromagnetic wave in other experiments like a particle
SiO2 deBroglie postulated that in contradiction particles may be described as wave with a wavelength depending on velocity (momentum):

energy W wave: c   
h h h
   Dualism of wave and particle
Photons: E  h   mc 2 mc mv p
wave function
non-zero
of electrons
transmission 1.23nm
for electrons 
probability
Quantum well Ekin eV 
of channel
Energy level of for thermal electrons with E=0.026 eV the wave length is:  ~ 7,6 nm
electrons in the channel

metal

coordinate x

Because of the non-infinite barrier height of SiO2 (3.1eV) the quantum-mechanical wave function
of electrons has a non-zero transmission probability through the gate oxide.

This results in leakage current and long-term degradation of the gate oxide

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 36
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Limits of Gate Dielectrics Scaling

From material properties of SiO2 we calculate: very high breakthrough field: >10 MV/cm = 1V/nm

With reduced 0.5 V /nm the tunneling current due to Fowler-Nordheim is ~ 10-9 A /cm²
The increase of tunneling current is ~ 1 order/ 0.25 nm (1 monolayer)

1.5 nm -> 10 A/cm² 12 days

2 nm -> 0.1 A/cm²

from: Stathis (IBM),IBM J. Res. & Dev., 46 (2002)

This current damages the gate oxide

and reduces the lifetime of the gate oxide
from: Yanagiya et al. (Toshiba), "A 65nm CMOS Technology ...", IEDM 2002

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 37
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Limits of Gate Dielectrics Scaling

But from roadmap to avoid SCE

we need oxide thickness < 1nm

Solution: We are searching for new gate dielectrics with k> 3.9 (SiO2) -> high-k dielectrics

 0 ox  A we achieve the same high capacitance C with higher ox and thicker tox
Because: C
tox

Example: SiO2 = 3.9 , if we use ox = 20, we can use tox = tSiO2 * ox/ SiO2 = 5 * tox
-> if tSiO2 < 1nm is needed from roadmap, we can use tox < 5nm, which is too thick for tunneling

Possible candidates:

most promising
candidates

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 38
4 The Short-Channel MOSFET
4.4 Limits of Scaling Limits of Gate Dielectrics Scaling: New high-k materials

A new gate dielectric material must fulfill many requirements (as it is done by SiO 2):

1) 3.9 < k < ~20

2) isolating material -> bandgap > 3 eV

3) band position compared to Si > high barrier for electrons in conduction band + high barrier for holes in valence band

4) density of interface states < 1010 eV-1cm-2

5) amorphous or single-crystalline lattice with no phase changes between room temperature and 1050°C, 30 sec
(if Gate is fabricated first, then S/D. But fabrication of dummy-gate, then S/D (high-temperature), then Gate may be possible)

6) No reaction with surrounding material, e.g. Si and gate metal

(if Gate is fabricated first, then S/D. But fabrication of dummy-gate, then S/D (high-temperature), then Gate may be possible)

7) compatible elements to CMOS-technology (for example no iron-oxides)

8) good adhesion to Si, SiO2, nitride, ....

9) dry etch possible (-> all elements should build volatible compounds)

10) selectively etchable to Si, SiO2, nitride, ....

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 39
4 The Short-Channel MOSFET
4.4 Limits of Scaling Limits of Gate Dielectrics Scaling: New high-k materials

Selection parameters: k, Egap, band position

Conduction band Si

Valence band Si

14-25 22-40
~25 12-18
7 ~12
k-value: 3.9 8-11

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 40
4 The Short-Channel MOSFET
4.4 Limits of Scaling Limits of Gate Dielectrics Scaling: New high-k materials

In most cases the high-k dielectrics is not stable

in the gate stack concerning high temperature

Possible solutions:
* further search and development of materials
* replacement gate (also good for metal gate)
ZrO2, k> 15
after temperature treatment 900°C, 10 sec
interfacial layers of SiOx are created to Si and poly-Si

Leading candidate materials in 2005: HfO2 (Keff~15 - 30); HfSiOx (Keff~12 - 16) an then in 2007
Materials, process, integration issues to solve INTEL presented HfOSiN

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 41
4 The Short-Channel MOSFET
4.4 Limits of Scaling Limits of Gate Dielectrics Scaling: New high-k materials

Interface states < 5*1010 cm-2eV-1

INTEL, IEDM 2007

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 42
4 The Short-Channel MOSFET
4.4 Limits of Scaling Limits of Gate Dielectrics Scaling: New high-k materials

INTEL, IEDM 2007 INTEL, 2012

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 43
 4 The Short-Channel MOSFET
4.4 Limits of Scaling
Limits of interconnect- Scaling: RC-Delay

Due to shrinking the resistance of interconnects itself and by narrowing the parasitic capacitances are increasing.
Both increases switching times, although the single transistor is getting faster and faster.

The interconnect resistivity:

L
R  ( usually an aspect ratio of T : W = 2 :1 can be filled by technology without problems)
T W Cv t
L T
R  ( statistically most interconnects exhibit a length of about 100µm, d
2W W but longer interconnects are existing, see next page) CL L
W
Example: 100nm Generation SiO2 = 3.9
L 100µm low-k:  < 3.9
R   3.0* 106 cm   150
2 W 2  100nm
2 2

The Parasitic Capacity:

20
L T L W 18 gate-delay [ps]
C  2  Clateral  2  Cvertikal  2 0 SiO2   2 0 SiO2  RC-Leiterbahn (L=100µm), Al+SiO2
d t 16 RC Gate+Leiterbahn
RC-Leiterbahn (L=100µm), Cu+low-k
T W   2W W  14
C  2 0 SiO2  L      2 0 SiO2  L      6 0 SiO2  L 12

Delay [psec]
d t  W W
10
(d,t ~W, see next page) 8
6
Example: 100nm Generation 4
2
C  6 0 SiO2  L  6  8.85 *1014 F  3.9 100µm  2 *1014 F
cm 0
1000 100
All together: RC = 150 * 2*10-14 F = 3 psec Generation [nm]

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 44
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Limits of Interconnect Scaling

Year
Copper 2003 2005 2008 2011 2014
Parameter
Conductors
Technology(nm) 120 100 70 50 35
(8 Levels) # of Transistors 95.2M 190M 539M 1523M 4308M
Clock Frequency 1724 MHz 2000 MHz 2500 MHz 3000 MHz 3600 MHz
Chip Area (mm2) 372 408 468 536 615

Low-k Wiring Levels 8 8-9 9 9-10 10

Dielectric Pitch(L/I/G)(nm) 330/420/690 265/340/560 185/240/390 130/165/275 95/115/190

A/R (L/I/G) 1.6/2.2/2.8 1.7/2.4/2.8 1.9/2.5/2.9 2.1/2.7/3.0 2.3/2.9/3.1
Dielectric Const. 2.2-2.7 1.6-2.2 1.5 <1.5 <1.5

Copper
Plugs

At sub-0.25um feature sizes, 90% of the total capacitance is dominated by line-to-line capacitance.

THE DEVICE
Increasing clock speeds and reduced sizes require new dielectrics with k values of less than 3.

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 45
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Limits of interconnect: Metal levels and pitch
INTEL, Dec.2012, IEDM conference GlobalFoundries, 2012 Common Platform Tech Forum (CPFT)

22 nm FINFETs Gate pitch: 90nm

20nm node
- replacement-gate
- metal1 pitch: 64 nm
Fin pitch: 60nm

14nm node
Fin pitch: 48 nm
Contacted gate pitch: 64 nm

up to 12 levels metallization

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 46
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Limits of interconnect: Low-k materials

•Material •di
•Free space •1 Low-k Materials:
•Acrogels •1.5
1) Vacuum/air exhibit the smallest possible dielectric constant, this is k=1
•Teflon AF •2.1
•Aromatic thermosets (SiLK) •2.6 – 2.8 Free, non-supported interconnects are not mechanically stable,
•Polyimides (organic) •3.1 – 3.4 CMP is not possible (may be with etching-out isolation at last step)
•Silicon dioxide •3.9 – 4.5
•Glass epoxy (PCBs) •5
•Silicon nitride •7.5
•Alumina (package) •9.5
•Silicon •11.7

2) Try to introduce air in isolation -> Nanoporos

Since (2005) the most promising candidates are polymeres, which create nanopores when annealed

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 47
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Principles for the Reduction of the k-Value

Dielectric Constant Reduction Methods

Reduce polarization strength and density

basic concept is to replace strong Si-O bond basic concept is to create polymers, because during
by weaker bond types as provided by C, F formation a lot of free space ( =1) is created

more based on inorganic SiO2 hybrides more based on organics C, O, H, ..

(Si,O,C,F,H)

Table of polarization strength with covalent C- bonds from: Miller et al., Macromolecules 23(1990)3865 (polarizability)
Pine, Organic chemistry 5th ed., 1987 (bond strength)

Bond C≡N C≡C C=C C=O O-H C-H C-O C-F C-C

Polarizability [A] 2.24 2.04 1.64 1.02 0.71 0.65 0.58 0.56 0.53

bond strength [kcal/mole] 213 200 146 176 102 99 84 116 83

avoid 3-fold bonds avoid 2-fold bonds low polarizability

+ high bond strength

additional porosity
air gaps by space creators (porogenes

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 48
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Market Overview

About 10 manufacturer are developing low-k materials, the market value is about 300 Mill. € (2005)
status 2007
Equipment manufacturer try to force the development Manufacturers of chemicals offer Spin-on materials
of CVD-materials

Advantage: due material composition additional porosity

Advantage: for SiO2-based CVD-layers established can be created -> Ultra-low k (ULK)
tools and integration experience exists Disadvantage: problems with integration

Disadvantage: due to temperature limitation T< 400°C organics: (based on C,O,H,F) (polymeric)
in the metal layers there is not much freedom
for material development SiLK (porous polymer, k>2.2) from Dow Chemical

Black Diamond von Applied Materials GX-3 from Honeywell Electronic Materials (Sunnyvale, Calif.)
(based on trimethylsilane, fabricated by Dow Corning, inorganics: (mainly based on Si,O,H,F)
distributed by Air Products silicon-based systems with carbon (or methyl) groups and/or
hydrogen attached (hydrogen silsesquioxane)
CORAL, TOMCATS (porous SiO:C) from Novellus * advantage: better temperature stability, lower density
(based on tetramethyl silane, tetramethylcyclotetrasiloxane, compared to organics
distributed by Air Products) XLK from Dow Corning (porous version of FOx)

ORION (porous SiO:C, k>2.2) from Trikon Technologies Nanoglass E (porous SiO2) from Honeywell Electronic Materials

Most suppliers of CVD-tools offer processes for deposition Air Products (world´s largest producer of SiF4)
of SiO2-based layers with k between 2.7 to 2.4 , porous silica material called MesoELK
layers with k~2.0 were demonstrated
LKDxx (porous MSQ, k>1.9 from JSR (Tokyo),

ZIRKON (porous MSQ, k>1.8) from Rohm and Haas (Shipley)

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba
Modul 1254 AdMOS, 4- 49
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Example of Spin-on Low-k Material

Basic Process: spin-on

typical: Silsesquioxane (abreviated SQ or SSQ)

Silsesquioxane forms precise 3-dim structures (like bucky balls) and with radicals X
properties like polymerisation, solubilization, polaribility, stability,.. can be tailored.
some of the polar Si-O bonds are Formation of cross-linked Oligomeres (here octamere)
replaced by less polar Si-X bonds (creating free space by cage-like arrangement)

O HC H O
Si Si
H CH O O H
O H
H Si Si H C H
O O O
O O Si Si If the X is:
Si Si Si H O
O O C O
O a hydrogen atom then
X Si Si O H Si Si
O HC H O
O H O the crosslink is done by
H
a bridging oxygen (HSQ)
O If X is: O O
H
Si Si O
Si Si
- a methyl-group, then O O O O O
O
Si-O-Si bond is named siloxane the crosslink is done by Si O Si O Si O
Si
O
a bridging CH2 (MSQ) H
C H H O O
Si Si
O O H
Si O Si O
Properties: H H

+: kmin > 2.6

HSQ: k>2.9
-: weak mechanical strength MSQ: k> 2.7
-: low thermal stability, T ~ 500°C
-: bad adhesion -> improved by promoters

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 50
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Example of Spin-on Ultra Low-k Material

Typically in the low-k polymer (the matrix) an additional thermal instable polymer (called porogen, ~ 25 vol %) is added.
At formation temperature of the low-k network the instable polymer decomposes and evaporates, leaving nanopores
H O
Si Si
O O
O
Matrix Porogen
Si O Si H O
O Si Si
H O O
O O O O O
Si Si Si Si Si O Si
O O
O H O O
Si Si O O O
O Si O Si O
HO H O Si Si
O O H
O O Si O
Si Si Si O
O O HH H
Si Si O
O
HO HO O typical: co-polymeres
Si Si
H O O
Si O Si
O - poly(methyl methacrylate-co-dimethylaminoethyl methacrylate)
O
= P(MMA-co-DMAEMA)
O O
Si Si
O O H
typical: silsesquioxane Si O Si O
H H

Typical Process:

SSQ

wafer

spin-coat mixture of matrix bake-out at 430°C, 5min at room temperature

and porogen -> matrix crosslinking at ~200°C porous are remaining
-> decomposition of porogen at 400°C (up to 90% of porogen content)

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 51
4 The Short-Channel MOSFET Integration of Low-k in Cu-Damascene
4.4 Limits of Scaling
O* O*
resist O*
cap layer
ULK
etch stop layer
BPSG
W
Gate Ti/TiN barrier
Source Drain

via etch resist stripping + via clean

* low-k changes properties of resist
* etching changes ULK properties * chemicals/O2-plasma changes ULK
* sealing of porous for resist
(surface, gas incorporation)

sealing/smoothing ULK Cu-fill, Cu-anneal, CMP

* best is use already Cu-barrier (e.g. TaN) * mechanical strength important
* perfect sealing of porous important

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 52
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Air-Gaps as Low-k

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 53
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Limits of Junction Depth Scaling

thin body for double-gate

from: Nanostructures Laboraty at MIT

http://nano-web.mit.edu/annual-report00/13.html

To achieve low contact resistance and shallow junctions selective epitaxial growth could be used

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 54
4 The Short-Channel MOSFET
4.4 Limits of Scaling
Limits of Junction Depth Scaling

INTEL, 45nm n-MOS

Fig. 2 Intel IDF image of 32-nm NMOS gate (left) and Chipworks
image of 45-nm NMOS gate

INTEL, 45nm p-MOS

Saving area but keeping resistance low

-> try vertical S/D
Fig. 3 Comparative cross-sections of Intel 32-nm NMOS (left) and
-> but: sophisticated design for SCE
45-nm PMOS transistors
Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba
Modul 1254 AdMOS, 4- 55
Summary: In this chapter we have seen:

4.1 Shrinking
Economical pressure requires a lateral shrink (channel length) of ~ 13% / year -> area shrink of factor 2 every 3 years

Shrinked devices have the advantage of better dynamic performance, but the disadvantage of worse static behavior

4.2 Short Channel Effects

The disadvantage of worse static behavior appears, if the electrical fields are changed

The classical short channel effect appears, if the Source/Drain depletion zones occupy most of the channel length

This results in a lowering of the threshold voltage and in an IV-characteristics dependent on S/D voltage

This results in higher leakage current, lower S-factor

The classical short channel effect can be analyzed by two similar models:

The Charge-sharing model explains the lowering of threshold voltage by shared depletion zones of Gate and S/D

The DIBL model explains extreme lowering of threshold voltage by channel barrier lowering due to connected S/D depletion zones

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 56
Summary: In this chapter we have seen:

4.2 Short Channel Effects (cont.)

In addition to the classical short channel effect shrinked devices usually show higher and 2/3-dim electric fields

This results in many effects like modifications in carrier transport and break-through phenomena

4.3 Scaling
Scaling describes the attempt to keep the electric fields the same in a shrinked device

The starting point of scaling is the simple, classical long-channel MOSFET without any modifications

Due to external requirements (as given by technological capability and circuit requirements) several scaling models exist:

Electrostatic scaling, with special conditions like Constant-Field Scaling, (Quasi)-Constant-Voltage Scaling, General Scaling

Subthreshold scaling

Scaling rules are overruled by addition of doping structures in the MOSFET structure

Todays and future MOSFET design is high sophisticated task to balance all parameters to a good compromise

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 57
Chap 4 The Short-Channel MOSFET

4.1 Shrinking
Advantages
Disadvantages

4.2 Short Channel Effects

Discovery and first analysis
Quantitative analysis
- Charge Sharing Model
- Drain-Induced Barrier-Lowering Model

4.3 Scaling Models

Electrostatic Scaling
Subthreshold Scaling

4.4 Limits of Scaling

Gate dielectrics, high-k
Interconnect Materials: Cu and low-k

Advanced MOSFETs and Novel Devices Prof.Dr.W.Hansch, Dr. J. Biba

Modul 1254 AdMOS, 4- 58