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This document outlines the objectives and units of two courses: AP5301 Advanced Microprocessors and Microcontrollers Architectures, and AP5005 System on Chip Design. AP5301 covers modern microprocessor and microcontroller architectures including Intel and ARM processors, as well as features such as caches, pipelines, and interrupts. AP5005 focuses on system on chip design including system modeling with SystemC, hardware/software co-design, transaction level modeling, and verification and testing of integrated systems on chip. The goals are to understand advanced processor architectures and gain skills in designing highly integrated systems on a single chip following co-design principles.

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Prabhu Subramaniam
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128 views

Me Syllabus

This document outlines the objectives and units of two courses: AP5301 Advanced Microprocessors and Microcontrollers Architectures, and AP5005 System on Chip Design. AP5301 covers modern microprocessor and microcontroller architectures including Intel and ARM processors, as well as features such as caches, pipelines, and interrupts. AP5005 focuses on system on chip design including system modeling with SystemC, hardware/software co-design, transaction level modeling, and verification and testing of integrated systems on chip. The goals are to understand advanced processor architectures and gain skills in designing highly integrated systems on a single chip following co-design principles.

Uploaded by

Prabhu Subramaniam
Copyright
© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
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AP5301 ADVANCED MICROPROCESSORS AND

MICROCONTROLLERS ARCHITECTURES LTPC


3003
OBJECTIVES:
• To familiarize about the features, specification and features of modern microprocessors.
• To gain knowledge about the architecture of Intel 32 and 64 bit microprocessors and salient
features associated with them.
• To familiarize about the features, specification and features of modern microcontrollers.
• To gain knowledge about the 32 bit microcontrollers based on ARM and PIC32 architectures

UNIT I FEATURES OF MODERN MICROPROCESSORS 9


Evolution of microprocessors - Data and Address buses – clock speed – memory interface -
multi-core architectures – cache memory hierarchy – operating modes – super scaler execution
– dynamic execution – over clocking – integrated graphics processing - performance
benchmarks.

UNIT I HIGH PERFORMANCE CISC ARCHITECTURES 9


Introduction to IA 32 bit architecture – Intel Pentium Processors family tree – Memory
Management – Branch prediction logic - Superscalar architecture – Hyper threading technology
– 64 bit extension technology – Intel 64 bit architecture - Intel Core processor family tree –
Turbo boost technology – Smart cache - features of Nehalem microarchitecture

UNIT II HIGH PERFORMANCE RISC ARCHITECTURE - ARM 9


RISC architecture merits and demerits – The programmer's model of ARM Architecture –
3stage pipeline ARM organization - 3-stage pipeline ARM organization – ARM instruction
execution – Salient features of ARM instruction set - ARM architecture profiles (A, R and M
profiles)

UNIT III FEATURES OF MODERN MICROPROCESSORS 9


Introduction to microcontrollers – microcontroller vs microprocessors – microcontroller
architecture - Processor Core – Memory interfaces– Communication interfaces (SPI,I2C, USB
and CAN) – ADC - PWM – Watchdog timers – Interrupts – Debugging interfaces

UNIT IV HIGH PERFORMANCE MICROCONTROLLER ARCHITECTURES 9


Introduction to the Cortex-M Processor Family - ARM 'Cortex-M3' architecture for
microcontrollers – Thumb 2 instruction technology – Internal Registers - Nested Vectored
Interrupt controller - Memory map - Interrupts and exception handling – Applications of Cotex-
M3 architecture
TOTAL : 45 PERIODS

OUTCOMES:
After completion of the course, the students should be able
• To explain the features and important specifications of modern microprocessors
• To explain the salient features CISC microprocessors based on IA-32 bit and IA-64 bit
architectures
• To explain the salient features RISC processors based on ARM architecture and different
application profiles of ARM core
• To explain the features and important specifications of modern microcontrollers
• To explain about ARM – M3 architecture and its salient features

1
AP5005 SYSTEM ON CHIP DESIGN L TP C
3 00 3
OBJECTIVES:
• understanding of the concepts, issues, and process of designing highly integrated SoCs
following systematic hardware/software co-design & co-verification principles

UNIT I INTRODUCTION 9
Introduction to SoC Design, system level design, methodologies and tools, system hardware: IO,
communication, processing units, memories; operating systems: prediction of execution, real time
scheduling, embedded OS, middle ware; Platform based SoC design, multiprocessor SoC and
Network on Chip, Low power SoC Design

UNIT II SYSTEM LEVEL MODELLING 9


SystemC: overview, Data types, modules, notion of time, dynamic process, basic channels, structure
communication, ports and interfaces, Design with examples

UNIT III HARDWARE SOFTWARE CO-DESIGN 9


Analysis, partitioning, high level optimisations, real-time scheduling, hardware acceleration,
voltage scaling and power management; Virtual platform models, co-simulation and FPGAs for
prototyping of HW/SW systems.

UNIT IV SYNTHESIS 9
System synthesis: Transaction Level Modelling (TLM) based design, automaticTLM generation
and mapping, platform synthesis; software synthesis: code generation, multi task synthesis,
internal and external communication; Hardware synthesis: RTL architecture, Input models,
estimation and optimisation, resource sharing and pipelining and scheduling

UNIT V SOC VERIFICATION AND TESTING 9


SoC and IP integration, Verification : Verification technology options, verification methodology,
overview: system level verification, physical verification, hardware/software co-verification; Test
requirements and methodologies, SoC design for testability - System modeling, test power
dissipation, test access mechanism
TOTAL : 45 PERIODS
OUTCOMES:
• Analyse algorithms and architecture of hardware software inorder to optimise the system based
on requirements and implementation constraints
• Model and specify systems at high level of abstraction
• appreciate the co-design approach and virtual platform models
• Understand hardware, software and interface synthesis

REFERENCES
1. D. Black, J. Donovan, SystemC: From the Ground Up, Springer, 2004.
2. D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner, Embedded System Design: Modeling, Synthesis,
Verification, Springer, 2009
3. Erik Larson, Introduction to advanced system-on-chip test design and optimisation, Springer
2005
4. Grotker, T., Liao, S., Martin, G. & Swan, S. System design with System C, Springer, 2002.
5. Ghenassia, F. Transaction-level modeling with SystemC: TLM concepts and applications for
embedded systems, Springer, 2010.
6. Hoi-junyoo, Kangmin Lee, Jun Kyoungkim, “Low power NoC for high performance
SoCdesing”,CRC press, 2008.
2
AP5094 SIGNAL INTEGRITY FOR HIGH SPEED DESIGN LTPC
3 00 3
OBJECTIVES:
• To identify sources affecting the speed of digital circuits.
• To introduce methods to improve the signal transmission characteristics

UNIT I SIGNAL PROPAGATION ON TRANSMISSION LINES 9 Transmission


line equations, wave solution, wave vs. circuits, initial wave, delay time, Characteristic impedance ,
wave propagation, reflection, and bounce diagrams Reactive terminations – L, C , static field maps of
micro strip and strip line cross-sections, per unit length parameters, PCB layer stackups and layer/Cu
thicknesses, cross-sectional analysis tools, Zo and Td equations for microstrip and stripline Reflection
and terminations for logic gates, fan-out, logic switching , input impedance into a transmission-line
section, reflection coefficient, skin-effect, dispersion

UNIT II MULTI-CONDUCTOR TRANSMISSION LINES AND CROSS-TALK 9 Multi-


conductor transmission-lines, coupling physics, per unit length parameters ,Near and far-end cross-talk,
minimizing cross-talk (stripline and microstrip) Differential signalling, termination, balanced circuits ,S-
parameters, Lossy and Lossles models

UNIT III NON-IDEAL EFFECTS 9 Non-ideal signal return paths – gaps,


BGA fields, via transitions , Parasitic inductance and capacitance , Transmission line losses – Rs, tanδ
, routing parasitic, Common-mode current, differential-mode current , Connectors

UNIT IV POWER CONSIDERATIONS AND SYSTEM DESIGN 9 SSN/SSO ,


DC power bus design , layer stack up, SMT decoupling ,, Logic families, power consumption, and
system power delivery , Logic families and speed Package types and parasitic ,SPICE, IBIS models ,Bit
streams, PRBS and filtering functions of link-path components , Eye diagrams , jitter , inter-symbol
interference Bit-error rate ,Timing analysis

UNIT V CLOCK DISTRIBUTION AND CLOCK OSCILLATORS 9 Timing margin,


Clock slew, low impedance drivers, terminations, Delay Adjustments, canceling parasitic capacitance,
Clock jitter.
TOTAL : 45 PERIODS
OUTCOMES:
• Ability to identify sources affecting the speed of digital circuits.
• Able to improve the signal transmission characteristics.

REFERENCES:
1. Douglas Brooks, Signal Integrity Issues and Printed Circuit Board Design, Prentice Hall PTR,
2003
2. Eric Bogatin , Signal Integrity – Simplified , Prentice Hall PTR, 2003.
3. H. W. Johnson and M. Graham, High-Speed Digital Design: A Handbook of Black Magic,
Prentice Hall, 1993.
4. S. Hall, G. Hall, and J. McCall, High-Speed Digital System Design: A Handbook of Interconnect
Theory and Design Practices, Wiley-Interscience, 2000.

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