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Apb SRAM Core Verification Plan

This verification plan describes an APB SRAM core testbench using a UVM structure. The testbench includes a standalone APB master verification IP as the testbench, with agents, sequencers, drivers, monitors, and a scoreboard to drive and check the APB SRAM core design under test. Tests and sequences will generate APB transactions to verify the core functionality.

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Rohit Pandey
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207 views

Apb SRAM Core Verification Plan

This verification plan describes an APB SRAM core testbench using a UVM structure. The testbench includes a standalone APB master verification IP as the testbench, with agents, sequencers, drivers, monitors, and a scoreboard to drive and check the APB SRAM core design under test. Tests and sequences will generate APB transactions to verify the core functionality.

Uploaded by

Rohit Pandey
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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APB SRAM CORE

VERIFICATION PLAN
Author: Farshad

Revision: 1.0

17 June 2018
Introduction
About APB Verification Environment
A standalone APB master verification IP is developed for using it as testbench with APB SRAM Core. The UVM
testbench structure is shown in the following figure:

Top

Tests
Sequences

Environment
Scoreboard Agent_Config

Env_Config
Agent Sequencer Coverage Monitor

Driver Monitor
Seq_item

APB_SRAM (DUT)

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