Converters with 8-Channel Analog Multiplexer

Using the ADC0808/ADC0809 8-Bit µP Compatible A/D

National Semiconductor
Using the Application Note 247
Larry Wakeman
ADC0808/ADC0809 8-Bit µP September 1980

Compatible A/D Converters

with 8-Channel Analog
Multiplexer
Introduction The second function block, the successive approximation
A/D converter, transforms the analog output of the multi-
The ADC0808/ADC0809 Data Acquisition Devices (DAD) plexer to an 8-bit digital word. The output of the multiplexer
implement on a single chip most the elements of the stan- goes to one of two comparator inputs. The other input is
dard data acquisition system. They contain an 8-bit A/D derived from a 256R resistor ladder, which is tapped by a
converter, 8-channel multiplexer with an address input latch, MOSFET transistor switch tree. The converter control logic
and associated control logic. These devices provide most of controls the switch tree, funneling a particular tap voltage to
the logic to interface to a variety of microprocessors with the the comparator. Based on the result of this comparison, the
addition of a minimum number of parts. control logic and the successive approximation register
These circuits are implemented using a standard metal-gate (SAR) will decide whether the next tap to be selected should
CMOS process. This process is particularly suitable to ap- be higher or lower than the present tap on the resistor ladder.
plications where both analog and digital functions must be This algorithm is executed 8 times per conversion, once
implemented on the same chip. every 8 clock periods, yielding a total conversion time of 64
These two converters, the ADC0808 and ADC0809, are clock periods.
functionally identical except that the ADC0808 has a total When the conversion cycle is complete the resulting data is
unadjusted error of ± 1⁄2 LSB and the ADC0809 has an loaded into the TRI-STATE ® output latch. The data in the
unadjusted error of ± 1 LSB. They are also related to their big output latch can then be read by the host system any time
brothers, the ADC0816 and ADC0817 expandable 16 chan- before the end of the next conversion. The TRI-STATE ca-
nel converters. All four converters will typically do a conver- pability of the latch allows easy interface to bus oriented
sion in ∼100 µs when using a 640 kHz clock, but can convert systems.
a single input in as little as ∼50 µs. The operation of these converters by a microprocessor or
some control logic is very simple. The controlling device first
Functional Description selects the desired input channel. To do this, a 3-bit channel
The ADC0808/ADC0809, shown in Figure 1, can be func- address is placed on the A, B, C input pins; and the ALE
tionally divided into 2 basic subcircuits. These two subcir- input is pulsed positively, clocking the address into the mul-
cuits are an analog multiplexer and an A/D converter. The tiplexer address register. To begin the conversion, the
multiplexer uses 8 standard CMOS analog switches to pro- START pin is pulsed. On the rising edge of this pulse the
vide for up to 8 analog inputs. The switches are selectively internal registers are cleared and on the falling edge the start
turned on, depending on the data latched into a 3-bit multi- conversion is initiated.
plexer address register.

00562301

FIGURE 1. ADC0808/ADC0809 Functional Block Diagram

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TRI-STATE ® is a registered trademark of National Semiconductor Corp.

© 2002 National Semiconductor Corporation AN005623 www.national.com

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Functional Description (Continued) full-scale is of great importance. For example, the potentio-
metric displacement transducers of Figure 2 have this fea-
As mentioned earlier, there are 8 clock periods per approxi- ture. When the wiper is at midscale, the output voltage is
mation. Even though there is no conversion in progress the VO = VF x (Wiper Displacement) = VF x 0.5. This enables the
ADC0808/ADC0809 is still internally cycling through these 8 use of much less accurate and less expensive references.
clock periods. A start pulse can occur any time during this The important consideration for this reference is noise. The
cycle but the conversion will not actually begin until the reference must be “glitch free” because a voltage spike
converter internally cycles to the beginning of the next 8 during a conversion cycle could cause conversion inaccura-
clock period sequence. As long as the start pin is held high cies.
no conversion begins, but when the start pin is taken low the
conversion will start within 8 clock periods.
The EOC output is triggered on the rising edge of the start
pulse. It, too, is controlled by the 8 clock period cycle, so it
will go low within 8 clock periods of the rising edge of the
start pulse. One can see that it is entirely possible for EOC to
go low before the conversion starts internally, but this is not
important, since the positive transition of EOC, which occurs
at the end of a conversion, is what the control logic is looking
for.
Once EOC does go high this signals the interface logic that
the data resulting from the conversion is ready to be read.
The output enable (OE) is then raised high. This enables the
TRI-STATE outputs, allowing the data to be read. Figure 3
shows the timing diagram.

Analog Inputs
RATIOMETRIC INPUTS
The arrangement of the REF(+) and REF(−) inputs is in-
tended to enable easy design of ratiometric converter sys-
tems. The REF inputs are located at either end of the 256R
resistor ladder and by proper choice of the input voltages
several applications can be easily implemented. 00562316

Figure 2 shows a typical input connection for ratiometric

transducers. A ratiometric transducer is a conversion device FIGURE 2. Ratiometeric Converter with Separate
whose output is proportional to some arbitrary full-scale Reference
value. In other words, the transducer’s absolute output value
is of no particular concern but the ratio of the output to the

00562317

FIGURE 3. ADC0808/ADC0809 Timing Diagram

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Analog Inputs (Continued) enables several variations on these basic connections, and
are shown in Figures 5, 6. The magnitude of the reference
Since highly accurate references aren’t required it is pos- voltage, VREF = REF(+) − REF(−), can be varied from about
sible to use the system power supply as a reference, as ∼0.5V to VCC, but the center voltage must be maintained
shown in Figure 4. If the power supply is to be used in this within ± 0.1V of VCC/2. This constraint is due to the design of
manner supply noise must be kept to a minimum to preserve the transistor switch tree, which could malfunction if the
conversion accuracy. If possible the supply should be well offset from center scale becomes excessive. Variation of the
bypassed and separate reference and supply PC board reference voltage can sometimes eliminate the need for
traces, originating as close as possible to the power supply external gain blocks to scale the input voltage to a full-scale
or regulator, should be used. This is illustrated in Figure 4. range of 5V.
External accessibility of both ends of the resistor ladder

00562315

FIGURE 4. Ratiometric Converter with Power Supply Reference

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Analog Inputs (Continued)

00562303

FIGURE 5. Mid-Supply Centered Reference Using LM336 2.5V Reference

00562304

FIGURE 6. Mid-Supply Centered Reference Using Buffered Resistors

Figure 5 shows a center referencing technique, using two

equal resistors to symmetrically offset an LM336 2.5V refer-
ence, from both supplies. The offset from either supply is:

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Analog Inputs (Continued) unregulated supply voltage > 5V is required, but the
LM336-5.0 functions as both a regulator and reference. The
These resistors should be chosen so that they limit current dropping resistor R must be chosen so that, for the whole
through the LM336 to a reasonable value, say 5 mA. The range of supply currents needed by the system, the
total resistor current is: LM336-5.0 will stay in regulation. As in Figure 4 separate
IR = IREF + ILADDER + ITRAN supply and reference traces should be used to maintain a
noiseless supply.
where ILADDER is the 256R ladder current, ITRAN is the
current through all the transducers, and IREF is the current If the system requires more power, an op amp can be used
through the reference. R1 and R2 should be well matched as shown in Figure 8 to isolate the reference and boost the
and track each other over temperature. supply current capabilities. Here again, a single unregulated
supply is required.
For odd values of reference voltage, the reference could be
replaced by a resistor, but due to loading and temperature
DIFFERENTIAL INPUTS
problems, these resistors should be buffered to the REF(+)
and REF(−) inputs, Figure 6. The power supply must be well Differential measurements can be obtained by playing a little
bypassed as supply glitches would otherwise be passed to software trick. This simply involves sequentially converting
the reference inputs. The reference voltage magnitude is: two channels then subtracting the two results. For example,
if the difference voltage between channel 1 and 2 is required,
merely convert channel 1 and read the result. Then convert
channel 2, input the result, and subtract it from the first
result. (See Figure 9.) When using this procedure, both input
signals must be stable throughout both conversion times or
the end result will be incorrect. One way to get around this is
There are several op amps that can be used for buffering this
to use two sample/holds which are sampled at the same
ladder. Without adding another supply, an LM358 could be
time.
used if the REF(+) input is not to be set above 3.5V. The
LM10 can swing closer to the positive supply and can be
used if a higher VREF(+) voltage is needed.
As the REF(+) to REF(−) voltage decreases the incremental
voltage step size decreases. At 5V one LSB represents
∼20 mV, but at 1V, one LSB represents ∼4 mV.
As the reference voltage decreases, system noise will be-
come more significant so greater precaution should be en-
forced at lower voltages to compensate for system noise;
i.e., adequate supply and reference bypassing, and physical
as well as electrical isolation of the inputs.

ABSOLUTE ANALOG INPUTS

The ADC0808/ADC0809 may have been designed to easily
utilize ratiometric transducers, but this does not preclude the
use of non-ratiometric inputs. A second type of input is the
absolute input. This is one which is independent of the
reference. This implies that its absolute numerical voltage
value is very critical, and to accurately measure this voltage
the accuracy of the reference voltage becomes equally criti-
cal. The previous designs can be modified to accommodate
absolute input signals by using a more accurate reference.
In Figure 4 the power supply reference could be replaced by 00562320
LM336-5.0 reference. R1 and R2 of Figure 6, and R1 and R3
of Figure 7 may have to be made more accurately equal. FIGURE 7. Precision Reference used as a Power
In some small systems it is possible to use the precision Supply
reference as the power supply as shown in Figure 7. An

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Analog Inputs (Continued)

00562322

FIGURE 9. Software Controlled Differential Converter

A second method is to use two chips to convert a differential

channel, Figure 10. Typically each channel 1 would be con-
nected to opposite sides of the differential input. Both con-
verters are started simultaneously. When both converters’
00562321 EOC outputs go high the output of the AND gate will go high
indicating that the data is ready to be read.
FIGURE 8. Precision Reference Buffered for Power The circuit in Figure 10 can be slightly modified to provide
Supply increased data throughput by using two converters in a
parallel data acquisition scheme. Figure 11 shows this circuit
in which all the input channels are connected in pairs
through LF398 monolithic sample/holds. Under normal op-
eration a sample/hold is accessed through an MM74C42
which will pulse an MM74C221, generating a sample pulse.
After a sample/hold is done sampling the signal, the appro-
priate channel is started. If this process is alternated be-
tween two converters the sample rate can be doubled.

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Analog Inputs (Continued)

00562306

FIGURE 10. Dual Converter Differential Circuit

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Analog Inputs (Continued) pedance of the transducer or buffer. Using transducers with
large source impedances can cause errors due to compara-
ANALOG INPUT CONSIDERATIONS tor input currents.
Analog inputs into the ADC0808/ADC0809 can handle any
input signal that is maintained within the supply limits, but
some careful consideration must be given to the output im-

00562307

FIGURE 11. Parallel Data Acquisition with Sample/Holds

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Analog Inputs (Continued) and, due to speed and drive requirements, incorporate many
TTL circuits. The data outputs of the ADC0808/ADC0809 are
To understand the nature of these currents a short discus- capable of driving one standard TTL load which is adequate
sion of comparator operation is required. Figure 12 shows a for most small systems, but for larger systems extra buffer-
simplified model of the comparator and multiplexer. This ing may be necessary. The EOC output is not quite as
comparator alternately samples the input voltage and the powerful as the data outputs, but normally it is not bussed
ladder voltage. As it samples the input, CC and CP are like the data outputs.
charged up to the input voltage. It then samples the ladder The converter inputs are standard CMOS compatible inputs.
and discharges the capacitor. The net charge difference is When TTL outputs are connected to any of the digital inputs
determined by a modified inverter chain and results in a 1 or a pull-up resistor should be tied from the TTL output to VCC,
0 state at the output. ∼ 5 kΩ. This will ensure that the TTL will pull-up above 3.5V.
Eight samples are made per conversion, resulting in eight Usually the converter clock will be derived from the micro-
spikes of varying magnitude on the input. processor system clock. Some slower microprocessor
If the source resistance is large, it adds to the RC time clocks can be used directly, but at worst a few divider stages
constant of the switched capacitor which will inhibit the input may be necessary to divide microprocessor clock frequen-
from settling properly, causing errors. As one might expect, cies above 1.2 MHz to a usable value.
the maximum source resistance allowable for accurate con- The timing of the START and ALE pulses relative to channel
versions is inversely proportional to clock frequency. This selection and signal stability can be critical. The simplest
resistance should be ≤1 kΩ at 1.2 MHz and ≤2 kΩ at 640 approach to microprocessor interfaces usually ties START
kHz. If a potentiometer-type ratiometric transducer is used it and ALE together. When these lines are strobed the address
should be ≤5 kΩ at 1.2 MHz and ≤10 kΩ at 640 kHz. is strobed into the address register and the conversion is
If large source impedances are unavoidable (≥2 kΩ at started. The propagation delay from ALE to comparator input
640 kHz), the transient errors can be reduced by placing a of the selected input signal is about ∼3.0 µs (input source
bypass capacitor ≥0.1 µF from the analog inputs to ground. resistance << 1 kΩ). If the start pulse is very short the
This will reduce the spikes to a small average current which comparator can sample the analog input before it is stable.
will cause some error as well, but this can be much less than When using a slow clock ≤500 kHz the sample period of the
the error otherwise incurred. The maximum voltage error for comparator input is long enough to allow this delay to settle
a potentiometer input with a bypass capacitor added is: out.
If the ADC0808/ADC0809 clock is > 500 kHz, a delay be-
tween the START and ALE pulses is required. There are
three basic methods to accomplish this. The first possibility
is to design the microprocessor interface so that the START
and ALE inputs are separately accessible. This is simple if
where RPOT = total potentiometer resistance; IIN = maximum
some extra address decoding is available. Separate acces-
input current at 640 kHz, 2 µA; and Ck=clock frequency.
sibility of the START and ALE pins allows the microproces-
For standard buffer source impedance the maximum error is: sor, via software, to set the delay time between the START
and ALE pulses.
If extra decoding is not available, then START and ALE could
be tied together. To obtain the proper delay, the micropro-
cessor would cause START/ALE to be strobed twice by
where RS = buffer source resistance; IIN = the maximum executing the load and start instruction twice. The first time
input current at 640 kHz, 2 µA; and Ck = clock frequency. this instruction is executed, the new channel address is
loaded and the conversion is started. The second execution
of this instruction will reload the same channel address and
Microprocessor Interfacing restart the conversion. But since the multiplexer address
The ADC0808/ADC0809 converters were designed to inter- register contents are unchanged the selected analog input
face to most standard microprocessors with very little exter- will have already settled by the time the second instruction is
nal logic, but there are a few general requirements which issued. Actual implementations of these ideas are shown in
must be considered to ensure proper converter operation. following sections.
Most microprocessors are designed to be TTL compatible

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Microprocessor Interfacing (Continued)

00562308

FIGURE 12. Analog Multiplexer and Comparator Input Model

A third possibility when ALE and START are tied together is Interfacing to the 8080
to stretch the microprocessor derived ALE/START pulse by
inserting a one-shot at these inputs and creating a positive The simplest interface would contain no address decoding,
pulse > 3 µs. Since ALE loads the multiplexer register on the which may seem unreasonable; but if the system ports are
positive going edge of the pulse and START begins the I/O mapped, up to 8 of them can be connected to the CPU
conversion on the falling edge, the width of the pulse sets the with no decoding. Each of the 8 I/O address lines would
ALE to START delay time. serve as a simple port enable line which would be gated with
read and write strobes to select a particular port. This
Most microprocessor interfaces would be designed such that
scheme is shown in Figure 13. A7 is the address line used
a START pulse is issued by a memory or I/O write instruc-
and, whenever it is zero and an I/O read or write is low, the
tion, although a memory or I/O read can be used. The ALE
port is accessed. This implementation shows A, B, C con-
strobe on the other hand, requires a write by the CPU when
nected to D0, D1, D2 causing the information on the data
A, B, and C are connected to the data bus, and could use a
bus to select the channel, but A, B, and C could be con-
read instruction if A, B, and C are connected to the address
nected to the address bus, with a loss of only 3 ports. Both
bus, but the software could get confusing. The logic to derive
decoding schemes are tabulated in Figure 14. (Remember
the OE strobe must be connected to the microprocessor so
A, B, C inputs are only valid when selecting a channel to
that a memory or I/O read instruction will cause OE to be
convert, and are not used to read data.)
pulsed. A read is required since the ADC0808/ADC0809
data must be read.

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Interfacing to the 8080 (Continued)

00562309

FIGURE 13. Minimum 8080/8224/8228 Interface

A7 A6 A5 A4 A3 A2 A1 A0 D2 D1 D0 Output Port
Description
1 1 1 1 1 1 1 0 X X X Spare Port
1 1 1 1 1 1 0 1 X X X Spare Port
1 1 1 1 1 0 1 1 X X X Spare Port
1 1 1 1 0 1 1 1 X X X Spare Port
1 1 1 0 1 1 1 1 X X X Spare Port
1 1 0 1 1 1 1 1 X X X Spare Port
1 0 1 1 1 1 1 1 X X X Spare Port
0 1 1 1 1 1 1 1 0 0 0 Channel 0 Port
0 1 1 1 1 1 1 1 0 0 1 Channel 1 Port
0 1 1 1 1 1 1 1 0 1 0 Channel 2 Port
0 1 1 1 1 1 1 1 0 1 1 Channel 3 Port
0 1 1 1 1 1 1 1 1 0 0 Channel 4 Port
0 1 1 1 1 1 1 1 1 0 1 Channel 5 Port
0 1 1 1 1 1 1 1 1 1 0 Channel 6 Port
0 1 1 1 1 1 1 1 1 1 1 Channel 7 Port

FIGURE 14. Write Address Decoding for 8080 Output Ports (A, B, C Connected to D0, D1, D2)

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Interfacing to the 8080 (Continued) loading and starting the conversion. When the CPU reads
the ADC0808/ADC0809 the OE input is taken high, and the
data outputs are enabled.
A7 A6 A5 A4 A3 A2 A1 A0 Output Port Figure 13 implements a simple interrupt concept where EOC
Description is tied directly to the 8080 interrupt input. When the INS8228
is used and the INTA pin is tied high through a 1 kΩ resistor,
0 1 1 1 1 0 0 0 Channel 0 Port the interrupt will cause a restart, RST, instruction to be
0 1 1 1 1 0 0 1 Channel 1 Port executed, which will then cause a jump to a restart vector
0 1 1 1 1 0 1 0 Channel 2 Port and execution of the interrupt routine. If a very simple
multi-interrupt system is desired, a wire OR’ed configuration
0 1 1 1 1 0 1 1 Channel 3 Port
employing resettable latches as shown in Figure 13’s inset
0 1 1 1 1 1 0 0 Channel 4 Port can be used. In this simple design the MM74C74 is reset
0 1 1 1 1 1 0 1 Channel 5 Port when the ADC0808/ADC0809 data is read. If more compli-
cated interrupt structures are required, then an interrupt
0 1 1 1 1 1 1 0 Channel 6 Port
controller is usually the best solution.
0 1 1 1 1 1 1 1 Channel 7 Port
The I/O port address structure for Figure 13’s implementa-
1 1 1 1 0 X X X Spare Port tion is shown in Figure 14. If the A, B, C inputs are tied to A0,
1 1 1 0 1 X X X Spare Port A1, A2 inputs the port structure is as shown in Figure 15. The
1 1 0 1 1 X X X Spare Port latter method makes each channel look like a separate port
address, whereas if A, B, C are tied to the data bus the
1 0 1 1 1 X X X Spare Port ADC0808/ADC0809 looks like one start conversion port ad-
X = don’t care dress whose channel is selected by the 3-bit status word
written to it on the data bus.
FIGURE 15. Modified Write Address Decoding for 8080
Output Ports (A, B, C Connected to A0, A1, A2) Figure 16 shows a slightly more complex interface, where
the address is partially decoded by a DM74LS139, dual 2-4
Two LSTTL NOR gates are used to generate the ADC0808/ line decoder which creates the read and write strobes to
ADC0809 read/write strobes. When the 8080 writes to the operate the converter. This design interfaces to the proces-
ADC0808/ADC0809 the ALE and START inputs are strobed, sor in a polled type of interface. An MM80C97 TRI-STATE
buffer is used to buffer the EOC line to the data bus, as well
as provide the correct level for the START, ALE, and OE
pulses. The converter clock is a divided 8080 system clock.

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Interfacing to the 8080 (Continued)

00562310

Address A7–A0 Description

0 0 X X X X X X Write-Start Conv.
0 0 X X X X X X Read-Input Data
0 1 X X X 0 0 0 Channel 1 Select
0 1 X X X 0 0 1 Channel 2 Select
0 1 X X X 0 1 0 Channel 3 Select
0 1 X X X 0 1 1 Channel 4 Select
0 1 X X X 1 0 0 Channel 5 Select
0 1 X X X 1 0 1 Channel 6 Select
0 1 X X X 1 1 0 Channel 7 Select
0 1 X X X 1 1 1 Channel 8 Select
0 1 X X X X X X Read-Input EOC

FIGURE 16. 8080/8224/8228 Interface Using Partial Decoding

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Interfacing to the 8080 (Continued) than A0, A1, A2, so that the information on the data bus
selects the channel to be converted. Figure 16 can be con-
Typically, the software to use Figure 16 would first select the nected in an interrupt mode by incorporating the interrupt
desired channel by writing the channel address to the ALE flip-flop of Figure 13.
port address, 01XXXCBA, where X=don’t care, and CBA is A few typical utility routines to operate the ADC0808/
the channel address. Next the conversion is started by writ- ADC0809 application in Figure 13 are shown in Figure 17.
ing to the START address, 00XXXXXX. Now the processor These routines assume that the resettable interrupt flip-flop
must wait a few instruction cycles to allow EOC to fall. Once is used. Figure 18 illustrates some typical polled I/O routines
EOC falls, its status can be checked by reading the EOC for Figure 16. Notice that in Figure 17 the OUT START1
line, address 01XXXXXX. When the EOC line is detected instruction is executed twice to allow the analog input signal
high again (a low on DO), the data can be read by accessing to settle as discussed earlier.
the OE port, address 00XXXXXX. As in the previous ex-
ample the A, B, C inputs can be tied to D0, D1, D2 rather

00562325

FIGURE 17. Typical 8080 Resettable Interrupt I/O Routines

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Interfacing to the 8080 (Continued)

00562326

FIGURE 18. Typical Polled I/O Routines for ADC0808/ADC0809

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Interfacing to the 8080 (Continued) memory would be set aside, as is accomplished by the
DM8131. Figure 20 also illustrates a typical 6800 interrupt
The application in Figure 19 uses a 6-bit bus comparator and scheme using a flip-flop and open collector transistor. The
a few gates to decode a read and write strobe. Viewed from interrupt is reset when the data is read. If more ports are
the CPU this interface looks like a bidirectional data port needed, a decoder could be added as shown in Figure 21.
whose address is set by the logic levels on the Tn inputs of Figure 21 also illustrates a polled I/O mode using TRI-STATE
the DM8131 comparator. When data is written to the buffer to gate EOC onto the data bus. As with the INS8080
ADC0808/ADC0809 the 3 least significant bits on the ad- the A, B, C inputs of the ADC0808/ADC0809 can be con-
dress bus define the channel to be converted. The rest of the nected to the address bus or the data bus.
bits are decoded to provide the START and ALE strobes. The 6800 differs from the INS8080 in that the 6800 has a
When the conversion is completed EOC sets the interrupt single read/write (R/W) strobe and a valid memory address
flip-flop, and when the data is read the interrupt is reset. (VMA), whereas the INS8080 has separate read and write
Both the decoder and the bus comparator methods of ad- strobes (I/OR and I/OW). Normally, to obtain a read pulse,
dress decoding have their own advantages. Bus compara- VMA, R/W and φ2 are gated together and, for a write R/W is
tors will more completely decode addresses but are capable inverted. φ2 is the 6800 phase 2 system clock. Also notice
of only a limited number of port strobes. Decoders, on the that the 6800 INT interrupt input is active low. This enables a
other hand, provide less decoding but more port strobes. standard wired-OR open collector design to be implemented.
There is a trade off for minimum parts systems as far as Figure 22 illustrates some typical 6800 software utility rou-
which route to go, and it will depend on the CPU and type of tines for either polled or interrupt interfaces. Again notice
system. double start instructions.

INTERFACING TO THE 6800 Z80 INTERFACE

The ADC0808/ADC0809 easily interface to more than one Interfacing the Z80 to the ADC0808 is much the same as
microprocessor. The 6800 can also be used to control the interfacing to an 8080/8224/8228 CPU group. CPU instruc-
converter. The 6800 has no separate I/O address space so tion timing is very similar, except the read/write control sig-
all I/O transfers must be memory mapped. In general more nals are slightly different. Instead of the I/OW write strobe
address decoding logic is required to ensure that the I/O there is the IOREQ and WR and instead of I/OR, IOREQ and
ports don’t overlap existing memory. For small systems a RD are supplied.
partial address decoding scheme is shown in Figure 20.
Generally, if several ports are desired, a small block of

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Interfacing to the 8080 (Continued)

00562311

FIGURE 19. Interrupt-Type 8080/8224/8228 Interface Using 6-Bit Bus Comparator

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Interfacing to the 8080 (Continued)

00562327

FIGURE 20. Typical 6800 Interface with Partial Address Decoding

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Interfacing to the 8080 (Continued)

00562328

FIGURE 21. Full Decoded 6800 Interface Address

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Interfacing to the 8080 (Continued)

00562329

FIGURE 22. Typical I/O Routines for ADC0808/ADC0809 and 6800 Interface

Figure 23 shows a very simple Z80 interface, which is similar

to the INS8080 interface of Figure 13, except that the inter-

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Interfacing to the 8080 (Continued) cated medium throughput applications can be handled with a
minimum of extra hardware, but additional hardware can
rupt flip-flop design is closer to the 6800 designs. This is increase flexibility and simplify software. Putting both the
because the Z80 INT is active low as is the 6800, but the multiplexer and A/D on the same chip frees the designer
INS8080 INT is active high. from matching multiplexers and A/Ds to implement a 7 or
Figure 24 shows a fully decoded bus comparator design 8-bit accurate system. Design time and overall system cost
where the DM8131 decodes 5 address bits and the IOREQ can be reduced by using these low cost converters.
I/O request strobe. Two NOR gates gate the RD and WR
strobes for ALE, START and OE inputs.

Conclusion
Both the ADC0808 and the ADC0809 can be easily used in
microprocessor controlled environments. Many sophisti-

00562313

FIGURE 23. Simple Z80 Interface

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Conclusion (Continued)

00562314

FIGURE 24. Z80 Partial Decoding Interface

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 Converters with 8-Channel Analog Multiplexer
Using the ADC0808/ADC0809 8-Bit µP Compatible A/D
Notes

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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform
into the body, or (b) support or sustain life, and can be reasonably expected to cause the failure of
whose failure to perform when properly used in the life support device or system, or to affect its
accordance with instructions for use provided in the safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.