A

Project Report On

ELECTRONIC VOTING MACHINE

Submitted in partial fulfilment of the requirements for award of the
degree of
BACHELOR OF TECHNOLOGY
In
ELECTRONICS AND COMMUNICATION ENGINEERING
By
B. NITYANAND KUMAR (11715016)
B. MOHAN SAI (11714356)
K. VENKAT RAO (11707888)
K. NIKHIL SAI (11713709)
Under the guidance of
Mr.SRIDHRA SHETTY
AGM , CED
Of
ECIL-ECIT
ELECTRONICS CORPORATION OF INDIA LIMITED
(A Government of India Enterprise)
 DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
LOVELY PROFESSIONAL UNIVERSITY

DECLARATION

We hereby declare that the project entitled Electronic Voting Machine in

partial fulfilment of the requirements for the award of degree of Bachelor of
Technology in Electrical and Electronics Engineering. This dissertation is our
original work and the project has not formed the basis for the award of any degree,
associate ship, fellowship or any other similar titles and no part of it has been
published or sent for the publication at the time of submission.

B. NITYANAND KUMAR(11715016)
B. MOHAN SAI(11714356)
K. VENKAT RAO(11707888)
K. NIKHIL SAI(11713709)

ACKNOWLEDGEMENT
 We wish to take this opportunity to express our deep gratitude to all those who
helped, encouraged, motivated and have extended their cooperation in various ways
during our project work. It is our pleasure to acknowledgement the help of all those
individuals who was responsible for foreseeing the successful completion of our
project.

We would like to thank Mr. Mr. SRIDHRA SHETTY (AGM , CED)

and express our gratitude with great admiration and respect to our project guide Mr. T.
Naveen Kumar Reddy and Ms. K.SIVA RAMALAKSHMI for their valuable
advice and help throughout the development of this project by providing us with
required information without whose guidance, cooperation and encouragement, this
project couldn’t have been materialized.

Last but not the least; we would like to thank the entire respondents for
extending their help in all circumstances.

B. NITYANAND KUMAR(11715016)

B. MOHAN SAI(11714356)
K. VENKAT RAO(11707888)
K. NIKHIL SAI(11713709)
 CONTENTS

I. Abstract

II. Organization Profile

III. VLSI Introduction

IV. FPGA Design Flow

V. Xilinx Procedure

VI. Project Description

VII. RTL Schematic

VIII. Waveforms

IX. Applications

X. Conclusion
 ABSTRACT

Surpassing of the planned budget and delivery time is a common feature during the
implementation of building investments in Poland. Only a small number of companies use
effective methods of project monitoring during investment performance. One of the
popular tools used to control projects with regard to cost and time is the earned value
method (EVM). There is, however, no detailed guidance how to deploy the method to the
specific characteristics and conditions during the execution of building investments. This
fact has contributed to this paper, which presents the results of application and adaptation
of the earned value method (EVM) and its further extensions in the control of building
projects during their execution (with regard to cost and time), prediction of the final
duration and costs, and presentation of the effects resulting from calculations. The
analyses were performed in terms of the contractor for 5 selected completed and ongoing
building projects in Poland.

5
 ORGANIZATION PROFILE

ECIL was setup under the department of Atomic Energy in the year 1967 with a
view to generate a strong indigenous capability in the field of professional grade
electronic. The initial accent was on self-reliance and ECIL was engaged in the Design
Development Manufacture and Marketing of several products emphasis on three
technology lines viz. Computers, control systems and communications. ECIL thus evolved
as a multi-product company serving multiple sectors of Indian economy with emphasis on
import of country substitution and development of products and services that are of
economic and strategic significance to the country.
Electronics Corporation of India Limited (ECIL) entered into collaboration with
OSI Systems Inc. (www.osi-systems.com) and set up a joint venture "ECIL_RAPSICAN
LIMITED". This Joint Venture manufacture the equipment’s manufactured by
RAPSICAN, U.K, U.S.A with the same state of art Technology, Requisite Technology is
supplied by RAPSICAN and the final product is manufactured at ECIL facility.
Recognizing the need for generating quality IT professionals and to meet the
growing demand of IT industry, a separate division namely CED has been established to
impart quality and professional IT training under the brand name of ECIT. ECIT, the
prestigious offshoot of ECIL is an emerging winner and is at the fore front of IT education
in the country.

Mission
ECIL’s mission is to consolidate its status as a valued national asset in the area of
strategic electronics with specific focus on Atomic Energy, Defense, Security and such
critical sectors of strategic national importance.

Objectives

6
 1. To continue services to the country’s needs for the peaceful uses Atomic Energy.
Special and Strategic requirements of Defence and Space, Electronics Security
System and Support for Civil aviation sector.
2. To establish newer Technology products such as Container Scanning Systems and
Explosive Detectors.
3. To re-engineer the company to become nationally and internationally competitive
by paying particular attention to delivery, cost and quality in all its activities.
4. To explore new avenues of business and work for growth in strategic sectors in
addition to working realizing technological solutions for the benefit of society in
areas like Agriculture, Education, Health, Power, Transportation, Food, Disaster
Management etc.

Divisions
The Company is organized into divisions serving various sectors, national and
Commercial Importance. They are Divisions serving nuclear sector like Control &
Automation Division (CAD), Instruments & Systems Division (ISD), Divisions Serving
defence sector like Communications Division (CND), Antenna Products Division (APD),
Servo Systems Division (SSD) etc., Divisions handling Commercial Products are Telecom
Division (TCD), Customer Support Division (CSD), Computer Education Division (CED).

Exports
ECIL is currently operating in major business EXPORT segments like Instruments
and systems design, Industrial/Nuclear, Servo Systems, Antenna Products,
Communication, Control and Automation and several other components.

Services
The company played a very significant role in the training and growth of high
calibre technical and managerial manpower especially in the fields of Computers and
Information Technology. Though the initial thrust was on meeting the Control &
7
Instrumentation requirements of the Nuclear Power Program, the expanded scope of self-
reliance pursued by ECIL enabled the company to develop various products to cater to the
needs of Defence, Civil Aviation, Information & Broadcasting, Tele communications, etc.

8
 VLSI INTRODUCTION

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by

combining thousands of transistors into a single chip. VLSI began in the 1970s when
complex semiconductor and communication technologies were being developed. The
microprocessor is a VLSI device. Before the introduction of VLSI technology most ICs
had a limited set of functions they could perform. An electronic circuit might consist of a
CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one
chip.

Hardware description language

In electronics, a hardware description language (HDL) is a specialized computer language

used to program the structure, design and operation of electronic circuits, and most
commonly, digital logic circuits.

A hardware description language enables a precise, formal description of an electronic

circuit that allows for the automated analysis, simulation, and simulated testing of an
electronic circuit. It also allows for the compilation of an HDL program into a lower level
specification of physical electronic components, such as the set of masks used to create an
integrated circuit.

Verilog

Verilog is a Hardware Description Language; a textual format for describing electronic

circuits and systems. Applied to electronic design, Verilog is intended to be used for
verification through simulation, for timing analysis, for test analysis (testability analysis
and fault grading) and for logic synthesis.

The Verilog HDL is an IEEE standard - number 1364. The first version of the IEEE
standard for Verilog was published in 1995. A revised version was published in 2001; this
9
is the version used by most Verilog users. The IEEE Verilog standard document is known
as the Language Reference Manual, or LRM. This is the complete authoritative definition
of the Verilog HDL.

IEEE Std 1364 also defines the Programming Language Interface, or PLI. This is a
collection of software routines which permit a bidirectional interface between Verilog and
other languages.

Verilog as both a language and a simulator. At the same time, Synopsys was marketing the
top-down design methodology, using Verilog. This was a powerful combination.

Modelling Styles in Verilog HDL

Normally we use Three type of Modelling Style in Verilog HDL -

1. Data Flow Modelling Style.

2. Gate level Modelling Style.

3. BehaviouralModelling Style.

1. Data Flow Modelling Style - Data Flow Modelling Style Shows that how the data /
signal flows from input output through the registers / Components. Data Flow Modelling
Style works on Concurrent Execution.

2. Gate levelModellingStyle:

Gate level Modelling Style shows the Graphical Representation of modules/ instances /
components with their Interconnection. In Gate Modelling Style We defines that how our
Components / Registers / Modules are Connected to each other using Nets/ Wires.
Gatelevel Modelling Style works on Concurrent Execution.

3.BehaviouralModelling Style -

10
BehaviouralModelling Style shows that how our system performs according to current
input values. In Behavioural Modelling, we define that what value we get at the output
corresponding to input values.

We Defines the function / Behaviour of our Digital Systems in BehaviouralModelling

Style.

BehaviouralModelling Style works on Sequential Execution.

11
 FPGA DESIGN FLOW OVERVIEW

The ISE® design flow comprises the following steps: design entry, design synthesis,
design implementation, and Xilinx® device programming. Design verification, which
includes both functional verification and timing verification, takes places at different
points during the design flow. This section describes what to do during each step. For
additional details on each design step, click on a link below the following figure.

 Design Entry
 Design Synthesis and verification
 Design Implementation and verification
 Device Programming
 In-Circuit Verification

12
Design Entry

Create an ISE project as follows:

 Create a project.
 Create files and add them to your project, including a user constraints (UCF) file.
 Add any existing files to your project.
 Assign constraints such as timing constraints, pin assignments, and area constraints.

Functional Verification

You can verify the functionality of your design at different points in the design flow as
follows:

 Before synthesis, run behavioural simulation (also known as RTL simulation).

 After Translate, run functional simulation (also known as gate-level simulation),
using the SIMPRIM library.
 After device programming, run in-circuit verification.

Design Synthesis

Synthesize your design.

Design Implementation

Implement your design as follows:

1. Implement your design, which includes the following steps:

a. Translate
b. Map
c. Place and Route

13
 2. Review reports generated by the Implement Design process, such as the Map
Report or Place & Route Report, and change any of the following to improve your
design:
a. Process properties
b. Constraints
c. Source files
3. Synthesize and implement your design again until design requirements are met.

Timing Verification

You can verify the timing of your design at different points in the design flow as follows:

1. Run static timing analysis at the following points in the design flow:
1.1. After Map
1.2. After Place & Route
2. Run timing simulation at the following points in the design flow:
2.1. After Map (for a partial timing analysis of CLB and IOB delays)
2.2. After Place and Route (for full timing analysis of block and net delays)

Xilinx Device Programming

Program your Xilinx device as follows:

1. Create a programming file (BIT) to program your FPGA.

2. Generate a PROM or ACE file for debugging or to download to your device.
Optionally, create a JTAG file.
3. Use impact to program the device with a programming cable.

14
15
 XILINX ISE 14.7 PROCEDURE

Xilinx ISE means Xilinx® Integrated Software Environment (ISE). This Xilinx® design
software suite allows you to take your design from design entry through Xilinx device
programming. The ISE Project Navigator manages and processes your design through
several steps in the ISE design flow. These steps are Design Entry, Synthesis,
Implementation, Simulation/Verification, and Device Configuration.

So, the steps are as follows;

Open Xilinx ISE

To open the Xilinx ISE 14.7, click on the Xilinx icon or ISE Simulator on the desktop or
go to the Start -> Programs -> Xilinx ISE Design Suit 14.7 -> ISE -> Project
Navigator. You can close the window for the "Tip of the Day".

Create a project
In this section, you will create a new ISE project. A project is a collection of all files
necessary to create and to download a design to a selected FPGA or CPLD device.

1. Select File > New Project. The New Project Wizard appears.
2. First, enter a location (directory path) for the new project, then give a name for the
project. For example, we name it Counter01.
3. Select HDL from the Top-Level Module Type list, indicating that the top-level file
in your project will be HDL, rather than Schematic or other stuffs.
4. Click on Next to move to the project properties page.
5. Fill in the properties in the table as shown below:
6. Device Family: Spartan3E
7. Device: XC3S100E
8. Package: VQ100
9. Speed: -5
10. Synthesis Tool: XST [VHDL/Verilog]
11. Simulator: ISE Simulator [VHDL/Verilog]
12. Preferred Language: VERILOG
13. All the rest should be default
14. Click Next to proceed to the Create New Source window in the New Project
Wizard. At the end of the next section, your new project will be created.

16
Create VERILOG Source
In this section, you will create a top-level HDL file for your design. You are going to
design an up-down counter which is the same as what you did in the previous lab.
Click New Source in the New Project Wizard to add to one new source to your
project.

1. Type in the file name.

2. Select VERILOG Module as the source type in the New Source Dialog box.
3. Verify that the Add to Project checkbox is selected.
4. Click Next.
5. Define the ports for your VERILOG source. For example,
o In the Port Name column, type the port names on three separate rows:
CLOCK, DIRECTION, and COUNT_OUT.
o In the Direction column, indicate whether each port is an input, output, or
inout. For CLOCK and DIRECTION, select in from the list. For the
COUNT_OUT, select out from the list.
o To indicate that COUNT_OUT is a 4-bit bus, use the arrows to select 3 in
the MSB (Most Significant Bit) field, and select 0 in the LSB (Least
Significant Bit) field.
6. Click Next in the Define Module dialog box.
7. Click Finish in the New Project Wizard - Summary dialog box to complete the new
source file template.
8. If the following window appears, click on "yes".
9. Click Next in the New Project Wizard.
10. Click Next again.
11. Click Finish in the New Project Wizard - Project Summary dialog box.
ISE creates and displays the new project in the Source in Project window and adds
the file to the project.

The file contains:

o Module declaration for counter with input and output ports.

Enter and Edit VERILOG Code

After entering the code proceed to Checking the Syntax of the New Counter.

17
Check the Syntax of your VERILOG source - Synthesize Your Code
When source files are complete, the next step is to check the syntax of the design. Syntax
errors and typos can be found using this step.

1. Select the counter design source in the ISE Sources window to display the related
processes in the Processes for Source window.
2. Click + next to the Synthesize-XST process to expand the hierarchy.
3. Double-click on the Synthesize -XS process.
When an ISE process completes, you will see a status indicator next to the process
name.
o If the process completed successfully, a green check mark appears.
o If there were errors and the process failed, a red X appears.
o A yellow exclamation point means that the process completed successfully,
but some warnings occurred.
o An orange question marks means the process is out of date and should be
run again.
4. Look in the Console tab of the Transcript window and read the output and status
messages produced by any process you run.
5. You must correct any errors found in your source files. If you continue without
valid syntax, you will not be able to simulate or synthesize your design.
6. You would like to see "Process 'synthesis' completed successfully". or "Process
'Check Syntax' completed successfully".

Design Simulation - Simulate the Module Using the ISE Simulator

Create a Test Bench for Simulation

This test bench waveform is a graphical view of a test bench. It is used with simulator to
verify that the design meets both Behavioural and timing design requirements. You will
use the waveform editor to create a test bench waveform (TBW) file.

1. Select the counter HDL file in the Sources in Project window.

2. Create a new source by selecting project -> New Source.
3. In the New Source window, select Test Bench Waveform as the source type, and
fill the File Name field.
18
 4. Make sure the box for Add to Project is checked.
5. Click Next.
6. The Continue File dialog box shows that you are associating the test bench with the
source file: counter. Click Next.
7. Click Finish.
You need to set the initial values for test bench waveform in the Initialize Timing
dialog box before the test bench waveform editing window opens.
8. Fill in the fields in the Initialize Timing dialog box using the information below:
o Clock Time High: 20 ns.
o Clock Time Low: 20 ns.
o Input Setup Time: 10 ns.
o Output Valid Delay: 10 ns.
o Initial Offset: 100 ns.
o Global Signals: GSR (FPGA). Note: The GSR value of 100 is added to the
Initial Offset value automatically.
o initial Length of Test Bench: 1000 ns.
o Leave the remaining fields with their default values.
9. Click Finish to open the waveform editor.

The blue shaded areas are associated with each input signal and corresponding to
the Input Setup Time in the Initialize Timing dialog box. In this design, the input
transitions occur at the edge of the blue cells located under each rising edge of the
CLOCK input.

10. Look at the following picture for the setup of the DIRECTION port.
11. Select File -> Save to save the waveform.
12. Select the Behavioural Simulation in the Source window.
13. On the Sources in Project Window, the TBW file is automatically added to your
project.

Simulating Behavioural Model (ISE Simulator)

To run the integrated simulation process in ISE:

1. Select the testbench file waveform in the Sources in Project window. You can see
Xilinx ISE Simulator processes in the Processes for Source window.
2. Double-click on the Simulate Behavioural Model process in the Project window.
The ISE Simulator opens and run the simulation to the end of the test bench.

19
20
 PROJECT DESCRIPTION

INTRODUCTION
Voting is the sole criteriaforchoosing their representatives by people in any democracy,
so, this entire process shouldbedone with utmost care so that only a fair and deserving
candidate is selected that is solely basedonpublic opinion.Inearlierdays,elections were
conducted using ballot papersystemwhereby people casted theirvotesto their favourite
candidate,merely,by putting stamp against his/her name but this methodoftensuffered
from various flaws such as stealingofvotes and unfair results[6]. To overcome all these
discrepancies, electronic voting machine was designed. But the designofsimple
electronic voting machine with removable memory card was not enough as access to
memory card[7]for even a minute can tamper all the votes with some other
maliciouscode.Soweneeded the system which could provide some better way of
implementing Electronic Voting Machine.Since we all know that it is very difficult to
manipulate signals, sowehave designed electronic voting machine in VHDL using
XILINX ISE 9.2i as a platform which canbeimplementedonFPGA (Field Programmable
Gate Array) hardware using SPARTAN 3E kit. Since FPGA’s have in builtRAMandeach
voterequires only one bit of memory, this implementation is quite memory
andcostefficient. Further, this implementation also contains password which itself is
digital in nature and is very difficult tobehacked.

DESCRIPTION OF SIGNALS USED IN

IMPLEMENTATION
The IEEE standard used for implementation purpose ofmodules are
IEEE.STD_LOGIC_1164.ALL,
IEEE.STD_LOGI C_ARITH.ALL
IEEE.STD_LOGIC_UNSIGNED.ALL
IEEE.STD_LOGIC_SIGNED.ALL
21
The various signals that are used are
S.no Signal Description
11 Selection This signal is to select the candidate to whom vote is being casted.
Signal The size of this signal will depend on number of candidates who
will standin
elections.

2 Clock This signal is used to cast the vote. Vote will be casted on positive
Signal or negative edge of clock depending on priority of programmer.
The clock will last for particular period of time in which voter has
tocast
his/her vote.
3 Password This signal will mark the initial stage of opening of Electronic
Signal voting machine. The machine will work only when valid password
is applied to machine. The password can be as longasintended by
programmer. A 32 bit password pattern will yield 4294967296
permutations and combination of patterns which is very difficult
tohack.

4 Canditate The number of such signals will depend on the number of

Signals candidates standing in the elections.

5 Winning The winning signal=1 corresponding to particular candidate will

Signals indicate that candidate has won the elections.

6 Equality There may be a case where equal number of votes are casted to
Signals two or more candidates leading to tie condition. The equality
signal in that condition will signify a tie.

22
RTL (REGISTER TRANSFER LANGUAGE) AND
TECHNOLOGYSCHEMATIC

RTL is a design abstraction which models the digital synchronous signals in terms of
flow of digital signals between hardware registers and logical operations performed on
that signals[1]. It creates high level representation from the circuit from which lower
levels can be derived and ultimately actual wiring can be derived.
RTL view of the designed circuit is shown in the figure

Figure
RTL Schematic for implementation of Electronic Voting Machine

Technology schematic opens the NGC file that canbe viewedas architecture specific
schematic. The schematic is generated after the optimization and technology targeting
phase of synthesis process. It shows a representationofthe design in termsoflogic
elements optimized to the target Xilinx device. The schematic enables the user to see a
technology level representationofHDL optimisedforspecific XILINX architecture which
may help userdiscover

23
 design issues in beginning of design process [4]. The Technology Schematic of designed
logic is shown in figure

Figure
Technology Schematic for Electronic Voting Machine

Code for Electronic Voting Machine

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity voting_machine is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
24
 enable1 : in STD_LOGIC;
enable2 : in STD_LOGIC;
total : out STD_LOGIC_vector(3 downto 0);
led1 : out STD_LOGIC;
led2 : out STD_LOGIC);
end voting_machine;

architecture Behavioral of voting_machine is

signal temp1:std_logic_vector(3 downto 0);

signal temp2:std_logic_vector(3 downto 0);

begin

process(clk,reset,enable1,enable2)

begin

if(clk='1' and reset='1') then

temp1<="0000";
temp2<="0000";
led1<='0';
led2<='0';
end if;
if(clk='1' and reset='0') then
if(enable1='1') then
temp1<=temp1 + 1;
led1<='1';
led2<='0';
elsif(enable2='1') then
temp2<=temp2 + 1;
led1<='0';
led2<='1';
else
temp1<=temp1;
temp2<=temp2;

end if;
end if;
total<= temp1 + temp2;
end process;

end Behavioral;

25
 GENERATION FOR TESTBENCH

The testbench stores the clock period set by the programmer,forthe process of
castingofvotes[1]. The vote is casted when the clock is high and is recorded when the
clock goes low. In our implementation, the clock period is set tobe100 ns, where 50 ns
isforpositive edge and 50 ns when negative edge. If thevoteris not able to cast his/her
vote in the positive edge, then he has to wait for the next clock cycletocast hisvote.The
generated testbench is used for casting of votes by the voter and the recorded votes are
then displayed in the form of signals asshown.

Figure Generation of Test Bench

CODE FOR TESTBENCH

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY voting_machine_tb IS
END voting_machine_tb;
26
ARCHITECTURE behavior OF voting_machine_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT voting_machine
PORT(
clk : IN std_logic;
reset : IN std_logic;
enable1 : IN std_logic;
enable2 : IN std_logic;
total : OUT std_logic_vector(3 downto 0);
led1 : OUT std_logic;
led2 : OUT std_logic
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal enable1 : std_logic := '0';
signal enable2 : std_logic := '0';

--Outputs
signal total : std_logic_vector(3 downto 0);
signal led1 : std_logic;
signal led2 : std_logic;

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: voting_machine PORT MAP (
clk => clk,
reset => reset,
enable1 => enable1,
enable2 => enable2,
total => total,
led1 => led1,
led2 => led2
27
 );

-- Clock process definitions

clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

wait for clk_period*10;

-- insert stimulus here

reset<='0';
wait for 10 ns;
reset<='1';
wait for 10 ns;
reset<='0';
wait for 10 ns;
enable1<='0';
wait for 10 ns;
enable2<='0';
wait for 10 ns;
reset<='0';
wait for 10 ns;
enable1<='0';
wait for 10 ns;
enable2<='1';
wait for 10 ns;
reset<='0';
wait for 10 ns;
enable1<='1';
wait for 10 ns;
enable2<='0';
wait for 10 ns;
28
reset<='0';
wait for 10 ns;
enable1<='1';
wait for 10 ns;
enable2<='1';
wait for 10 ns;
reset<='1';
wait for 10 ns;
enable1<='0';
wait for 10 ns;
enable2<='0';
wait for 10 ns;
reset<='1';
wait for 10 ns;
enable1<='0';
wait for 10 ns;
enable2<='1';
wait for 10 ns;
reset<='1';
wait for 10 ns;
enable1<='1';
wait for 10 ns;
enable2<='0';
wait for 10 ns;
reset<='1';
wait for 10 ns;
enable1<='1';
wait for 10 ns;
enable2<='1';
wait for 10 ns;

wait;
end process;

END;

29
 SIMULATION

After all the votes have been recorded, Behavioural simulation [5]is done to obtain the
final results. The behavioural simulation of the test bench gives the authenticated results
in the form of high and low of signals. The winner gets his/her signal high at the end
of behavioural simulation and it marks the endofthe voting process. In case of tie of two
or more candidates, a signal high corresponding to twoormore candidate isshownagainst
their corresponding signal.

Figure Result of Simulation

HARDWAREIMPLEMENTATION

The Electronic Voting Machine can be implemented on hardware using SPARTAN 3E

FPGA kit by burning the VHDL code into it. Once the VHDL code is burned and the
FPGA chip is ready, we can designate various ports to various signals present in our
software.After designating ports a PROM file is generated and load FPGA with specified
bit file and the designed logic is ready for implementation..
Since on a typical SPARTAN 3E kit provided by Texas Instruments, we have only four
input ports, in order to accommodate our signals we can interface a 100 pin female
connector[1]with the SPARTAN 3E kit.

30
 CONCLUSION

The designed Electronic Voting Machine canbeused for secure voting, where the
tamperingofvotes has very less probability. It is easy to build and a large
numberofvotes canbecasted and recorded dependingonthe memory of the system.
Since it does not contain any memory card and has a password which is digital in
nature. It provides a secure system for conducting elections. This system is also
memory efficient as it uses only one bit for recording avotecasted by user.Since
thecostincurred in its manufacturing is less, therefore it can easily replace the paper
ballotsystempresent in certainareas.

APLLICATIONS OF EVM

Following are the applications of Electronic Voting Machine:

• Electronic Voting Machine (also known as EVM ) is voting using electronic means to
either aid or take care of the chores of casting and counting votes. An EVM is designed
with two units: the control unit and the balloting unit.

• The EVM aims to make the electoral process secure, fair and transparent.

31