VLSI System Design

ECE3002
Winter 2018-19
Jayakrishnan P
Assistant Professor (senior)
Dept. of Micro and Nano Electronics
SENSE
 Evaluation
• CAT 1 - 15
• CAT 2 - 15
• Quiz 1 - 10 (6th Feb. 2019)
• Quiz 2 - 10 ( 13th Mar. 2019)
• DA1 - 10 (Due Date: 29th Mar. 2019)
Reference Books
• Neil H.Weste, Harris, A. Banerjee, “CMOS VLSI Design, A circuits and
System Perspective”, Fourth Edition, Pearson Education, 2014.
• Jan M. Rabaey, Anantha Chadrakasan, BorivojeNikolic, “Digital
Integrated Circuits: A Design Perspective”, Third Edition, Prentice Hall
India, 2014.
Very Large Scale Integration (VLSI)
 Recent Processors and Technology
Transistor Date of
Processor Designer Process Area
count introduction
Apple A12 Bionic (hexa-core
6,900,000,000 2018 Apple 7 nm 83.27 mm2
ARM64 "mobile SoC")
HiSilicon Kirin 980 (octa-core
6,900,000,000 2018 Huawei 7 nm 74.13 mm2
ARM64 "mobile SoC")
Centriq 2400 18,000,000,000 2017 Qualcomm 10 nm 398 mm2
22-core Xeon Broadwell-E5 7,200,000,000 2016 Intel 14 nm 456 mm²
GC2 IPU 23,600,000,000 2018 Graphcore 16 nm 825 mm2
 Silicon Die

Single die

Wafer

Going up to 12” (30cm)

From http://www.amd.com
6
 Design Abstraction Levels
SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

7
 nMOS Transistor
• Four terminals: gate, source, drain, body
• Gate – oxide – body stack looks like a capacitor
• Gate and body are conductors
• SiO2 (oxide) is a very good insulator
• Called metal – oxide – semiconductor (MOS) capacitor
• Even though gate is
Source Gate Drain
no longer made of metal Polysilicon
SiO2

n+ n+

p bulk Si
 nMOS Operation
• Body is commonly tied to ground (0 V)
• When the gate is at a low voltage:
• P-type body is at low voltage
• Source-body and drain-body diodes are OFF
• No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

Slide 9
 pMOS Transistor
• Similar, but doping and voltages reversed
• Body tied to high voltage (VDD)
• Gate low: transistor ON
• Gate high: transistor OFF
• Bubble indicates inverted behavior

Source Gate Drain

Polysilicon
SiO2

p+ p+

n bulk Si

Slide 10
 Symbols
• An ON transistor passes a finite amount of current
• Depends on terminal voltages
• Transistor gate, source, drain all have capacitance
• Capacitance and current determine speed
 Transistors as Switches
• We can view MOS transistors as electrically controlled switches
• Voltage at gate controls path from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

Slide 12
MOS Capacitor Vg < 0
polysilicon gate
silicon dioxide insulator
+
- p-type body

• Gate and body form MOS capacitor

(a)
• Operating modes
• Accumulation 0 < Vg < Vt

• Depletion
depletion region
+
-

• Inversion
(b)

Vg > Vt
inversion region
+
- depletion region

(c)

13
 Terminal Voltages
• Mode of operation depends on Vg, Vd, Vs
• Vgs = Vg – Vs
• Vgd = Vg – Vd Vg

• Vds = Vd – Vs = Vgs - Vgd +

Vgs
+
Vgd
• Source and drain are symmetric diffusion terminals - -
• By convention, source is terminal at lower voltage Vs
- +
Vd
Vds
• Hence Vds  0
• nMOS body is grounded. First assume source is 0 too.
• Three regions of operation
• Cutoff
• Linear
• Saturation (Pinchoff)
 nMOS Cutoff
• No channel
• Ids ≈ 0
Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b
 nMOS Linear
• Channel forms
• Current flows from d to s Vgs > Vt
+ g +
Vgd = Vgs

- -
• e- from s to d s d
Vds = 0
• Ids increases with Vds
n+ n+

p-type body

• Similar to linear resistor b

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b
 nMOS Saturation/ Pinchoff
• Channel pinches off
• Ids independent of Vds
• We say current saturates
• Similar to current source
Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b
 Summary
• Design abstraction levels
• MOS transistors
• nMOS & pMOS
• MOS as switch
• MOS mode of operations
I-V Characteristics