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Adc Dac Report

This experiment involves designing an interface for an analog-to-digital converter (ADC) and processing digital samples using a moving average filter. In part A, an analog signal is sampled by the ADC and output to a digital-to-analog converter (DAC) to observe the direct digital output. In part B, a moving average filter is implemented using a finite state machine to filter the digital samples before output to the DAC. The results show the filtering effect on signals of varying frequencies and measure the frequency response of the digital filter.

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141 views

Adc Dac Report

This experiment involves designing an interface for an analog-to-digital converter (ADC) and processing digital samples using a moving average filter. In part A, an analog signal is sampled by the ADC and output to a digital-to-analog converter (DAC) to observe the direct digital output. In part B, a moving average filter is implemented using a finite state machine to filter the digital samples before output to the DAC. The results show the filtering effect on signals of varying frequencies and measure the frequency response of the digital filter.

Uploaded by

atg
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EE214: Digital Circuits Lab

Experiment-9
A Signal Processing Chain
Jian Vora, 170100026
Shaurya Chopra, 170100108
Denil Mehta, 170100004
Vishwas Bharti, 170070060
April 5, 2019

1 Aim
The aim of the experiment is to design an interface for an ADC, and
1. Observe output by directly giving ADC output to the DAC, for various
sampling frequencies
2. Design a moving-average filter in order to process the digital samples, and
observe corresponding DAC output

2 Methods
2.1 Part A:
In this part, first we sampled a given Analog signal at the interval of 1ms and
converted it into digital signal using ADC block, then in next cycle we fed this
signal into DAC block for converting it into analog signal and observed the out-
put of DAC block using oscilloscope.
The main aim of this part to implement an algorithm for ADC interface for
writing and reading a signal in proper time interval. State machine for imple-
menting this algorithm is given in Figure 1 below.
Whenever reset input is given, it goes to IDLE state in which all CS ,WR and
RD variables are set to 1. After IDLE state, it will go to INITIAL state. In
this state ADC block is initialized by making CS to ’0’. After INITIAL state,
it will go toWRI state, in which it starts the conversion because we make WR
to be ’0’ in this state. ADC does conversion when WR is low and it requires
100ns to complete the conversion process so, we made counter variable for this
state.

1
The inbuilt clock of the krypton board has a time period of 20ns, so we require
5 cycles for which it remains in state WRI and if count goes above 5, it will
transit to next state which is WRI DONE.
INTR signal indicates the end of conversion, and it will take 300ns to complete
this process so, we can read after that. Counter variable defined in this state is
for this purpose.
We require 9 cycles to perform this because we have already completed 6 cycles
in WRI and in transition from WRI to WRI DONE. After 9 cycles it will go to
next state, which is RDI. It will take 135ns for data to be available at bus after
making RD to be ’0’ and it remains for 125ns after that. So, we made 7 cycles
after making RD ’0’ and read the data after 140ns. After this state, it will go
to DONE state.
In all above states, we were updating a timer variable on each execution of par-
ticular state. We are sampling at 1ms so, we will remain in DONE state until
timer variable will become 49999 and in last cycle, we updated the DAC output
by data which we have read in RDI state.

Figure 1: FSM for implementing algorithm for ADC interface

2
2.2 Part B:

Figure 2: FSM for implementing low pass filer

In this part, we passed the ADC output to digital logic given by equation be-
low. After that we passed it through DAC block and observed the output on
oscilloscope. Pn=7
x(k − n)
y(k) = n=0 (1)
8
We made combinational logic for this and implemented this low pass filter by
adding one extra state to the already designed FSM:
After RDI state , go to a state called input update and update the register
with previous seven sample value and also newly received input. Using this, we
compute the new ouput.
And after this state, it will transit to DONE state which is same as the DONE
state of part-a.

3
3 Results
3.1 Part-a
In this part, we observe the output for an input signal of frequency 40Hz.

Figure 3: Output for ADC Output directly given to DAC

Output resembles a sinusoidal wave with steps as per the sampling.

4
3.2 Part-b
For this part, we observe the low-pass filtering action, and also measure the
frequency characteristics of the digital filter.

(a) f=10Hz (b) f=50Hz

(c) f=100Hz (d) f=150Hz

Figure 4: Output for increasing frequencies

5
3.2.1 Frequency Response

Frequency(Hz) Pk-Pk value(V) Gain(dB)


10 2.16 6.689075023
20 2.08 6.361266699
50 2 6.020599913
70 1.92 5.666024574
100 1.68 4.506185635
125 1.34 2.542095967
150 1.2 1.583624921
175 0.88 -1.110346557
200 0.78 -2.158107946
250 0.14 -17.07743929
300 0.18 -14.8945499
350 0.2 -13.97940009
400 0.22 -13.15154638
450 0.16 -15.91760035
500 0.1 -20

Table 1: Frequency response of moving average filter

Figure 5: Frequency response of moving average filter

3dB cut-off frequency is approximately 120Hz.

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