Lecture #3:

Sequential
Logic
From Nand to Tetris
www.nand2tetris.org

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 1
Sequential VS combinational logic
• Combinational devices: operate on data only;
provide calculation services (e.g. Nand … ALU)
• Sequential devices: operate on data and a clock signal;
as such, can be made to be state-aware and provide storage and synchronization
services
• Sequential devices are sometimes called “clocked devices”
• The low-level behavior of clocked / sequential gates is tricky
• The good news:
– All sequential chips can be based on one low-level sequential gate,
called “data flip flop”, or DFF
– The clock-dependency details can be encapsulated at the
low-level DFF level
– Higher-level sequential chips can be built on top of DFF gates
using combinational logic only.

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 2
Outline
• Clock

• A hierarchy of memory chips:

– Flip-flop gates

– Binary cells

– Registers

– RAM

• Counters

• Perspective.

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 3
The Clock HW
simulator
demo

tock tock tock tock

clock tick tick tick tick

signal
cycle cycle cycle cycle

• In our jargon, a clock cycle = tick-phase (low), followed by a

tock-phase (high)

• In real hardware, the clock is implemented by an oscillator

• In our hardware simulator, clock cycles can be simulated either

– Manually, by the user, or

– “Automatically,” by a test script.

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 4
Flip-flop HW
simulator
demo
in DFF out

out(t) = in(t-1)

• A fundamental state-keeping device

– Outputs the input value from the previous time unit
• For now, let us not worry about the DFF implementation
– Built into simulator
• Memory devices are made from numerous flip-flops,
all regulated by the same master clock signal
• Notational convention:

in
sequential
chip out = in
sequential
chip out
(notation)

clock
signal

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 5
1-bit register
(we call it “Bit”)
load
Objective: build a storage unit that can:
(a) Change its state to a given input
in Bit out
(b) Maintain its state over time (until changed)

if load(t-1) then out(t)=in(t-1)

else out(t)=out(t-1)

binary cell (Bit)

What part
can be used
out in out
in DFF instead?
DFF
Use DFF to
out(t) = in(t-1) Implement…

Basic building block

out(t) = out(t-1) ?
out(t) = in(t-1) ?

Won’t work

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 6
Bit register (cont.) HW
simulator
demo

Interface Implementation

load
load load

in
in in Bit out out in Bit Bit ... Bit out out

MUX
DFF w DFF
w

if load(t-1) then out(t)=in(t-1) if load(t-1) then out(t)=in(t-1)

else out(t)=out(t-1) else out(t)=out(t-1)

binary cell (Bit) w-bit register

o Load
out(t) = out(t-1) ? bit if load(t-1) then out(t)=in(t-1)
out(t) = in(t-1) ? else out(t)=out(t-1)
o Write logic (load = 1)
Invalid design 1-bit register (Bit)
o store new input
o Read logic (load = 0)
o keep storing internal value

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 7
Multi-bit register HW
simulator
demo

load load

in Bit out in Bit Bit ... Bit out

w w

if load(t-1) then out(t)=in(t-1) if load(t-1) then out(t)=in(t-1)

else out(t)=out(t-1) else out(t)=out(t-1)

1-bit register w-bit register

o Register’s width: a trivial

parameter (Word size)
o Contents = word
o Write logic (load = 1)
o store new input
o Read logic (load = 0)
o keep storing internal value
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 8
Aside: Hardware Simulation
HW
simulator
demo
Relevant topics from the HW simulator tutorial:
• Clocked chips: When a clocked chip is loaded into the
simulator, the clock icon is enabled, allowing clock
control
• Built-in chips:
– feature a standard HDL interface yet a Java
implementation
– Provide behavioral simulation services
– May feature GUI effects (at the simulator level
only).

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 9
Counter Needed: a storage device that can:
(a) set its state to some base value
(b) increment the state in every clock cycle
(c) maintain its state (stop incrementing) over clock cycles
(d) reset its state

inc load reset

in PC (counter) out
w bits w bits

If reset(t-1) then out(t)=0

else if load(t-1) then out(t)=in(t-1)
else if inc(t-1) then out(t)=out(t-1)+1
else out(t)=out(t-1)

• Typical function: program counter

• Implementation: register chip + some combinational logic.

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 10
 Counter Simulation Lab
Remember:
• Output latches on tock (end of cycle)
• Control bits dictate NEXT output (see
above)

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 11
 BREAK!

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 12
Random Access Memory HW
simulator

(RAM)
demo

load

o RAM
register 0

o Any word in memory can be register 1

accessed directly, in equal register 2
speed in .. out

o How? .
(word) (word)
register n-1

o Word = register contents

RAM n
o Size = # of addresses = # of address
registers = word size Direct Access Logic
(0 to n-1)

o Read logic (0)

o Write logic (1)
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 13
RAM interface

load

in

16 bits out
RAMn
address 16 bits

log 2 n
bits

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 14
RAM anatomy
RAM 64

RAM8

RAM 8
.. 8
.
register
..
. 8 RAM8
Register
register

Bit Bit .. . Bit register

...

Recursive ascent

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 15
Recap: Sequential VS
combinational logic
Combinational chip chip
Combinational Sequential chipchip
Sequential

(optional)
(optional) time delay
time delay (optional)
(optional)

comb. comb. comb.comb. DFFDFF comb.

comb.
in in logic logic out outin in logiclogic gate(s)
gate(s) logic
logic
out
out

out = some
out =function of (in)of (in)
some function out(t)out(t)
= some function
= some of (in(t-1),
function out(t-1))
of (in(t-1), out(t-1))

o Maintain state (memory), or

o Operate on state (counter)
o Feedback loop

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 16
Time matters
tock tock tock tock

clock tick tick tick tick

signal
cycle cycle cycle cycle

n During a tick-tock cycle, the internal states of all the clocked chips are allowed
to change, but their outputs are “latched” (changes to input have no immediate
effect on their outputs)
n At the beginning of the next cycle, the outputs of all the clocked chips in the
architecture commit to the new values (not within cycle itself!)

Implications:
a Reg1
q Challenge: propagation delays

q Solution: clock synchronization

sel
out
q Cycle length and processing
+

b Reg2
speed.

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 17
Perspective
• All the memory units described in this lecture are standard
Access
time Cost
• Typical memory hierarchy
– SRAM (“static”), typically used for the cache
– DRAM (“dynamic”), typically used for main memory
– Disk
(Elaborate caching / paging algorithms)
• A Flip-flop can be built from Nand gates
• But ... real memory units are highly optimized, using a great variety
of storage technologies.
– Classic Design = Nand gates + feedback loops

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 18
End notes: some poetry
about the limits of logic ...
There exists a field where things are neither true nor false;
I’ll meet you there. (Rumi)

In the place where we are always right

No flowers will bloom in springtime (Yehuda Amichai)

A mind all logic is like a knife all blade;

It makes the hand bleed that uses it.
(Rabindranath Tagor)

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 19