VLSI Basics

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3 April 2015

Clock Tree Optimization

Clock can be shielded so that noise is not coupled to other signals. But shielding
increases area by 12 to 15%.
CTO is achieved by buffer sizing, gate sizing, buffer relocation, level adjustment
and HFN(high fan-out net) synthesis.(cloning is the tech. for HFN.)
We try to improve setup slack in pre-placement, in placement and post placement
optimization before CTS stages while neglecting hold slack.
In post placement optimization after CTS hold slack is improved. As a result of CTS
lot of buffers are added.
ØWhat kind of optimizations done in CTO?
The different options in CTO to reduce skew are described in the following list

Buffer and Gate sizing

Sizes up or down buffers and gates to improve both skew and insertion delay.
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You can impose a limit on the type of buffers and gates to be used.
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No new clock tree hierarchy will be introduced during this operation.

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VLSI design flow

VLSI Design Flow
VLSI design Flow The
VLSI design cycle
starts with a formal
specification of a VLSI chip, follows
a series of steps...

Physical location of the buffer or gate is moved to reduce skew and insertion delay. Floorplanning
What is
No new clock tree hierarchy will be introduced during this operation. Floorplanning???? A
floorplanning is the
Level Adjustment process of placing
blocks/macros in the chip/core
area, thereby determining th...
 Electromigration & IR
drop
What is
Electromigration???
Electromigration is
the gradual displacement of metal
atoms in a semiconductor. It occurs
when the current d...

Power Planning
What is Power
Planning????
Power planning is a
step which typically is
done with floorplanning in which
power grid network is ...
Adjust the level of the clock pins to a higher or lower part of the clock tree
hierarchy. Blockages and Halo
Blockages Blockages are specified
No new clock tree hierarchy will be introduced during this operation. locations where placing cells are
prevented or blocked. These act as
Reconfiguration guidelines for placing standard c...

Topics

Arrival time
Backend
Basic Terminology
Blockages
Buffer and Gate Relocation
Buffer and Gate Sizing
Clock Tree Optimization
Clock Tree Synthesis
congestion
congestion driven placement
Clustering of sequential logic. CTS goals
Buffer placement is performed after clustering. Delay
Delay Insertion
Longer runtimes.
Design Flow
No new clock tree hierarchy will be introduced during this operation.
Detailed placement
Delay Insertion Dummy Load Insertion
Effects of CTS
Electromigration
Floorplanning
gate array placement
Global Placement
Halo
Hold time
In-placement optimization
IR Drop
Jitter
Latest News
Legalization
Level Adjustment
Delay is inserted for shortest paths. macro block placement
Delay cells can be user defined or can be extracted from by the tool. mixed size placement
By adding new buffers to the clock path the clock tree hierarchy will change. OCV
Physical Design
Dummy Load Insertion
Placement
Post placement optimization
Powerplanning
Pre-placement optimization
Reconfiguration
Recovery time
Removal time
Required time
Routing
Setup & Hold
Setup time
 Skew
Slack
standard cell placement
VLSI Design Flow

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Routing
Clock Tree Optimization
Clock Tree Synthesis
Uses load balancing to fine tune the clock skew by increasing the shortest path Congestion
delay.
Dummy load cells can be user defined or can be extracted by the tool. ► March (13)
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No new clock tree hierarchy will be introduced during this operation.

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Posted by Jimmy Sutaria at 11:46 am

Labels: Backend, Buffer and Gate Relocation, Buffer and Gate Sizing, Clock Tree Optimization, Delay Insertion,
Dummy Load Insertion, Level Adjustment, Reconfiguration
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