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Congestion Prediction in Vlsi Routing

This document discusses congestion prediction in VLSI routing. It begins with an introduction to global routing and congestion factors. Section 2 provides a literature review of previous works on congestion estimation. Section 3 defines the objectives of congestion prediction problems. Section 4 discusses metrics for evaluating global routing like wire length, overflow, runtime and wire quality. Section 5 defines congestion and its causes. Section 6 covers detoured wire length and how detours can be used to avoid congestion.

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0% found this document useful (0 votes)
174 views18 pages

Congestion Prediction in Vlsi Routing

This document discusses congestion prediction in VLSI routing. It begins with an introduction to global routing and congestion factors. Section 2 provides a literature review of previous works on congestion estimation. Section 3 defines the objectives of congestion prediction problems. Section 4 discusses metrics for evaluating global routing like wire length, overflow, runtime and wire quality. Section 5 defines congestion and its causes. Section 6 covers detoured wire length and how detours can be used to avoid congestion.

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AnushaChitti
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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60

CHAPTER 4

CONGESTION PREDICTION IN VLSI ROUTING

4.1 INTRODUCTION

Global routing is a technique in the physical VLSI design in which


several interconnects are used to design the chip. It decomposes the routing
issue into a smaller controllable routings for the detailed router. Initially, the
global router searches a path for each net by minimizing the chip size, the wire
length and distributing the congestion across the routing area compared with
other techniques. Fast routing metrics calculation is useful for finding
congestion factor and wire length information in both placement and routing
tools. In VLSI routing, congestion is an important factor other than timing,
wire length and power. Routing congestion is mainly depends on the total wire
length used in the VLSI system. However, the performance of the optimization
is controlled due to the presence of the fixed cells at this stage. A highly
congested part of the cells deteriorates in the placement leads to routing
deviation around the region. Hence, this chapter addresses a novel algorithm
that is implemented in a VLSI layout by placing the cells in both rows and
columns and the performance in terms of run time, congestion factor
estimation and overflow parameters has been analyzed. The proposed
algorithm depends on the wire density, the number of connections involved in
the layout. The benchmarks results are useful for the proposed algorithms‟
evaluation for comparing other techniques.
61

4.2 LITERATURE REVIEW

VLSI routing is based on connecting pins and ports using metal


wires represented in a logical connection called net list. The routing
parameters are inter connect delay, power consumption and chip reliability etc.
A Global routing is helpful for generating a lower congestion factor where the
wiring demands across the layout is below its capacity or global edge capacity.
There are many research papers in the literature for developing high
performance global router to resist congestion with given global edge capacity.

Initially, Kusnadi and Carothers‟ (1999) method for measuring


routability based on calculating the number of unblocked paths for two-pin
nets, similar to the true freedom method. This method attempts to estimate
routability directly and cannot be used for congestion estimation. Lou et al
(2001) mentioned a quick estimation for congestion in a statistical manner.
They assumed that each net incorporates the shortest route with equal
probability. Based on this assumption, they estimated the congestion for the
routing area.The authors modified Lou's algorithm with calibration data and
used it for wire length estimation. Moreover, Lou‟s Model (Lou et al 2001)
has an assumption that at the interior of the bounding box span by a net with
high probability.

Kahng & Xu (2003) extended Lou‟s work that the accuracy depends
on the distribution of bends in the estimation of congestion. The problem has
been raised by the authors in literature for the number of bends depends only
on the probability of event in a net. The accuracy of a net depends on the
accuracy of the prediction of number of bends in a circuit (Sham et al 2005 &
2009, Saeedi et al 2006). The performance of the congestion estimation
depends on the distribution of bends (Taghavi et al 2007).
62

In literature, because of the significance of this congestion


estimation problem, many congestion models have been proposed such as
Lou‟s Model (Lou et al 2001), Westra‟s Model (Westra et al 2004), SMD and
Detour Model (Sham et al 2009). In Lai et al (2003), the congestion factor
depends on the average net thickness on the boundaries of different regions in
a floor plan. The number of bends depends on the routing path with probability
of event of the path.

During global routing it is assumed that the last paths are close to
shortest paths within the layout. Peyer et al (2009) proposed a method to
represent the partial grid graph by a set of intervals of adjacent vertices and to
label these intervals rather than individual vertices in his goal-oriented version
of Hetzel‟s algorithm.

Hence, minimizing wire length and overflow have been used since
they correlated well with enhancing routability, timing, power, design rule
violations, and other interconnect-related issues that are of concern in the
lower stages of the design (Wu 2011). In literature, there are many algorithms
have been proposed for global routing. Chi Dispersion algorithm is
implemented exclusively for cost amplification. Predictable routing is
implemented for global routing at a specific reason. Archer, Box Router, FGR,
Fast Route, Maize Route, NTHU-Route, NTUgr and NCTU global routers
have been proposed in literature. Based on Real detailed routing congestion
factors including fat vias, stacked vias, pin access paths, and related design
rules in global routing stage, Qi et al (2015) proposed a practical congestion
model in global routing.

4.3 PROBLEM FORMULATION AND OBJECTIVES

Congestion factor is a major research issue in routing resources.


Over congested wiring will deteriorate the design performance and lead to an
63

unroutable solution. Thus, routability optimization has become the most


important concern in floorplanning and many other designing steps.
Unfortunately, small wire length procedure does not have important impact on
routability. Consequently, congestion analysis is useful in industries for
routing. Given netlist, a placement area with dissection in tiles, a standard cell
placement and a set of pre routes, the aim of the congestion prediction problem
is to find congestion prediction for the tiles (or edges) due to the remaining
signal wires as accurately as possible, but at least one order of magnitude
faster than global routing.

Due to the prevalent application of nanometer-scale technology in


the modern integrated circuits, the excessively high density of interconnections
will result in negative effect towards the routability of the chip. This is because
of the over congestion of wires which will severely damage the quality of the
signal transmission in each network, affecting the circuit performance. As a
result, routability optimization has become a main concern in the VLSI
physical design. Thus, routability optimization has become important factor in
the physical VLSI routing design. Unfortunately, small wirelengths not have
major impact on routability (Wang et al 2000). So we need an exact
congestion estimation and removal methods.

Researchers claimed that the bends allocation of a net are important


and the calculation of probabilistic procedure at each net is to be proposed. An
accurate prediction of a placement result is an effective metric to evaluate the
behavior of the corresponding placer. Hence, the evaluation of congestion factor
for the proposed layout is an important indicator for various routing techniques.
64

4.4 METRICS FOR GLOBAL ROUTING

4.4.1 Wire Length

It is a performance measure of placement and routing in VLSI


system but less significant. In global routing, Dijkstrastyle shortest path
algorithm is used for a minimum wire length (Peyer et al 2009).
4.4.2 Overflow

It is an abstraction of the wiring overflow where routing demand


exceeds the routing resources.

4.4.3 Run time

This is an appropriate metric since the global router will be running


early and frequent in the design flow.

4.4.4 Wire quality

 The quantity of vias is an amount of layer changes in a net.


 The amount of stacked vias that connect between nonadjacent
layers. The wiring track is blocked in the layers and it will
cause congestion.
 The amount of detouring is the deviation of the shortest
possible wire length.
 The evenness of the usage of routing resources – is not
suitable for routing violation avoidance, and also enables
routers to improve the manufacturability by spacing out wire
patterns.

The metrics mentioned above should be minimum for easier routing.


Global routing contradictory objectives diagram is shown in Figure 4.1.
65

Figure 4.1 Global routing trade off

4.5 CONGESTION

If the wiring demand in an edge exceeds supply, it indicates


congestion. The local clusters of edges in a detailed router can get a capacity
from neighbouring areas. The congestion causes due to the sum of the
overflowed routing tracks in all edges. Overflow and congestion are important
parameters that could be measurable in a layer by layer basis. If a connection
is in the horizontal direction, the detailed router may insert additional vias to
gain access to a layer with the same direction. The horizontal routing cannot
be exchanged with vertical resource. The number of layers, track pitch, and
circuit placement is to be carefully considered where there is a mismatch
between routing demand and routing resource in a desired direction.

4.6 DETOURED WIRELENGTH

A detour is a net path but is not consisting of minimum wire length.


Since it can be generated by obstacles, wires can be used to avoid congestion.
The distribution of detours is useful for placement delay estimation.

The timing estimation is an important factor when the size of


detours are large or in smaller number. It is also noted that if the routing tool is
not working, the detours are considered as in uncongested design. In literature,
it is observed that all detour distributions are not published for benchmarks.
Hence, the total detour length as a function of total wire length needs to be
proposed and analyzed.
66

Meanwhile, the wire length is an important factor in placement


tools, but is less metric in routing methods. Given a placement is fixed; the
detour metric is a suggestion of routing demand that is to be increased in
global routing. In order to avoid congestion, how much detours are to be
specified is a real challenging task.

4.7 CONGESTION FACTOR

It is a parameter which measures the relationship between


congestion and detoured wire length (Sham et al 2009).

 Ax, y, z B x, y  z

R z   x , yB

 B  x, y 
z (4.1)
x , yB

where R z  is a congestion factor of a net z, x, y  is a co-ordinate points,


Ax, y, z  is the addition of wire density of all nets except the net z on the line
segment, B is a bounding box of a net z (Sham et al 2009) .
 
 B t xi , yi  
B  x, y      
'


z t
B x , y (4.2)
x , y S   B  xi , yi 
t
i i 
 x , y S
i i 

where Bt xi , yi  is the wire density of vertical line segment with no blockage,

B t x, y  is the wire density of the line segment of pseudo net between (0,0)
'

and x, y  .

4.8 OVER FLOW

The overflow of an edge is defined as

q  w  r if q  w
OF   (4.3)
0 elsewhere
67

where q is the maximum number of nets routed in all edges, w is a constant


and its value depends on the length of an edge and r is a threshold value.
Equation 4.3 shows that if maximum number of nets is greater than the length
of an edge, then overflow occurs in the net. The total overflow of a routing is
defined as the summation of number of bin edges in a net. Total overflow is an
important indicator to measure the congestion.

4.9 CONGESTION ESTIMATION

In a VLSI net, consider a rectangular loop as shown in Figure 4.2


congestion is being analyzed in every grid. The capacity of a grid is modelled
as the number routing paths in a grid. The horizontal capacity is named as the
number of horizontal routing paths and the vertical capacity of a grid is named
as the number of vertical routing paths. The horizontal congestion price of a
grid is defined as the ratio between the number of horizontal routing paths and
the horizontal capacity of the grid. The vertical congestion price of a grid is
defined as the ratio between the number of vertical routing paths and the
vertical capacity of the grid.

Figure 4.2 Grid loop design

The horizontal capacity is defined as


NH
1
HC  H   (4.4)
i 1 LH
68

where H is the height of each grid, NH is the number of horizontal routing


layers and LH is the minimum pitch for the horizontal layer.

The vertical capacity is defined as


NV
1
VC  W   (4.5)
i 1 LV
where W is the width of each grid, NV is the number of vertical routing layers
and LV is the minimum pitch for the vertical layer.

4.10 STEINER TREES

In literature, there are a set of global routing algorithms have been


proposed. These algorithms are useful only for finding the paths in a routing
region directly of a two pin nets. Steiner tree algorithm is suitable for multi pin
nets. In multi pin net, the technique is to decompose each net into a set of two
pin connections, and then route the connections.

MST (Minimum Spanning Tree) is a minimum length tree of edges


connecting all the pins. The MST can be computed in polynomial time.
However, the decomposition results in suboptimal solutions. Figure 4.3 shows
the 4 pin net rectilinear MST, where each segment runs vertically or
horizontally.

Figure 4.3 Four pin minimum rectilinear tree


69

The minimum rectilinear Steiner tree (MRST) is used for routing a


multi pin net with the minimum wire length. Given the points in the plane, an
MRST connects all points by rectilinear lines in the way of points called
Steiner points, to achieve a minimum wire length. Let M denotes the points
and V denotes the steiner points respectively.
MRST (M )  MST (M U V ) (4.6)

Figure 4.4 shows an example of the MRST with two Steiner points
s1 and s2 for the four pins p1, p2, p3, and p4.

Figure 4.4 A minimum rectilinear Steiner tree (MRST) and its Hanan grid

It can be seen that there is an infinite number of Steiner points are to


be considered for the MRST construction. Hanan theorem says that for M pins,
there exists an MRST of M with all Steiner points chosen from the grid points
of the Hanan grid, which is obtained by constructing vertical and horizontal
lines through every pin in M. The Hanan theorem greatly reduces the search
space for the MRST construction from an infinite number of choices to only
m2-m candidates for the Steiner points, where m=|P|. However, the MRST
construction is still an NP-hard problem. The relationship between MST and
MRST can be stated by Hwang‟s theorem as follows:
Wirelength MST ( M ) 3

Wirelength MRST (M ) 2
(4.7)
70

This algorithm says that with an MST, iteratively select one steiner
point that can reduce the most wire length and then add the steiner point to the
tree. The iterations continue until the wire length cannot be improved. Figures
4.5 illustrates the first, second, and third iterations after inserting steiner points
s1, s2, and s3 into the initial MST respectively.

Figure 4.5 Step by step iterative example of steiner tree

4.10.1 Iterated Steiner algorithm

Input : M-a set of m pins.


Output : a Steiner tree on P.

1. V  ;
/* H (M  V ) : Set of Hanan points */
* / MST ( A, B)  Wirelength(MST ( A))  Wirelength(MST ( AUB)) * /
2. While (C and
 ( x  H ( M  V ) / MST ( M  V , ( X ))  0)   )do

3. Find X  C and which maximizes MST (M  V , ( X ));


4. V  VU (X ) :
71

5. Remove points in S which have degree  2inMST ( M  V );


6. End While
7. Output MST (MUV ) :

4.10.2 Rip-up and Re-Route Algorithm

Figure 4.6 Rip-up and Re- Route Algorithm

4.11 BENCHMARKS FOR LAYOUT SYNTHESIS

The use of benchmarks for algorithm estimation in comparing


various techniques to solve design problems. The criteria used are below.
 The maximum wiring length used in a placement subsystems
 An actual wiring length used in a place and route subsystems
 via counts in a routing subsystems
 routing completion in gate arrays
 layout area
 Capability to achieve the pre-specified aspect ratio of the layout.
72

4.12 RESULTS AND DISCUSSION

4.12.1 Specifications
 The number of horizontal and vertical tiles
 The number of horizontal and vertical layers
 Horizontal and vertical capacities in each layer
 netlist

Our objective is to minimize the total number of overflows and to


minimize the total wire length. The overflow on a tile boundary is calculated
as the amount of demand that exceeds the given capacity. Consider a routing
problem shown in figure 4.7, an input, output and its performance is analyzed.

Figure 4.7 Routing problem

Input:
grid 2 2 2
vertical capacity 0 2
horizontal capacity 2 0
num net 4
73

A02
011
111
B12
011
101
C22
001
111
D32
001
101

Output
A0
(0, 1, 1)-(1, 1, 1)
!
B1
(0, 1, 1) - (1, 1, 1)
(1, 1, 1) - (1, 1, 2)
(1, 1, 2) – (1, 0, 2)
(1, 0, 2) – (1, 0, 1)

!
C2
(0, 0, 1) – (1, 0, 1)
(1, 0, 1) – (1, 0, 2)
(1, 0, 2) – (1, 1, 2)
(1, 1, 2) – (1, 1, 1)
!
D3
(0, 0, 1) – (1, 0, 1)
!
:
It is observed that the total wire length is ten and total overflow is
zero.The algorithm is validated using MCNC benchmark circuits given below.
74

MCNC (Microelectronics Centre of North Carolina) Benchmarks


Benchmark Run time
apte 0.05 seconds
xerox 16.85 seconds
hp 3.89 seconds

Apte layout

xerox layout

Hp layout
75

150

145

140
overflow

135

130

125
0 2 4 6 8 10 12 14 16 18 20
Number of moves in the model

Figure 4.8 Overflow versus number of moves in the model

Figure 4.8 shows the overflow value for the first twenty values. It is
the real congestion overflow value obtained from the global router. This global
router is implemented using Steiner tree (used in industries), Minimum
Spanning Tree (MST) and the shortest path algorithm. MST finds the shortest
route in multi terminal nets. Once the nets are routed, rip up and reroute
procedure helps to improve the global route. Then, consecutively remove each
net and reroute it to reduce the congestion in the chip.

0.95

0.9
wire length

0.85

0.8

0.75

0.7

0.65
9
8
7 9
6 8
7
5 6

net height 4
3
3
4
5

2
net width
2
1 1

Figure 4.9 Distribution wire length as a function of net width and height
76

Figure 4.9 shows the distribution of wire length as a function of


height and width of a net. After Specifying the number of obstacles with their
dimensions & locations and number of terminals, to calculate the
redistribution of wire length, obstacles can be treated as areas where net
terminals cannot be allowed and the wires can be passed.

150
Number of occurrences

100

50

0
0 10 20 30 40 50 60 70 80 90 100
Number of detours

Figure 4.10 Histogram for detour

Figure 4.10 shows the number of occurrences as a function of


number of detours. The routing result can be plotted in MATLAB also, since
statistical analysis is useful for routing. It is observed that if we increase the
number of detours, the number of occurrences of routing involved is reduced.
Figure 4.11 shows the congestion factor as a function of detoured wirelength.
It is seen that the detoured wire length increases from 10 microns to 20
microns, the congestion factor is also increased to the number 1.8. But for wire
length from 21 micron to 40 micron, the congestion factor is minimum. This
figure is very useful for estimating the congestion factor calculation by
considering the detour wirelength. The size of the detour wirelength is chosen
as from 20 to 40 nano meter with a minimum congestion factor to avoid
congestion.
77

1.8

1.6
Congestion factor

1.4

1.2

0.8

10 15 20 25 30 35 40 45 50
Detoured wirelength

Figure 4.11 Congestion factor as a function of detour wirelength

4.13 SUMMARY

This chapter addresses the algorithm to predict congestion


parameter. The performance of routing techniques shows that the estimation
outcomes of our approaches are more accurate in terms of overflow and run
time than the previous congestion models. The Steiner tree algorithm is
developed to consider global routing, but the improvement on the estimation
accuracy is found to be non significant. Results show that our congestion
model can estimate routing congestion with smaller error efficiently.

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