Congestion Prediction in Vlsi Routing
Congestion Prediction in Vlsi Routing
CHAPTER 4
4.1 INTRODUCTION
Kahng & Xu (2003) extended Lou‟s work that the accuracy depends
on the distribution of bends in the estimation of congestion. The problem has
been raised by the authors in literature for the number of bends depends only
on the probability of event in a net. The accuracy of a net depends on the
accuracy of the prediction of number of bends in a circuit (Sham et al 2005 &
2009, Saeedi et al 2006). The performance of the congestion estimation
depends on the distribution of bends (Taghavi et al 2007).
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During global routing it is assumed that the last paths are close to
shortest paths within the layout. Peyer et al (2009) proposed a method to
represent the partial grid graph by a set of intervals of adjacent vertices and to
label these intervals rather than individual vertices in his goal-oriented version
of Hetzel‟s algorithm.
Hence, minimizing wire length and overflow have been used since
they correlated well with enhancing routability, timing, power, design rule
violations, and other interconnect-related issues that are of concern in the
lower stages of the design (Wu 2011). In literature, there are many algorithms
have been proposed for global routing. Chi Dispersion algorithm is
implemented exclusively for cost amplification. Predictable routing is
implemented for global routing at a specific reason. Archer, Box Router, FGR,
Fast Route, Maize Route, NTHU-Route, NTUgr and NCTU global routers
have been proposed in literature. Based on Real detailed routing congestion
factors including fat vias, stacked vias, pin access paths, and related design
rules in global routing stage, Qi et al (2015) proposed a practical congestion
model in global routing.
4.5 CONGESTION
Ax, y, z B x, y z
R z x , yB
B x, y
z (4.1)
x , yB
z t
B x , y (4.2)
x , y S B xi , yi
t
i i
x , y S
i i
where Bt xi , yi is the wire density of vertical line segment with no blockage,
B t x, y is the wire density of the line segment of pseudo net between (0,0)
'
and x, y .
q w r if q w
OF (4.3)
0 elsewhere
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Figure 4.4 shows an example of the MRST with two Steiner points
s1 and s2 for the four pins p1, p2, p3, and p4.
Figure 4.4 A minimum rectilinear Steiner tree (MRST) and its Hanan grid
This algorithm says that with an MST, iteratively select one steiner
point that can reduce the most wire length and then add the steiner point to the
tree. The iterations continue until the wire length cannot be improved. Figures
4.5 illustrates the first, second, and third iterations after inserting steiner points
s1, s2, and s3 into the initial MST respectively.
1. V ;
/* H (M V ) : Set of Hanan points */
* / MST ( A, B) Wirelength(MST ( A)) Wirelength(MST ( AUB)) * /
2. While (C and
( x H ( M V ) / MST ( M V , ( X )) 0) )do
4.12.1 Specifications
The number of horizontal and vertical tiles
The number of horizontal and vertical layers
Horizontal and vertical capacities in each layer
netlist
Input:
grid 2 2 2
vertical capacity 0 2
horizontal capacity 2 0
num net 4
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A02
011
111
B12
011
101
C22
001
111
D32
001
101
Output
A0
(0, 1, 1)-(1, 1, 1)
!
B1
(0, 1, 1) - (1, 1, 1)
(1, 1, 1) - (1, 1, 2)
(1, 1, 2) – (1, 0, 2)
(1, 0, 2) – (1, 0, 1)
!
C2
(0, 0, 1) – (1, 0, 1)
(1, 0, 1) – (1, 0, 2)
(1, 0, 2) – (1, 1, 2)
(1, 1, 2) – (1, 1, 1)
!
D3
(0, 0, 1) – (1, 0, 1)
!
:
It is observed that the total wire length is ten and total overflow is
zero.The algorithm is validated using MCNC benchmark circuits given below.
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Apte layout
xerox layout
Hp layout
75
150
145
140
overflow
135
130
125
0 2 4 6 8 10 12 14 16 18 20
Number of moves in the model
Figure 4.8 shows the overflow value for the first twenty values. It is
the real congestion overflow value obtained from the global router. This global
router is implemented using Steiner tree (used in industries), Minimum
Spanning Tree (MST) and the shortest path algorithm. MST finds the shortest
route in multi terminal nets. Once the nets are routed, rip up and reroute
procedure helps to improve the global route. Then, consecutively remove each
net and reroute it to reduce the congestion in the chip.
0.95
0.9
wire length
0.85
0.8
0.75
0.7
0.65
9
8
7 9
6 8
7
5 6
net height 4
3
3
4
5
2
net width
2
1 1
Figure 4.9 Distribution wire length as a function of net width and height
76
150
Number of occurrences
100
50
0
0 10 20 30 40 50 60 70 80 90 100
Number of detours
1.8
1.6
Congestion factor
1.4
1.2
0.8
10 15 20 25 30 35 40 45 50
Detoured wirelength
4.13 SUMMARY