International Journal of Engineering and Techniques - Volume 4 Issue 1, Jan – Feb 2018

RESEARCH ARTICLE OPEN ACCESS

Design of Radix- 4 Signed Digit Encoding for

Pre- Encoded Multipliers Using Verilog.
V.Indumathi1, P.Nagaraju2
1
M-Tech, Dept. of ECE,kakinada Institute of Engineering and technology, korangi.
2
Assoc. Prof,Dept. of ECE,kakinada Institute of Engineering and technology, korangi.

Abstract:
In this paper, we introduce an architecture of pre-encoded multipliers for digital signal processing
applications based on off-line encoding of coefficients. To this extend, the Non-Redundant radix-4 Signed-
Digit (NR4SD) encoding technique, which uses the digit values f1; 0; þ1; þ2g or f2; 1; 0; þ1g, is proposed
leading to a multiplier design with less complex partial products implementation. Extensive experimental
analysis verifies that the proposed pre-encoded NR4SD multipliers, including the coefficients memory, are
more area and power efficient than the conventional Modified Booth scheme.

Keywords — Multiplying circuits, modified Booth encoding, pre-encodedmultipliers, VLSI

implementation.

1. INTRODUCTION switching activity. However, the CSD

Multimedia and digital signal processing encoding involves serious limitations.
(DSP) applications (e.g., fast Fourier Folding technique, which reduces silicon
transform (FFT), audio/video CoDecs) carry area by time-multiplexing many operations
out a large number of multiplications with into single functional units, e.g., adders,
coefficients that do not change during the multipliers, is not feasible as the CSD-based
execution of the application. Since the multipliers are hard-wired to specific
multiplier is a basic component for coefficients. In, a CSD-based programmable
implementing computationally intensive multiplier design was proposedfor groups of
applications, its architecture seriously pre-determined coefficients that share
affects their performance. Constant certain features. The size of ROM used to
coefficients can be encoded to contain the store the groups of coefficients is
least nonzero digits using the canonic signed significantly reduced as well as the area and
digit (CSD) representation. CSD multipliers power consumption of the circuit. However,
comprise the fewest non-zero partial this multiplier design lacks flexibility since
products, which in turn decreases their the partial products generation unit is

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 International Journal of Engineering and Techniques - Volume 4 Issue 1, Jan – Feb 2018

designed specifically for a group of At one time, there was a push to name and
coefficients and cannot be reused for another adjust different levels of huge scale joining
group. Also, this method cannot be easily above VLSI. Terms like Ultra-substantial
extended to large groups of predetermined scale Integration (ULSI) were utilized. In
coefficients attaining at the same time high any case, the gigantic number of entryways
efficiency. Modified Booth (MB) encoding and transistors accessible on regular gadgets
tackles the aforementioned limitations and has rendered such fine refinements
reduces to half the number of partial debatable.Terms recommending more
products resulting to reduced area, critical prominent than VLSI levels of combination
delay and power consumption. However, a are no more in boundless use. Indeed, even
dedicated encoding circuit is required and VLSI is presently to some degree
the partial products generation is more interesting, given the regular suspicion that
complex. In, Kim et al. proposed a technique all chip are VLSI or better. Starting mid
similar to , for designing efficient MB 2008, billion-transistor processors are
multipliers for groups of pre-determined economically accessible, an illustration of
coefficients with the same limitations which is Intel's Montecito Itanium chip. This
described in the previous paragraph. is relied upon to wind up more typical as
semiconductor manufacture moves from the
present era of 65 nm procedures to the
following 45 nm eras (while encountering
new difficulties, for example, expanded
variety crosswise over procedure corners).
Another outstanding case is NVIDIA's 280
arrangement GPU.

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 International Journal of Engineering and Techniques - Volume 4 Issue 1, Jan – Feb 2018

to a more complex design. However, due to

the pre-encoding technique, there is no
area/delay overhead at the circuit. The
partial products, properly weighted, and the
COR of (11) are fed into a CSA tree. The
input carry cin;j of (11) is computed as cin;j
¼ sj based on (12) and Table 1. The CS
output of the tree is finally merged by a fast
CLA adder. However, the ROM width is
2. SIMULATION increased. Each digit requests three
IMPLEMENTATION encoding bits (i.e., s, two and one (Table 1))
Pre-Encoded Mb Multiplier Design to be stored in the ROM. Since the n-bit
In the pre-encoded MB multiplier scheme, coefficient B needs three bits per digit when
the coefficient B is encoded off-line encoded in MB form, the ROM width
according to the conventional MB form requirement is 3n/2 bits per coefficient.
(Table 1). The resulting encoding signals of Thus, the width and the overall size of the
B are stored in a ROM. The circled part of ROM are increased by 50 percent compared
Fig. 3, which contains the ROM with to the ROM of the conventional scheme.
coefficients in 2’s complement form and the Pre-Encoded NR4SD Multipliers Design
MB encoding circuit, is now totally replaced The system architecture for the pre-encoded
by the ROM of Fig. 5. The MB encoding NR4SD multipliers is presented in Fig. 6.
blocks of Fig. 3 are omitted. The new ROM Two bits are now stored in ROM: n 2jþ1, nþ
of Fig. 5 is used to store the encoding 2j (Table 2) for the NR4SD or nþ 2jþ1, n 2j
signals of B and feed them into the partial (Table 3) for the NR4SDþ form. In this way,
product generators (PPj Generators PPG) on we reduce the memory requirement to n + 1
each clock cycle. Targeting to decrease bits per coefficient while the corresponding
switching activity, the value ‘1’ of sj in the memory required for the pre-encoded MB
last entry of Table 1 is replaced by ‘0’. The scheme is 3n/2 bits per coefficient. Thus, the
sign sj is now given by the relation: As a amount of stored bits is equal to that of the
result, the PPG of Fig. 4a is replaced by the conventional MB design, except for the
one of Fig. 4b. Compared to (4), (12) leads most significant digit that needs an extra bit

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 International Journal of Engineering and Techniques - Volume 4 Issue 1, Jan – Feb 2018

as it is MB encoded. Compared to the pre

encoded MB multiplier, where the MB
encoding blocks are omitted, the pre-
encoded NR4SD multipliers need extra
hardware to generate the signals of (6) and
(8) for the NR4SD and NR4SDþ form,
respectively.
3. SIMULATION RESULTS

Fig:-3 Block Diagram

Fig:-4 RTL Schematic

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 International Journal of Engineering and Techniques - Volume 4 Issue 1, Jan – Feb 2018

Implementation, Hoboken, NJ, USA: Wiley,

2007.
[3] Y.-E. Kim, K.-J. Cho, J.-G. Chung, and
X. Huang, “CSD-based programmable
multiplier design for predetermined
coefficient groups,” IEICE Trans. Fundam.
Electron. Commun. Comput. Sci., vol. 93,
no. 1, pp. 324–326, 2010.
[4] O. Macsorley, “High-speed arithmetic in
binary computers,” Proc. IRE, vol. 49, no. 1,
Fig:-5 Simulation output
pp. 67–91, Jan. 1961.
4. CONCLUSION
[5] W.-C. Yeh and C.-W. Jen, “High-speed
In this paper, new designs of pre-encoded
booth encoded parallel multiplier design,”
multipliers are explored by off-line encoding
IEEE Trans. Comput., vol. 49, no. 7, pp.
the standard coefficients and storing them in
692–701, Jul. 2000.
system memory. We propose encoding these
[6] Z. Huang, “High-level optimization
coefficients in the Non-Redundant radix-4
techniques for low-power multiplier
Signed-Digit (NR4SD) form. The proposed
design,” Ph.D. dissertation, Dept. Comput.
pre encoded NR4SD multiplier designs are
Sci., Univ. California, Los Angeles, CA,
more area and power efficient compared to
USA, 2003.
the conventional and pre-encoded MB
[7] Z. Huang and M. Ercegovac, “High-
designs. Extensive experimental analysis
performance low-power left-to-right array
verifies the gains of the proposed pre-
multiplier design,” IEEE Trans. Comput.,
encoded NR4SD multipliers in terms of area
vol. 54, no. 3, pp. 272–283, Mar. 2005.
complexity and power consumption
[8] Y.-E. Kim, K.-J. Cho, and J.-G. Chung,
compared to the conventional MB
“Low power small area modified booth
multiplier.
multiplier design for predetermined
5. REFERENCES
coefficients,” IEICE Trans. Fundam.
[1] G. W. Reitwiesner, “Binary arithmetic,”
Electron. Commun. Comput. Sci., vol. E90-
Adv. Comput., vol. 1, pp. 231–308, 1960.
A, no. 3, pp. 694–697, Mar. 2007.
[2] K. K. Parhi, VLSI Digital Signal
Processing Systems: Design and
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 International Journal of Engineering and Techniques - Volume 4 Issue 1, Jan – Feb 2018

[9] C. Wang, W.-S. Gan, C. C. Jong, and J.

Luo, “A low-cost 256-point FFT processor
for portable speech and audio applications,”
in Proc. Int. Symp. Integr. Circuits, Sep.
2007, pp. 81–84.
[10] A. Jacobson, D. Truong, and B. Baas,
“The design of a reconfigurable continuous-
Mr. P.NAGARAJU was born
flow mixed-radix FFT processor,” in Proc.
DRAKSHRAMAM, AP, on MAY 01 1982.
IEEE Int. Symp. Circuits Syst., May 2009,
He graduated from the Jawaharlal Nehru
pp. 1133–1136.
Technological University, Hyderabad, Post-
Authors Profile
graduated from the Jawaharlal Nehru
Technological University, Kakinada, and
Pursuing Ph.D. from JNTUK. Presently He
is working as an Assoc. Prof in Kakinada
Institute of Engineering & Technology,
Korangi. So far he is having 12 Years of
Teaching Experience in various reputed
engineering colleges. His special fields of
V.Indumathi interest included VLSI-Signal Processing,
I Indumathi was born in warangal ,telangana Embedded Systems, Digital Signal
on february 17, 1994 . I graduated from the Processing & communication Systems.
V.S Lakshmi Enginering college for women
(JNTU) kakinada . Presently I am studying
M.Tech in kakinada Institute of
Engineering and technology, korangi.

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