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UVM Questions

The document contains 35 interview questions related to the Universal Verification Methodology (UVM). Some of the key topics covered include: 1. The differences between language and methodology, module and class-based testbenches, copy and clone of transactions, and new() and create(). 2. The evolution of UVM from OVM and the hierarchy of UVM components including agents which have monitor and sequencer components. 3. Phases in UVM like run_phase which have top-down, bottom-up and parallel features and how messages are handled hierarchically. 4. Other concepts like reference models, factories for creating components, transactions and their classes, seeds for simulation, analysis

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Vigna Vinod
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197 views

UVM Questions

The document contains 35 interview questions related to the Universal Verification Methodology (UVM). Some of the key topics covered include: 1. The differences between language and methodology, module and class-based testbenches, copy and clone of transactions, and new() and create(). 2. The evolution of UVM from OVM and the hierarchy of UVM components including agents which have monitor and sequencer components. 3. Phases in UVM like run_phase which have top-down, bottom-up and parallel features and how messages are handled hierarchically. 4. Other concepts like reference models, factories for creating components, transactions and their classes, seeds for simulation, analysis

Uploaded by

Vigna Vinod
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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UVM -Interview Questions

1. What is the difference between language and methodology


2. What is the evolution of UVM and it's relation with OVM.
3. What is the difference between a module and class based TB.
4. Explain the hierarchy of UVM.
5. Which are the 2 types of agents in UVM. Explain.
6. List the components and objects in a UVM testbench
7. Is a scoreboard mandatory for a testbench. Explain your answer.
8. Which of these phases is a task and why.
9. What is an objection. How to raise it and when to raise it.
10. Explain all phases with their features(top-down, bottom-up, parallel).
11. Which are functions and why?
12. What is a reference model. Why do we need it? What happens without it. What is the
difference between a reference model and DUT.
13. How do you set display message severity for different components.
14. How do you set different severity for messages down a hierarchy.
15. What is the difference between copy and clone. When and where do we use it. If we clone a
transaction, and copy a transaction and then compare which will pass and which will
fail/miscompare.
16. What is a seed in a simulation. How do you used it. When and where do we use it? Explain
clearly.
17. What is factory. Can you write a testbench without factory.
18. What are steps to follow for factory method of creating components. ?
19. Write a transaction class with example and explain.?
20. How to override using a factory?
21. Which method activates UVM testbench? How? Give examples and explain?
22. Is start method on a sequence blocking or non-blocking? Explain.
23. What is the upper hierarchy class of uvm_component?
24. Where do you write user defined methods in a sequence item.
25. How does phase of different components get called when you run a test in UVM.
26. What are flag and radix arguments for?
27. List some of the verbosity settings and actions that could be taken.
28. What is an UVM switch?
29. What is TLM FIFO?
30. What is analysis port?
31. What is p_sequencer? What is m_sequencer? What is the difference?
32. What is an agent? What are the components inside an agent? Explain each?
33. What is the difference between new() and create?
34. Can we have user defined phase in UVM.
35. What is the difference between uvm_sequence_item and transaction?

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