- - ----- --I

1-
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MCS® .. 968X9X
Architectural Overview

MCS® .. 96 8X9X Hardware

Design Information and
Data Sheets

MCS® .. 96 Instruction Set

80C196KB User's Guide

and Data Sheets

80C196KC User's Guide

and Data Sheets

~MCS® .. 96
Development
Support Tools

Memories Data SJ:1eet

 Table of Contents
Alphanumeric Index ........................ ' .. '............................. x
MCS®·96 FAMILY
Chapter 1
MCS-96 8X9X Architectural (Jverview . . .. . . . . . .. . . . . . . . . . . . . . . .. . . . .. . . . . . . . . 1-1
Chapter 2
8X9X Hardware Design Information.......................................... 2-1
MCS®-96 DATA SHEETS
MCS-96 809XBH, 839XBH, 879XBH Advanced 16-Bit Microcontroller with 8- or '
16-Bit External Bus .................. ; ..................... : . . . . . . . . . . . . . 2-58
MCS-96 809XBH/839XBH/879XBH Express ............................... , . 2-80
MCS-96 809XJF, 839XJF, 879XJF Advanced 16-Bit Microcontroller with 8- or
16-Bit External Bus ............................................. '. . .... . . . . 2-83
MCS-96 809XJF/839XJF/879XJF Express................................... 2-102
EV8097BH Evaluation Board Fact Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-107
Chapter 3 ,
MCS-96 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . 3-1
Chapter 4 .
80C196KB User's Guide ........................... :....................... 4-1
DATA SHEETS
87C196KB/83C196KB/80C196KB 1S-Bit High Performance CHMOS ,
Microcontroller . '............... : '................................... '. . . . . 4-98
87C196KB1616-Bit High Performance CHMOSMicrocontroller ................. 4-126
83C198/80C198, 83C194/80C194 16-Bit CHMOS Microcontroller .............. 4-153
87C198/87C194 16-Bit CHMOS Microcontroller .............................. 4-173
8XC196K13 Express .............................. '......................... 4-194
EV80C196KB Evaluation Board Fact Sheet. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. 4-211
Chapter 5
80C196KC User's Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
DATA SHEETS
8XC196KC 16-Bit High Performance CHMOS Microcontroller ................... 5-104
, 8XC196KC 16-Bit Microcontroller Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-130
EV80C196KC Evaluation Board Fact Sheet................................... 5-132
Chapter 6
MCS®-96 DEVELOPMENT SUPPORT TOOLS
ACE 196TM Software . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
8096/196 Software Development Packages......... ......................... 6-2
VLSiCE-96 In-Circuit Emulator .............................................. 6-5
Real-Time Transparent 80C196 In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
ICE-196KB/HX In-Circuit Emulator.......................................... 6-13
Chapter 7
MEMORIES
87C257 256K (32K x 8) CHMOS EPROM..................................... 7-1

ix
 Alphanumeric Index
8096/196 Software Development Packages ................................... , . . . .. 6-2
80C196KB User's Guide ........................................................ '. . 4-1
80C196KC User's Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
83C198/80C198, 83C194/80C194 16-Bit CHMOS Microcontroller . . . . . . . . . . . . . . . . . . . .. 4-153
. 87C196KB/83C196KB/80C196KB 16-Bit High Performance CHMOS Microcontroller. . . . . 4-98
87C196KB16 16-Bit High Performance CHMOS Microcontroller. . . . . . . . . . . . . . . . . . . . . . .. 4-126
87C198/87C194 16-Bit CHMOS Microcontroller .................................... , 4-173
87C257 256K (32K x 8) CHMOS EPROM........................................... 7-1
8X9X Hardware Design Information ................................................ 2-1
8XC196KB Express .............................. : .................... : .......... 4-194
8XC196KC 16-Bit High Performance CHMOS Microcontroller .......................'... 5-104
8XC196KC 16-Bit MicroControlier Express .......................................... 5-130
ACE196™ Software .... :........................................................ '. 6-1
EV8097BH Evaluation Board Fact Sheet. ....... : ............................. : ...... 2-107
EV80C196KB Evaluation Board Fact Sheet ..................................... ;... 4-211
EV80C196KC Evaluation Board Fact Sheet ......................................... 5-132
ICE-196KB/HX In-Circuit Emulator ................................................. · 6-13
MCS-96 809XBH/839XBH/879XBH Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
MCS-96 809XBH, 839XBH, 879XBH Advanced 16-Bit Microcontroller with 8- or 16-Bit
External Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
MCS-96 809XJF/839XJF/879XJF Express. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . .. 2-102
. MCS-96 809XJF, 839XJF, 879XJF Advanced 16-Bit Microcontroller with 8- or 16-Bit
External Bus .................................................................. 2-83
MCS-96 8X9X Architectural Overview .....,......................................... 1-1
MCS"96 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Real-Time Transparent 80C196 In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . 6-10
VLSiCE-96 In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 6-5

x
 MCS®-968X9X 1
" Architectural Overview
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 October 1990

MCS®-96 8X9X
Architectural Overview

Order Number: 270250·005

1·1
 MCS®-96 8X9X ARCHITECTURAL OVE'RVIEW
CONTENTS PAGE CONTENTS PAGE

1.0 CPU OPERATION .................... 1-3 7.0 HIGH SPEED OUTPUTS ........ ~ ... 1-34
1.1 CPU Buses ........................ 1-3 7.1 HSO CAM ........................ 1-34
1.2 CPU Register File .................. 1~4 7.2 HSO Status ....................... 1-35
1.3 RALU Control ...................... 1-4 7.3 Clearing the HSO ................. 1-35
1.4 RALU ............................. 1-4 7.4 Using Timer 2 with the HSO ....... 1-35
1.5 Internal Timing ..................... 1-5 7.5 Software Timers .................. 1-36
2.0 MEMORY SPACE .................... 1-6 8.0 ANALOG INTERFACE .............. 1-36
2.1 Register File ....................... 1-6 8.1 Analog Inputs ...................... 1-36
2.2 Special Function Registers ......... 1-7 8.2 A/D Commands .................. 1-37
2.3 Power Down ....................... 1-7 8.3 AID Results ......... , ............ 1-37
2.4 Reserved Memory Spaces ......... 1-9 8.4 Pulse Width Modulation Output
2.5 Internal ROM and EPROM ......... 1-9 (D/A) .............................. 1-38
2.6 Internal Executable RAM 8.5 PWM Using the HSO ............. 1-39
(XRAM)-8X9XJF Only ............. 1-10
9.0 SERIAL PORT ...................... 1-39
2.7 Memory Controller ................ 1-10
9.1 Serial Port Modes ................. 1-39
2.8 System Bus ...................... 1-10
9.2 Controlling the Serial Port ......... 1-40
3.0 SOFTWARE OVERViEW ............ 1-17 9.3 Determining Baud Rates .......... 1-41
3.1 Operand Types ................... 1-17 9.4 Multiprocessor Communications .. 1-42
3.2 Operand Addressing .............. 1-18
10.0110 PORTS ........................ 1-42
3.3 Program Status Word ............. 1-20
10.1 Input Ports ...................... 1-42
3.4 Instruction Set ..... ',' ............. 1-21
10.2 Quasi-Bidirectional Ports ........ 1-43
3.5 Software Standards and
Conventions ....................... 1-25 10.3 Output Ports .................... 1-43
10.4 Ports 3 and 4/ ADO-15 .......... 1-43
4.0 INTERRUPT STRUCTURE .......... 1-26
4.1 Interrupt Control .................. 1-28 11.0 STATUS AND CONTROL
REGISTERS .......................... 1-44
4.2 Interrupt Priorities ................. 1-28
11.1 I/O Control Register 0 (lOCO) .... 1-44
/ 4.3 Critical Regions ................... 1-29
11.2 I/O Control Register 1 (IOC1) .... 1-45
4.4 Interrup~ Timing ................... 1-30
11.3 I/O Status Register 0 (IOSO) ..... 1-45
5.0 TIMERS .. ........................... 1-31 11.4 I/O Status Register 1 (IOS1) .... :, 1-45
5.1 Timer 1 .......-.................... 1-31
5.2 Timer 2 ........................... 1-31 12.0 WATCHDOG TIMER . ~ ............. 1-46
5.3 Timer Interrupts .................. 1-31 12.1 SoftWare Protection Hints . ; ...... 1-46
5.4 Timer Related Sections ........... 1-32 12.2 Disabling the Watchdog ......... 1-46

6.0 HIGH SPEED INPUTS .. ............. 1-32 13.0 RESET .......... ," .. ,............... 1-46
6.1 HSI Modes ....................... 1-33 13.1 Reset Signal .................... 1-46
6.2 HSI FIFO ........ ; ............... : 1-33 13.2 Reset Status .................... 1-47
6.3 HSllnterrupts .................... 1-33 13.3 Reset Sync Mode ............... 1-47
6.4 HSI Status ........................ 1-33

1-,2
 MCS®·96 8X9X ARCHITECTURAL OVERVIEW

This overview is written about the 8X9XBH, 8X9XJF, 1.0 CPU OPERATION
and 8X98 devices. These devic~ are generically re-
ferred to as the gX9X. All information in this overview The, major components of the CPU on the 8X9X are
refers to the 8X9XBH, the 8X9XJF, and the 8X98 un- the Register File and the RALU. Communication with
less otherwise noted. the outside world is done through either the Special
Function Registers (SFRs) or the Memory Controller.
The 8X9X can be separated into several secti~ns for the The RALU (Register/Arithmetic Logic Unit) does not
purpose of describing its operation. There is a l6-bit use an accumulator, it operates directly on the 256-byte
CPU, a programmable High Speed I/O Unit, an analog register space made up of the Register File and the
to digital converter, a seriaf port, artd a Pulse Width SFRs. Efficient I/O operations are possible by directly
Modulated (PWM) output for digital to analog conver- controlling the I/O through the SFRs. The main bene-
sion. In addition to ihese functional units, there are fits of this structure are the ability to quickly change
some sections which support overall operation of the context, the absence of accumulator bottie!leck, and
chip such as the clock generator. The CPU and the fast throughput and I/O times.
programmable I/O. make the 8X9X very different from
any other microcontroller. Let us first examine the
CPU. 1.1 CPU Buses
A "Control Unit" and two buses connect the Register
File ahd RALU. Figure 1 shows the CPU with its

POWER FREQUENCY
VRE~ ANGND DOWN REFERENCE

······t······~···· ~::~~···l
A- BUS
CLOCK
tEN
8
.. ON-CHIP
EPROM 879 X BH
.....-r----,r-...
I
I
:
I
I
I CONTROL
SIGNALS

ADDR
] DATA
BUS

: PORT 4
HIGH I
SPEED I
I/O I
I
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I

PORT 0 PORT 1 PORT 2 HSI HSO

ALT FUNCTIONS
270250-1

Figure 1. Block Diagram

1-3
intJ MCS®~96 8X9X ARCHITECTURAL OVERVIEW

major bus connections. The two buses are the "A-Bus" the Register File is reserve,d for use as the stack pOinter
which is 8,bits wide, and the "D-Bus" which is 16-bits so it can not be used for data when stack manipubitions
wide. The D-Bus transfers data only between the are taking place. Addresses for accessing the Register
RALUandthe Register File or Special Function Regis- File and· SFRs are temporarily stored in two 8-bit ad-
ters (SFRs). The A-Bus is used as the address bus for dress registers by the CPU hardware.
the above transfers or' as' a multiplexed address/data
bus connecting to the "Memory Controller". Any ac-
cesses of either the internal ROM or external memory 1.3 RALU Control
are done through the -Memory Controller. '
Instructions to the RALU are taken from the A-Bus
Within the memory controller is a slave program coun- and stored temporarily in the instruction register. The
ter (Slave PC) which keeps track of the PC in the CPU. Control Unit decodes the instructions and generates the
By having most program fetches from memory refer- correct sequence of signals to have the RALU perform
enced to the slave PC, the processor saves time as ad- the desired function. Figure I shows, the instruction
dresses seldom have to be sent to the memory control- register and the control unit.
ler. If the address jumps sequence then the slave PC is
loaded with a new value and processing continues.
Data fetches from memory are also done through the 1.4 RALU
memory controller, but the slave PC is bypassed for
this operation. Most calculations performed by the 8X9X take place in
the RALU. The RALU, shown in Figure 2, contains a
l7-bit ALU, the Program Status Word (PSW), the Pro-
1.2 CPU Register File gram Counter (PC), a loop counter, and three tempo-
rary registers. All of the registers are 16-bits or
The Register File contains 232 bytes of RAM' which 17-bits (16 + sign extension) wide. Some of the regis-
can be accessed as bytes, words, or double-words. Since ters have the ability to perform simple operations to off-
each of these locations can be used by the RALU, there load the ALU.
are essentially 232 "accumulator,s". The' first word in

6-BIT
A-BUS

UPPER WORD REGISTER/SHIFTER

LOWER WORD REGISTER/SHIFTER

~_ _ _ _-..,~16'--_ _ _-t-. . TEMPORA~Y REGISTER 14---,,=6--i

LOWER

270250-2

Figure 2. RALU Block Diagram

1-4
intJ MCS@·96 aX9X ARCHITECTURAL OVERVIEW

A separate incrementor is used for the PC; however,' The crystal or external oscillator frequency is divided
jumps must, be handled through the ALU. Two of the by 3 to genc:rate the three internal timing phases as
temporary registers have their own:' shift logic. These shown in Figure 4. Each of the internal phases repeat
registers are used for the operations which require logi- every 3 oscillator periods: 3 oscillator periods are re-
cal shifts, including Normalize, Multiply, and Divide. ferred to as one "state time", the basic time measure-
The "Lower Word" register is used only when double- ment for 8X9X operations. Most internal operations
word quantities are being shifted, the "Upper Word" are synchronized to either Phase A, B or C, each of
register is used whenever a shift is performed or as a which have a 33% duty cycle. Phase A is represented
temporary register for many instructions. Repetitive externally by CLKOUT, a signal available on the
shifts are counted by the 5.bit "Loop Counter". 68-pin device. Phases Band C are not available exter-
nally. The relationships of XTALl, CLKOUT, and
A temporary register is used to store the second oper- Phases A, B, and C are shown in Figure 4. It should be
and of two operand instructions. This includes the mul- noted that propagation delays have not, been taken into
tiplier during multiplications and the divisor during account in this diagram. Details on these and other tim-
divisions. To perform subtractions, the output of this ing relationships can be found In the Hardware Design
register can be complemented before being placed into chapter. .
the "B" input of the ALU.

The DELAY shown in Figure 2 is used to convert the

.16-bit bus into an 8-bit bus. This is required as all ad-
dresses and instructions are carried on the 8-bit A-Bus. INTERNAL
Several constants, such as 0, I and 2 are stored in the CIRCUITRY
RALU for use in speeding up certain calculations.
These come in'handy when the RALU needs to make a
2's complement number or perform an increment or
decrement instruction.

1.5 Internal Timing

The 8X9X requires an input clock frequency of be-
tween 6.0 MHz and 12 MHz to function. This frequen- 270250-3
cy can be applied directly to XTALI. Alternatively,
since XTAL 1 and XTAL2 are inputs and outputs of an Figure 3. Block Diagram of Oscillator
inverter, it is also possible to 'use a crystal to genera~e
the clock. A block diagram of the oscillator section is The RESET line can be used to start the 8X9X at an
shown in Figure 3, Details of the circuit and sugges- exact time to provide for synchronization of test equip-
tions for its use can be found in Section I of the Hard- ment and multiple chip systems. Use of this feature is
ware Design chapter. fully explained under RESET, Section 13 ..

XTAL 1

PHASE A

_....'
(CLOCKOUT)

PHASE B ....--,
''--~'
....--,
,'-----'
r
PHASE C -'~_ _ -,rl...__-,rl,-__
270250-4

Figure 4. Internal Timings Relative to XTAL 1

1-5
 I '
MCS®·96 8X9XARCHITECTURAL OVERVIEW

2.0 MEMORY SPACE 2.1 Register File

The addressable memory space on the'8X9X consists of Locations OOH difough OFFH contain the Register File
64K bytes, most of which is available to the I;lser for and Special Function Registers, (SFRs). No code, can
program or data memory, Locations which have special be executed from this internal RAM section. If an at-
purposes are OOOOH through OOFFH, OlOOH through tempt to execute instructions from locations OOOH
OlFFH (8X9XJF only), and IFFEH through 2080H. through OFFH is made; the instructions will be fetched
All other locations can be used for either program or from external memory. This section of external memo-
data storage or for memory mapped peripherals. A ry is reserved fot use by Intel development tools. Exe-
memory map is shown in Figure 5. cution of a nonmaskable interrupt (NMI) will force a

FFFFH
OFFH 255,
EXTERNAL MEMORY
POWER-DOWN
RA~
OR I/O
OFOH 240
OEFH 1--------------1 239 BOOOH
INTERNAL EXTERNAL MEMORY OR I/o 5FFFH
REGISTER FILE (8X9XBH)
(RA~)
INTERNAL PROGRAM STORAGE
RO~/EPROM OR EXTERNAL
IAH 1-_ _ _....._ _....._ _ _ _ _--1
26 MEIIORY' (8X9XJF) 4000H
3FFFH
19H 25 INTERNAL PROGRAM
S'T ACK POINTER STACK POINTER STORAGE ROM/EPROM
l.8H 24 OR
17H PWILCONtROL 23 EXTERNAL MEMORY
2080H
16H 10Sl 10Cl 22
RESERVED 2072H - 207FH
15H 10SO lOCO 21
SIGNATURE WORD 2070H - 2071H
14H 20
RESERVED 2030H - 20BFH
13H RESERVED RESERVED 19
SECURITY KEY 2020H - 202FH
12H 18
RESERVED 201CH - 201FH
llH SP_STAT SP_CON 17
SELF JU~P OPCODE (27H FEH) 201AH-201BH
10H 10 PORT 2 10 PORT 2 16
'RESERVED 2019H
OFH 10 PORT 1 10 PORT 1 15
CHIP CONFIGURATION eYTE 2018H
OEH 10 PORT 0 BAUD_RATE 14
RESERVED 2012H - 2017H
ODH TIMER2 (HI) 13

OCH TI~ER2 (LO) RESERVED 12

INTERRUPT VECTORS
OBH TIMERl (HI) 11
2000H
OAH TIMERl (LO) WATCHDOG 10
PORT 4 lFFFH
09H INT_PENDING INT_PENDING 9
PORT 3 lFFEH
08H INLMASK INLMASK 8
EXTERNA~ MEMORY
07H SBUF (RX) SBUF (TX) 7 OR I/o 01FFH
06H HSI_STATUS HSO,COMMAND 6
EXTERNAL MEMORY OR I/O (8X9XBH)
05H HSI31ME (HI) HSO_ TIME (HI) 5 INTERNAL EXECUTABLE RAM
(XRAM) (8X9XJF)
04H HSUIME (LO) HSO_ TIME (LO) 4
03H AD_RESULT (HI) HSLMODE 3
L-, 0100H

INTERNAL RAM \ OOFFH

02H AD_RESULT (LO) AD_COMMAND 2 REGISTER FILE
STACK POINTER
01H RO (HI) RO (HI) 1 SPECIAL FUNCTION REGISTERS
(WHEN ACCESSED AS DATA MEMORY)
OOH RO (LO) RO (LO) 0 OOOOH

(WHEN READ) (WHEN WRITTEN)

270250-5

Figure 5. Memory 'Map'

intJ MCS®-96 8X9X ARCHITECTURAL OVERVIEW

call to external location OOOOH, therefore, the NMI and 2.3 Power Down
TRAP interrupt are also reserved for Intel development
tools. The upper 16 RAM locations (OFOH through OFFH)
receive their power from the VPD pin. If it is desired to
The RALU can operate on any of the 256 internal reg- keep the memory in these locations alive during a pow-
ister locations. Locations OOH through 17H are l,Ised to er down situation, one need only keep voltage on the
access the SFRs. Locations 18H and 19H contain the VPD pin. The current required to keep the RAM alive
stack pointer. These are not SFRs, al).d may be used as is approximately 1 milliamp (refer to the data sheet for
standard RAM if stack operations are not being per- the exact specification). Both Vee and VPD must have
formed. The stack pointer must be initialized by the power applied for normal operation. If VpD is not ap-
user program and can point anywhere in the 64K mem- plied the power down RAM will not function properly,
ory space. The stack builds down. There are no restric- even if Vee is applied. .
tions on the use of the remaining 230 locations except
that code cannot be executed from them. To place the 8X9X into a power down mode, the
RESET pin is pulled low. Two state times later the
device will be in reset. This is necessary to prevent the
2.2 Special Function Registers device from writing into RAM as the power goes down.
The power may now be removed from the Vee pin, the
All of the 110 on the 8X9X is controlled through the VPD pin must remain within specifications. The 8X9X
SFRs. Many of these registers serve two functions; one can remain in this state for any amount of time and the
if they are read from, the other if they are written to. 16 RAM bytes will retain their values.
Figure 5 shows the locations and names of these regis-
ters. A summary of the capabilities of each of these To bring the 8X9X out of power down, RESET is held
registers is shown in Figure 6, with complete descrip- low while Vee is applied. Two state times after the
tions reserved for later sections) oscillator has stabilized, the RESET pin c!m be pulled
high. The 8X9X will begin to execute code at location
There are several restrictions on using special function 02080H 10 state times after RESET is pulled high. Fig-
registers. ure 7 shows a timing diagram of the power down se-
quence. To ensure that the 2 state time minimum reset
Neither the source or destination addresses of the Mul- time (synchronous with CLKOUT) is met, it is recom-
tiply and Divide instructions can be a writable special mended that 10 XT AL I cycles be used. Suggestions for
function register. actual hardware connections are given in the Hardware
Design Chapter. Reset is discussed in Section 13.
These registers may not be used as base or index regis-
ters for indirect or indexed instructions. To determine if a reset is a return from power down or
a complete cold start a "key" can be written into pow-
.These registers can only be accessed as bytes unless er-down RAM while the device is running. This key
otherwise specified in Figure 6. Note that some of these can be checked on reset to determine which type of
registers can only be aCcessed as words, and not as reset has occurred. In this way the validity of the pow-
bytes. er-down RAM can be verified. The length of this key
determines the probability that this procedure will
Within the SFR space are several registers labeled work, however, there is always a statistical chance that
"RESERVED". These registers are reserved for future the RAM will power up with a replica of the key.
expansion and test purposes. Operations should not be
performed with theSe registers as reads from them and Under most circumstances, the power-fail indicator
writes to them may produce unexpected results. For which is used to initiate a power-down condition must
example, in some versions of the 8X9X writing to loca- come from the unfiltered, unregulated seetion of the
tion OCH will set both timers to OFFFXH. This may power supply. The power supply must have sufficient
not be the case in future products, so it should not be storage capacity to operate the 8X9X until it has com-
used as a feature. pleted its reset operation.

1-7
 MCS®·96 8X9X ARCHITECTURAL OVERVIEW

Register Description Section

/
RO Zero Register - Always reads as a zero, useful for a base when 3
indexing and as a constant for calculations and compares.
AD_RESULT AID Result Hi/Low - Low and high order Results of the A/D 8
converter (byte read only)
AD_COMMAND AID Command Register - Controls the A/D 8,
HSI_MODE HSI Mode Register - Sets the mode of the High Speed Input unit. 6
HSLTlME HSI Time Hi/Lo - Contains the time at which the High Speed 6
Input unit was 1riggered. (word read only)
HSO_TIME HSO Time Hi/Lo - Sets the time or count·for the High Speed 7
Output to execute the command in the Command Register. (word
write only)
HSO_COMMAND HSO Command Register - Determines what will happen at the 7
time loaded into the HSO Time registers.
HSI_STATUS HSI Status Registers - Indicates which HSI pins were detected at 6
the time in the HSI Time registers and the current state of the pins.
SBUF (TX) Transmit buffer for the serial port, holds contents to be outputted. 9
SBUF (RX) Receive buffer for the serial port, holds the byte just received by 9
, the serial port.
INT_MASK Interrupt Mask Register - Enables qr disables the individual 4
interrupts.
INT_PENDING Interrupt Pending Register - Indicates tliat an interrupt signal has 4
occurred on one of the sources and has not been serviced.
WATCHDOG Watchdog Timer Register - Written to periodically to hold off 12
automatic reset every 64K state times.
TIMER1 Timer 1 HilLo - Timer 1 high and low bytes. (word read only) 5
TIMER2 Timer 2 HilLo - Timer 2 high and low bytes. (word read only) 5
10PORTO Port 0 Register - Levels on pins of port O. 10
BAUD_RATE Register which determines the baud rate, this register is loaded 9
sequentially.
IOPORT1 Port 1 Register - Used to read or write to Port 1. 10
IOPORT2 Port 2 Register - Used to read or write to Port 2. 10
SP_STAT Serial Port Status - Indicates the status of the serial port. 9
SP_CON Serial Port Control - Used to set the mode of the serial port. 9
10SO I/O Status Register 0 - Contains information on the HSO status 11
IOS1 I/O Status Register 1 - Contains information on the status of the 11
timers and of the HSI.
lOCO I/O Control Register 0 - Controls alternate functions of HSI pins, 11
Timer 2 reset sources and Timer 2 clock sources.
10Cl I/O Gontrol Register 1 --- Controls alternate functions of Port 2 11
pins, timer interrupts and HSI interrupts.
PWM_CONTROL Pulse Width Modulation Control Register - Sets the duration of 8
the PWM pulse.
Figure 6. SFR Summary

1-8
inter MCS®·96 8X9X ARCHITECTURAL OVERVIEW

YCC----------------------~ POWER DOWN

YPD---------------------+------~~------;_-----------------
a 5:1:.5V
RESET - - - - - - " \

XTALl
IflJIIIJLJ1JlfulI1IU1
10 XTALl CYCLES CLOCK NOT NECESSARY 10 XTALl CYCLES
AFTER CLOCK IS STABLE
270250-6

Figure 7. Power Down Timing

2.4 Reserved Memory Spaces OOOOH- 0017H Register Mapped I/O (SFRs)
0018H- 0019H Stack Pointer
A listing of locations with special significance is shown
in Figure 8. The locations marked "Reserved" are re- 1FFEH- 1FFFH Ports 3 and 4
served by Intel for use in testing or future products. All 2000H- 2011H Interrupt Vectors
reserved locations except 2019H must be filled with 2012H- 2017H Reserved
Hex value OFFH to insure compatibility with future 2018H Chip Configuration Byte
devices. Location 2019H must be filled with 20H. 2019H Reserved
201AH- 201BH "Jump to Self" Opcode (27H FEH)
Locations lFFEH and IFFFH are reserved for Ports 3 201CH- 201FH Reserved
and 4 respectively. This is to allow easy reconstruction 2020H- 202FH Security Key
of these ports if external memory is used in the system.
2030H- 207FH Reserved
An example of reconstructing the I/O ports is given in
section 7 of the Hardware Design chapter. If ports 3 2080H Reset Location
and 4 are not going to be reconstructed, these locations Figure 8. Registers with Special Significance
can be treated as any other external memory location.

The 9 interrupt vectors are stored in locations 2000H 2.5 Internal ROM and EPROM
through 2011H. The 9th vector is used by Intel devel-
opment systems, as explained in Section 4. When a ROM device is ordered, or an EPROM device
is programmed, the internal memory locations 2080H
Locations 20l2H through 201 7» are reserved for fu- through 3FFFH on the 8X9XBH and 8X98 and loca-
ture use. Location 2018H is the Chip Configuration tions 2080H through 5FFFH on the 8X9XJF are user
byte which will be discussed in the next section. The specified, as are the interrupt vectors, Chip Configura-
Jump~To-Seif opcodes at locations 201AH and 20lBH tion Register and Security Key in locations 2000H
are provided for EPROM programming as detailed in through 202FH.
the Hardware Design chapter. Locations 2020H
through 202FH are the security key used with the Instruction and data fetches from the internal ROM or
ROM Lock feature which will be discussed in the next EPROM occur only if the device has a ROM or
section. All unspecified addresses in locations 2000H EPROM, EA is tied high, and the address is between
through 207FH, including those marked Reserved, 2000H and 3FFFH on the 8X9XBH and 8X98 and
should be considered reserved for use by Intel. between 2000H and 5FFFH on the 8X9XJF. At all
other times data is accessed from either the internal
Resetting the 8X9X causes instructions to be fetched RAM space or external· memory and instructions are
starting from location 2080H. This location was chosen fetched from external memory. The EA pin is latched
to allow a system to have up to 8K of RAM continuous on RESET rising. Information on programming
with the register file. Further information on reset can EPROMs can be found in Section 10 of the Hardware
be found in Section 13. Design chapter.

Do not execute code out of the last three locations of

internal ROM/EPROM.

1-9
 MCS®·968X9X ARCHITECTURAL OVERVIEW

2.6 Internal Executable RAM In addition to holding ~ slave PC, the memory control-
(XRAM)-&X9XJF only ler contains a 4 byte queue to help speed execution.
This queue is transparent to the RALU and to the user
Locations OIOOH through OlFFH (8X9XJF only) con- unless wait states are forced during external bus cycles.'
tain the internal executable RAM (XRAM) space. In- The instruction execution times shown in Section 14.8
struction fetches will be performed in this region if the show the normal execution times' with no wait states
program counter points to the addresses OlOOH added and the t"6-bit bus selected. Reldading the slave
through OIFFH. Data accesses can also be performed PC and fetching the first byte of the new instruction
from this region. stream takes 4 state times. This is reflected in the jump
taken/not-taken times shown in the table.
The XRAM is accessed and executed from as if it ~ere
external RAM that is contained on chip. No external
bus signals will be generated when accessing the 2.& System Bus
XRAM.
There are several operating modes on the 8X9X. The
The XRAM is not part of the Register File. 8-bit direct standard bus mode uses a 16-bit multiplexed address/
addressing can not be used on this address space. data bus. Other bus modes include an 8-bit mode and a
mode in which the bus size can dynamically be
switched between 8-bits and l6-bits. In addition, there
2.7 Memory Controller , are several options available on the type of control sig-
nals used by the bus.
The RALU talks to the memory (except for the loca-
tions in the register file and SFR space) through the In the standard mode, external memory is addressed
memory controller which is connected to the RALU by through lines ADO through AD15 which form a 16-bit
the A-Bus and several control lines. Since the A-Bus is multiplexed (address/data) data bus. These lines share
eight bits wide, the memory controller uses a Slave Pro- pins with I/O Ports 3 and 4. The falling edge of the
gram Counter to avoid having to always get the instruc- Address Latch Enable (ALE) line is used to provide a
tion location from the RALU. This slave PC is incre- clock to a transparent latch (74LS373) in order to de-
mented after each fetch. When a jump or call occurs,
the slave PC must be loaded from the A-Bus before
instruction fetches can continue.

PHASE A
(CLKOUT)

PHASE B

PHASE C

REAllY \\\\~\\\\\\\

ALE -f''--____ ---.<OL...-.l-_ _

AD \\-._ _---JI

WR

AIIIIRESSII)ATA ~
\
- - - '/
.....

IIATAOUT n O;AIN

IIHE,INST ==X~ ____ C

.-..::VA::U::II:......;,_ _ _ _ _
270250-7

Figure 9. External Memory Timings

1-10
 MCS®-96 8X9X ARCHITE'CTURAL OVERVIEW

CLKOUT

ALE

READY

A ONE WAIT STATE CYCLE NORMAL CYCLE

Ri5 or ViR
--~~\~----------~I~"';"""'---'\,--_~I
270250-42

Figure9A.
multiplex the bus. A typical circuit and the required pins, and the RD (Read) signal goes low. When RD
timings are shown in Section 7 of the Hardware Design falls, external memory should present its data to the
chapter. Since the 8X9X's external memory can be ad- 8X9X.
dressed as either bytes or words, the decoding is con-
trolled with two lines, Bus High Enable (BHE) and
Address/Data Line 0 (ADO). READ
The data from the external memory must be on the bus
To avoid confusion during the explanation of the mem- and stable for a minimum of the specified set-up time
ory system it is reasonable to give names to the demulti- before the rising edge of RD. The rising edge of RD
plexed address/data signals. The address signals will be latches the information into the 8X9X. If the read is for
called MAO through MAIS (Memory Address), and data, the INST pin will be low wheh the address is
the data signals will be called MDO through MDIS valid. if it is for an instruction the INST' pin will be
(Memory Data). high during this time. The 48-lead device dOes not have
the INST pin. The INST pin will be low for the Chip
When BHE is active (low), the memory connected to Configuration Byte and Interrupt Vector fetches.
the high byte of the data bus should be selected. When
MAO is low the memory connected to the low byte of
the data bus should be selected. In this way accesses to WRITE
a 16-bit wide memory can be to the low (even) byte
only (MAO=O, BHE= I), to the high (odd) byte only Writing to external memory requires timings that are
(MAO = I, BHE=O), or to both bytes (MAO=O, similar to those required when reading from it. The
BHE = 0). When a memory block is being used only for main difference is that the write (WR) signal is used
reads, BHE and MAO need not be decoded. instead of the RD signal. The timings are the same until
the falling edge of the WR line. At this point the 8X9X
removes the address and places the data on the bus.
TIMINGS When the WR line goes high the data should be latched
to the external memory. In systems which can write to
Figure 9 shows the idealized waveforms related to the byte locations, the ADO and BHE lines must be used to
following description of external memory manipula- decode WR into WRite to Low byte (WRL) and WRite
tions. For exact timing specifications pl~ase refer to the to High byte (WRH) signals. INST is always low dur-
latest data sheet. W4en an external memory fetch be- ing a write, as instructions cannot be written. The exact
gins, the address latch enable (ALE) line rises, the ad- timing specifications for memory accesses can be found
dress is put on ADO-AD1S and BHE is set to the re- in the data sheet.
quired state. ALE then falls, the address is taken off the

1-11
 MCS®-96 8X9X ARCHITECTURAL OVERVIEW

READY For the rising edge of READY, sampling is done inter-

nally on the rising edge of Phase A. The rising edge
A ready line is available on the 8X9X to extend the logic is fully synchronized, so it is nOt possible to cause
width of the RD and WR pulses in order to allow ac- a metastable condition once the device is in a valid not-
cess of slow memories or for DMA purposes. If the ready condition. To cause one wait state to occur the
READY line.is low by the specified time after ALE rising edge of READY must occur before TLLYH
falls, the 8X9X will hold the bus lines to their values at MAX after ALE falls. If the signal is brought up after
the falling edge of CLKOUT. When the READY line this time two wait states may occur. If two wait states
rises the bus cycle will continue with the next falling are desired, READY should be brought high within the
edge of CLKOUT. (See Figure 9A.) TLLYH specification + 3 Tosc. Additional wait states
can be caused by adding additional state, times to the
Since the bus is synchronized to CLKOUT, it can be READY low time. The maximum amount of time that
held only for an integral number of state times. If more a device may be held not-ready is specified as TYLYH.
than TYLYH nanoseconds are added the processor will
act unpredictably. The 8X9X has the ability to internally limit the number
of wait states to 1, 2, or 3 as determined by the value in
There are several set-up and hold times associated with the Chip Configuration Register, (CCR). Using the
the READY signal. If these timings are not met, the CCR for ready timing is discussed at, the end of this
device may not respond with the proper number of wait section. If a ready limit is set, the TLL YH MAX speci-
states. ' fication is not used.

For falling edges of READY, sampling is done inter-

nally on the falling edge of Phase A. Since Phase A OPERATING MODES
generates CLKOUT, (after some propagation delay)
The 8X9X supports a variety of options to simplify
the sample will be taken prior to CLKQUT falling. The memory systems, interfacing requirements and ready
timing specifiqtion for this is given as TLL YV, the
control. Bus flexibility is provided by allowing selection
time between when ALE falls and READY must be
of bus control signal definitions and runtime selection
valid. ,If READY chartges between TLL YV max and
of the external bus width. In addition, several ready
the falling edge of CLKOUT (TLLYH MIN on 48-lead control modes are available to simplify the external
devices) it would be possible to have the READY sig-
hardware requirements for accessing slow devices. The
nal transitioning as it is being sampled.
Chip Configuration Register (CCR) is used to store the
operating mode information.
This situation could cause a metastable condition
which could make the device operate unpredictably.

1-12
inter MCS®·96 8X9X ARCHITECTURAL OVERVIEW

CHIP CONFIGURATJPN REGISTER (CCR) address/8-bit data bus. The 8X98 external bus must be
configured as a 16-bit address/8-bit data bus.
Configuration information is stored in the Chip Config-
uration Register (CCR). Four of the bits in the register ~ During 16-bit bus cycles, Ports 3 and 4 contain the
specify the bus control mode and ready control mode. address multiplexed with data using ALE to latch the
Two bits also govern the level of ROM/EPROM pro- address. In 8-bit bus cycles, Port 3 is multiplexed ad-
tection and one bit is NANDed with the BUSWIDTH dress/data while Port 4 is address bits 8 through IS.
pin every bus cycle to determine the bus size. The ,CCR The address bits on Port 4 are valid throughout an 8-bit
bit map is shown in Figure 10. The functions associated bus cycle. Figure II shows the two options.
with each bit are described in this section.
The bus width can be changed each bus cycle on the
8X9XBH and the 8X9XJF and is controlled using bit I
of the CCR with the BUSWIDTH pin. If either CCR.I
17161514131211101 CHIP CONFIGURATION REGISTER or BUSWIDTH is a 0, external accesses will be over a
L RESERVED (Set to 1 for
16-bit address/8-bit data bus. If both CCR.I and BUS-
compatIbility wIth future WIDTH are Is, external accesses will be over a 16:bit
parts) address/16-bit data bus. Internal accesses are always
16-bits wide. The BUSWIDTH pin is not available on
' - - BUS WIDTH SELECT
(16 - BIT BUS /8';--=-><;BIT"'-;;;BU"'S) °
the 8X98. CCR.I must be a on the 8X98.
- WRITE STROBE MODE SELECT
(WR AND BHE/WRL AND WRJi) The bus width can be changed every external bus cycle
ADDRESS VALID STROBE SELECT if a I was loaded into CCR bit I at reset. If this is the
(ALE/ ADV) case, changing the value of the BUSWIDTH pin at run-
time will dynamically select the bus width. For exam-
(IRCO) } INTERNAL READY ple, the user could feed the INST line into the BUS-
(IRC1) CONTROL MODE WIDTH pin, thus causing instruction accesses to be
word wide from EPROMs while data accesses are byte
(LOCO) } PROGRAM LOCK wide to and from RAMs. A second example would be
(LOCI) MOD~ to place an inverted version of Address bit 15 on the
270250-8 BUSWIDTH pin. This would make half of external
memory w.ord wide, while half is byte wide.
Figure 10. Chip Configuration Register
Since BUSWIDTH is sampled after address decoding
The CCR is ,loaded on reset with the Chip Configura- has had time to occur, even more complex memory
tion Byte, located at address 20l8H. The CCR register maps could be constructed. See the timing specifica-
is. a non-memory mapped location that can only be tions ·for an exact description of BUSWIDTH timings.
written to during the reset sequence; once it is loaded it The bus width will be determined by bit 1 of the CCR
cannot be changed until the next reset occurs. The alone on 48-pin devices since they do not have a BUS-
8X9X will correctly read this location in every bus WIDTH pin.
mode.
When using an 8-bit bus, some performance degrada-
If the EA pin is set to a logical 0, the access to 2018H tion is to be expected. On the 8X9X , instruction execu-
comes from external memory. If EA is a logical I, the tion times with an 8-bit bus will slow down if any of
access comes from internal ROM/EPROM. If EA is three conditions occur. First, word writes to external
+ 12.75V, the CCR is loaded with a byte from a sepa- memory will cause the executing instruction to take
rate non-memory-mapped location called PCCB (Pro- two extra state times to complete. Second, word reads
gramming CCB). The Programming mode is described from external memory will cause a one state time exten-
in Section 10 of the Hardware Design chapter. sion of instruction execution time. Finally, if the pre-
fetch queue is empty when an instruction fetch is re-
BUS WIDTH
quested, instruction execution is lengthened by one
state time for each byte that must be externally ac"'
The 8X9XBH and 8X9XJF external bus width can be quired (worst case is the number of bytes in the instruc-
run-time configured to operate as a standard 16-bit tion minus one.)
multiplexed address/data bus, or as an 8051 style 16-bit

1-13
 MCS®-96 8X9X ARCHITECTURAL OVERVIEW

BUS CONTROL

8X9X 8X9X

8-BIT
PORT 4 LATCHED

PORT 4
PORT 3

PORT 3

270250-9 270250-10
16-Bit Bus a·Bit Bus
Figure 11. Bus Width Options

BUS CONTROL o Standard Bus Control

Using the CCR, the 8X9X can be made to provicJe bus If CCR bits 2 and 3 are Is, then the standard 8X9X
control signals of several types. Three.controllines have control ~Is WR, BHE and ALE are provided (Fig-
dual functioJls designed to reduce external hardware. ure 12). WR will come out for every write. BHE will be
Bits 2 and 3 of the CCR specify the functions per· valid throughout the bus cycle and can be combined
formed by these control lines. Figures 12~ 15 show the with WR and address line 0 to form WRL and WRH.
sigllals which can be modified by changing bits in the ALE will rise as the address starts to come out, and will
CCR, all other lines will operate as shown in Figure ~. fall to provide the signal to externally latch the address.

ALE Jl rL ALE
Jl rL
WR WR
I
BHE VALID ADO -7 ~ADDR LOwl DATA OUT
~
~ ~ ~
ADO-15 ADDR DATA OUT
~
'270'250-11
ADS-15 ADDRESS HIGH

270250-12
16·Bit Bus Cycle a-Bit Bus Cycle
Figure 12. Standard Bus Control

1-14
 MCS®·96 8X9X ARCHITECTURAL OVERVIEW

Write Strobe Mode Address Valid Strobe Mode

The Write Strobe Mode eliminates the necessity to ex- If CCR bit 3 is a 0, then an Address Valid strobe is
ternally decode for odd or even byte writes. If CCR bit provided in the place of ALE (Figure 14). When the
2 is a 0, and the bus is in a 16-bit cycle, WRL and address valid mode is selected, ADV will go low after
WRH signals are provided in place of WR and BHE an external address is set up. It will stay low until the
(Figure 13). WRL will go low for all byte writes to an end of the bus cycle, where it will go inactive high. This
even address and all word writes. WRH will go low for can be used by ROM devices to provide a chip select for a
all byte writes to an odd address and all word writes. single external RAM device in a minimum chip count
system.
Write Strobe Mode is particularly well suited to memo-
ry systems latching data on the falling edge of WRITE.
Address Valid with Write Strobe
WRL is provided for all 8-bit bus write cycles. If both CCR bits 2 and 3 are Os, both the Address Valid
strobe and the Write Strobes will be provided for bus
control. Figure 15 shows these signals.

ALE -.n IL ALE

WRL VALID WRL

WRH VALID ADO -7 -1ADDR LOW I DATA OUT

I-
ADO -15
--I ADDR DATA OUT
I-
270250-13
AD8 -15
-1
ADDRESS HIGH
I-
270250-14
16·Blt Bus Cycle a·Blt Bus Cycle
\

Figure 13. Write Strobe Mode

ADV
r- ADV

WR
I WR

SHE
[ VALID ADO:" 7 . --1 ADDR LOwl DATA OUT
I-
ADO -15 ~ ADDRI DATA OUT
I- AD8-15 --1 ADDRESS OUT HIGH .1-
270250-15 270250-16
16·Blt Bus Cycle a·Blt Bus Cycle
Figure 14. Address Valid Strobe Mode

1-15
inter MCS®·96 8X9X ARCHITECT,URAL OVERVIEW

WRL VALID WRL

WRH I VALID ADO -7 -1 AD DR LOW I DATA OUT J---

ADO -15 --i ADDR DATA OUT J--- ADS -15 -1. . __ J---
A_D_D_RE_S_S_H_IG_H_ _.....
270250-17 270250-18
16·Bit Bus Cycle 8·Bit Bus Cycle

Figure 15. Write Strobe with Address Valid Strobe

READY CONTROL executing from external memory. The modes are shown
in Table 2. Internal ROM/EPROM addresses 2020H
To simplify ready control, four modes of internal ready through 3FFFH on the 8X9XBH and the 8X98 and
control logic have been provided. The modes are cho- addresses 2020H through 5FFFH on the 8X9XJF are
sen by properly configuring bits 4 and 5 of the CCR. protected from reads. 2000H through 3FFFH on the
8X9XBH and the 8X98 and 2000H through 5FFFH on
The internal ready control logic can be used to limit the the 8X9XJF are protected from writes, as set by the
number of wait states that slow devices can insert into CCR.
the bus cycle. When the READY pin is pulled low,
wait states will be inserted into the bus cycle until the Table 2. Program Lock Modes
READY pin goes high, or the number of wait states
equals the number specified by CCR bits 4 and 5, LOC1 LOCO Protection
whichever comes first. Table 1 shows the number of 0 0 Read and Write Protected
wait states that can be selected. Internal Ready control 0 1 Read Protected
can be disabled by loading 11 into bits 4 and 5 of the 0 Write Protected
CCR. No Protection
Table 1. Internal Ready Control
Only code executing from internal memory can read
IRC1 IRCO Description protected internal memory, while a write protected
o o Limit to 1 Wait State memory can not be written to, even from internal exe-
o 1 Limit to 2 Wait States cution. As a result of 8X9X prefetching of instructions,
1 o Limit to 3 Wait States however, accesses to protected memory are not allowed
for instructions located above 3FFAH on the 8X9XBH
1 Disable Internal Ready Control and the 8X98 and above 5FFAH on the 8X9X)F, This
is becaus~the lock protection mechanism is gated off of
This feature provides for simple ready control. For ex- the Memory Controller's slave program counter and
ample, every slow memory chip select line could be not the CPU program counter. If the bus controller
ORed together and be connected to the READY pin receives a request to perform a read of protected memo-
with CCR bits 4 and 5 programmed to give the desired ry, the read sequence occurs with, indeterminate data
number of wait states to the slow devices. ' being returned to the CPU. Note that the interrupt vec-
tors and the CCR are not protected .
. ROM IE PROM LOCK To provide verification and testing when the program
Four modes of program memory lock are available on lock feature is enabled, the 8X9X verifies the security
the 8X9X devices. CCR bits 6 and 7 (LOCO, LOCI) key before, programming or test modes are allowed to
select whether· internal· program memory can' be read ' read from protected memory. Before protect,ed memory
(or written in EPROM devices) by a program can be read, the chip reads external memory locations
4020H through 402FH and compares the values

, 1-16
 MCS®~96 8X9X ARCHITECTURAL OVERVIEW

/
found to tlje internal security key located from 2020H result must be interpreted in modulo 256 arithmetic.
through 202FH. Only when the values exactly match Logical operations on BYTES are applied bitwise. Bits
will accesses to protected memory be allowed. The de- within BYTES are labeled from 0 to 7, with 0 being the
tails of ROM/EPROM accessing are discussed in Sec- least significant bit. There are no alignment restrictions
tion 10 of the Hardware Design chapter. for BYTES, so they may be placed anywhere in the
MCS-96 address space.
3.Q SOFTWARE OVERVIEW
WORDS
This section provides information on writing programs
to execute in the 8X9X. Additional information can be WORDS are unsigned 16-bit variables which can take
found in the following documents: on the values between 0 and 65535. Arithmetic and
relational operators can be applied to WORD operands
MCS®-96 M;ACRO ASSEMBLER USER'S GUIDE but the result must be interpreted modulo 65536. Logi-
Order Number 186 ASM 96 (Intel Systems) cal operations on WORDS are applied bitwise. Bits
Order Number 086 ASM 96NL (DOS Systems) within words are labeled from 0 to 15 with 0 being the
least significant bit. WORDS must be aligned at even
C-96 USER'S GUIDE byte boundaries in the MCS~96 address space. The least
'Order Number 086 C96NL (DOS Systems) significant byte of the WORD is in the even byte ad-
dress and the most significant byte is in the next higher
PL/M·96 USER'S GUIDE (odd) address. The address of a word is the address of
Order Number 186 PLM 96 (Intel Systems) its least significant byte. Word operations to odd ad-
Order Number 086 PLM 96NL (DOS Systems) dresses are' not guaranteed to operate in a consistent
manner.
Throughout this section, short sections of code are used
to illustrate the operation of the device. For these sec-
tions it has been assumed that a set of temporary regis- SHORT-INTEGERS
ters have been predeclared. The names of these registers SHORT-INTEGERS are 8-bit signed variables which
have been chosen as follows: can take on the values betweep -128 and + 127.
AX, BX, CX, and OX are 16-bit registers. Arithmetic operations which generate results outside of
AL is the low byte of AX, AH is the high byte. the range ofa SHORT-INTEGER will set the overflow
indicators in the program status word. The actual nu-
BL is the low byte of BX meric result returned will be the same as the equivalent
CL is the low byte of CX operation on BYTE variables. There are no alignment
DL is the low byte of OX restrictions on SHORT-INTEGERS so they may be
placed anywhere in the MCS_96 address space.
These are the same as the names for the general data
registers used in the 8086 (80186). It is important to INTEGERS
note, however, that in the 8X9X, these are not dedicat-
ed registers but merely the symbolic names assigned by INTEGERS are 16-bit signed variables which can take
the programmer to an eight byte region within the on- on the values between -32,768 and 32,767. Arithmetic
board register file. operations which generate results outside of the range
of an INTEGER will set the overflow indicators in the
3.1 Operand Types program status word. The actual numeric result re-
turned will be the same as the equivalent operation on
The MCS®-96 architecture provides support 'for a vari- WORD variables. INTEGERS conform to the same
ety of data types which are likely to be useful in a con- alignment and addressing rules as do WORDS.
trol application. In the discussion of these operand
types that follows, the names adopted by the PLM-96 BITS
programming language will be used where appropriate.
To avoid confusion, the name of an operand type will BITS are single-bit operands which can take on the
be capitalized. A "BYTE" is an unsigned eight bit vari- Boolean values of true and false. In addition to the nor-
able; a "byte" is an eight bit unit of data of any type. mal support for bits as components of BYTE and
WORD operands, the 8X9X provides for the direct
BYTES testing of any bit in the internal register file. The MCS-
96 architecture requires that bits be addressed as com-
BYTES are unsigned 8-bit variables which can take on ponents of BYTES or WORDS, it does not support the
the values between 0 and 255. Arithmetic and relational direct addressing of bits that can occur in the MCS-51
operators can be applied to BYTE operands but the architecture.

1-17
 inter MCS<B?-96, 8X9X ARCHITECTURAL OVI;RVIEW

DOUBLE-WORDS _ LONG-INTEGERS

DOBBLE-WORDS are unsigned 32-bit variables LONG-INTEGERS are 32-bit signed variables which
which can take on the values, between 0 and 'can take on the values between -2,147,483,648 and
4,294,967,295. The MCS-96 architecture provides di- 2,147,483,647. The MCS-96 architecture provides di-
rect support for this operand type only for shifts and as rect support for this data type only for shifts and as the
the dividend in a 32 by 16 divide and the product of a dividend in.a 32 by 16 divide and the product of a 16 by
16 by 16 multiply. For these operations a DOUBLE- 16 multiply.
, WORD variable must reside in the on-board register
file of the 8096 and be aligned at an address which is LONG-INTEGERS can also be normalized. For these
evenly divisible by 4. A DOUBLE-WORD operand is operations a LONG-INTEGER variable must reside in
addressed by the address of its least significant byte. the onboard register file of the 8X9X and be aligned at '
DOUBLE-WORD operations which are not directly an address which is evenly divisible, by 4. A LONG-IN-
supported can be easily implemented wjth two WORD TEGER is addressed by the address of its least signifi-
operations. For consistency with Intel provided soft- cant byte.
ware the user should adopt the conventions for address-
ing DOUBLE-WORD operands which are discussed in LONG-INTEGER operations which are not directly
Section 3.5. supported can be easily implemented with two INTE-
GER operations. For consistency with Intel provided
software, the user should adopt the conventions for ad-
dressing LONG operands which are discussed in Sec-
tion 3.5.
3.2 Operand Addressing
Operands are accessed within the address space of the modes will be described as they are seen through the
8X9X with one of six basic addressing modes. Some of assembly language. The six basic address modes which
the details of how these addressing modes work are will be described are termed register-direct, indirect, in-
hidden by the assembly language. If the programmer is direct with auto-increment, immediate, short-indexed,
to take full advantage of the architecture, it is impor- and long-indexed. Several other useful addressing oper-
tant that these details 'be understood. This section will ations can be achieved by combining these basic ad-
describe-the addressing modes as they are handled by dressing modes with specific registers such as the
the hardware. At the end of this section the addressing ZERO register or the stack pointer.

REGISTER·DIRECT REFERENCES

The register-direct mode is used to directly access a alignment rules for the operand type. Depending on the
register from the 256 byte on-board register file. The instruction, up to three registers can take part in the
register is selected by an 8-bit field within the instruc- calculation.
tion and register address and must conform to the
--.-.--------~--- . -----'J
U xamPles
ADD
MUL
INCB
AX,BX
CL
'
AX,BX,CX AX:=BX+CX
, AX ':=AX*BX
CL:=CL+l
-------------------
'

INDIRECT REFERENCES

The indirect mode is used to access an operand by plac- register which con til-ins the indirect address is selected
ing its address in a WORP variable in the register fiJe, by an eight bit field within the instruction. An instruc-
The calculated address must conform to the alignment tion can contain only one indirect 'reference and the
rules for the operand type. Note that the indirect ,ad- remaining operands of the instruction (if any) must be
dress can refer to an operand anywhere within the ad- register-direct references.
dress space of the 8X9X, including the register file. The

Examples
LD AX, [A~] AX:=MEM_WORD(AX)
ADDB AL,BL, [CX] AL:=BL+MEM_BYTE(CX)
POP ,[AX] MEM_WORD(AX) :=MEM_WORD(SP)

1-18
 MCS®-96 8X9X ARCHITECtURAL OVERVIEW

INDIRECT WITH AUTO-INCREMENT REFERENCES

This addressing mode is the same as the indirect mode SHORT-INTEGERS the indirect address variable will
except that the WORD variable whiCh contains the in- be incremented by one. if the instruction operates on
direct address is incremented after it is used to address WORDS or INTEGERS the indirect address variable
the operand. If the instruction operates on BYTES or will be incremented by two.

Examples
LD AX, [BX]+ AX:=MEM_WORD(BX) ; BX:=BX+2
ADDB AL,BL,[CX]+ AL:=BL+MEM_BYTE(CX) ; CX:=CX+1
PUSH [AX]+ SP:=SP-2;
MEM_WORD(SP) :=MEM_WORD(AX)
AX:=AX+2

IMMEDIATE REFERENCES .

This addressing mode allows an operand to, be taken INTEGER operands the field is 16 bits wide. An in-
directly from a field in the instruction. For operations struction can contain only one immediate reference and
on BYTE or SHORT-INTEGER operands this field the remaining operand(s) must be register-direct refer-
is eight bits wide. for operations on WORD or ences.

Examples
ADD AX,#340 AX:=AX+340
PUSH #1234H SP:=SP-2; MEM_WORD(SP) :=1234H
DIVB AX,#10 AL:=AX/10; AH:=AX MOD 10

SHORT-INDEXED REFERENCES

In this addressing mode an eight bit field in the instruc- Since the eight bit field is sign-extended. the effective
tion selects a WORD variable in the register file which address can be up to 128 bytes before the address in the
is assumed to contain 'an address. A second eight bit WORD variable and up to 127 bytes after it. An in-
field in the instruction stream is sign-extended and struction can contain only one short-Indexed reference
summed with the WORD variable to form the address and the remaining operand(s) must be register-direct
of the operand which will take part in the calculation. references.

Examples
LD AX,12[BX] AX:=MEM_WORD(BX+12)
MULB AX,BL,3[CX] AX:=BL*MEM_BYTE(CX+3)

LONG-INDEXED REFERENCES

This addressing mode is like the short-indexed mode struction can contain only one long-indexed reference
except that a 16-bit field is taken from the instruction and the remaining operand(s) must be register-direct
and added to the WORD variable to form the address references.
of the operand. No sign extension is necessary. An in-

Examples
AND AX,BX,TABLE[CX] AX:=BX AND MEM_WORD(TABLE+CX)
STAX,TABLE[BX] MEM_WORD(TABLE+BX) :=AX
ADDB AL,BL,LOOKUP[CX] AL:=BL+MEM_BYTE(LOOKUP+CX)

1-19
 MCS®-96 8X9X ARCHITECTURAL OVERVIEW

ZERO REGISTER ADDRESSING

The first two bytes in the register file are fixed at zero able in a long-indexed reference. This combination of
by the 8096 hardware. In addition to providing a fixed register selection and address mode allows any location
source of the constant zero for cakulations and com- in memory to be addressed directly.
parisons, this register can be used as the WORD vari-

Examples
ADD AX,1234[0] AX:=AX+MEM_WORD(1234)
POP 5678[0] MEM_WORD(5678) :=MEM_WORD(SP)
SP:=SP+2

STACK POINTER REGISTER ADDRESSING

The system stack pointer in the 8X9X can be accessed ~an be accessed by using the stack pointer as the
as register ISH of the internal register file. In addition WORD variable in an indirect reference. In a similar
to providing for convenient manipulation of the stack fashion, the stack pointer can be used in the short-in-
pointer, this also facilitates the accessing of operands in dexed mode to access data within the stack.
the stack. The top of the stack, for example,

Examples
PUSH ESP] DUPLICATE TOP_OF_STACK'
LD' AX,2[SP] AX:=NEXT_TO_TOP

ASSEMBLY LANGUAGE ADDRESSING MODES

The 8X9X assembly language simplifies the choice of The use of these features of the assembly language sim-
addressing modes to be used in several respects: plifies the programming task and should be used wher-
ever possible.
Direct Addressing. The assembly language will choose
between register-direct addressing and long-indexed
with the ZERO register depending on where the oper- 3.3 Program Status Word
and is in memory. The user can simply refer to an oper-
and by its symbolic name; if the operand is in the regis- The program status word (PSW) is a collection of Bool-
ter file, a register-direct reference will be used, if the ean flags which retain information concerning the state
operand is elsewhere in memory, a long-indexed refer- of the user's program. The format of the PSW is shown
ence will be generated. in Figure 16. The information in the PSW can be bro-
ken down into two basic categories; interrupt control
Indexed Addressing. The assembly language will and condition flags. The PSW can be saved in the sys-
choose between short and long indexing depending on tem stack with a single operation (PUSHF) and re-
the value of the index expression. If the value can be stored in a like manner (POPF).
expressed in eight bits then short indexing will be used,
if it cannot be expressed in eight bits then long indexing
will be used.

Figure 16. PSW Register

1-20
 MCS®-96 8X9X ARCHITECTURAL OVERVIEW

INTERRUPT FLAGS C. The C (Carry) flag is set to indicate the state of the
arithmetic carry from the most significant bit of the
The lower eight bits of the PSW are used to individual- ALU for an arithmetic operation or the state of the last
ly mask the various sources of interrupt to the 8096. A bit shifted out of the operand for a shift. Arithmetic
logical '1' in these bit positions enables the servicing of Borrow after a subtract operation is the complement of
the corresponding interrupt. These mask bits can be the C flag (i.e. if the operation generated a borrow then
accessed as an eight bit byte (INT_MA&K.-address C = 0).
8) in the on-board register file. Bit 9 in the PSW is the
global interrupt disable. If this bit is cleared then all ST. The ST (STicky bit) flag is setto indicate that dur-
interrupts will be locked out except for the Non Maska- ing a right shift a 1 has been shifted first into the C flag
ble Interrupt (NMI). Note that the various interrupts and then been shifted out. The ST flag is undefined
are collected in the INT_PENDING register even if after a multiply operation. The ST flag can be used
they are locked out. Execution of the corresponding along with the C flag to control rounding after a right
service routines will procede according to their priority shift. Consider multiplying two eight bit quantities and
when they become enabled. Further information on the then scaling the result down to 12 bits:
interrupt structure of the 8X9X can be found in Section 4.
MULUB AX,CL,DL ;AX:=CL*DL
SHR AX.#4 ;Shift right 4 places
CONDITION FLAGS

The remaining bits in the PSW are set as side effects of If the C flag is set after the shift, it indicates that the
instruction execution and can be tested by the condi- bits shifted off the end of the operand were greater-than
tional jump instructions. or equal-to one half the least significant bit (LSB) of the
result. If the C flag is clear after the shift, it indicates
Z. The Z (Zero) flag is set to indicate that the operation that the bits shifted off the end of the operand were less
than half the LSB of the result. Without the ST flag,
generated a result equal to zero. For the add-with-carry
(ADDC) and subtract-with-borrow (SUBC) operations the rounding decision must be made on the basis of this
the Z flag is cleared if the result is non-zero but is never information alone. (Normally the result would be
set. These two instructions are normally used in con- rounded up if the C flag is set.) The ST flag allows a
junction with the ADD and SUB instructions to per- finer resolution in the rounding decision:
form multiple precision arithmetic. The' operation of
the Z flag for these instructions leaves it indicating the CST Value of the Bits Shifted Off
proper result for the entire multiple precision calcula-
tion.
00 Value =0
01 0< Value < %LSB
N. The N (Negative) flag is set to indicate that the
operat\on generated a negative result. Note that the N
10 Value = % LSB
flag will be set to the algebraically correct state even if 11 Value> %LSB
the calculation overflows.
Figure 17. Rounding Alternatives
V. The V (overflow) flag is set to indicate that the oper-
ation generated a result which is outside the range that Imprecise rounding can be a major source of error in a
can be expressed in the destination data type. For the numerical calculation; use of the ST flag improves the
SHL, SHLB and SHLL instructions, the V flag will be options available to the progranimer.
set if the most significant bit of the operand changes at
any time during the shift. 3.4 Instruction Set
VT. The VT (oVerflow Trap) flag is set whenever the V The MCS-96 instruction set contains a full set of arith-
flag is set but can only be cleared by an instruction metic and logical operations for the 8-bit data types
which explicitly operates on it such as the CLRVT or ' BYTE and SHORT INTEGER and for the 16-bit data
JVT instructions. The operation of the VT flag allows types WORD and INTEGER. The DOUBLE-WORD
for the testing for a possible overflow condition at the and LONG data types (32 bits) are supported for the
end of a sequence of related arithmetic operations. This products of 16 by 16 multiplies and the dividends of 32
is normally more efficient than testing the V flag after
each instruction.

1-21
 MCS®·96 8X9X ARCHITECTURAL OVERVIEW

by 16 divides and for shift operations. The remaining LDBZE (load byte zero extended) converts a BYTE to
operations on '32-bit variables can be implemented by a WORD and LDBSE (load byte sign extended) con-
combinations of 16-bit operations. As an example the verts a SHORT-INTEGER into an INTEGER.
sequence: WORDS can be converted to DOUBLE-WORDS by
simply clearing the upper WORD of the DOUBLE-
ADD AX,ex WORD (CLR) and INTEGERS can be converted to
ADDe BX,DX LONGS with the EXT (sign extend) instruction.

performs a 32-bit addition, and the sequence The MC~-96 instructions for addition, subtraction, and
compalison do not distinguish between unsigned words
SUB AX,ex and signed integers. Conditional jumps are provided to
SUBe BX,DX allow the user to treat the results of these operations as
either signed or unsigned quantities. As an example, the
performs a 32-bit subtraction. Operations on REAL CMPB (compare'byte) instruction is used to compare
(i.e. floating point) variables are not supported directly both signed and unsigned eight bit quantities. A JH
by the hardware but are supported by the floating point (jump if higher) could be used following the compare if
library for the 8X9X (FPAL-96) which implements a unsigned operands were involved or a JGT (jump if
single precision subset of the proposed IEEE standard greater-than) if signed operands were involved.
for floating point operations. The performance of this
software is significantly improved by the 8X9X Table 3 summarizes the operation of each of the in-
NORMl- instruction which normalizes a 32-bit vari- structions. Complete descriptions of each instruction
able and by the existence of the ST flag in the PSW. and its timings can be found in the Instruction Set
chapter. A summary of instruction opcodes and timing
In addition to the operations on the various data ,types, is included in the quick reference section at the end of
the 8X9X supports conversions between these types. this chapter.

1-22
 MCS®·96 8X9X ARCHITECTURAL OVERVIEW

Table 3. Instruction Summary

Oper· Flags
Mnemonic Operation (Note 1) Notes.
ands Z N V
C VT ST
ADD/ADDB 2 D - O+A I" I" I" I" i -
ADD/AD DB 3 D - B+A I" I" I" I" i -
ADDC/ADDCB 2 D-'D+A+C !. I" I" I" i -
SUB/SUBB 2 D - D-A I" I" I" I" i -
SUB/SUBB 3 D - B-A I" I" I" I" i -
SUBC/SUBCB 2 D_D-A+C-i !. I" I" I" i -
CMP/CMPB 2 D-A I" I" I" I" i -
MUL/MULU 2 D,D +2 - D' A - - - - - ? 2
MULIMULU 3 Q, D + 2 - B*A - - - - - ? 2
MULB/MULUB 2 D,D + 1 - D' A - - - - - ? 3
MULB/MULUB 3 D,D + 1 - B' A - - - - - ? 3
DIVU 2 o - (0, 0 + 2)/ A, D + 2 - remainder - - - I" i - 2
OIVUB 2 0 _ (0,0 + i)/A, 0 + 1 - remainder - - - I" i - 3
DIV
- 2 0 - (0:0 + 2)/A,D + 2 - remainder - - - ? i -
OIVB 2 0 - (0,0 + i)/A,D + 1 - remainder - - - ? i -
AND/ANOB 2 0 - DandA I" I" 0 0 - -
ANO/ANOB 3 0 - BandA I" I" 0 0 - -
OR/ORB 2 0 - DorA I" I" 0 0 - -
XOR/XORB 2 o- 0 (excL or) A I" I" 0 0 - -
LD/LDB 2 O-A - - - - - -
ST/STB 2 A-O - -, - - - -
LDBSE 2 D-A;D+1 - SIGN(A) - - - - - - 3,4
LDBZE 2 D-A;D+i - 0 - - - - - - 3,4
PUSH 1 SP - SP - 2; (SP) - A - - - - - -
POP 1 A - (SP); SP - SP + 2 - - - - - -
PUSHF 0 SP - SP - 2; (SP) - PSW; 0 0 0 0 0 0
PSW - OOOOH 1- 0
POPF 0 PSW - (SP); SP - SP + 2; I-I" I" I" I" I" I" I"
SJMP 1 PC - PC + it-bit olfset - - - - - - 5
LJMP 1 PC +- PC + i6-biroflset - - - - - - 5
BR (indirect) 1 PC - (A) - - - - - -
SCALL 1 S~ - SP - 2; (SP) - PC; - - - - - - 5
PC - PC + i1-bit offset
LCALL 1 SP - SP - 2; (SP) - PC; - - - - - - 5
PC - PC + i6-bit offset
RET 0 PC - (SP);SP - SP + 2 - - - - - -
J (conditional) ; PC - , PC + a-bit offset (il taken) - - - - - - 5
JC 1 JumpilC =1 - - - - - - 5
JNC 1 JumpilC =0 - - - - - - 5
JE 1 JumpilZ = 1 - - - - - - 5
NOTES:
1. II the mnemonic ends in "B", a byte operation is performed, otherwise a word operation is done. Operands 0, S, and A
must conform to the alignment rules for the required operand type. 0 and B are locations in the register file; A can be
located anywhere in memory.
2. D, D + 2 are consecutive WORDS in memory; D is DOUBLE-WORD aligned.
3. D, D. + 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to a word.
5. Offset is a 2's complement number.

1·23
 MCS®·96 8X9X ARCHITECTURAL OVERVIEW

Table 3. Instruction Summary (Continued)

Oper- Flags
M(lemonlc Operation (Note 1) Notes
ands Z N C V VT ST
JNE 1 Jump if Z = 0 - - - - - - 5
JGE 1 JumpifN = 0 - - - - - - 5
JLT 1 Jump if N = 1 - - - - - - 5
JGT 1 Jump if N = 0 and Z = 0 - '- - - - - 5
JLE 1 Jump if N = 1 or Z = 1 - - - - - - 5
JH 1 JumpifC = 1 andZ= 0 - ~
- - - - 5
JNH 1 Jump if C = 0 or Z = 1 - - - - - - 5
JV 1 Jump if V =1 - - - - - - 5
JNV 1 Jump if V =0 - - - - - - 5
JVT
JNVT
1
1
Jump if VT = 1; Clear VT
Jump if VT = 0; Clear VT
-
-
-
-
-- -
-
0
0
-'

-
5
5
JST 1 Jump if ST = 1 - - - - - - 5
JNST 1 Jump ifST = 0 - - - - - - 5
JBS 3 Jump if Specified Bit = 1 - - - - - - 5,6
JBC 3 Jump if Specified Bit = 0 - - - - - - 5,6
DJNZ 1 D ~ D - 1; if D "" 0 then

DEC/DECB 1
PC ~ PC + 8-bit offset
D ~ 0-1
- - - -
,;,
-
-t
-
-
5

NEG/NEGB 1 D ~ O-D
'" '" '" t -
INC/INCB 1 D ~ 0+ 1
'" '" '" '" t -
EXT 1 D ~ 0; D + 2 - Sign (D)
'" '" '"0 '"0 - - 2
EXTB 1 O-D;O+l ~ Sign(D)
'" '" 0 0 - - 3
D ~ Logical Not (D)
'" '" - -
NOT/NOTB
CLR/CLRB
1
1 D~O
'"1 '"0 00 00 - -
C ~ msb-----Isb ~ 0 t - 7
SHLlSHLB/SHLL
SHRISHRB/SHRL
2
2 o~ msb-----Isb ~ C
'" ?? '" '"0 - 7
SHRAISHRAB/SHRAL 2 msb -+ msb-----Isb -+'C
'" '" 0 - '" 7
SETC 0 C~l -'" -'" '"1 - - '"
-
,
CLRC 0 C~O - - 0 - - -
CLRVT 0 VT ,~ 0 - - - - 0 -
RST 0 PC ~ 2080H 0 0 0 0 0 0 8
DI 0 Disable All Interrupts (I ~ 0) - - - - - -
EI 0 Enable All Interrupts (I ~ 1) - - - - - -
Nap 0 PC ~ PC+ 1 - - - - - -
SKIP 0 PC~PC+2 - - - - - -
NORML 2 Left shift till msb = 1; D ~ shift count ? 0 - - - 7
TRAP 0 SP ~ ,SP - 2; (SP) ~ PC
'"
PC ~ (2010H) - - - - - - 9

NOTES:
1. If the mne,monicends in "B", a byte operation is performed, otherwise a word operation is done. Operands D, B and A
must conform to the alignment rules for the required operand type. D and B are locations in the register file; A ,can be
located anywhere in memory. "
5. Offset is a2's complement number.
6. Specified bit is one of the 2048 bits in the register file.
7. The "L" (Long) suffix indicates,double-word operation.
8. Initiates a Reset by pulling RESET low. Software should re~initialize ali the necessary registers with code starting at
2080H.
9. The assembler will not accept this mnemonic.

1-24
inter MCS®·96 8X9X ARCHITECTURAL OVERVIEW

3.5 Software Standards and byte undefined. Thirty-two bit parameters (LONG-
Conventions INTEGERS, DOUBLE-WORDS, and REALS) are
pushed into the stack as two 16-bit values; the most
For a software project of any size it is a good idea to significant half of the parameter is pushed into the
modularize the program and to establish standards . stack first.
which control the communication between these mod-
ules. The nature of these standards will vary with the As an example, consider the following PLM-96 proce-
needs of the final application. A common component of dure:
all of these standards, however, must be the mechanism
for passing parameters to procedures and returning re- example_procedure: PROCEDURE
sults from procedures. In tlie absence of some overrid- (paraml,param2,param3);
ing consideration which prevents their use, it is suggest- DECLARE paraml BYTE,
ed that the user conform to the conventions adopted by param2 DWORD,
the PLM-96 programming language for procedure link- param3 WORD;
age. It is a very usable standard for both the assembly
language and PLM-96 environment and it offers com- When this procedure is entered at run time the stack
patibility between these environments. Another advan- will contain the parameters in the following order:
tage is that it allows the user access to the same floating
pointarithmetics library that PLM-96 uses to operate ?????? : param1
on REAL variables.
high word of param2
,-

REGISTER UTILIZATION low word of param2

param3
The MCS-96 architecture provides a 256 byte register
file. Some of these registers are used to control register- return address ~ Stack_pointer
mapped I/O devices and for other special functions
such as the ZERO register and the stack pointer. The Figure 18. Stack Image
remaining bytes in the register file, some 230 of them,
are available for allocation by the programmer. If these If a procedure returns a value to the calling code (as
registers are to be used effectively, some overall strategy opposed to modifying more global variables) then the
for their allocation must be adopted. PLM-96 adopts result is returned in the variable PLMREG. PLMREG
the simple and effective strategy of allocating the eight is viewed as either an 8-, 16- or 32-bit variable depend-
bytes between addresses lCH and 23H as temporary , ing on ~he type of the procedure.
storage. The starting address of; this region is called
PLMREG. The remaining area in the register file is The standard calling convention adopted by PLM-96
treated as a segment of memory which is allocated as has several key features:
required. a) Procedures can always assume that the eight bytes of
register file memory starting at PLMREG can be
used as temporaries within the body 'Of the proce-
ADDRESSING 32-B11 OPERANDS dure,
These operands are formed from two adjacent 16-bit b) Code which calls a procedure must assume that the
words in memory. The least significant wdrd of the eight bytes of register file memory starting at
double word is always in lower address, even when the PLMREG are modified by the procedure.
data is in the stack (which means that the most sig- ' c) The Program Status Word (PSW-see Section 3,3) is
nificant word must be pushed into the stack first). A not saved and restored by procedures so the calling
double word is addressed by the address of its least code must assume that the condition flags (Z, N, V,
significant byte. Note that the hardware supports some VT, C, and ST) are modified by the procedure.
operations on double words (e.g. normalize and divide).
d) Function results from procedures are always re-
For these operations the double word must be in the
turned in the variable PLMREG.
internal register file and must have an address which is
evenly divisible by four. '
PLM-96 allows the definition of INTERRUPT proce-
dures which are executed when a predefineQ interrupt
SUBROUTINE LINKAGE {lCcurs. These procedures do not conform to the rules of
a normal procedure. Parameters cannot be pas,sed t6
Parameters are passed to subroutines in the stack. Pa- these procedures and they cannot return results. Since
rameters are pushed into the stack in the order that they can execute essentially at any time (hence the term
they are encountered in the scanning of the source text. interrupt), these procedures must save the PSW and ,
Eight-bit parameters (BYTES or SHORT-INTE- PLMREG when they are entered and restore these val-
GERS) are pushed into the stack with the high order ues before they exit.

1-25
 MCS®·96 8X9X ARCHITECTURAL OVERVIEW

4.0 INTERRUPT STRUCTURE' . PSW which contain.s a global disablebi.t. A block dia-
gram of the system is shown in Figure 21.· The tran-
There are 21 sources of interrupts on the 8X9X. These sition detector looks for OJo I transitions' on any of the
sources are gathered into 8 interrupt types as indicated sources. External sources have a maximum transition
in Figure 19. The 110 control registers which coritrol . speed of om;" edge every state time. If this is exceeded
some of the sources are indicated in the figure. Each of the. interrupt may not be detected.
the eight types of interrupts has its own interrupt vectbr
as listed in Figure 20. In addition to the 8 standard Vector Location
interrupts, there is a TRAP instruction which acts as a Vector (Hjgh (Low Priority
software generated interrupt. This instruction is not Byte) . Byte)
currently supported by the MCS-96 Assembler and is
reserved for use in Intel development systems. Software Trap 2011H ·2010H Not Applicable
Extint 200FH 200EH 7 (Highest)
The programmer must initialize the interrupt vector ta- Serial Port 200DH 200CH 6
ble with the starting address of the appropriate inter- Software 200SH 200AH 5
rupt service routine. It is suggested that any unused Timers
interrupts be vectored to an error handling routine. The HSI.O 2009H 2008H 4
error routine should contain recovery code that will not High Speed 2007H 2006H 3
further corrupt an already erroneous situation. In a de- Outputs
bug environment; it may be desirable to have the rou- HSI Data 2005H 2004H 2
tine lock into a jump to self loop which would be easily Available
traceable with emulation tools. More sophisticated rou-
AID Conversion 2003H 2002H 1
tines may be appropriate for production code recover-
Complete
ies.
Timer Overflow 2001H 2000H o(Lowest)
Three registers control the operation of the interrupt Figure 20. Interrupt Vecto.r Locations
system: Interrupt Pending,. Interrupt Mask, and the

SOURCE

r---
IOC1.l
EXTINT ~..._ _ _ _ _ _ _ EXTINT
ACH.7 ---<>
n FLAG ,...--y-------- SERIAL PORT
RI FLAG --.l r--- HSO_COMMAND.4

SOFTWARE TIMER
SOFTWARE TIMER 1
O~~ SOFTWARE TIMER

SOFTWARE TIMER Z
SOFTWARE TIMER 3
. RESEt TIMER Z'
START AID CONVERSION'
HSI.O,----------HSI.O

,.:--- HSa..cOMMAND.4
ANY tISO OPERATION - - 0 ~ . HIGH SPEED OUTPUTS

, FIFOISFULL~ ".
HOLDING REGISTER LOADED _ .' HSI DATA AVAILABLE

AID CONVERSION COMPLETE - - - - - - - - - - AID CONVERSION COMPLETE

~---IOC1.2
nMERl OVERFLOW _
.
_----r-- TIMER OVERFLOW
nMER2 OVERFLOW ~ •
--IOC1.3
270250-20
NOTE:
'Only when initiated by the HSO unit.

Figure 19, All Possible Interrupt Sources

1-26.
intJ MCS®·96 8X9X ARCHITECTURAL OVERVIEW

SOFTWARE TIMER
EXTINT SERIAL PORT TIMERS, HSI.O HSO HSI ADCONV. OVERFLOW
6 o

TRANSITION
DETECTOR

INTERRUPT MASt< REG

PRIORITY ENCODER

I bit
(PSW.9)

GLOBAL DISABLE

INTERRUPT
_NMI
GENERATOR

D.BUS CONTROL
UNIT

270250-21

Figure 21. Block Diagram of Interrupt System

1-27
intJ MCS®·96 8X9X ARCHITECTURAL OVERVIEW

4.1 Interrupt Control The INT_MASK register can be read or written as

byte register. A one in any bit position will enable the
corresponding interrupt source and a zero will disable
Interrupt Pending Register the source. The hardware will save any interrupts that"
occur by setting bits in the pending register, even if the
When the hardware detects one of the eight interrupts interrupt mask bit is cleared. The INT_MASK regis-
it sets the corresponding bit in the pending interrupt ter also can 1)e accessed as the lower eight bits of the
register (INT_PENDING-09H). When the interrupt psw so the PUSHF and POPF instructions save and
vector is taken, the pending bit is cleared. This register, restore the INT_MASK register as well as the global
the format of which is shown in Figure 22, can be read interrupt lockout and the arithmetic flags.
or modified as a byte register. It can be read to deter-
mine which of the interrupts are pending at any given
time or modified to either clear pending interrupts or GLOBAL DiSABLE
generate interrupts under software control. Any soft~
ware which modifies the INT_PENDING register The processing of all interrupts can be disabled by
should ensure that the entire operation is .indivisible. clearing the I bit in the PSW. Setting the I bit will
The easiest way to do this is to use the logical.instruc- enable interrupts that have mask register bits which are
tions in the two or three operand format, for example: set. The I bit is controlled by the EI (Enable Interrupts)
and 01 (Disable Interrupts) instructions. Note that the
ANDB INT_PENDING,#llllllOlB I bit only controls the actual servicing of interrupts.
; Clears the AID Interrupt Interrupts that occur during periods of lockout will be
ORB INT_PENDING,#OOOOOOlOB held in the pending register and serviced on a priori-
. ; Sets the AID Interrupt tized basis when the lockout period ends.

Caution must be used when writing to the pending reg-

ister to clear interrupts. If the interrupt has already 4.2 Interrupt Priorities
been acknowledged when the bit is cleared, a 4 state
time "partial" interrupt cycle will occur. This is be- The priority encoder looks at all of the interrupts which
cause the 8X9X will have to fetch the next instruction are both pending and enabled, and selects the one with
of the normal instruction flow, instead of proceeding the highest priority. The priorities are shown in Figure
with the interrupt processing as it was going to. The 20 (7 is highest, 0 is lowest). The interrupt generator
effect on the program will be essen,tially that of an extra then forces a call to the location in the indicated vector
NOP. This can be prevented by clearing the bits using a location. This location would be the starting location of
2 operand immediate logical, as the 8X9X holds off the Interrupt Service Routine (ISR).
acknowledging interrupts during these "read!modify!
write" instructions. This priority selection controls the order in which
pending interrupts are passed to the software via inter-
rupt calls. The software can then implement its own
(LOCATION 09H)
priority structure by controlling the- mask register
(INT_MASK). To see how this is done, consider the
17 16 151413121 1 101 case ofa serial I/O service routine which must run at a
priority level which is lower than the HSI data avail-
III I I .~ ~:i:~~£~"
HSO EVENT
able interrupt but hight;r than any other source. The
"preamble" and exit code for this interrupt service rou-
tine would look like this:
HSI BIT 0
SOFTWARE TIMERS
L -_ _ _ _ _' - -_ _ SERIAL I/O serial_io_isr:
L -_ _ _ _ _ _ _ _ _ EXTERNAL INTERRUPT PUSHF Save the PSW
270250-19 (Includes INT_MASK)
LDB INT_MASK,#00000100B

I
Figure 22. Interrupt Pending Register EI Enable interrupts again
\

Interrupt Mask Register,

Individual interrupts can be enabled or disabled by set- S.rvi.. tho int.rrupt

ting or clearing bits in the interrupt mask register
(INT_MASK-08H). The format of this register is the
same as that of the Interrupt Pending Register shown
in Figure 22. POPF Restore the PSW
RET

1-28.
 MCS®·96 8X9X ARCHITECTURAL OVERVIEW

Note that location 200CH: in the interrupt vector table INT_MASK register (part of the PSW), so any
would have to be loaded with the value of the label changes made to this register during a routine which
serial_io_isr and the interrupt be enabled for this ends with a POPF will be lost.
routine to execute.
Notice that the "preamble" and exit code for the inter-
There is an interesting chain of instruction side-effects rupt service routine does not include any code for sav-
which makes this (or any other) 8X9X interrupt service ing or restoring registers. This is because it has been
routine execute properly: ' assumed that the interrupt service routine has been al-
a) After the hardware decides to process an interrupt, it located its own private set of registers from the on-
generates and executes a special interrupt-call in- board register file. The availa15ility of some 230 bytes of
struction, which pushes the current program counter register storage makes this quite practical.
onto the stack and then loads the program counter
with the contents of the vector table entry ~orre­
sponding to the interrupt. The hardware will not al- 4.3 Critical Regions
low another interrupt to be serviced immediately fol-
lowing the interrupt-call. This guarantees that once Interrupt service routines must share some data with
the interrupt-call starts, the first instruction of the other routines. Whenever the programmer is coding
interrupt service routine will execute. those sections of code which access these shared pieces
of data, great care must be taken to ensure that the
b) The PUSHF instruction, which is now guaranteed to integrity of the data is maintained. Consider clearing a
execute, saves the PSW in the stack and then clears bit in the interrupt pending register as part of a non-in-
the PSW. The PSW contains, in addition to the terrupt routine: •
arithmetic flags, the INT_MASK register and the
global disable flag (I). The hardwarewiIl not allow LDB AL,INT_PENDING
an interrupt following a PUSHF instruction and, by ANDB AL,#biLmask
the time the LD instruction starts, all of the inter- STB AL,INT_PENDING
rupt enable flags will be cleared. Now there is guar-
anteed execution of the LD INT_MASK instruc- This code works if no other routines are operating con-
tion. currently, but will cause occasional but serious prob-
c) The LD INT~MASK instruction enables those in- lems' if used in a concurrent envin:mment. (All pro-
terrupts that the programmer chooses to allow to grams which make use of interrupts must be considered
interrupt the serial I/O interrupt service rO,lltine. In to be part of a concurrent environment.) To demon-
this example only ll1e HSI data available interrupt strate this problem, assume that the INT_PENDING
will be allowed to do this but any interrupt or combi- register contains OOoollllB and bit 3 (HSO event in-
nation of interrupts could ,be enabled at this point, terrupt pending) is to be reset. The code does work for
even the serial interrupt. It is the loading of the this data pattern but what happens if an HSI interrupt
INT_MASK register which allows the software to occurs somewhere between the LOB and the STB in-
establish its own priorities for interrupt servicing in- structions? Before the LOB instruction INT_PEND-
dependently from those that the hardware enforces. ING contains oooo1111B and after the LOB instruc-
d) The EI instruction reenables the processing of inter- tion so does AL. If the HSI interrupt service routine
rupts. executes at this point then INT_PENDING will
change to 0000101 lB. The ANDB changes At to
e) The actual interrupt service routine executes within , OOOOOll,IB and the STB ,changes INT_PENDING to
the priority structure established by the software. 00000 III B. It should be 000000 lIB. This code se-
t) A:t the end of the service routine the POPF instruc- quence has manged to generate a false HSI interrupt
tion restores the PSW to its state when the interrupt- The same basic process can generate an amazing assort-
call occurred. The hardware will not allow interrupts ment of problems and headaches. These problems can
to be processed following a,POPF instruction s6the be avoided by assuring mutual exclusion which basical-
execution of the last instruction (RET) is guaranteed ly means that if more than one routine can change a
before further interrupts can occur. The reason that variable, then the programmer must ensure exclusive
this RET instruction must be prote;cted in this fash- access to the variable during the entire operation on the
ion is that it is quite likely that the i>OPF instruction variable.
will reenable an interrupt which is already pending.
If this interrupt were serviced before the RET in- In many cases the instruction set of the 8X9X allows
struction, then the return address to the code that the variable to be modified with a single instruction.
was executing when the original interrupt occurred The code in the above example can be implemented
, would be left on the stack. While this does not pres- with a single instruction.
ent a problem to the program flow, it could result in
a sta,ck overflow if interrupts are occurring at a high ANDB
frequency. TliePOPF instruction also pops the

1-29
inter MCS®-96 8XgXARCHITECTVRAL OVERVIEW.

Instructions are indivisible so mutual exclusion is en- There are 6 instructiorts whiph always inhibit interrupts
sured in this case. Changes to the INT,-PENDING .. from I?eing acknowledged until after th~ next instru~­
register must be made·as a single instruction, since bits tion has been executed. These instructions are:
can be changed in this register even if interrupts are EI, DI ~ Enable and Disable Interrupts .'
disabled. Depending on system configurations, several
other SFRs might also need to be' changed in a single POPF, PUSHF-;- Pop and Push Flags
instruction for the same reason. SIGND ...,... Prefix tQ' perform signed multiply
and divide (Note that Jhisis not an
When variables must be modified without interruption, ASM-96 Mnemonic,but is used for
and a single instruction can not be used, the program- signed multiply and divide)
mer must create what is termed a critical region in SOFTWARE
which it is safe to modify the variable. One way to do TRAP - Software interrupt
this is to simply disable interrupts with a D I instruc-
tion, perform the modification, and then re-enable in- When an interrupt is acknowledged, the interrupt
terrupts with an EI instruction. The problem with this pending bit is cleared, and a call is forced to the loca-
approach is that it leaves the interrupts enabled even if tion indicated by the specified interrupt vector. This
they were not enabled at the start. A better solution is call occurs after the completion of the instruction in
to enter the critical region with a PUSHF instruction process, except as noted above. The procedure of get-
which saves the PSW and also clears the. interrupt en- ting the vector and forcing the call requires- 21 state
able flags. The region can then be terminated with a times. If the stack is in external RAM an additional 3
POPF instruction which. returns the interrupt enable to state times are required.
the state it was in before the code sequence. It should be
noted that some system configurations might require The maximum n).l)l1ber of state times required from the
more protection to form a critical region. An example time an interrupt is generated (not acknowledged) until
is a system in which more than one processor has ac- the 8X9X begins executing code at the desired location
cess to a common resource such as memory or external is the time of the longest instruction, NORML (Nor-
I/O devices. malize - 42 state times), plus the. 4 'state times prior to
the end of the previous instruction, plus the response
time (21 to 24 state times). Therefore, the maximum
4.4 Interrupt Timing response time is 70 (42 + 4 + 24) state times. This
does. not include the 12 state times required for PUSHF
Interrupts are not always acknowledged immediately. if it is used as the first instruction in the interrupt rou-
If the interrupt signal does not occur prior to 4 state- tine' or additional latency caused by having the inter-
times before the end of an instruction, the interrupt will rupt masked or disabled. Refer to Figure 22A, Inter-
not be acknowledged until after the next instruction has rupt Response Time, to visualize an example of a worst
been executed. This is because an instruction is fetched case scenario.
and prepared for execution a few state times before it is
actually executed.

STATE TIMES 432 1

EXECUTION ( ENDING
) INSTRUCTION
I '({
'NORML)",-
END 1 CALL IS
}_'_N_OR_M_L_'~.....
<(
F_OR_C_E_D.,./)
IF STACK
EXTERNAL

EXTINT~ 1 INTERRUPT ROUTINE

PENDING ..J"S~E~T-----------;lcLEARED
BIT •

RESPONSE TIME 114'~-------70 STATE TIMES-------"o....,..---I

270250-60

Figure 22A. Interrupt Response Time

1-30
 MCS®·96 8X9X ARCHITECTURAL OVERVIEW

Interrupt latency time can be reduced by careful selec- tiple functionality of the timer is determined by the
,tion of instructions in areas of code where interrupts state of 1/0 Control Register 0, bit 7 (IOCO.7). To en-
are expected. Using. 'El' followed immediately by a sure that all CAM entries are chec\<.ed each count of
long instruction (e.g. MUL, NORML, etc.) will in- Timer 2, the maximum transition speed is limited to
crease the maximum latency by 4 state. times, as an once per eight state times. Timer 2 can be cleared by~
interrupt cannot occur between EI and the instruction executing a reset, by setting lOCO. I, by triggering HSO
following in. The "DI", "PUSHF", "POPF" and channel OEH, or by pulling T2RST or HSI.O high. The
:'TRAP" instructions will also cause the same situa- HSO and CAM are described in Section 7 and 8.
tion. Typically the PUSHF, POPF and TRAP instruc- IOCO.3 and ICOO.S control the resetting of Timer 2.
tions would only effect latency when one interrupt Figure 23 shows the different ways of manipulating
routine is already in process, as these instructions are Timer 2. It is recommended that the lOCO register only
seldom used at other times. be used once during power on reset to initialize the
timers and pins, fohowed by an HSO command 14 to
clear Timer 2 internally; or externally cleared by the
5.0 TIMERS T2RST or HSI.O pins. T2RST is not available on the
8X98. Some 8X9XBH devices have errata associated
Two l6-bit timers are available for use on the 8096. The with Timer 2. See the data sheets for more information.
first is designated "Timer I", the second, "Timer 2".
Timer I is used to synchronize events to real time,
while Timer 2 can be clocked externally and synchro- 5.3 Timer Interrupts
nizes events to external occurrences.
Both Timer I and Timer 2 can be used to trigger a
timer oyerflow interrupt and set a flag in the 1/0 Status
5.1 Timer 1 Register I (lOS 1). The interrupts are controlled by
IOC1.2 and IOC1.3 respectively. The flags are set in
Timer 1 is clocked once every eight state times and can IOS1.S and 1081.4, respectively.
be cleared only by executing a reset. The only other
way to change its value is by writing to OooCH but this Caution must be used when examining the flags, as any
is a test mode which sets both timers to OFFFXH and access (including Compare and Jump on Bit) of 10SI
should not be used in programs. clears bits 0 through S including the software timer
flags. It is, therefore, recommended to write the byte to
a temporary register before testing bits. The general en-
5.2 Timer 2 abling and disabling of the timer iriterrupts are con-
trolled by the Interrupt Mask Register bit O. In all cas- .
Timer 2 can be incremented by transitions (one count . eg., setting a bit enables a function, while clearing a bit
each transition, rising and falling) on either T2CLK or disables it.
HSI.1. T2CLK is not available on the 8X98. The mul-

.
IOCO.S
270250-22

Figure 23. Timer 2 Clock and Reset Options

1-31.
 MCS®·96 8X~X ARCHITECTURAL OVERVIEW

5.4 Timer Related Sections, 6.0 HIGH SPEED INPUTS

The High Speed I/O unit is coupled to the timers in The High Speed Input Unit (HSI), can be used to rec-
that the HSI records the value on Timer 1 when tran- ord the time at which an event occurs with respect to
sitions occur and the HSO causes transitiOlis to occur Timer 1: There are 4 lines (HSI.O through HSI.3)
based on values of either Timer 1 or Timer 2. The baud which clm be used in this mode' and up to a total of 8
rate generator can use the T2CLK pin as input to its events can be recorded. HSI.2 and HSI.3 are bidirec-
counter. a complete listing of the functions of 10Sl, tional 'pins which can also be used as HSO.4 and
lOCO, and lOCI are in Section 11. HSO.S. The I/O Control Registers (lOCO and IOCt)
are used to determine the functibns of these pins. A
block diagram of the HSI unit is shown in Figure 24:

FIfO
INTERRUPT
&;
CONTROL LOGIC

4 8x20 BIT
FIFO

+iSI PINS
4
~LO

~OHI
--'Hi(,R LoL-
t t
.IlJ'1.I'lJ1.I1
EVERY EIGHTH POSITIVE
TRANSITION
270250-23

Figure 24. High Speed Input Unit

.1-32
 ,

intJ MCS®·96 8X9X ARCHITECTURAL OVERVIEW

6.1 HSI Modes events. It can take up to 8 state times for this informa-
tion to reach the holding register. For this reason, 8
There are 4 possible modes of operation for each of the state times must be allowed between consecutive reads
HSI pins. The HSI mode register is used to control of HSI_TIME. When the FIFO is full, for a total of 8
which pins will look for what type of events. The 8-bit events, were be stored by considering the holding regis-
register is set up as shown in Figure 25. ter part of the FIFO. If the FIFO and holding register
are full, any additional events will cause an overflow
High and low levels each need to be held for at least 1 condition. Any eight consecutive events will overflow
. state time to ensure proper operation. The maximum on the ninth event if the program does not clear all
input speed is I event every 8 state times except when e.ntries in the FIFO before the ninth event occurs. Some
the 8 transition mode is used, in which case it is I versions of the 8X9X have errata associated with the
transition per state' time. The divide by eight counter HSI unit. See the data sheets for more infor.mation.
can only be zeroed in mid-count 'by performing a hard-
ware reset on the 8X9X.
6.3 HSI Interrupts
HSI_Mode (03H) Interrupts can be generated by the HSI unit in three
ways; two FIFO related interrupts and 0 to I tran-
171 6 I 5 4 I 3 2111 0 I sitions on the HSLO pin. The HS10 pin can generate
L HSI.O ~ODE
interrupts even if it is not enabled to the HSI FIFO.
Interrupts generated by this pin cause a vector through
HSI.l· ~ODE
location 2008H. The FIFO related interrupts are con-
HSI.2 ~ODE
trolled by bit 7 ofI/O Control Register I, (IOCI.7). If
HSI.3 MODE
the bit is a 0, then an interrupt will be generated every
WHERE EACH 2 - BIT MODE CONTROL FIELD
DEFINES ONE OF 4· POSSIBLE MODES: time a value is Iqaded into the holding register. If it is a
I, an interrupt will only be generated when the FIFO,
00 8 POSITIVE TRANSITIONS
01 EACH POSITIVE TRANSITION (independent of the holding register), has six entries in
10 EACH NEGATIVE TRANSiTION it. Since all interrupts are rising edge triggered, if
11 EVERY TRANSITION
(POSITIVE AND NEGATIVE) IOCI.7 = I, the processor will not be re-interrupted
270250-24 until the FIFO first contains 5 or less records, then
contains six or more.
Figure 25. HSI Mode Register Diagram

The HSI lines can be individually enabled and disabled 6.4 HSI Status
using bits in lOCO, at location OOI5H. Figure 26 shows
the bit locations which control the HSI pins. If the pin Bits 6 and 7 of the I/O Status register I (lOS I) indicate
is disabled, transitions will not be entered in the FIl2'O. the status of the HSI FIFO. If bit 6 is a I, the FIFO
contains at least six entries. If bit 7 is a 1, the FIFO
contains at least 1 entry and the HSI holding register
has data available to be read. The FIFO may be read

I
T2RST~5
Y,lO-,---:-- T2 RESET after verifying that it contains valid data. Caution must
"-·IOCO.3 be used when reading or testing bits in IOS1, as this
;--IOCO.O
action clears bits 0-5, including the softwah; and hard-
HSI.O :i""-o_-..,..---- HSI ware timer overflow flags. It is best to store the byte
• _. IOCO.2
~'-o---"---- HSI and then test the stored value. See Section 11.
HSI.l ~ TIMER2
T2CLK ~ : _. IOCO.7 CLOCK Reading the HSI is done in two steps. First, the HSI
r-- IOCO.4 Status register is read to obtain the current state of the
HSI,2 ~""'-oo------ HSI . HSI pins and which pins had changed at the recorded
; _. IOCO.6 time. The format of the HSI_STATUS Register is
HSI.3 ~""'-o_----- HSI shown in Figure 27. Second, the HSI Time register is
270250-25 read. Reading the Time register unloads one level of the
FIFO, so if the Time.register is read before the Status
Figure 26. lOCO Control Of HSI Pin Functions register, the event information in the Status register will
be lost. The HSI Status register is at location 06H and
the HSI Time registers are in locations 04H and 05H:
6.2 HSI FIFO
If the HSI_TIME register is read without the holding
When an HSI event occurs, a 9x20 FIFO stores the 16 register being loaded, the returned value will be indeter-
bits of Timer I and the 4 bits indicating which pins had minate. Under the same conditions, the four bits in

1-33
 MCS®~96 8X9X ARCHITECTURAL OVERVIEW

HSI_STATUS indicating which events have occurred 7;1 HSO CAM

will also be indeterminate. The four, HSI_STATUS
bits which indicate the current state of the pins will A block diagram of the HSO .unit is shown in Figure
always return the correct value. 28. The Content Addressable Memory (CAM) file is
the center of. control. One CAM register is compared
It should be noted that many of the Status register con- with the timer values every state time, taking 8 state
ditions are changed by a reset, see Section 13. A com- times to compare all CAM registers with the timers.
plete listing of the functions of IOS0, lOS 1, and IOC 1 This defines the time resolution of the HSO to be 8
can be found in Section 11. state times (2.0 microseconds at an oscillator frequency·
of 12 MHz).
,-----------------,
7.0 HIGH SPEED OUTPUTS
HSI Status,.Register (HSI....;Status)
The High Speed Output unit, (HSO), is used to trigger , LOCATION 06H
events at specific times with minimal CPU overhead.
These events include: starting an A to D conversion,
resetting Timer 2, setting 4 software flags, and switch-
ing 6 output lines (HSO.O through HSO.5). Up to eight HSI.O STATUS
events can be pending at one time and interrupts can be ~--- HSt1 STATUS
generated whenever any. of these events are triggered. L..--,----,-.,.._ _ HSI.2 STATUS
HSO.,4 and HSO.5 are bidirectional pins which can also
' - - - - - - - - - HSI.3 STATUS
be used as HSI.2 and HSI.3 respectively. Bits 4 and 6 of 270250-26
I/O Control Register 1, (IOCI.4, IOC1.6), enable Where for each 2-bit. status fieio the lower bit indicates
HSO.4 <lnd HSO.5 <IS outputs. whether or not an event has occurred on this pin at the
time in HSI_TIME and the upper bit inoicates the cur-
The HSO unit can generate two types of interrupts. The rent status of the pin.
HSO execution interrupt (vector = (2006H» is gener-
ated (if enabled) for HSO commands which operate one Figure 27. HSIStatus Register Diagram
or more of the six output pins. The other HSO inter-
rupt is the software timer interrupt (vector = Each CAM register is 23 bits wide. Sixteen bits specify
(200BH» which is generated (if enabled) by any other the time at which the action is to be carried out and 7
HSO command, (e.g. triggering the A/D, resetting bits specify both the nature of the action alld whether
Timer 2 or generating a software time delay). Timer 1 or Timer 2 is the reference. The format bf the

TIMER 2 INPUT

'-1--"~ TIMER 2 RESET

16

HIGH SPEED OUTPUT CONTROL

• 6 'OUTPUT PiNS
• 4 SOFTW/l,RE TIMERS
• INITIATE AID CONVERSION
• RESET TIMER 2

PORT PINS
270250-27
~---------------------------.---------------------~--~-----
Figure 28. High Speed Output Unit
1-34
inter MCS®-96 8X9X ARCH.ITECTURAL OVERVIEW

command to the HSO unit is shown in Figure 29. Note 7.2 HSO Status
that bit 5 is ignored for command channels 8 through
OFH. Before writing to the HSO, it is desirable to ensure that
the Holding Register is empty. If it is not, writing to the
To enter a command into the CAM file, write the 7-bit HSO will'overwrite the value in the Holding Register.
"Command Tag" into location 0006H followed by the I/O Status Register 0 (IOS0) bits 6 and 7 indicate the
time at which the action is to be carried out into word status' of the HSO unit. This register is describeq in
address 0004H. The typical code would be: Section II. If IOS0.6 equals 0, the holding register is
empty and at least one CAM register is empty. If
LDB HSO_COMMAND,#what_to_do IOSO.7 equals 0, the holding register is empty.
ADD HSO_TIME,TIMERl,#when_to_do_it
The programmer should carefully decide which of these
Writing the time value loads the HSO Holding Register two flags is the best to use for each application.
with both the time and the last written command tag.
The command does not actually enter the CAM file
until an empty CAM register becomes available. . 7.3 Clearing the HSO
Commands in the holding register will not execute even All 8 CAM locations of the HSO are compared before
if their time tag is reached. Commands must be in the any action is taken. This allows a pending external
CAM for this to occur. Commands in the holding regis- event to be cancelled by simply writing the opposite
ter can also be overwritten. Since it can take up to 8 event to the CAM. However, once an entry is placed in
state times for a command to move from the holding the CAM, it cannot be removed until either the speci-
register to the CAM, 8 states must be allowed between fied timer matches the written value or the chip is reset.
successive writes to the CAM. If, as an example, a command has been issued to set
HSO.l when TIMER 1 = 1234, then entering a second
To provide proper synchronization, the minimum time command which clears HSO.I when TIMER I = 1234
that should be loaded to Timer I is Timer I + 2. will result in no operation on HSO.1. Both commands
Smaller values may cause the Timer match to occur will remain in the CAM until TIMER I = 1234.
65,636 counts later than expected. A similar restriction
applies if Timer 2 is used. Internal events are not synchronized to Timer I, and
therefore cannot be cleared. This includes events on
Care must be taken when writing the command tag for HSO channels 8 through F and all interrupts. Since
the HSO. If an interrupt occurs during the time be- interrupts are not synchronized it is possible to have
tween writing the command tag and loading the time multiple interrupts at the same time value.
value, and the interrupt service routine writes to the
HSO time register, the command tag used in the inter-
rupt routine will be written to the CAM at both the 7.4 Using Timer 2 with the HSO
time specified by the interrupt routine and the time
specified by the main program. The command tag from Timer 1 is incremented only. once every 8 state-times.
the main program will not be executed. One way of When it is being used as the reference timer for an HSO
avoiding this problem would be to disable interrupts action, the comparator has a chance to' look at all 8
when writing commands and times to the HSO unit. CAM registers before Timer I changes its value. Fol-
See also Section 4.5. lowing the same reasoning, Timer 2 has been synchro-
nized to anow it to change·at a maximum rate of once
per 8 state-times. Timer 2 increments on both edges of
CHANNEL: the input signal.
0-5 HSO.O - HSO.5
BIT: HSO.O AND HSO.l When using Timer 2· as the HSO reference, caution'
HSO.2 AND HSO.3 must be taken that Timer 2 is not reset prior to the
8-B SOFTWARE TIMERS highest value for a Timer 2 match in the CAM. This is
E RESET TIMER2 because the HSO CAM will hold an event pending until
START A I D CONVERSION a time match occurs, if that match is to a time value on
Timer 2 which is never reached, the event will remain
INTERRUPT I NO INTERRUPT
pending in the CAM until the device is reset.
SET ICI,.EAR
TIMER 2/TIMER 1
Additional caution must be used when Timer 2 is being
reset using the HSO unit, since resetting Timer 2 using
X the HSO is an internal event and can therefore happen
270250-28
at any time within the eight-state-time window. This
situation arises .when the event is, set to. occur .when
Figure 29. HSO Command Tag Format
1-35
 MCS®·96 8X9X ARCHITECTURAL OVERVIEW

Timer 2 is equal to ze~o. If HSI.O or the T2RST pin is 8.0 ANALo.G INTERFACE
used to clear Timer 2, and Timer 2 equal to zero trig-
gers the event, then the, event may not occur. This is The 8X9X can easily interface to analog signals using
because HSI.O and T2RST clear Timer 2 asynchro- its Analog to Digital Converter and its Pulse-Width-
nously, and Tinler 2 may then be incremented to one Modulated (PWM) output and HSO Unit. There are 8
before the HSO CAM entry can be read and acted inputs to the lO-bit A to D converter on the 8X9XBH
upon. This can be avoided by setting the event to occur and 8X9XJF. There are 4 inputs on the 8X98. The
when Timer 2 is equal to one. This method will ensure PWM and HSO units provide digital signals which can
that there is enough time for the CAM entry recogni .. be filtered for use as analog outputs.
tion. .

The same asynchronous nature can affect events sched- 8.1 Analog Inputs
uled to occur at the same time as an internal Timer 2
reset. These events should be logged into the CAM A to D conversion is performed on one input at a time
with a Timer 2 value of zero. When using this method using successive approximation with a result equal to
to make a programmable· modulo' counter, the count the ratio of the input voltage divided by the analog
will stay at the maximum Timer 2 value only until the supply voltage. If the ratio is 1.00, then the result will
Reset T2 command is recognized. The count will stay be all ones. The AID converter is available on selected
at zero for the transition which would have changed the members of the MCS-96 family. See Section 14 for the
count from "N" to zero, and then changed to a one on device selection matrix.
the next transition.
Each conversion on the 8X9X requires 88 state-times
(22 ,""S at 12 MHz) independent of the accuracy desired
7.5 'Software Timers or value of input voltage. The input voltage must be in
the range of a to VREF, the analog reference and supply
The HSO can be ,programmed to generate interrupts at voltage. For proper operation, VREF (the reference
preset times'. Up to four such "Software Timers" can be voltage and analog power supply) must be 'between
in operation at a time. As each preprogrammed time is 4.5V and 5.5V. The AID result is calculated from the
reached, the HSO unit sets a Software Timer Flag. If formula:
the interrupt bit in the command tag was set then a
Softwar,e Timer Intern,lpt will also be generated. The 1023 x (Input voltage-ANGND)/(VREF-ANGND)
interrupt service routine can then examine I/O Status
register I (IOSI) to determine which software timer It can be seen from this formula that changes in VREF
expired and caused the interrupt. When the HSO resets or ANGND effect the output of the converter. This clm
Timer 2 or starts an A to D conversion, it can also be be advantageous if a ratiometric sensor is used since
programmed to generate a software timer interrupt but these sensors have an output that can be measured as a
there is no flag to indicate that this has occurred. proportion of V REF.

If more than one software timer interrupt occurs in the ANGND must be tied to Vss (digital ground) in order
same time frame it is P9ssible that multiple software for the 8X9X to operate properly. This common con-
timer interrupts will be generated. nection should be made as close to the chip as possible,
and using good bulk and high frequency by-pass capaci-
Each read or test of any bit in lOS 1 will clear bits a tors to decouple power supply variations and noise
through 5. Be certain to save the byte before testing it from the circuit. Analog design rules can for one and
.unless you are only concerned with I bit. See also Sec- only one common connection be.tween analog and digi-
tion 11.5. tal returns to eliminate unwanted ground variations.

A complete listing of the functions of 10SO, 10SI, and

lOCI can be found jn Section II. The Timers are de-
scribed ill Section Sand the HSI is described in Section 6.

1-36
inter MCS<I!l-96 8X9X ARCHITECTURAL OVERVIEW

The AID converter has sample and hold. The sampling The command register is double buffered so it is possi-
window is open for 4: state times which are included in ble to write a command to start a conversion triggered
the 88 state-time conversion period. The exact timings by the HSO while one is still in progress. Care must be
of the AID converter'can be found in Section 3 of the taken when this is done since if a new conversion is
Hardware Design chapter. started while one is already in progress, the conversion
in progress is cancelled and the neW one is 'started.
When a conversion is started, the result register is
8.2 AID Commands cleared. For this reason the result register must be read
before a new conversioh is started or data will be lost.
Analog signals can, be sampled by anyone "of the 8
analog input pins' (ACHO through ACH7) which are
shared with Port O. ACH7 can also be used as an exter- 8.3 AID Results
nal interrupt if IOCl.! is set (see Sections 4 and 11).
The AID Command Regi~ter, at location 02H,' selects Results of the analog conversions are read from the
which channel is to be converted and whether the con- AID Result Register at locations 02H and 03H. Al-
version should start immediately, or when the HSO though these addresses are on a word boundary, they
(Channel #OFH) triggers it. The AID command regis- must be read as individual bytes. Information in the
ter must be written to for each conversion, even if the AID Result register is formatted as shown in Figure
,HSO is used as the trigger. A to D commands are for- 31. Note that the status bit may not be set until 8 state
matted as shown in Figure 30.

AID Command Register

(LOCATION O2H)

~ CHANNEL /I SELECTS WHICH OF THE 8 ANALOG INPUT

, CHANNELS IS TO BE CONVERTED TO DIGITAL FORM,

GO INDICATES WHEN THE CONVERSION IS TO BE

=
INITIATED (GO 1 MEANS START NOW, GO 0 =
MEANS THE CONVERSION IS TO BE INITIATED
BY THE HSO UNIT AT A SPECIFIED TIME),
270250-29

Figure 30. AID Command Register

AID RESULT REGISTER

(LOCATION 03H) (LOCATION O2H)

AID CHANNEL NUMBER

....._ ......- STATUS
o =AID CURRENTLY IDLE
1 = CONVERSION IN PROCESS
L.-_______ AID RESULT:
LEAST SIGNIFICANT 2 BITS-
MOST SIGNIFICANT BYTE
270250-30

Figure 31. AID Result Register

1-37
infef I\IICS®-96 8X9X ARCHITECTURAL OVERVIEW

times after the go ~ommand, so it is necessary to wait 8 Figure 33. Note that when the. PWM r~gister equals 00,
state times before testing it. Information on using the the output is always low. Additionally, the PWM regis-
HSO is in Section 7. te, will only be reloaded from the temporary latch
when the counter 'overflows. This means that the com-
pare circuit will not recognize a new value to compare
8.4 Pulse Width Modulation Output against until the counter has expired the remainder of
. (D/A) the current 8-bit count.

to
Digital analog conversion can be done with the Pulse The output waveform is a variable duty cycle pulse
Width Modulation output; a block diagram of the cir- which repeats every 256 state times (64 /-Ls at 12 MHz).
cuit is shown in Figure 32. The 8-bit counter is incre- Changes in the duty cycle are made by writing to the
mented every state time. When it equals 0, the PWM PWM register at location 17H..There are several types
output is set to a one. When the counter matches the of motors which require a PWM waveform for most
value in the PWM register, the output is switched low. efficient operation. Addition,ally, if this waveform is in-
When the counter overflows, the output is once again tegrated it will produce a DC level which can be
switched high. A typical output waveform is shown in changed in 256 steps by varying the duty cycle.

PWM/P2.5
PIN

OVERFLOW
270250-31
• PWM Period (XTAL = 12 MHz) = '64 /Ls, Frequency = 15.625 KHz
• Duty Cycle Programmable in 256 Steps

Figure 32. Pulse Width Modulated (01 A) Output

DUTY PWM CONTROL

CYCLE REGISTER VALUE OUTPUT WAVEFORM
HI
0% 00
LO

10% 25
~~J1 n n
HI
50"10 128
LO

90% 230 HI
LO
.J U U
HI
99.6% 255
L9 .1
270250-32

Figure 33. Typical PWM Outputs

1-38
 MCS@·96 8X9X ARCHITECTUR~L OVERVIEW

Details about the hardware required for smO(~th, accu- Control of the serial port is handled through the Serial
rate D/A conversion can be found in Section 4 of the Port ControVStatus'Register at location IIH. Figure
Hardware Design chapter. Typically, some form of 37 shows the layout of this register. The detail~ of using it
butTer and integrator are needed to obtain the most use- to control the serial port will be discussed in Section 9.2.
fulness from this feature.
Data to and from the serial port is transferred through
The PWM output shares a pin with Port 2, pin 5 so SBUF (rx) and SBUF (tx), both located at 07H. Al-
that these two features cannot be used at the same time. though these registers share the same address, they are
10CI.0 equal to I selects the PWM function instead of physically separate, with SBUF (rx) containing the data
the standard port function. More information on lOCI received by the serial port and SBUFr (tx) used to hold
is in Section II. ' data ready for transmission. The program cannot write
to SBUF (rx) or read from SBUF (tx).

8.5 PWM Using the HSO The baud rate at whicb. the serial port operates is con-
trolled by an independent baud rate generator. The in-'
The HSO unit can be used to gen:erate PWM wav~- puts to this generator can be either the XTALI or the
, forms with very little CPU overhead. If the HSO is not' T2CLK pin. Details on setting up the baud rate are
being used for other purposes, a 4 line PWM unit can given in Section 9.3. '
be made by loading the on and otT times into the CAM
in sets of 4. The CAM would then always be loaded and
only 2 interrupts per PWM period would be needed. 9.1 Serial Port Modes

MODE 0
9.0 SERIAL PORT
The ,serial port on the 8X9X has 3 asynchronous and Mode 0 is a synchronous tpode which is commonly
one synchronous mode. The asynchronous modes are used for shift register based I/O expansion. In this
full duplex, meaning they can transmit and receive' at mode the TXD pin outputs a set of 8 pulses while the
the same time. The receiver is double butTered so that RXD pin either transmits or receives data. Data is
the reception of a second byte can begin before the first transferred 8 bits at a time with the LSB first. A dia-
byte has been read. The port is functionally compatible gram of the relative 'timing of theSe signals is shown in
with the serial port on the MCS-51 family of microcon- Figure 34. Note that this is the only mode which uses
trollers, although the software used to control the ports RXD as an output.
is ditTerent.

TXD "'lJ "'lJ "'lJ '''U '''U '''if "'if "'lJ

RXD(out)

~~~~~~~M~~~~~~~~~
IIXD (In) VALID VALID VALID, VALID VALID VAUD VALID VALID
--J\.....I\.....I\.....I\.....I\.....I\.....I\.....I\-I\..-I\.....J\-I\.....J\-I\-I\.....I~
270250-34

Figlu8,34. Serial Port Mode 0 Timing'

1-39
inter MCS®·96 8X9X: ARCHI"FECTURAL OVERVIEW

Although, it is not possible to transmit and receive at MODE 3

the same time:using this mode, two ,external gates and a
port pin can be used to time-multiplex the two func- Mode 3 is the asynchronous 9th bit mode. The data
tions. An,'example of multiplexing transmit and receive frame for this mode is identical ,to that of Mode 2. The
is discussed in Section 6.1 of the Hardware Design transmission differences between Mode 3 and Mode 2
chapter. are that parity can be enabled (PEN = 1) and cause the
9th data bit to take the even parity value. The TB8 bit
can still be used if parity is not enabled (PEN = 0).
MODE 1 When in Mode 3, a reception always causes an inter-
Mode I is the standard asynchronous communications rupt. regardless of the state of the 9th bit. The 9th bit is
mode. The data frame used in this mode is shown in stored if PEN = 0 and can be read in bit RB8. If
PEN = I then RB8 becomes the Receive Parity Error
a
Figure 35. It consists of 10 bits; start bit (0). 8 data
(RPE) flag.
bits (LSB first). and a stop bit (I). If parity is enabled,
(the PEN bit is set to a I). an even parity bit is sent
instead of the 8th data bit and parity is checked on
reception.' ' 9.2 ContrOlling the Serial Port
Control of the serial port is done through the Serial
MODE 2 Port Control (SP_CON) and Serial Port Status
(SP_STAT) registers shown in Figure 37. Writing to
Mode 2 is the asynchronous 9th bit recognition mode. location I1H accesses SP_CON while reading it access
This mode is commonly used with Mode 3 for multi- SP_STAT. Note that reads of SP_STAT will return
processor communications. Figure 36 shows the data indeterminate data in the lower 5 bits and writing to the
frame used in this mode. It consists of a start bit (0). 9 upper 3 bits of SP_CON has no effect on chip func-
data bits (LSB first). and a stop bit (I). When transmit- tionality. The TB8 bit is cleared after each transmission
ting. the 9th bit can be set to a one by setting the TB8 and both TI and RI are cleared whenever
bit in the control register before writing to SBUF (tx). SP_STAT (not SP_CON) is accessed. Whenever the
The TB8 bit is cleared on every transmission. so it must TXD pin is used for the serial port it' must be enabled
be set prior to writing to SBUF (tx) each time it is by setting IOCI.5 to a 1. lOCI is discussed further in
desired. During reception. the serial port interrupt and Section 11.3. Information on the hardware connections
the Receive Interrupt (RI) bit will not be set unless the and timing of the serial port is in Section 6 of the Hard-
9th bit being received is set. This provides an easy way ware Design chapter.
to have selective reception on a data link. Parity cannot
be enabled in this mode.

STOP

11).BIT FRAME,
270250-35

Figure 35. Serial Port Frame..,....Mod~ 1

STOP

PROGRAMMABLE 9TH BIT

11-BIT FRAME
270250-36

Figure 36. Serial Port Frame Modes 2 and 3

1-40
 MCS®·96 8X9X ARCHITECTURAL OVERVIEW

LOCATION 11H

SP_STAT SP_CON
, (READ ONLY) (WRITE ONLY)

• ,
IRI'~RPE I RI I '5
'TI T88
3
REN
1 I 2
PEN
1
M2
1
0
Ml J
~
J
L M2,Ml SPECIFIES THE MOD E,
0,0= MODE 0
0,1 = MODEl
1,0= MODE 2
1,1 = MODE 3

-PEN ENABLE THE PARITY FUNCTION (EVEN PARITY),

REN ENABLES THE RECEI VE FUNCTION;

,
TBB PROGRAMS THE 9TH DATA BIT (IF NOT PARITY) ON
TRANSMISSION,
TI IS THE TRANSMIT IN TERRUPT FLAG,

RI IS THE RECEIVE INTE RRUPT FLAG, '

RBI IS THE 9TH DATA BIT RECEIVED (IF NOT PARITY),

RPE IS THE PARITY ERROR INDICATOR (IF PARITY ACTIVE).

270250-33
NOTE:
TI and RI are cleared when SP_STAT is read.

Figure 37. Serial Port Control/Status Register

In Mode 0, if REN = 0, writing to SBUF (tx) will start 9.3 Determining Baud Rat,es
a transmission. Causing a rising edge on REN, or clear-
ing RI with REN = I, ~ilI start a reception. Setting
°
REN ;: will stop a reception in progress and inhibit
further receptions. To avoid a partial or complete unde-
Baud rates in all modes are determined by the contents
of a 16-bit register at location OOOEH. This register
must be loaded sequentially with 2 bytes (least signifi-
sired reception, REN must be set to zero before RI is cant byte first). The serial port will notJunction be-
cleared. This can be handled in an interrupt environ- tween the loading of the first and second bytes. The
ment by using software flags or in straight-line code by MSB of this register selects one of two sources for the
using the Interrupt Pending register to signal the. com- input frequency to the baud rate generator, If it is a: I,
pletion of a rec,eption. the frequency on the XTALl pin is selected, if not, the
external frequency from the T2CLK pin is used. It
In the asynchronous modes, writing to SBUF (tx) starts should be noted that the maximum speed of T2CLK is
a transmission. A falling edge on' RXD will begin a one transition every 2 state times, with a minimum pe-
receptio'n if REN is set to 1. New data placed in SBUF riod of 16 XTALl cycles. This provides the needed
(tx) is held and will not be transmitted uqtil the end of synchronization to the internal serial port clocks.
the stop bit has been sent.
The unsigned integer represented by the lower 15 bits
In all modes, the RI Rag is set after the last data bit is of the baud rate register defines a number B, where B
sampled approximately in the middle of the bit time. has a maximum value of 32767, The baud rate for the
Also for all modes, the TI flag is set after the last data four serial modes using either XTALI or T~CLK as
bit (either 8th or 9th) is sent, also in the middle of the the clock source is given by:
bit time. The flags clear when SP_STAT is read, but
do not have to be clear for the port to receive or trans- Using XTALl:
mit. The serial port interrupt bit is set as a logical OR
of the RI and TI bits. Note:; that changing m04es will Mode 0: Baud XTAL1 frequency B "'" 0
reset the Serial Port and abort any transmission or re- Rate = 4' (B + 1) ;
ception in progress on the channel. If the Tx and Rx
pins are tied together for loopback testing, the RI flag
will be written first.
1-41
intJ MCS®·96.8X9X ARCHITEC.TURAL OVERVIEW

Oth . Baud = XTAL 1 frequency provide extra 1/0 lines if the timer related features of
€Irs. Rate 64 *(B + 1) these lines are not needed.

Using T2CLK: Input ports cOnnect to the internal bus through an in-
put buffer. Output ports connect through an output
Mode 0'. Baud T2CLK frequency B buffer to an internal register that hold the bits to be
Rate = B ; '* 0 output. Bidirectional ports consist of an internal regis-
ter, an input buffer, and an output buffer.
Others: Baud T2CLK frequency B
Rate = 16 * B ; '* 0 Port 0 is an input port which is also used as the analog
input for the A to D converter. Port 1 is a quasi-bidi-
Note that B cannot equal 0, except when using XTALI rectional port. Port 2 contains three types of port lines:
in other than mode O. ql,lasi-bidirectional, input and output. The input and
output lines are shared with other functions in the
Common baud rate values, using XTALl at 12 MHz, 8X9X as shown in Table 4. Ports 3 and 4 are open-
. are shown below. drain 'bidirectional ports which share their pins with the
addressldata bus.

Baud Baud Register Value Table 4. Port 2 Alternate Functions

Rate Mode 0 Others Alternate Controlled
Port Function
9.600 8137H 8013H Function by
4800 8270H 8026H P2.0 Output TXD (Serial Port IOC1.5
2400 84E1H 804DH Transmit)
1200 89C3H 809BH P2.1 Input RXD (Serial Port N/A
300 A70FH '8270H Receive M1-3)
Output RXD (Serial Port
The maximum baud rates are 1.5 Mbaud synchronous Output MO)
and 187.5 Kbaud asynchronous with 12 MHz on P2.2 Input EXTINT IOC1.1
XTAL1. (External Interrupt)
P2.3 Input T2CLK (Timer IOCO.7
2 Input)
9.4 Multiprocessor Communications
P2.4 Input T2RST (Timer IOCO.5
Mode 2 and 3 are provided for multiprocessor commu- 2 Reset)
nications. In Mode 2 if the received 9th data bit is not P2.5 Output PWM IOC1.0
1, the serial port interrupt'is not activated. The way to (Pulse-Width
use this feature in multiprocessor systems is described Modulation)
below.
i
P2.6 Quasi-Bidirectional
When the master processor wants to transmit a block of P2.7 Quasi-Bidirectional
data to one 'of several slaves, it first sends out an ad-
dress frame which identifies the target slave. An ad-
dress frame will differ from a data frame in that the 9th Section 2 of the Hardware Design chapter contains ad-
data bit is I in an address frame and 0 in a data frame. ditional information on the timing, drive capabilities,
Slaves in Mode 2 will not be interrupted by a data and input impedances of 1/0 pins.
frame. An address fr.ame, however, will interrupt all
slaves so that each slave can examine the received byte
and see if it is being addressed. The addressc;d slave 10.1 Input Ports
switches to Mode 3 to receive the coming data frames,
while the slaves that were not addressed stay in Mode 2 Input ports and pins can only be read. There are no
and goon about their business. output drivers on these pins. The input leakage of these
pins is in the microamp range. The speCific values I;:an
be found in the data sheet for the device being consid~
ered.· ,
10.0 1/0 PORTS
There are five8-bit I/O ports on the 8096. Some of In addition to acting as a digital input, each line of Port
these pmts are input only, some are output only, some ocan be selected to be the input of the A to D converter
are bidirectional. and some have alternate functions. In as discussed in Section 8. The pins on Port 0 are tested
addition to these ports, the HSIIO unit can be used to

1-42
 inter MCS®·96 8X9X ARCHITECTURAL OVERVIEW

to have D.C. leakage of 3 microamps or less, as speci- and leave the pin pulled up with a relatively high im-
fied in, the data sheet for the device being considered. pedance pullup device which can be easily driven down
The capacitance on these pins is' approximately 5 pF by the device driving the input.
and will instantaneously increase by around 5 pF when
the pin is being sampled by the A to D converter. If some pins of a port are to be used as inputs and some
are to be used as outputs the programmer should be
The 8X98 devices only have 4 Port 0 pins. careful when writing to the port.

The 8X9X samples the input to the A/D for 4 state Particular care should be exercised when using XOR
times at the beginning of the conversion. Details on the opcodes or any opcode which is a read-modify-write
A to D converter can be found in Section '8 of this instruction. It is possible for a Quasi-Bidirectional Pin
chapter and in Section 3 of the Hardware Design chap- to be written as a one, but read back as a zero if an
ter. external deviqe (i.e., a transistor base) is pulling the pin
below VIH' See the Hardware Design Chapter Section
2.2 for further details on using the Quasi-Bidirectional
10.2 Quasi-Bidirectional Ports Ports.

Port 1, Port 2.6 and Port 2.7 are quasi~bidirectional

ports. Port 1, Port 2.6 and Port 2.7 are not availabk on 10.3 Output Ports
the 8X98. "Quasi-bidirectional" means that the port
pin has a weak internal pullup that is always active and Output pins include the bus control lines, the HSO
an internal pulldown which can be on to output a 0, or lines, and some of Port 2. These pins can only be used
off tooiltput a 1. If the internal pulldown is left off (by as outputs as there are no input buffers connected to
writing a 1 to the pin), the pin's logic level can be con- them. It ,is not possible to use immediate logical instruc-
trolled by an external pulldown. If the external pull- tions such as XOR PORT2, #OOlIIB to toggle these·
down is on, it wlII input a 0 to the 8X9X, if it is off, a 1 pins. The output currents on these ports is higher than
. will be input. From the user's point of view, the main that of the quasi-bidirectional ports.
difference between a quasi-bidirectional port and a
standard input port is that the quasi-bidirectional port
will source current if externally pulled low. It will also 10.4 Ports 3 and 4/ADO-15,
pull itself high if left unconnected.
These pins have two functions. They are either bidirec-
In parallel" with the weak internal pullup is a much tional ports with open-drain outputs or System Bus
stronger internal pullup that is activated for one state pins which the memory controller uses when it is acces-
time when the pin is internally driven from 0 to 1. This ing off-chip memory. If the EA line is low, the pins
is done to speed up the O-to-l transition time. When always act as the System Bus. Otherwise they act as bus
this pullup is on the pin can typically source 30 milli- pins only during a memory access. If these pins are
amps to VSS' being used as ports and bus pins, ones must be written
to them prior to bus operations.
When the processor writes to the pins of a quasi-bidi-
rectional port it actually writes into a register which in Accessing Port 3 and 4 as I/O is easily done from inter-
turn drives the port pin. When the processor reads nal registers. Since the LD and ST instructions require
these ports, it senses the status of the pin directly. If a the use of internal registers, it may be necessary to first
port pin is to be used as an input then the software move the port information into an internal location be-
should write a one to its associated SFR bit, this will fore utilizing the data. If the data is already internal,
cause the low-impedance pun-down device to tum off the LD is unnecessary. For instance, to write a word
value to Port 3 and 4 ...

LD intreg, portdata register ~ data

not needed if already internal
ST intreg, lFFEH register -+ Port 3 and 4

1-43
 MCS®-96 8X9X ARCHITECTURAL OVERVIEW

To read Port t3 and 4 requires that "ones" be written to the port registers to first setup the input port configuration
circuit: Note that the ports are reset to this input condition, but if zeroes have been written to the port, then ones
must be re-written to any pins which are to be used as inputs., Reading Port 3.and 4 from a previously written zero
condition is as follows ...

LD intregA.,#OFFFFH , setup port change mode pattern

ST 'intregA, lFFEH register -+ Port 3 and 4
LD & ST not' needed if previously
written as ones
LD intregB, lFFEH regist~r +- Port 3 and 4
Note that while the format of the LD and ST instructions are similar, the source and destination directions change:

When acting as the system bus the pins have strong' 11.0 STATUS AND CONTROL
drivers to both Vee and Vss. These drivers are used REGISTERS
whenever data is being output on the system bus and
are not used when data is being output by Ports 3 and There are two I/O Control registers, lOCO and lOCI.
4. Only the pins and input buffers ate shared between lOCO controls Timer 2 and the HSI lines. lOCI con-
the bus and the ports, The ports use different output trols some pin functions, interrupt sources and 2 HSO
buffers which are configured as open-drain, and require pins.
pullup resistors. (open-drain is the MOS version of
open-collector.) the port pins and their system, bus Whenever input Hnes are switched between two sourc-
functions are shown in Table 5. es, or enabled, it is possible to generate transitions on
these 'lines. This could cause problems with respect to
. Table 5. P3,4/ADO-15 Pins edge sensitive lines such as the HSI lines, Interrupt line,
System Bus .' and Timer 2 control lines.
Port Pin
Function
P3.0 ADO 11.1 110 Control Register 0 (lOCO)
P3.1 AD1
P3.2 AD2 lOCO is located at 0015H. The four HSllines can be
P3.3 AD3
enabled or disabled to the HSI unit by setting or clear-
ing bits in lOCO. Timer 2 functions including clock and
P3.4 AD4
reset sources are also determined by lOCO. The control
P3.5 AD5 bit locations are shown in Figure 38. lOCO is for initial-
P3.6 AD6 ization only.
,
P3.7 AD7
P4.0 ADS
P4.1 AD9
HSI.O INPUT ENABLE / DISABLE
P4.2 AD10
P4.3 AD11 TIMER 2 RESET EACH WRITE
P4.4 AD12 HSI.l INPUT ENABLE / DISABLE
P4.5 AD13 TIMER 2 EXTERNAL RESET ENABLE / DISABLE
P4.6 AD14
HSI.2 INPUT ENABLE / DISABLE
P4.7 AD15
TIMER 2 RESET SOURCE HSI.O / T2RST
HSI.3 INPUT ENABl.E / DISABLE
TIMER 2 CLOCK SOURCE HSI.l / T2CLK
270250-37

Figure 38. I/O Control Register 0 (lOCO)

1-44
 MCS®·96 8X9X ARCHITECTURAL OVERVIEW

11.2 1/0 Control Register 1 (IOC1)

lOCI is used to select some pin functions and enable or
SOFTWARE TIMER 0 EXPIRED
disable some interrupt sources. Its location is OOI6H.
Port pin P2.5 can be selected to'be the PWM output SOFTWARE TIMER 1 EXPIRED
instead of a standard 'output. The external interrupt SOFTWARE TIMER 2 EXPIRED
source can be selected to be either EXTINT (same pin
as P2.2) or Analog Channel 7 (ACH7, same pin as SOFTWARE TIMER 3 EXPIRED
PO.7). Timer I and Timer 2 overflow interrupts can be TIMER 2 HAS OVERFLOW
individually enabled or disabled. The HSI interrupt can
TIMER 1 HAS OVERFLQW
be selected to activate either when there is I FIFO en-
try or 7. Port pin P2.0 can be selected to be the TXD HSI FIFO IS FULL
output. HSOA and HSO.5 can be enabled or disabled HSI HOLDING REGISTER DATA AVAILABLE
to the HSO unit. More informatiOn on interrupts is
available in Section 4. The positions of the lOCI con- 270250-40
trol bits are shown in Figure 39.
Figure 41. HSIO Status Register 1 (1051)

11.3 1/0 Status Register 0 (IOSO)

11.4 1/0 Status Register 1 (I0S1)
There are two I/O Status registers, 10SO and 10SI.
10SO, located at 0015H, holds the current status of the 10SI is located at 016H. It contains status bits for the
HSO lines and CAM. The status bits of 10SO are timers and the HSl/O. The positions of these bits are
shown in Figure 40. shown in Figure 41.

Whenever the processor reads this register all of the

time-related flags (bits 5 through 0) are cleared. This
applies not only to explicit reads such as:
SELECT PWM !SELECT P2.5
EXTERNAL INTERRUPT ACH7 / EXTINT LDB AL,IOS1
TIMER 1 OVERFLOW INTERRUPT ENABLE / OISABLE
but also to implicit reads such as:
TIMER 2 OVERFLOW INTERRUPT ENABLE / DISABLE
HSO.4 OUTPUT ENAB~E / i5iSABLE JB IOS1.3,somewhere_e1se
SELECT TXD / SELECT P2.0
which jumps to somewhere_else if bit 3 of lOS 1 is set.
HSO.5 OUTPUT ENABLE / OISABLE In most cases this situation can best be handled by hav-
7 HSI INTERRUPT ing a byte in the register filewhich is used to maintain
FIFO FULL / H"'O"'L-D""IN"'G-R"'EG"'I"'ST""E"'"R"c,L""OA'"O--E'"'O an image of lower five bits of the register. Any time a
hardware timer interrupt or a HSO software timer in-
terrupt occurs the byte can be updated: '
'270250-38

Figure 39.110 Control Register 1 (IOC1)

ORB IOSLlmage,tOSl
leaving IOSl_image containing all the flags that were
set before plus all the new flags that were read and
HSO.O CURRENT STATE cleared from lOS 1. Any other routine which needs to
sample the flags can safely check lOS I_image. Note
HSO.l CURRENT STATE
that if these routines need to clear the flags that they
HSO.2 CURRENT STATE have acted on, then the modification of IOSL.:..image
HSO.3 CURRENT STATE
must be done from inside a critical region (see Section
4.4). '
HSO.4 CURRENT STATE
HSO.5 CURRENT STATE

CAM QB HQLDING REGISTER IS FuLL

HSO HOLDING REGISTER IS FULL

270250-39

Figure 40. 1/0 Status Register 0 (1050)

1-45
intJ MCS®-96 8X9X ARCHITECTURAL OVERVIt:W

12.0 WATCHDOG TIMER are within reasonable values. Simply using a software
timer to reset the WDT every 15 milliseconds will not
The WatchDog Timer (WDT) provides a means to re- provide much protection against minor problems.
cover gracefully from a software upset. When the
watchdog is enabled it. will initiate, a hardware reset It is also recommended that unused areas of code be
unless the software clears it every 64K state times. filled with NOPs and periodic jumps to an error routine
or RST (reset chip) instructions. This is particularly
The WDT is implemented as an 8-bit timer with an important in the code around lookup tables, since if
8-bit prescaler. The prescaler is not synchronized, so lookup tables are executed undesired results will occur.
the timer will overflow between 65280 and 65535 state Wherever space allows, each table should be surround-
times after being reset. When the timer overflows it ed by 7 NOPs (the longest 8096 instruction has 7 bytes)
pulls down the RESET pin for at least one state time, and a RST or jump to error routine instruction. Since
resetting the 8X9X and any other devices tied to the RST is a one-byte instruction, the NOPs are not needed
RESET line. If a large capacitor is· connected to the if RSTs are used instead of jumps to an error routine.
line, the pin may take a long time to go low. This will This will help to ensure a speedy recovery should the
effect the length of time the pin is low and the voltage processor have a glitch in the program flow. Since RST
on the pin when it is finished falling. Section 1.4 of the instruction has an opcode of OFFH, pulling the data
Hardware Design chapter contains more information lines high with resistors will cause an RST to be execut-
,about leset hardware connections. ed if unimplemented memory is addressed.

The WDT is enabled the first time it is cleared. Once it

is enabled, it can only be disabled by resetting the 12.2 Disabling The Watchdog
8X9X. The internal bit which controls the watchdog
can typically maintain its state through power glitches The watchdog should be disabled by software not' ini-
as low as VSS and as high as 7.0V for up to one millisec- tializing it. If this is not possible, such as during pro-
ond. gram development, the watchdog can be disabled by
holding the RESET pin at 2.0V to 2.5V. Voltages over.
Enabling and clearing the WDT is done by writing a 2.5V on the pin could quickly damage the device. Even
"OI~H" followed by a "OElH" to the WDT register at at 2.5V, using this technique for other than debugging
location OAH. This double write is used to help prevent purposes is not recommended, as it may effect long
accidental clearing of the timer. term reliability. It is further recommended that any de-
vice used in this way for more than several seconds, not
be used in production versions of products. Section 1.6
12.1 Software Protection Hints of the Hardware Design chapter has more information
on disabling the Watchdog Timer.
Glitches and noise on the PC board can cause software
upsets, typically by changing ejthermemory locations
or the program counter. These. changes can be internal 13.0 RESET
to the chip or be caused by bad data returning to the
chip.
13.1 Reset Signal
There are both hardware and software solutions to
noise problems, but the best solution is good design As with all processors, the 8X9X must be re~et each
practice and a few ounces of prevention. The software time the power is turned on. This is done by holding the
, can be designed so that the watchdog times out if the RESET pin low for at least 2 state times after the power
program dOes not progress properly. The watchdog will supply is within tolerance and the oscillator has stabi-
also time-out if the software error was due to ESD lized. (See Figure 44, TRLPV.)
(Electrostatic Discharge) or other hardware related
problems. This prevents the controller from having a After the RESET pin is brought high, a ten state reset
malfunction for i6nger than 16 milliseconds if a 12 sequence is executed. During this time, the Chip Con-
MHz oscillator is used. figuration Byte (CCB) is read from .location 2018H and
written to the 8X9X ,Chip Configuration Register
When using the WDT to protect software it is desirable (CCR). If the voltage on the EA pin selects the inter-
to reset it from only one place in code. This wiI1lessen nal/external execution mode the CCB is read from in-
the chance that an undesired WDT reset will occur. ternal ROMIEPROM. If the voltage on .the EA pin
The section of code that resets the WDT should moni- selects the external execution only mode 'the CCB is
tor the other code sections for proper operation. This read from external memory.
can be done by checking variables to make sure they

1-46
intef MCS®·96 8X9X ARCHITECTURAL OVERVIEW

The 8X9X can be reset using a capacitor, I-shot, or any Port I and Port 2.6, 2.7 reset to a strong or weak pull-
other method capable of providing a pulse of at least 2 up condition. HSO.4 and HSO.5 reset to a floating con-
state times longer than required for Vee and the oscil- dition as they are disabled by IOCl.4 and IOCI.6.
lator to stabilize. '
Other conditions following a reset are:
For best functionality, it is suggested that the reset pin
be pulled low with an open collector device. In this
way, several reset sources can be wire ORed tdgether. Pin Reset Value
Remember, the RESET pin itself can .be a reset source RD high
when the RST instruction is executed or when the WR/WRL high
Watchdog Timer overflows. Details of hardware sug- ALE/ADV high
gestions for reset can be' found in Section 1.4 of the BHE/WAH high
Hardware Design chapter.
INST low
HSO Lines XXOOOOB
13.2 Reset Status Figure 43. Bus Control Pins Reset Status
The I/O lines and control lines of the 8X9X will' be in It is important to note that the Stack Pointer and Inter-
their reset state within 10 XT ALl periods after reset is rupt Pending Register are undefined, and need to be
low, with Vee and the oscillator stabilized (See Figure initialized in software. The Interrupts are disabled by
44, TRLPV), Prior to that time, the status of the I/O both the mask register and PSW.9 after a reset.
lines is indeterminate. After the 10 state time reset se-
quence, the Special Function Registers will be set as
follows: 13.3 Reset Sync Mode
Register Reset Value The RESET line can be used to start the 8X9X at an
exact state time to provide for synchronization of test
Port 1 XXXXXXXXB equipment and multiple chip systems. RESET is active
. Port 2 XXOXXXX1B low. To synchronize devices, RESET is brought high
Port 3 11111111B on the rising edge of XT AL I. Complete details on syn-
Port 4 11111111B chronizing devices can be found in Section 1.5 of the
PWMControl OOH Hardware Design chapter.
Serial Port (Transmit) undefined
Serial Port (Receive) undefined It is very possible that devices which start in sync may
Baud Rate Register undefined not stay that way. The best example of this would be
Serial Port Control XXXXOXXXB when a "jump on I/O bit" is being used to hold the
Serial Port Status XOOXXXXXB processor in a loop. If the line changes during the time
A/DCommand undefined it is being tested, one processor may see it as a one,
AID Result undefined while the other sees it as a zero. The result is that one
Interrupt Pending undefined processor will do an extra loop, thus putting it several
Interrupt Mask OOOOOOOOB states out of sync with the other.
Timer 1 OOOOH
Timer 2 OOOOH
Watchdog Timer OOOOH
HSI Mode XXXXXXXXB
HSI Status undefined
10SO OOOOOOOOB
IOS1 OOOOOOOOB
lOCO XOXOXOXOB
IOC1 XOXOXXX1B
HSI FIFO empty
HSOCAM empty
HSOSFR OOOOOOB
PSW OOOOH
Stack Pointer undefined
Program Counter 2080H
Figure 42. Register Reset Status

1-47
infef MCS®·96 8X9)( ARCHITECTURAL OVERVIEW'

- r-- Power Supply Rise Time

~5.5VDe

t-:":c4.5 VDe
Vee f--

XTAL
- f-- Start Time from Pow~r Supply Rise ·to. External Output Low

411flllill 111I1111111111111111111111111111I1I111111I1I111111111111111111111111111111111111111

r--
RESET
-I f..- External to Internal

-
Release Time

HSO.0-HSO.3,
P2.0, P2.5
10 STATE TIMES
PORT 3 8c 4
WITH· PULLUPS \ADDRESSe ADDRESS \
201BH ,CCB 20BOH
r--- FIRST BUS FETCH CYCLE PROGRAM
TRLPV = 10 XTAL CYCLES
START
External RESET Low to
Port Valid Time RESET FUNCTION REGISTERS
\
TOTAL 8X9XJF RESET TIME

270250-43

Figure 44. TRLPV

1-48
MCS® ..96 8X9X Hardware 2
Design Information and
Data Sheets
 November 1990

8X9X HARDWARE DESIGN .

INFORMATION

Order Number: 270246-004 .

2-1
 8X9X HARDWARE DESIGN INFORMATION
CONTENTS PAGE CONTENTS PAGE
OVERVIEW ..................' ............ 2·3 7.S BUSWIDTH Pin Usage· ............ 2·27
1.0 REQUIRED HARDWARE 7.6 Address Decoding ................ 2·27
CONNECTIONS ................•...... 2~3 7.7110 Port Reconstruction ...... : ... 2·30
1.1 Power Supply Information .......... 2·3.
8.0 NOISE PROTECTION. TIPS ......... 2·30
1.2 Other Needed Connections ..•..... 2·3
9.0 PACKA~ING ........................ 2·30
1.3 Oscillator Information ......... ; .... 2;3
1.4 Reset Information .......... " ....... 2·5 10.0 USING THE EPROM ....... : ....... 2·32
1.5 Sync Mode ........................ 2·8 10.1 Power·Up and Power·Down ..... ?·32
1.6 Disabling the Watchdog Timer ..... 2·8 10.2 Reserved Locations ............. 2·33
1.7 Power Down Circuitry .............. 2·9 10.3 Auto Configuration Byte
Programming Mode ................ 2·35
2.0 DRIVE AND INTERFACE
LEVELS ......................... ·...... 2·9 10.4 Auto Programming Mode ........ 2·36

2.1 Quasi·Bidirectional Ports ........... 2·9 10.4.1 Auto Programming Mode

and the CCB/PCCB ............. 2·36
2.2 Quasi·Bidirectional Hardware
Connections ........................ 2·9 10.4.2 Gang Programming with the
Auto Programming Mode ........ 2·36
2.3 Input Only Ports .................. 2·11
10.5 Slave Programming Mode ....... 2·38
2.4 Open Drain Ports ................. 2·11
10.5.1 Slave Programming
2.5 HSO Pins, Control Outputs and Commands ..................... 2·38
Bus Pins' ...... ; .................... 2·12
10.5.2 Gang Programming with the
3.0 ANALOG INPUTS .............. : .... 2·12 Slave Programmin-g Mod~ ....... 2·39.
3.1 AID Overview ........ ; ............ 2·13 10.5.3 Slave Programming Mode
and the CCB/PCCB ............. 2·39
3.2 AID Interface Suggestions ........ 2·13
10.6 Run· Ti~e Programming ......... 2·39
3.3 Analog References ............... 2·14
10.6.1 Run·Time Programming and
3.4 The AID Transfer Function ....... 2·14 the CCB/PCCB ................. 2·40
3.5A1DGlossary?fTerms ........... 2·19 10.7 ROM/EPROM Program Lock .... 2"41
4.0 ANALOG OUTPUTS ................ 2·20 10.7.1 Lock Features .............. 2·41
5.0 1/0 TIMINGS ........................ 2·21 10.7.2 ROM Dump Mode .......... 2·42
5.1 HSO Outputs ..................... 2·21 10.8 Modified Quick·Pulse
5.2 HSllnputSampling ............... 2·21 Programming™ Algorithm ......... '. 2·42

5.3 Standard 110 Port Pins ............ 2·22 10.9 Signature Word .................. 2·42
10.10 Erasing the EPROM ............ 2·42 .
6.0 SERIAL PORT TIMINGS ............ 2·22
6.1 Mode 0 ........................... 2·22 11.0 QUICK REFERENCE .............. 2·42
6.2 Mode 1 Timings ............... ; .. 2·22 11.1 Pin Description .................. 2·42
6.3 Mode 2 and 3 Timings ............ 2·23 11.2 Pin List .......................... 2·45
11.3 Packaging ....................... 2·46
7.0 BUS TIMING AND MEMORY
INTERFACE .......................... 2·23 11.4 Package Diagrams .............. 2·47
7. t Bus Functionality .......... '.' ..... 2·23 11.5 Memory Map .................... 2·49
7.2 Timing Specifications ............. 2-24 11.6 Instruction Summary .............. 2·50
7.3 READY Li~e Usage ............... 2·24 . 11.7 Opcode and State Time Listing .. 2·52
7A 1NST Line Usage ..... c .••••••.••• 2·27 ; 11.8 SFR Summary ................... 2.55
2·2/
 8X9X HARDWARE DESIGN INFORMATION
OVERVIEW lems due"tQ vQltage drQPs acrQSS the wiring. There
shQuld be no. measurable vQltage difference between
This chapter Qf the manual is devoted to' the hardware VSSI and VSS2. The two. VSS pins and the ANGND pin
eng1neer. All Qf the infQrmatiQn yQU need to' CQnnect must all be nQminally at 0 volts. The maximum current
the CQrrect pin to' the CQrrect el\.ternal circllit is provid- drain Qf 'the 8X9X is arQund 180 rnA, with all lines
ed. Many Qf the special functiQn pins have different unlQaded.
characteristics which are under sQftware cQntrQI.
TherefQre, it is necessary to' define the system cQmplete- When the analQg CQnverter is being used, clean, stable
ly befQre the hardware is wired-up .. PQwer must be prQvided to. the analQg sectiQn Qf the
chip to. assure highest accuracy. To. achieve this, it may
Frequently within this chapter a specificatiQn fQr a cur- be desirable to. separate the analQg PQwer supply frQm
rent, vQltage, Qr time period is referred to.; the values the digital PQwer supply. The VREF pin supplies the
prQvided are to. be used as an apprQximatiQn Qnly. The digital circuitry in the A/D CQnverter and prQvides the
el\.act specificatiQn can be fQund in the latest data sheet ~ -VQlt reference to' the analQg PQrtion of the converter.
fQr the particular device and temperature range that is VREF and ANGND must be cQnnected even if the
being used. A/D cOllverter is not used. More infQrmation Qn the
analQg PQWer supply is in SectiQn 3.1. '
This chapter is written abQut 8X9XBH, 8X9XJF, and
8X98 devices. These devices are generically referred to.
as the 8X9X. All infQrmatiQn in this chapter refers to. 1.2 Other Needed Connections
the 8X9XBH, the 8X9XJF, and the 8X98 unless Qther-
wise nQted. Several Qther. cQnnectiQns are needed to' cQnfigure the
8X9X,. In nQrmal QperatiQn the fQllQwing pins shQuld
be connected to' the indicated PQwer supply.
1.0 REQUIRED HARDWARE
CONNECTIONS Pin Power Supply
NMI Vee
AlthQugh the 8X9X is a single-chip microcQntrQller, it
still requires several ~xternal cQnnectiQns to. make it
EA Vee (to allow internal execution)
wQrk. PQwer must be applied, a clQck SQurce pwvided, Vss (to forCe external execution)
and SQme fQrm Qf reset circuit~y must be present. We
will lQQk at each Qf these areas Qf circuitry separately. AlthQugh the EA pin has an internal pulldQwn, it is
Figure 6 shQWS the CQnnectiQns that are needed fQr a best to' tie this pin to' the desired level. This will prevent
single-chip system. induced nQise from disturbing the system. Raising EA
to' + 12.75 VQlts will place an 8X9X in a special Qperat-
ing mQde desigped fQr programming and program
1.1 Power Supply Information memQry verification (see SectiQn 10). .

PQwer fQr the 8X9X flQWS thrQugh six pins. They are:
three PQsitive vQltage pins-Vee (digital), V REF (PQrt 1.3 Oscillator Information
o digital I/O and A/D PQwer), VPD(PQWer dQwn
mQde), and three CQmmQn returns-two. Vss pins and The 8X9X requires a clock SQurce to Qperate. This
Qne ANGND pin. All six Qf these pins must be CQn- clQck is provided to' the chip through the XTALI in-
nected Qn the 8X9X fQr nQrmal' QperatiQn. The Vee put. The (requency Qf QperatiQn is from 6 MHz to'
pin, VREFPin and VPD pinshQuld be tied to. 5 VQlts. 12 MHz.
The two. Vss pins and the ANGND pin must be
grounded. When the analQg to. digital CQnverter is being The Qn-chip circuitry for the 8X9X Qscillator is a single
used it may be desirable to. CQnne.ct the VREF pin to. a stage linear inverter as shQwn in Figure 1. It is intended
separate'PQwer supply, Qr at least a separate PQwer sup- fQr use as a crystal-contrQlled, positive reactance Qscil-
ply line. lator with external connectiQns as shown in Figure 2.
-In this application, the crystal is being Qperated in its
The three CQmmo.n return pins shQt/ld b~ cQnnected at fundamental response mode as an inductive reac-
the chip with as shQrt a lead as PQssible to. aVQid prob-

2-3
inter 8X9X HARDWARE DESIGN INFORMATION

tance in parallel resonance with shunt capacitartce e~­ should be specified for parallel resonance with 25 pF
ternal to the crystal. load capacitance, if C1 and C2 are 30 pF.

The crystal specifications and capacitance values (Cl An external oscillator may encounter as much as a
and C2 in Figure 2) are not critical. Thirty picofarads 100 pF load at XTALl when it starts up. This is due to
can be used in these positions at any frequency with interaction between the amplifier and its feedback ca-
good quality crystals. For 0.5% frequency accuracy, pacitance,'Once the external signal meets the VIL and
the crystal frequency can be specified at series reso- VIH specifications the capacitance will not exceed
nance or for parallel resonance with any load capaci- 20pF.
tance. (In other words, for that degree of frequency I

accuracy, the load capacitance simply doesn't matter.) A more in-depth,discussion of crystal specifications and
For 0.05% frequency accuracy the crystal frequency the selection of vall,les for C1 and C2 can be found in
the Intel Application Note, AP-155, "Oscillators for
Microcontrollers."
TO DIVIDER CIRCUITRY
Vee
To drive the 8X9X with an external clock'source, apply
the external clock signal to XTALl and let XTAL2
float. An example of this circuit is shown in Figure 3.
The required voltage levels on XTALI are specified in
the data sheet. The signal on XTALl must be clean
with good solid levels.'

It is important that the minimum high and low times

are met to avoid having the XTALl pin in the tran-
sition range for long periods of time. The longer the
signal is in the transition region, the higher the proba-
bility that an external noise glitch could be seen by the
clock generator circuitry. Noise glitches on the 8X9X
internal clock lines will cause unreliable operation. '

The cIock generator provides a 3 phase clock output

270246-1
from the XTAL1 pin input. Figure 4 shows the wave-
forms of the major internal timing signals.
Figure 1. 8X9X Oscillator Circuit

DIVIDER CIRCUITRy
DIVIDER CIRCUITRY
Vee
Vee Q3 !

Q1

Vee
XTAL1 XTAL2
XTAL2 5K ,FLOAT

270246-3
30 pf .,.. 30pf
270246-2 Figure 3. External Clock Drive
Figure 2. Crystal Oscillator Circuit

2-4
 8X9X HARDWARE DESIGN INFORMATION

XTAL1
lONE STATE TIME
PHASE A
(CLKOUT)

PHASE B

PHASE C

a.c
PHASE
I LJ LJ 270246-4

Figure 4. Internal Timings

1.4 Resetlnformation ternal ROM/EPROM. If the voltage on the EA pin

selects the external execution only mode the CCB is
In order for the 8X9X to function properly it must be read from external memory. See Figure 5, and 5A.
reset. This is done by holding the RESET pin low for at
least 10 XTALl cycles after the power supply is within There are several ways to provide a good reset to an
tolerance and the oscillator has stabilized. 8X9X, the simplest being just to connect a capacitor
from the reset pin to ground. The capacitor should be
After the RESET pin is brought high, a ten state reset on the order of 2 microfarads for every millisecond of
sequence is executed. During this time, the Chip Con- reset time required. This method will only work if the
figuration Byte (CCB) is read from location 2018H and rise time of Vee is fast. and the total reset time is less
written to the 8X9X Chip Configuration Register than around 50 milliseconds. It also may not work if
(CCR). If the voltage on the EA pin selects the inter- the RESET pin is to be used to reset other devices on
nal/external execution mode the CCB is read from in- the board. An 8X9X with the minimum required con-
nections is shown in Figure 6.

ALE/ ADV
\ .w S~r-- _ pt?'''m
U U
ADBUS----------------~

CHIP THE BYTE(8-BIT BUS).

CONFIGURATION OR WORD( 16-BIT BUS),
BYTE AT 2080H
270246-5

Figure 5. Reset Sequence

2-5
inter 8X9XHARDWARE DESIGN INFORMATION

- _ Power Supply Rise Time

,..-- S.SVoc
_4.SVOC
Vcc -

XTAL
- I+- Start Time from Power Supply Rise to External Output Low

I11111111 11111111111111111111111111111111111111111111111111111111III111111111111111111111111
,

-
RESET -I ~
"
External to Internal
Release Time
r---I--
HSO.O-HSO.3,
P2.0, P2.S
10 STATE TIMES
PORT 3 8c <I
WITH PULLUPS IADDRESS~ ADDRESS I
2018H CCB 2080H
- FIRST BUS FETCH CYCLE PROGRAM
TRLPV = 10 XTAL CYCLES START
External RESET Low to
Port Valid TIme RESET FUNCTION REGISTERS
I

TOTAL 8X9X RESET TIME

270246-44

Figure 5A. TRLPV

Vpp , FLOAT Vpp FLOAT

VpD VpD
VREF VREF
48 LEAD 68 LEAD
DEVICES EA DEVICES EA
Vee Vee

270246-7 270246-40
NOTES:
1. These capacitors are needed only if A to D is used.
2. VREF & ANGND may be connected to the same traces as the digital power supply if the A to D is not used.

Figure 6. Minimum Hardware Connections

2·6
inter 8X9X HARDWARE DESIGN INFORMATION

The 8X9X RESET pin can be used to allow other chips A capacitor directly connected to RESET cannot be
on the board to make use of the Watchdog Timer or the used to reset the device if the pin is to be used as an
RST instruction. When this is done the reset hardware output. If a large capacitor is used, the pin will pull-
should be a one-shot with an open collector output. The down more slowly than normal. It will continue to pull-
reset pulse going to the other devices may have to be down until the 8X9X is reset. It could fall so slowly
buffered and lengthened with a one-shot, since the that it never goes below the internal switch point of the
RESET low duration is only one state. If this is done, it reset signal (I to 1.5 volts), a voltage which may be
is possible that the 8X9X will be reset and.start running above the guaranteed switch point of external circuitry
before the other devices· on the board' are out of reset. connected to the pin. A circuit example is shown in
The software must account for this possible problem. Figure 7.

8X9X
OTHER
CIRCUITRY

(1)
lOOK

'/. 74SL06
OR

r1.o)J.r '/2 7406

270246-8
NOTE: ,
1. The diode will provide a faster cycle time repetitive power-on-resets.

Figure 7. Multiple Chip Reset Circuit

2-7
inter 8X9X HARDWARE DESIGN INFORMATION

1.5 Sync Mode resetting the Watchdog Timer in software will not clear
the flip-flop which keeps the RESETpulldown on.
If RESET is brought high at the same time as or just
after the rising edge 'Of XTALl, the device will start The pulldown is capable of sinking on the order of 30
executing the 10 state time RST instruction exactly 6'/. milliamps if it is held at 2.0 volts. This amount of cur-
XTALl cycles later. This feature can be used to syn- rent may cause some long term reliability problems due
chronize several MCS-96 devices. A diagram of a typi- to IDealized chip. heating. For this reason, devices that
cal connection is shown in Figure 8. It should be noted will be used .in production should never have had the
that devices that start in sync may not stay,that way, WatchdDg Timer over-ridden for more than a second or
due to propagation delays which may cause the syn- two.
chronized devices to receive signals at slightly different
times. Whenever the reset pin is being pulled high while the
pulldown is on, it should be through a resistor that will
limit the voltage on RESET to 2.5 volts and the current
1.6 Disabling the Watchdog Timer through the pin to 40 milliamps.

The Watchdqg Timer will pull the RESET pin low If it is necessary to disable the Watchdog Timer for
when it overflows. See Figure 9. If the pin is being more than a brief test the software solution of never
externally held above the low going threshold, the pull- initiating the timer should be used. See Section 14 in
down transistor will remain 'On indefinitely. This means the Architecture Chapter.
that 'Once the watchdog overflows, the device must be
reset or RESET must be held high indefinitely. Just

270246-9 .

Figure 8. Reset Sync Mode

RESET
8X9X CHIP
PIN
RESET

WATCHDOG TIMER
OVERFLOW
RESET INSTR\JCTION
(OFFH)
270246-10

Figure 9. Reset Logic

2-8
 8X9X HARDWARE DESIGN INFORMATION

1.7 Power Down Circuitry the depletion pullup holds the line at a logical '1' state.
The low-impedance pullup is used to shorten the rise
Battery backup can be provided on the 8X9X with a 1 time of the pin, and has current source capability on the
rnA current drain at 5 volts. This mode will hold loca- order of 100 times that of the depletion pullup.
tions OFOH through OFFH valid as long as the power to
the VPD pin remains on. The required timings to put While the depletion mode pullup is the only device on,
the device into power-down and an overview of this the pin may be used as an input with a leakage of
mode are given in Section 2.3 in the 8X9X Archite,cture around 100 microamps from 0.45 volts to Vee. It is
Chapter. ideal for use with TTL or CMOS chips and may even
be used directly with switches. However if the switch
A 'key' can be written into power-down RAM while option is used, certain precautions should be taken. It is
the device is running. This key can be checked on reset important to note that any time the pin is read, the
to determine if it is a start-up from power-down or a value returned will be the value on the pin, not the
complete cold start. In this way the validity of the pow- value placed in the control register. This could cause
er-down RAM can be verified. The length of this key logical operations made directly on these pins to inda-
determines the probability that this procedure will vertently write a 0 to pins being used as inputs. In order
work, however, there is always a statistical chance that to perform logical operations on a port where a quasi-
the RAM will power up with a replica of the key. bidirectional pin is an input, it is necessary to guarantee
that the bit associated with the input pin is always a one
Under most circumstances, the power-fail indicator when writing to the port.
which is used to initiate a power-down condition must
come from the unfiltered, unregulated section of the
power supply. The power supply must have sufficient 2.2 Quasi-Bidirectional Hardware
storage capacity to operate the 8X9X until it has com- Connections'
pleted its reset operation.
When using the quasi-bidirectional ports as inputs tied
to switches, series resistors may be needed if the ports
2.0 DRIVE AND INTERFACE LEVELS will be written to internally after the device is initial-
ized. The amount of current sourced to ground from
There are five types of I/O lines on the 8X9X. Of these, each pin is tyically 20 rnA or more. Therefore, if all 8
two are inputs and three are outputs. All of the pins of pins are tied to ground, 160 rnA will be sourced. This is
the same type have the same current/voltage character- equivalent to instantaneously doubling the power used
istics. Some of the control input pins, such as XTALI by the,chip and may cause noise in some applications.
and RESE'f, may have slightly different characteristics.
These pins are discussed in 'Section 1. This potential problem can be solved in hardware or
software. In software, never write a zero to a pin being
While discussing the characteristics of the I/O pins used as an input.
some approximate current or voltage specifications will
be given. The exact specifications are available in the In hardware, a 1K resistor in series with each pin will
lastest version of the data sheet that corresponds to the limit current to' a reasonable value without impeding
device being used. the ability to override the high impedance pull up. If all
8 pins are tied together a 120n resistor would be rea-
sonable. The problem is not' quite as severe when the
2.1 Quasi-Bidirectional Ports inputs are tied to electronic devices instead of switches,
as most external pUlldowns will not hold 20 rnA to 0.0
The Quasi-Bidirectional pins of Port 1, Port 2.6, and volts. .
Port 2.7 have both input and output port cpnfigura-
tions. They have three distinct states; low impedance Writing to a QuaSi-Bidirectional Port with electronic
current sink (Q2), low impedance current source (QI), devices attached to the pins requires special attention.
and high impedance current source (Q3). As a low im- Consider using P1.0 as an input and trying to toggle
pedance current sink, the pin has specification of sink- P 1.1 as an output:
ing up to around 0.5 rnA, while staying below 0.45
volts. The'pin is placed in this condition by writing a '0' ORB IOPORTl. #OOOOOOOlB ~ Set Pl.O
to the SFR (Special Function Register) controlling the for input
pin. XORB IOPORTl. #OOOOOOlOB Complement
PI'; 1
Examine Figure 10. When the SFR contains a '0' and a
'1' is written to it, QI (a low impedance MOSFET pull-
up} is turned on for ,one state, then it is turned off and

2-9
 8X9X HARDWARE DESIGN INFORMATION

PORT 1
PORT 2.6. PORT 2.7
PORT
PIN

READ
PORT

270246-11

LOW IMPEDANCE HIGH IMPEDANCE LOW IMPEDANCE

PULLUP PULLUP PULLDOWN
Q1 Q3 Q2

-160 /loA SOmA

C!-~
TYPICAL

j -90, /loA j 30mA

-30 p.A 10mA

4V OV OV 2V 4V
VOH VOH Vol
270246-12

NOTE:
These graphs show typical pin capabilities. they are not guaranteed specifications

Figure 10. Quasi-Bidirectional Port

The first instruction will work as expected but two The first situation can best be solved by the external
problems can qccur when the second instruction exe- driver design. A series resistor between the port pin and
cutes. The first is that even though PI. I is being driven the base of the transistor often works by bringing up
high by ,the 8X9X it is possible that it is being held low the voltage present on the port pin. The second case can
externally. This typically happens when the port pin is be taken care of in the software fairly easily:
used to drive the base of an NPN transistor which in
turn drives whatever there is in the outside world which LDB AL, IOPORTI
needs to be toggled. The base of the transistor will XORB AL, #OlOB
clamp the port pin to the transistor's Vbe above ORB AL, #OOIB
ground, typically O.7V. The 8X9X will input this va,lue STB AL, IOPOR~l
as a zero even if a one has b,een written to the port pin.
When this happens the XORB instruction will always A software solution to both cases is to keep a byte in
write a one to the port pin's SFR and the pin will not RAM as an image.of the data to be output to fhe port;
togglt;. any time the software,wants to modify the data on the
port it can then modify the image byte and copy jt to
The seCond proplem, which is related to the first, is that the port.
if Pl.O happens to be driven to a zero when Port I is
read by the XORB instruction, then the XORB will , If a switch is used on a long line connected to a quasi,
write a zero, to Pl.O and it will no longer be useable as bidirectional pin, a' pullup resistor is recolWllended to
an input. reduce the possibility 6f noise glitphes and to decrease

2-10
 8X9X HARDWARE DESIGN INFORMATION

the rise time of the line. On extremely long lines that 2.4 Open Drain Ports
are handling slow signals, a capacitor may be helpful in
addition to the resistor to reduce noise. Ports 3 and 4 on the 8X9X are open drain ports. There
is no pullup when these pins are used as 110 ports.
These pins have different characteristics when used as
2.3 Input Only Ports bus pins as described in the next section. A diagram of
the output buffers connected to Ports 3 and 4. and ·the
The high impedance input pins on the 8X9X have an bus pins is shown in Figure 11.
input leakage of.a few microa~ps and are predominant-
ly capacitive loads on the order of 10 pF. When Ports 3 and 4 are to be used as inputs, or as bus
pins, they must first be written with a '1'. This will put
Port 0 pins are special in that they may individually be the ports in a high impedance mode. When they are
used as digital inputs, or as analog inputs. A Port 0 pin used as outputs, a pullup resistor must be used external-
being used as a digital input acts as the high impedance ly. The sink. capability of these pins is on the order of
input ports just described. However, Port 0 pins being 0.8 milliamps so the total pullup current to the pin
used as analog inputs are required to provide current to must be less than this. A 15K pullup resistor will
the internal sample capacitor when a conversion begins. source a maximum of 0.33 milliamps, so it would be a
This means that the input characteristics of a pin will reasonable value to choose if no other circuits with
change if a conversion is being done on that pin. See pullups were connected to the pin.
Section 3. In either case, if Port 0 is to be used as analog
or digital 110, it will be necessary to provide power to
this port through the VREF pin.

vcc
DATA
IN

BUS OUTPUT
ENABLE

PORT DATA

270246-19

.-P-
BUSPULLUP BUS PULLDOWN PORT PUL.LDOWN
BUS BUS, P1, P2 BUS, P1, P2
25mA

VOH
e e'
.9 30 mA

10mA

OV 2V
VOL
4V
.9 15 mA

5mA

OV 2V
VOL
4V

270246-20

NOTE:
These graphs show typical, pin capabilities, they are not guaranteed specifications.

Figure 11. Bus and Port 3 and 4 Pins.

2-11
 8X9X' HARDWARE Da::SIGN'INFORMATION

2.5 HSO Pins, ControlOutputs and generated with either the chip's PWM output or HSO
Bus Pins unit. This se<;:,tion describes the analog input sugges-
tions. See Section 4 for analog output.
The control outputs and HSO pins have output buffers
with the same output characteristics as those of the bus The 8X9X's Integrated AID converter includes an
pins. Included in the category of control outputs are: eight channel analog multiplexer, sample-and-hold cir-
TXD, RXD (in Mode 0), PWM, CLKOUT, ALE, cuit and lO-bit analog to digital converter (Figure 12).
BHE, RD, and WR. The bus pins have 3 states: output The 8X9X can therefore select one of eight analog in-
high, output low, and high impedance input. As a high puts to convert, sample-and-hold the input voltage and
output, the pins are specified to source around 200 /-tA convert the voltage into a digital value. Each conver-
to 2.4 volts, but the pins can source on the order of ten sion takes 22 microseconds, including the time required
times that value in order to provide the fast rise times. Jor the sample-hold (with XTALI "" 12 MHz). The
When, used as a low output, the pins can sink around method of conversion is successive approximation.
2 mA at 0.45 volts, and considerably more as the volt-
age increases., When in the high impedance state, the Section 3.5 contains the definitions of numerous terms
pin acts as a capacitive load with a few microamps of used in connection with the AID converter.
leakage. Figure II shows the internal configuration of a
bus pin.

3.0 ANALOG INPUTS

The on-chip AID converter of the 8X9X can be used to
digitize analog inputs while analog outputs can be

VREF

START
CONVERSION
270246-13

Figure 12. AID Converter Block Diagram

2-12
inter 8X9X HARDWARE DESIGN INFORMATION

3.1 AID Overview The total number of state times required is 88 for a
IO-bit conversion. Attempting to short-cycle the IO-bit
The conversion process is initiated by the execution of conversion process by reading AID results before the
RSO command OFR, or by writing a one to the GO Bit done bit is set is not recommended.
in the AID Control Register. Either activity causes a
start conversion signal to be sent to the AID converter
control logic. If an HSO command was used, the con- 3.2 AID Interface Suggestions
version process will begin when Timer 1 increments.
This aids applications attempting to approach spectral- ThCl. external interface circuitry to an analog input is
ly pure sampling, since successive samples spaced by highly dependent upon the application, and can impact
equal Timer 1 delays will occur with a variance of converter characteristics. In the external circuit's de·
about t 50 ns (assuming a stable clock on XT AL 1). sign, important factors such as input pin leakage, sam-
However, conversions initiated by writing a one to the ple capacitor size and mllitiplexer series resistance from
ADCON register GO Bit will start within three state the input pin to the sample capacitor must be consid-
times after the instruction has completed execution re- ered.
sulting in a variance of about 0.75 J.l.s (XTALl =
12 MHz). For the.-8X9X, these factors are idealized in Figure 13.
The external input circuit must be able to charge a sam-
Once the AID unit receives a start conversion signal, ple capacitor (Cs) through a series resistance (RI) to an
there is a one state time delay before sampling (sample accurate voltage given a D.C. leakage (IL). On the
delay) while the successive approximation register is re- 8X9X, Cs is around 2 pF, RI is around 5 KO and IL is
set and the proper multiplexer channel is selected. Af- specified as 3 J.l.A maximum. In determining the neces-
ter the sample delay/the multiplexer output is connect- sary source impedance Rs, the value of VBIAS is not
ed to the sample capacitor and remains connected for important.
four'state times (sample time). After this four state time
"sample window" closes, the input to the sample capac-

~t-yI>
itor is disconnected from the multiplexer so that chang-
es on the input pin will not alter the stored charge while
the conversion is in progress. The comparator is then
auto-zeroed and the conversion begins. The sample de-
lay and sample time uncertainties are each approxi-
..:..
mately t 50 ns, independent of clock speed.
VB1A:L
To perform the actual analog-to-digital conversion the
8X9X implements a successive approximation algo- 270246-14
rithm. The converter hardware consists of a 256-resis-
Figure '13. Idealized AID Sampling Circuitry
tor ladder, a comparator, coupling capacitors 'and a
IO-bit successive approximation register (SAR) with
External circuits with source impedances of 1 KO or
'Iogic that guides the process. The resistor ladder pro·
less will be able to maintain an input voltage within a
vides 20 mV steps (VREF = 5.12V), while capacitive
tolerance of about to.61 LSB (1.0 KO x 3.0 J.l.A
coupling is used'to create 5 mV steps within the 20 mV
= 3.0 mY) given the D.C. leakage. Source impedances
ladder voltages. Therefore, 1024 internal reference volt-
above 2 KO can result in an external error of at least
ages are available for comparison against the analog
input to generate a IO-bit conversion result. one LSB due to the voltage drop caused by the 1 J.l.A
leakage. In addition, source impedances above 25 KO
may degrade converter accuracy as a result of the inter-
A successive approximation conversion is performed by
n~1 sample capacitor not being fully charged during the
comparing a sequence of reference voltages, to the ana-
log input, in a binary search for the reference voltage 1 J.l.s (12 MHz clock) sample window.
that most closely matches the input. The '/. full scale
If large source impedances degrade converter accuracy
reference voltage is the first tested. This corresponds to
because the sample capacitor is not charged during the
a 10·bit result where the most significant bit is zero,
sample time, an external capacitor connected to the pin
and all other bits are ones (011 U 111.11 b). If the ana·
log input was less than the test vbltage, bit 10 of the will compensate for this degradation. Since the sample
capacitor is 2 pF, a 0.005 J.l.F capacitor will charge the
SAR is left a zero, and a new test voltage of '/. full scale
(00 11.1111.11 b) is tried. If this test voltage was lower sample capacitor to an accurate input voltage of to.S
LSB(2048 X 2 pF). An external capacitor does not
than the analog input, bit 9 of the SAR is set and bit 8
is cleared for the next test (0101.1111.11b). This binary compensate for the voltage drop across the source re-
sistance, but charges the sample capacitor fully during
search continues until 10 tests have occurred, at which
time the valid IO-bit conversion result resides in the the sample time.
SAR where it can be read by software.

2-13
 8X9X HARDWARE DESIGN INFORMATION

Placing an external capacitor on each analog input will Note that if only ratiometric information is desired,
also reduce the sensitivity to noise, as the capacitor VREF can be connected to V. In addition, VREF and
combines with series resistance in the external circuit to ANGND must be connected even if the AID converter
form a low-pass filter. In practice, one should include a is not being used. Remember that Port 0 receives its
small series resistance prior to the external capacitor on power from the VREF and ANGND pins even when it
the analog input pin and choos~ the largest capacitor is used as digital 1/0.
value practical, given the frequency of the signal being
converted. This provides -a low-pass filter on the input,
while the resistor will also limit input current during 3.4 The AID Transfer Function
over-voltage conditions.
The conversion result is a lO-bit ratiometric representa-
Figure 14 shows a simple analog interface circuit based tion of the input voltage, so the numerical value ob-
upon the discussion above. The circuit in the figure also tained from the conversion will be:
provides limited protection against over-voltage condi-
tions on the analog input. Should the input voltage in- INT [1023 x (VIN - ANGND)/(VREF - ANGND)].
appropriately drop significantly below ground, diode
D2 will forward bias at about 0.8 VDC. Since the speci- This produces a stair-stepped transfer function when
fication of the pin has an absolute maximum low volt- the output code is plotted versus input voltage (see Fig-
age of -0.3V, this will leave about 0.5V across the ure 15). The resulting digital" codes can be taken as
270n transistor, or about ~ mA of current. This should simple ratiometric information, or they can be used to
limit the current to a safe amount. However, before any provide information abou't absolute voltages or relative
circuit is used in an actual application, it should be thor- voltage changes on the inputs. The more demanding
oughly analyzed for applicability to the specific problem the application is on the AID converter, the more im-
at hand. portant it is to fully understand the converter's opera-
tion. For simple applications, knowing the absolute er-
ror of the converter is sufficient. However, closing a
VREF servo-loop with analog inputs ll,ecessitates a detailed
understanding of an AID converter's operation and er-
01 rors.
FROM USER CIRCUIT ::>--....---'WIr-_.rlI ANALOG
INPUT PIN
The errors inherent in an analog-to-4igital conversion
02 process are many: quantizing error; zero offset; full-
o scale error; differential non-linearity; and non-linearity.
These are "transfer function" errors related to the AID
ANGNO converter. In addition, cOhverter temperature drift,
270246-15 . Vee rejection, sample-hold feedthrough, multiplexer
off-isolation, channel-to-channel matching and random
Figur, 14. Suggested AID Input Circuit
noise should be considered,. Foitunately, one "Absolute
!?rror" specification is available which describes the
sum total of all deviations between the actual conver-
3.3 Analog. References sion process and an ideal converter. However, the vari-
Reference supply levels strongly influence the absolute ous sub-componenfs of error are important in many
accuracy of the conversion. For this reason, it is recom- applications. These error components are described in
mended that the ANGND pin be tied to the two Vss Section 3.5 and in the text below where ideal and actual
pins as close to the chip as possible with minimum trace I
converters are compared.
length.' Bypass capacitors should also be used between
VREF and ANGND. ANGND should be within about An unavoidable error simply results from the conver-
a tenth of a volt Vss. VREF should be well regulated sion of a continuous voltage to an integer digital repre-
and used only for the AID converter. The VREF supply sentation. This error is called quantizing error, and is
can be between 4.5V and 5.5V and needs to be able to always ± 0.5 LSB. Quantizing err~r is the only error
source around 5 mAo Figure 6 shows all of these cdn- seen in a perfect AID converter, and is obviously pres-
nections. ent in actual converters. Figure 15 sho~s the transfer
function for an ideal 3-bit AID converter (i.e. the Ideal
Characteristic).

2-14
inter 8X9X HARDWARE DESIGN INFORMATION

Note that in Figure 15 the Ideal Characteristic possess- only. A converter is monotonic if every subsequent
es unique qualities: it's first code transition occurs when code change represents an input voltage change in the
the input voltage is 0.5 LSB; it's full-scale code tran- same direction.
sition occurs when the input voltage equals the full-
scale reference minus 1.5 LSB; and it's code widths are Differential Non-Linearity and Non-Linearity are
all exactly one LSB. These qualities result in a digitiza- quantified by measuring the Terminal Based Linearity
tion without offset, full-scale or linearity errors. In oth- Errors. A Terminal Based Characteristic results when
er words, a perfect conversion. an Actual Characteristic is shifted and rotated to elimi-
nate zero offset and full-scale error (see Figure 17). The
Figure 16 shows an Actual Characteristic of a hypo- Terminal Based Characteristic is similar to the Actual
thetical 3-bit converter, which is not perfect. When the . Characteristic that would be seen ifzero offset and full-
Ideal Characteristic is overlaid with the imperfect char- . scale error were externally trimmed away. In practice,
acteristic, the actual converter is seen to exhibit errors this is done by using input circuits which include gain
in the location of the first and final code transitions and and offset trimming. In addition, VREF on the 8X9X
code widths. The deviation of the first code transition could also be closely regulated and trimmed within the
from ideal is called "zero offset", and the deviation of specified range to affect full-scale error.
the final code transition from ideal is "full-scale error".
The deviation of the code widths from ideal causes two Other factors that affect a real AID Converter system
types of errors. Differential Non-Linearity and Non- include sensitivity to temperature, failure to completely
Linearity. Differential Non-Linearity is a local linearity reject all unwanted signals, multiplexer channel dissim-
error measurement, whereas Non-Linearity is an over- ilarities and random noise. Fortunately these effects are
all linearity error measure. small.

Differential Non-Linearity is the degree to which actual Temperature sensitivities are described by the rate at
code widths differ from the ideal one LSB width. Dif- which typical specifications change with a change in
ferential Non-Linearity gives the user a measure of how temperature.
much the input voltage may have changed in order to
produce a one count change in the conversion result. Undesired signals come from three main sources. First,
Non-Linearity is the worst case deviation of code tran- noise on Vee-Vee Rejection. Second" input signal
sitions from the corresponding code transitions of the changes on the channel being converted after the sam-
Ideal . Characteristic. Non-Linearity describes how ple window has closed-Feedthrough. Third, signals
much Differential Non-Linearities COUld add up to pro- applied to channels not selected by the multiplexer-
duce an overall maximum departure from a linear char- Off-Isolation.
acteristic. If the Differential Non-Linearity errors are
too large, it is possible for an AID converter to miss Finally, multiplexer on-channel resistances differ slight-
codes or exhibit non-monotonicity. Neither behavior is ly from one channel to the next causing Channel-to-
desireable in a closed-loop system. A converter has no Channel Matching errors, and random noise in general '
missed codes if there exists for each output code a results in Repeatability errors,
unique input voltage range that produces that code

2-15
 --
71

FINAL CODE TRANSITION OCCURS

WHEN THE APPLIED VOLTAGE IS
I It
EQUAL TO (Vref - 1 1/2 (LSB».

6
1 I
5-1 II 0)
)(
CO
)(
'TI :z:
US' ACTUAL CHARACTERISTIC OF >
...
C AN IDEAL A/D CONVERTER :D
...
CD
4
C
~
!"
.... >
Q.
CD
a THE VOLTAGE CHANGE
:D
m
!!!. BETWEEN ADJACENT CODE C
~ l>
.... TRANSITIONS (THE "CODE m
0)
c 3 =
WIDTH") IS 1 LSB,
en
0 is
..
:::T
III
Z
Z
-...
III
n "TI
0

-
CD
:D
iii" 2 s:
('j' >
~
0Z

1~ I
FIRST CODE TRANSITION OCCURS
WHEN THE APPLIED VOLTAGE IS
EQUAL TO 1/2 LSB,

0 1
1/2 2 3 4 5 6 61/2 7 B

INPUT VOLTAGE (LSBs)

270246-16
 7

- --1 ER~
fULL SCALE ERROR I l
6
I CHARACTERISTIC
IDEAL I

5 ABSOLUTE ERROR ~
~ CIt
!!
><
CD
'g
... ~ ~ CHARACTERISTIC
ACTUAL I ><
:::t
CD
-"
:a-
!» :D
C
» 4
~
c: Q
~
:D
!!!.
III m
::s C
~ a. ~-

m
...... a::CD en
!!!. is
z
9 Z
...
III
."

-...
III
()
CD
in
o:D
!!:
!:!:
() - ~
III
S
z

- ~ ZERO OFFSET I

1/2 2 3 4 5

INPUT VOLTAGE (LSBs)

270246-17
 7
IDEAL FULL-SCALE CODE
TRANSITION
ACTUAL
(
FULL-SCALE CODE
TRANSITION
6

ACTUAL
CHARACTERISTIC C»
5 ><
.., co
><
6c r '" -J TERMINAL BASED :z:
i1
CHARACTERISTIC
»lJ
.....
:"I C
- 4
~ ~
35" Q lJ
I\) \I) "'
o
m
.:.. Di
0) \I) !!!
3
io .C)
z
:T NON-LINEARITY z
...
\I)'
\I). --~
g. :u-
,CD 2 3:-
i0" ~
(5
:z
IDEAL CODE WIDTH

IDEAL FIRST TRANSITION

oV
1/2 .2 3 4 5 6 61/2 7 8

INPUT VOLTAGE (LSBs) 270246-18

 8X9X HARDWARE DESIGN INFORMATION

3.5 AID Glossary of Terms D.C. INPUT LEAKAGE-Leakage current to ground

from an analog input pin.
Figures 15,16 and 17 display many of these terms.
DIFFERENTIAL NON-LINEARITY-The differ-
ABSOLUTE ERROR---':The maximum difference be- ence between the ideal and actual code widths of the
tween corresponding actual and ideal code transitions. terminal based charaCteristic of a converter.
Absolute Error accounts for all deviations of an actual
converter from an ideal converter. FEEDTHROUGH-Attenuation of a voltage applied
on the selected channel of the AID converter after the
ACfUAL CHARACfERISTlC-The characteristic of sample window closes.
an actual converter. The characteristic of a given con-
verter may vary over temperature, supply voltage, and FULL SCALE ERROR-The difference between the
frequency conditions. An Actual Characteristic rarely expected and actual input voltage corresPonding to the
has ideal first and last transition locations or ideal code full scale code transition.
widths. It may even vary over multiple conversion un-
der the same conditions. IDEAL CHARACTERISTlC-'-A characteristic with
its first code transition at VIN = 0.5 LSB, its last code
BREAK-BEFORE-MAKE-The property of a multi- transition at VIN = (VREF - 1.5 LSB) and all code
plexer which guarantees that a previously selected widths equal to one LSB.
channel will be deselected before a new channel isse-
lected. (e.g. the converter will not short inputs INPUT RESISTANCE-The effective series resistance
together.) from the analog input pin to the sample capacitor.

CHANNEL-TO-CHANNEL MATCHING-The dif- LSB-LEAST SIGNIFICANT BIT: The voltage value

ference between corresponding code transitions of actu- corresponding to the full scaie voltage'divideC! 'by 2n,
al characteristics taken from different channels under where n is the number of bits of resolution of the con-
the same temperature, voltage and frequency condi- verter. For a lO-bit converter with a reference voltage
tions. of 5.12 volts, one LSB is 5.0 mV. Note 'that ihis is
different than digital LSBs, since an uncertainty of two
CHARACfERISTlC-A graph of input voltage ver- LSB, when referring to an AID converter, equals
sus the resultant output code for an AID converter. It 10 mY. (This has been confused with an uncertainty of
describes the transfer function of the AID converter. two digital bits, which would mean four counts, or
20 mV.)
CODE-The digital value output by the converter.
MONOTONIC-The property of successive approxi-
CODE CENTER-The voltage corresponding to the mation converters which guarantees that increasing in-
midpoint between two adjacent code transitions. put voltages produce adjacent codes of increasing value,
and that decreasing input voltages produce adjacent
CODE TRANSITION-The point at which the con- codes of decreasing value.
verter changes from an output code of Q, to a code of
Q+ 1. The input voltage corresponding to a code tran- NO MISSED CODES-For each and every output
sition is defined to be that voltage which is equally like- code, there exists a unique input voltage range which
ly to produce either of two adjacent codes. produces that code only.

CODE WIDTH-The voltage corresponding to the NON-LINEARITY -The maximum deviation of code
difference between two adjacent code transitions. transitions of the terminal based characteristic from the
corresponding code transitions of the ideal characteris-
CROSSTALK-See "Off-Isolation". tics.

2-19
 8X9X HARDWARE DESIGN INFORMATION

OFF.~SOLATlON-':Attenuation of a voltage applied TERMINAL BASED CHARACTERISTIC-An Ac-

on /l deselected channel of the AID converter. (Also tual Characteristic which as been rotated and translat-
referred to as Crosstalk.) ed to .remove zero offset and full-scale error.

REPEATABILITY-The difference between corre- VCC REJECTION-Attenuation of noise on the Vee

sponding code transitions from different actual charac- line to the AID converter.
teristics takim from the same converter on the same
channel at the same temperature, voltage and frequency ZERO OFFSET-The difference between the expected
conditions. and actual input voltage corresponding to the first code
transition.
RESOLUTION-The number of input voltage levels
that the converter cap unambiguously disting~ish 'be-
tween. Also d¢fines the number of useful bits of infor- 4.0 ANALOG OUTPUTS
mation which the converter can return.
Analog outputs can be generated by two methods, ei-
SAMPLE DELAY-The delay from receiving the start ther by using the PWM output or the HSO. Either
conversion signal .to when the sample window opens. device will generate a rectangular pulse train that varies
in duty cycle and/ (for the HSO only) period. If a
SAMPLE DELAY UNCERTAINTY-The variation smooth analog signal is desired as an output, the rec-
in the Sample Delay. tangular waveform must be filtered.

SAMPLE tIME-The time that the sample window is In most cases this filtering is best done after the signal
open. is buffered to make it swing from 0 to 5 volts since both
of the outputs are guaranteed only to TTL levels. A
S~PLE TIME UNCERTAINty-The variation in block diagram of the type of circuit needed is shown in
tlte sample time: Figure 18. By proper selection of components, account-
ing for temperature and power supply drift, a highly
SAMPLE WINDOW-Begins when the sample capac- accurate 8-bit D,to A converter can be made using ei-
itor is attached to a selected channel and ends when the ther the HSO or the PWM output. Figure 19 shows two
sample capaCitor is disconnected from the selected typical circuits. If the HSO is used the accuracy could
channel. be theoretically extended to 16-bits, however the tem-
perature and noise related problems wouid be extreme-
SUCCESSIVE APPROXIMATION-An AID con- ly hard to handle.
version method which uses a binary search to arrive at
the best digital representation of an analog input. When driving some circuits it may be desirable to use
unfiltered Pulse Width Modulation. This is particularly
TEMPERATURE COEFFICIENTS-Change in the true for motor drive circuits. The PWM output can be
stat~ variable per degree centigrade temperature used to generate these waveforms if a fixed period on
change. Temperature coefficients are added to the typi- the order of 64 J.ts is acceptable. If this .is not the case
cal values of a specification to see the effect of tempera- then the HSO unit can be used. The HSO can generate
ture drift. a variable waveform with a duty cycle variable in up to
65536 steps and a period of up to 131 milliseconds.
Both of these outputs produce TTL levels.

BUFFER
8X9X TO MAKE
FILTER

HSO
OR
PWM
OUTPUT
SWING
RAIL
TO
RAIL
(PASSIVE
OR
ACTIVE)

(OPTIONAL)
POWER
AMP

(OPTIONAL) - ANALOG
OUTPUT

270246-21

Figure 18. D/A Buffer Block Diagram

. 2-20
inter 8X9X HARDWARE DESIGN INFORMATION

Vcc

* 1/2 VQ3001P
6

270' 5.1~
PWM----~VV~---- __ .-____~~__--~.-----ANALOG
8
OUT

270246-22
'This resistor limits rise time to. reduce
spikes & high frequency noise.

8X9X
HSO R HIGH ANALOG
,OR ~---I ~~----~~----~r-------~ IMPEDANCE OUTPUT
PWM AMP
. CD4049

Rand C are chosen for best 270246-23

filtering at the user's frequency

Figure 19. Buffer Circuits for 01 A

5.0 1/0 TIMINGS during Phase B every eight state times. From an exter;
nal perspective the' HSO pin should change just prior to
The lIO pins on the 8X9X are sampled and changed at the rising edge of CLKOUT arid be stable by its falliI'lg
specific times within ll-n instruction cycle. The changes . edge. Information from the HSO can be latched on the
occur relative to the internal phases sjJ.own in Figure 4. CLKOUT falling edge. Internal events can occur any-
Note that the delayrrom XTALI to the internal clocks time during the 8 state time window.
range from about 30 ns to lOP ns over process and
temperature. Signals generated by internal phases are Timer 2 is synchronized to increment no faster than
further delayed by 5 ns to is ns. The timings shown in Timer I, so there will always be'at least one increment-
this section are idealized; no propagation delay factors ing of Timer I, while Timer 2 is at a specific value.
have been taken into account. Designing a system that
depends on an I/O pin to change within a window of
less than SO ns using the information in this section is 5.2 HSI Input Sampling.
not recommended.
The HSI pins are sampled internaUy once each state
time. Any value on these pins must remain stable for at
5,,1 HSO Outputs least 1 full state time to guarantee that it is recognized.
The actual sample occurs at the end of Phase A, which,
Changes in the HSO lines are synchronized to Timer 1. . due to propagation delay, ,is just after the rising edge of
All of the external HSO lines due to change at a certain CLKOUT. Therefore, 'if information is to be synchro-
value of a timer will change just pior to the increment- nized to the HSI it should be latched-in on CLKOUT
ing of Timer 1. This corresponds to an internal change

2-21
intJ 8XQX,HARDWARE DESIGN INFORMATION

falling. The time restriction applies even if t\le divide by the rest of the 8X9X so that information can be passed
eight mode is being used. If two events occur on the back and forth.
same pin within the same 8 state time wil).dow, only one
of the events will be recorded. If the events occur on The baud rate generator is clocked by either XTALI or
different pins they will always be 'reco~ded, regardless T2CLK. Because T2CLK needs to be synchronized to
of the time difference. The 8 state time window, (Le. the the XTALl signal its speed must be limited to '/'6 that
amount of time during which Timer 1 remains, con- of XTAL I. The serial port will not function during the
stant), is stable to within about 20, ns. The window time between the consecutive writes to the baud rate
starts roughly around the rising edge of CLKOUT, register. Section 11.4 of the 8X9X Architecture chapter
however this timing is very approximate due to the discusses programming the baud rate generator.
amount of internal circuitry involved.

6.1 Mode 0
5.3 Standard I/O Port Pins
Mode 0 is the shift register mode. The TXD pin sends
Port 0 is different from the other digital ports in that it out a clock train, while the RXD pin transmits or re-
is actually part of the A/D converter. The port is sam- ceives the data. Figure 20 shows the waveforms and
pled once every state time, however, sampling is not timing. Note that the port starts functioning when a '1'
synchronized to Timer 1. If this port is used, the input is written to the REN (Receiver Enable) bit in the serial
signal on the pin must be stable one state time before port control register. If REN is already high, clearing
the reading of the SFR. the RI flag will start a reception.

Port 1 and Port 2 have quasi-bidirectional I/O pins. In this mode the serial port can be used to expand the
When used as inputs the data on these pins must be I/O capability of the 8X9X by simply adding shift reg-
stable one state time prior to reading the SFR. This isters. A schematic of a typical circuit is shown in Fig-
timing is also valid for the input-only pins of Port 2 and ure 21. This circuit inverts the data coming in, so it
is similar to the HSI in that the sample occurs just after must be reinverted in software. The enable and latch
the rising edge of CLKOUT. When used as outputs, the connections to the shift registers can be driven by de-
quasi-bidirectional pins will change state shortly after coders, rather than directly from the low speed I/O
CLKOUT falls. If the change was from '0' to a '1' the ports, if the software and hardware are properly de-
low impedance pullup will remain on for one state time signed.' ,
after the change. '

Ports 3 and 4 are addressed as off-chip memory- 6.2 Mode 1 Timings

mapped I/O. The port pins will change state shortly
after the rising edge ofCLKOUT. When these pins are Mode 1 operation of the serial port makes use of lO-bit
used as Ports 3 and 4 they are open drains, their struc- data packages, a start bit, 8 data bits and a stop bit. The
ture is different when they, are used as part of the bus. transmit and receive functions are controlled by sepa-
See Section 10.4 of the 8X9X Architecture chapter. Ad- rate shift clocks. The transmit shift clock starts when
ditional information on port reconstruction is available the baud rate generator is initialized, the receive shift
in Section 7.7 of this chapter. clock is reset when a 'I to 0' transition (start bit) is
received. The transmit clock may therefore not be in
sync with the receive clock, although they will both be
6.0 SERIAL PORT TIMINGS at the same frequency. '

The serial port on the 8X9X was'designed to be com- The TI (Transmit Interrupt) and RI (Receive Inter-
patiblewith the 8051 serial port. Since the 8051 uses a rupt) flags are set to indicate when operations are com-
divide by 2 clock and the 8i\9X uses,a divide by 3, the plete. TI is set when the last data bit of the message has
serial port on the 8X9X had to be provided with its been sent, not when the stop bit is sent. If an, attempt to
own clock circuit to maximize its compatibility with send another byte is made before the stop bit is sent the
the 8051 at high baud rates. This means that the serial port will hold off transmission until the stop bit is com-
port itself does not krlow about state times. There is plete. RI is set when 8 data bits are received, not when
circuitry whiCh is synchronized to the serial port and to the stop bit is received. Note that when the serial port
status register is read both TI and RI are cleared.

2-22
inter 8X9X HARDWARE DESIGN INFORMATION

TXD

RXD(OUTj DO D1 D2 D3 04 05 De D7

'DO D1 D2 D3 '04 os De D7
AXD(INI

EXPANDED:

XTAL1~~

TXD ~~;---.

AXD(OUT) - - - - - ( DO c: D1 ~
DO 01
AXD(INI -t:::J----!~
270246-24

Figure 20. Serial Port Timings in Mode 0

CLOCK INHIBIT

---=------jpx.x
15K
DATA
>O-t"-------1 RXD

'--__t--__...,.......:C.:;cLO:..:C.:.;,K, TXD
INPUTS ..

OUTPUTS

ENABLE
1:>-----1 PX.X

270246-25

Figure 21. Mode 0 Serial Port Example

Caution should be used when using the serial port to 7.0 BUS TIMING AND MEMORY
connect more than two devices in half-duplex, (i.e. one INTERFACE
wire for transmit and receive). If the receiving proces-
sor does not wait for one bit time after .Rris set before
starting to transmit, the stop bit on the link could be 7.1 Bus Functionality
squashed. This could cause a problem,Jor other devices
listening on the link.. . The 8X9X has a multiplexed (address/data) bus which
can be dynamically configured to have an 8-bit or 16-
bit data width. There are control lines to demultiplex
6.3 Mode 2 and 3 Timings the bus (ALE or ADV), indicate reads (RD), indicate
writes (WRL and WRH, or WR with BHE and ADO),
Modes 2 and 3 operate in a manner similar to that of and a signal to indicate accesses that are for an instruc-
Mode I, The only difference is that the data is now tion fetch (INST). Section 3.5 of the 8X9X Architec-
made up of 9 bits, so II-bit packages are transmitted ture chapter contains an overview of the bus operation.
and received. This means that TI and RI will be set on
the 9th data bit rather than the 8th. The 9th bit can be
used for parity or multiple processor communications
(see Section 11 of the 8X9X Architecture chapter).

2-23
 8X9X HARDWAREDESIG,N INFORMATION

7.2 Timing Specifications number of inserted wait states is equal to the limit set in
the Chip Configutatidn Register (see Section 2 of the
Figure 22 shows the timing of the bus signals and data MCS-96 Architecture chapter). There is a maximum'
lines. Please refer to the latest data sheet for the exact time that the READY line can be held low without
device you are using to ensure that your system is de- risking a processor malfunction due to dynamic nodes
signed to the proper specifications. The major timing that have not been refreshed during the wait states.
specifications are described in Figure 23. This time is shown ~s TYLYH in the data sheet.

In most cases the READY line is brought low after the'

7.3 READY Line Usage address is decoded and it is determined that a wait state
is needed, It is very likely that some addresses, such as
When the processor has to address a memory location those addressing memory mapped peripherals, would
that cannot respond within the standard specifications, need wait states, and others would not. The READY
it is necessary to use the READY line to generate wait line must be stable within the TLLYV specification af-
states. When the READY line is held low, the proces- ter ALE falls or the processor could lock-up. There is
sor waits in a loop for the line to come high or until the

XTAL1

CLOCKOUT

READY
-- ...,--------.-
,
----------_.-
,
'----------

BHE,INST 1-_ _,-_....,~__ V_AL_I_D_____:-_-f ... ________ ____ ••

4TAVLL ·1 ,",,1.---TwLWH~
AD8-15 -~(~lL)____~::::::::::::::~VA~L~ID~::::::::::::~~~~-~-~-~-~-~-~-~-~'~-= ~.~.~.-
'---_ .... _--_.....
270246-26

.NOTES:
1. 8-bit bus only.
2. 8-bit or 16-bit bus and write strobe mode selected.
3. When ADV selected.
4. 8-bit or 16-bit bus and no write strobe mode selected.

Figure 22. Bus Signal Timings

2-24
 8X9X HARDWARE DESIGN INFORMATION

no requirement as to when READY may go high, as If a wait state is inserted, READY is internally latched
Ions- as the maximum READY low time (TYLYH) is on the next rising edge of Phase A. If a 1 is found the
not violated. To ensure that only one wait state is in- bus cycle resumes with the net impact being the inser-
serted it is necessary to provide external circuitry which tiQn of one wait state. If a 0 is seen, a second wait state
brings READY high TLLYH after the falling edge of is inserted. '
ALE!ADV, or program the Chip Configuration Regis-
ter to select a Ready Control limit of one. The READY pin is again latched on the next rising
edge of CLOCKOUT if two wait states were inserted.
Internally, the chip latches READY on the first falling If the chip Sees a I, the bus cycle is resumed with the
edge of Phase A after ALE/ADV falls. Phase A is buff- result being an insertion of two wait states. If another 0
ered and brought out externally as CLOCKOUT, so is seen, a third wait state is inserted in the bus cycle and
CLOCKOUT is a delayed Phase A., If a i 'is seen, the the READY pin is again latched on the following rising
, bus cycle proceeds uninterrupted with no wait state in- edge of CLOCKOUT. If internal Ready Control is not
sertions. If a 0 is seen, one wait state (3 Tosc) is insert- used, the READY line must at this point be a I to
ed. - ensure proper operation. -

Tosc-Oscillator Period, one cycle time on XTALI.

Timings the Memory System Must TLLGV-ALE/ADV low to BUSWIDTH valid:
Meet Maximum time after ALE/ADV is low until BU- -
SWIDTH must be valid. If this time is exceeded the
TLLYH-ALE/ADV low to READY high: Maxi- part could malfunction necessitating a chip reset.
, mum time after ALE/ADV falls until READY is Nominally less than 1 Tosc,
brought high to ensure no more wait states. If this
time is <;xceeded unexpected wait states may reSult. TLLGX-BUSWIDTH hold after ALE/ADV low:
Nominally I Tosc + 3 Tosc X number of wait states Minimum time that BUSWIDTH must be valid at'tCr
desired. - ALE/ADV is low Nominally 1 TOse.

TLLYV-ALE/ADV low to READY low: Maxi- TRLDV-READ low to DATA valid: Maximum
mum time after ALE/ADV falls until READY'must time that the memory has to output data after READ
be valid. If this time is exceeded the device could mal- goes low. Nominally, a maximum of 3 Tosc periods.
function necessitating a chip reset. Nominally '2 TOsc
periods. TRHD~READ high to DATA float: Time after
READ is high until the memory must float the bus.
TCLYX":'READY hold after CLOCKOUT low: The memory signal can be removed as soon as READ
Minimu~ time that the value on the READY pin is not low, and must be removed within the speci~ed
must be valid after CLOCKOUT falls. The minimum maximum time from when READ is high. Nominally
hold time is always zero nanoseconds. a maximum of I Tosc period.

TYLYH-READY low to READY high: Maximum TRHDX-DATA hold after READ goes high: Milti-
time the part can be in the not-ready state. If it is mum time that memory must hold input DATA valid
exceeded, the 8X9X dynamic nodes which hold the after RD is high., The hold time minimum is always
current instruction may 'forget' how to finish the in- zero nanqseconds.
struction. '
TRLAZ-READ low to ADDRESS float: This is the
TAVDV-ADDRESS valid to DATA valid: Maxi- bus control specifying the time from an active-low
mum time that the memory has to output valid data READ signal until the 8X9X ADDRESS drivers for
after the 8X9X outputs a valid address. Nominally, a the cy~le are off the bus. This is specified in order fdr
maximum of 5 Tosc periods. data to be returned from the memory system without
bus contention. TypicallY,this is 0 ns for no bus,con-
TAVGV-ADDRESS valid to BUSWIDTH valid: tention, However, up to 10 ns is acceptable in sys-
Maximum time after ADDRESS becomes valid until tems.
BUSWIDTH must be valid. Nominally less than 2
Tosc periods. - '
Figure 23. Timing Specification Explanations

2-25
intJ 8X9X HARDWARE DESIGN INFORMATION

Timings the 8096 Will Provide that proper memory decoding takes place before it is
output enabled. Nominally 2 Tosc periods.
T0HCH-XTALl high to CLOCKOUT high: Delay
from the rising edge of Xl'ALl to the resultant rising TRLRH-READ low to READ high: RD pulse
edge on CLOCKOUT. Needed in systems where the width, nominally I Tosc period.
signal driving Xl' ALl is also used as a clock for ex-
ternal devices. Typically 50 to 100 nanoseconds. TRHLH-READ high to ALE/ADV high: Time be-
tween RD going inactive and next ALE/ADV, also
TCHCH-CLKOUT high to CLKOUT high: The used to calculate time between RD inactive and next
period of CLKOUT and the duration of one state ADDRESS, valid. Nominally I Tosc period.
time. Always 3 Tosc average, but individual periods
could vary by a few nanoseconds. TRHBX--':REAQ high to INST, BHE, ADS-IS In-
active: Minimum time that the INST ·and BHE lines
TCHCL-CLKOUT high to CLKOUl' low: Nomi- will be valid after RD goes high. Also the minimum .
nally I Tosc period. time that the upper eight address lines (S-bit bus
mode) will remain valid after RD goes high. Nomi-
TCLLH-CLKOUT low to ALE high: A help in d!l- nally 1 Tosc.
riving other timings. Typically plus or minus 5 ns to
10 ns. TWHBX-WRITE high to INST, BHE, ADS-15
Inactive: Minimum time that the INST and BHE
TCLVL-CLOCKOUT low to ALE/ADV low: A lines will be valid after WR goes high. Also the mini-
help in deriving other timings. Nominally I Tosc. mum time that the upper eight address lines (S-bit bus
mode) will remain valid after WR goes high. Nomi- '
TLLCH-ALE/ADV low to CLKOUT high: Used nally I Tosc.
to derive other timings, nominally 1 Tosc period.
TWLWH-WRITE low to WRITE high: Write
TLHLL-ALE/ADV high to ALE/ADV low: pulse width, nominally 3 Tosc periods.
ALE/ADV high time. Useful in determining ALE/
ADV rising edge to ADDRESS valid time. Nominal- THLHH-WRL, WRH low to WRL, WRH high:
ly 1 Tosc period for ALE and 1 Tosc for ADY: with Write strobe signal pulse width. Nominally 2 Tosc
back-to-back bus cycles. periods.

TA VLL-ADDRESS valid to . ALE/ADY low: TQVHL-,OUTPUT valid to WRL, WRH low: Min-
Length of time ADDRESS is valid before ALE/ADV imum time that OUTPUT data is valid prior to write
falls. Important timing for address latch circuitry. stro1;>es becoming active. Needed for interfacing to
Nominally I Tosc period. memories that read data on the falling edge of write.
Nominally I Tosc.
TLLAX-ALE/ADV low to ADDRESS invalid:
Length of time ADDRESS is valid after ALE/ADV TQVWH-OUTPUT valid to WRITE J!!Ih: Time
falls. Important timing' for address latch circuitry. that the. OUTPUT data is valid before WR is high.
Nominally I Tosc period. Nominally 3 Tosc periods.

TLLRL-ALE/ADV low to READ or WRITE low: TWHQX-WRITE high to OUTPUT not valid:
Length of time after ALE/ADV falls before RD or Time that the OUTPUT data is valid after WR is
WR fall. Could be needed to ensure that proper mem- high. Nominally I Tosc period.
ory decoding takes place before it is.output enabled.
Nominally I Tosc period. TWHLH-WRITE high to ALE/ADV high: Tune
I '. ,
between write high and next ALE/ADV, also used to
TLLHL-ALE/ADV low to WRL, WRH low: Min- calculate the time between WR high and next AD-
imum time after ALE/ADV is low that the write DRESS valid. Nominally 2 Tosc periods.
strobe signals will go low. Could be needed to ensure
Figure 23. Timing Specification Explanations (Continued)
. )

2-26
 8X9X HARDWARE DESIGN INFORMATION

7.41NST Line Usage bus mode, or one 74LS373 for an 8X9X in 8-bit bus
mode. As explained in Section 3.5 of the 8X9X Archi-
The INST (Instruction) line is high during bus cycles tecture chapter, the latched address signals will be re-
that are for an instruction fetch and low for any other ferred to as MAO through MAl5 (Memory Address),
bus cycle. The INST signal (not present on 48-pin ver- and the data lines will be called MOO through MDl5
sions) can be used with a logic analyzer to debug a (Memory Data).
system. In this way it is possible to determine if a fetch
was for instructions or data, making the task of tracing Since the 8X9X can make accesses to memory for ei-.
the program much easier. . ther bytes or words, it is necessary to have a way of
determining the type of access desired when the bus is
l6-bits wide. For write cycles, the signals Write Low
7.5' BUSWIDTH Pin. Usage (WRL) and Write High (WRH) are provided. WRL
will go low during all word writes and during all byte
The BUSWIDTH pin is a control input which' deter- writes to an even location. Similarly, WRH will go low
mines the width of the bus access in progress. . during all word writes and during all byte writes to an
BUSWIDTH is sampled after the rising edge of the first odd loc~tion. During read cycles, an 8X9X in l6-bit
CLOCKOUT after ALE!ADV goes low. If a one is bus mode will always do a word read of an even loca-
seen, the bus access progresses as a l6-bit cycle. If a tion. If only one byte of the word is needed, the chip
zero is seen, the bus access progresses as an 8-bit cycle. discards the byte it does not need.
The BUSWIDTH setup and hold timing requirements
appear in the data sheet. Since 8X9X memory accesses over an 8-bit wide bus
are always bytes, only one write strobe is needed for
The BUSWIDTH pin can be overridden by causing the write cycles. For this purpose the WRL signal was
BUS WIDTH SELECT bit in the Chip Configuration made to go low for all write cycles during 8-bit bus
Register (CCR) to be zero. This will permanently select accesses. When a word operation is requested, the bus
an 8-bit bus width. However, if the BUS WIDTH SE- controller performs two byte-wide bus cycles.
LECT bit in the CCR is a one, the BUSWIDTH pin
determines the bus width. See Section 3.5 of the 8X9X In many cases it may be desirable to have a write signal
Architecture chapter. Since the BUSWIDTH pin is not with a longer pulse width than WRL/WRH. The Write
available on 48-pin or 64-pin devices, the BUS WIDTH (WR) line of the 8X9X is an alternate control signal
SELECT bit in the CCR determines bus width. . that shares a pin with WRL and is only available in
l6-bit bus mode. WR is nominally one Tosc longer
than the WRL/w,RH signals, 'hut goes low for any
write cycle. Therefore it is necessary to decode for the
7.6 Address Decoding type o'1:.vvrite (byte or word) desired.
The multiplexed bus of the 8X9X must be demulti-
plexed before it can be used. This can be done with two The Byte High Enable (BHE) signal and MAO can be
74LS373 transparent latches for an 8X9X in l6-bit used for this purpose. BHE is an alternate control

Vee

BHE--------------~

WRITE HIGH
ALE - - - - I ~~--D

WR - - - - - - - - - - - - -..... -cr""" WRITE LOW

270246-27

Figure 24. Decoding WR and SHE to Generate WriteLow and Write High

2-27
 8X9X HARDWARE DESIGN INFORMATION

signal that shares a pin with WRH. When.BHE is low, External memory systems for the ,8X9X can be set up
the high byte of the 16-bit bus is enabled. When MAO is in many ways. Figures 25 through 28 show block dia-
low,- the lower byte is enabled. When MAO is low and grams of memory systems using an 8-bit bus with a
BHE is low, both bytes are enabled. Figure 24 shows single EPROM, using an 8-bit bus with RAM and
how to use WR, BHE and MAO to decode bus accesses. EPROM, using a 16-bit bus with two external
It's important to note that this decoding inserts a delay EPROMs and using a 16-bit bus in a RAM and ROM
in the write signal which must be considered in a sys- system. (The timings for the systems shown are opti-
tem timing analysis. mized for 10 MHz operation.)

- -
RD OE
ADS-IS HIGH ADDRESS
DATA
8X9X
ADO-7
I ~

74LS
3'73
EPROM
LOW ADDRESS

ADV
""r-~ cs
\
OPTIONAL IF
LATCHED EPROM
IS USED
270246-28

Figure 25. An 8-Bit Bus with EPROM Only

ADIS
CS CS

ADS-IS HIGH ADDRESS

DATA
8X9X EPROM
ADO-7 LOW ADDRESS

ADV
OE OE WE

RD
WR
270246-29

Figure 26. An 8-Bit Bus with EPROM and RAM

2-28
 / '

inter 8X9)( HARDWARE DESIGN INFORMATION

270246-30

Figure 27. A 16-Blt Bus with EPROM Only

BUSWIDTH
AD8-1S

EPROM RAM

ADV r~;;~::JDATA
ADO-7 LOW ADDRESS

8X9X

270246-31

Figure 28. Memory System with Dynamic Bus Width

2-29
 8X9X HAfU)WAflE,DESIGN INFORMATION

.I '

7.7 I/O Port Reconstructlpn It is also recommended that unused areas of code be
filled with NOPs and periodic jumps to an error routine
When a single-chip system' is being designed using 'a or RST (reset chip) instructions. This is particularly
multiple chip system as a prototype, it may be neces- , important in the code around lookup tables, since if
sary to reconstruct 1/0 Ports j and 4 !'ising a: memory- lookup tables ,are executed all sorts of bad things can
mapped 1/0 technique. The circuit shown in Figure 30 ' happen. Wherever space allows, each table should be
provides this function. It can be attached to a 8X9X surrounded by 7 NOPs (the longest 8X9X instruction
system which has the required address decoding and has 7 bytes) and a RST or jump to error routine in-
bus demultiplexing. struotion. This will help to ensure a speedy recovery ,
should the proceSsor have a glitch in the program flow.
The output circuitry is basically just a latch that oper-
ates when IFFEH or IFFFH are placed on the MA Many hardw~e' ,solutions exist for keeping PC board
lines. The inverters surrounding the latch create an noise to a plinimum. Ground planes, gridded ground
open-collector output tQ' emulate the open-drain output and Vee structures, bypass papacitors, transient ab-
found on the 8X9X. The 'reset' line is, used to set the, sorbers and power busses with built·in capacitors can
ports to all l's when the 8X9X is reset. It should be , all be,of great help.,It is mucll easier to design a board
noted that the voltage and current characteristics of the with these' features than to try to retrofit them later.
port will differ from those of the 8X9X, but the basic Proper PC board layout is probably the single most
functionality will be the same. important and, unfortunately, least understood aspect
of project design. Minimizing loop areas and induc-
The input circuitFY is just a bus transceiver that is ad- tance, as well as providing clean grounds are very im-
dressed at lFFEH or IFFFH. If the ports are going to portant. More information on protecting against noise
be used for either input or output, but not both, some of can be found in the Application Note AP-125, "Design-
the circuitry can be eliminated. ing Microcontroller Systems for Noisy Environments".

8.0 NOISE PROTECTION TIPS 9.0 PACKAGING

Designing controllers differs ffom designing-other com- The MCS-96 family o( prcidu~ts is offered in many ver-
puter equipment in the area of noise protection. A mi- sions. They are lj.v~ilable in 48~pin or 68-pin packages,
crocontroller circuit under the h~ of a car, in a pho- with or without on-chip ROM/EPROM and with or
tocopier, CRT terminal, or a 'high speed printer is sub- without an AID converter. A summary of the available
ject to many :~ypes of electrical noise. Noise can get to options is shown'in Figure 31.
the processor-directly through the power supply, or it
can be induced onto the board by electromagnetic The 48-pin versions are a~ailable in ceramic and plastic
fields. It is also possible for, the PC board to find itself 48-pin Dual-In-Line package (DIP). The ceramic ver-
in the path of. electrostatic discharges. Glitches and sions have order numbers with the prefix '~C". The
noise on the PC board can' cause the processor to act plastic versions' have the prefix "P".
unpredictably, usually by changing either the memory
-locations or the program counter. The 68-pin versions are available in a ceramic pin grid
array (PGA), a plastic leaded chip carrier (PLCC) and
There are both hardware and software solutions to a Type B leadless 'chip carrier (LCC). PGA devices
noise problems, but the best solution -is good design , have part numbers with the prefix "0'. PLCC devices
practice and a few ounces of prevention. The 8X9X has have the prefix "N". LCC devices have the_prefix "R".
a Watchdog Timer which will reset the device if it fails
to execute the software properly. The software should SHRINK,-DIP is offered in 64-pin packages with a
be set up to take advantage of this feature. package designator of "U".

2-30
 8X9X HARDWARE DESIGN INFORMATION

MOO-MD7 P3

WRH

74LS
8 8 74LS 8
MD8-MD15 04 P4
(Xl\.'l) 273
CLR

RESET INPUT
ADDR = P3, P4
AD 8
ADO-AD7

ADa-AD15 8

270246-33

Figure 29. 1/0 Port Reconstruction

Factory
User Programmable
Masked CPU
ROM
EPROM OTP
68-Pln 64-Pln 48-Pin 68-Pln 64-Pin 48-Pin 68-Pin 64-Pin 48-Pin 68-Pln 64-Pin 48-Pin
ANALOG 8397BH 8397BH 8395BH 8097BH 8097BH 8095BH 8797BH 8795BH 8797BH 8797JF
8798
8397JF 8397JF 8398 8097JF 8097JF 8098 8798 8797JF 8797BH
NO ANALOG 8396BH 8X9X
Figure 30. HMOS MCS®96 Packaging
o48-Pin devices have four Analog Input pins. o68-Pin devices have all 48- and 64-pin features plus the following:
oFor ROM/OTP /EPROM devices, 8X9XBH and 8X98 = 8 Kbytes, Dynamic Buswidth sizing (8 or 16 bil"bus)
8X9XJF = 16 Kbytes Dedicated System Clock Output (CLKOUT)
o54-Pin devices have all "48-Pin device features plus the following: INST pin for memory expansion
Four additional Analog Input channels Non-Maskable Interrupt for debugging
One additional Quasi-Bidirectional 8 Bit Parallel Port oPackage Designators:
Four additional Port 2 pins with multiplexed features N = PLCC
Timer 2 Clock Source Pin C = Ceramic DIP
Timer 2 Reset pin A = Ceramic Pin Grid Array
Two additional quasi-bidirectional port pins P = Plastic DIP .
R = Ceramic LCC
U = Shrink DIP

2-31
inter 8X9X HARDWARE DESIGN INFORMATION

10.0 USING THE EPROM When an 879X EPROM device is not being erased, the
window must be covered with an opaque label. This
This section refers to the 879XBH,' 8798, and 879XJF prevents functional degradation and data loss from the
devices. These devices are generically referred to as the array.
879X. All information in this section refers to all three
devices unless otherwise noted.
10.1 Power-Up and Power-Down
879XBH and the 8798 contain 8 Kbytes of ultraviolet
Erasable and electrically Programmable Read Only To avoid damaging devices during programming, fol-
Memory (EPROM). The 879XJF contains 16 Kbytes low these rules:
of EPROM. When EA is a TTL high, the EPROM is RULE #l-Vpp must be within IV of Vee while
located at memory locations 2000H through 3FFFfl on Vee is below 4.SV.
the 879XBH and the 8798. It is at locations 2000H RULE #2- Vpp can not be higher than S.OV until
through SFFFH on the 879XJF.
Vee is above 4.SV.
Applying + 12.7SV to EA when the chip is reset places RULE #3- Vpp must not have a low impedance path
the 879X device in the EPROM Programming Mode: to ground when Vee is above 4.SV.
The Programming Mode supports EPROM program- RULE #4--EA must be brought to 12.7SV before
ming and verification. The following is a brief descrip- Vpp is brought to 12.7SV (not needed for
tion of each of the programming modes: run-time programming).
RULE #S-The PMODE and SID pins must be in
The Auto Configuration Byte Programming Mode . their desired state before RESET rises.
programs the Programming Chip Configuration Byte
and the Chip Configuration Byte. RULE #6- All voltages must be within tolerance and
the oscillator stable before RESET rises.
The Auto Programming Mode enables an 879X to RULE # 7- The supplies to Vee, Vpp, EA and
program itself and up to IS other .879X·s. RESET must be well regulated and free
of glitches and spikes.
The Slave Programming Mode provides a standard
interface to program any number of 879X's by a mas- To adhere to these rules you can use the following pow-
ter device such as an EPROM programmer or anoth- er-up and power-down sequences:
er 879X.

The Run-Time Programming Mode allows individu- POWER UP

al EPROM locations to be programmed at run-time
under complete software control. (Run-Time Pro- RESET = OV
gramming is done with EA = 5V.)
Vee = Vpp = EA = SV
Some I/O pins have new functions for programming.
These pins 'determine the programming function, pro- CLOCK on (if using an external clock instead of the
vide programming control signals and slave ID num- internal oscillator)
bers, and pass error information. Figure 32 shows how
the pins are renamed. Figure 33 describes each new pin PALE = PROG = PORn, 4 = VIH(1)
function. PMODE selects the function to be performed
(see Figure 31). SID and PMODE valid

EA == 12.7SV(2)
PMODE Programming Mode
0-4 Reserved Vpp = 12.75V(3)
5 Slave Progr~mming Mode WAIT (wait for supplies and clock to settle)
6 ROM Dump Mode
RESET = 5\1,
7-0BH Reserved
OCH Auto Programming Mode WAIT Tshll (see data sheet)
ODH Program Configuration. Byte BEGIN
OEH-OFH Reserved
Figure 31. Programming Function PMODE Values
 8X9X HARDWARE DESIGN INFORMATION

POWER DOWN NOTES:

1. VIH = logical 'I' (2.4V minimum)
RESET = OV
2. The same power sl!El!ly can be used for EA and
Vpp = 5V Vpp. However, the EA pin must be powered up be-
fore Vpp is powered up. Also, EA should be protect-
EA = 5V ed from noise to prevent damage to EA.
3. Exceeding the maximum limit on Vpp for any
PALE = PROG = SID = PMODE =:PORT3, 4 = amount of time could damage the device permanent-
OV ly. The Vpp source"must be well regulated and free
of glitches and spikes.
Vee = Vpp = EA = OV

CLQCKOFF 10.2 Reserved Locations

Fill all Intel Reserved locations except address 2019H,
when mapped internally or externally, with OFFH to
ensure compatibility with future devices. Fill address
2019H with 20H.

~gg:~~~~ ~~~-----------,
PROGRAIIIIING
VOLTAGE

8797BH

270246-34

Figure 32. Programming Mode Pin Function

2-33
 8X9)( HARDWARE DESIGN INFORMATION

Mode Name Function

General PMODE PROGRAMMING MODE SELECT: Determines the EPROM programming
.. (PO-.4, .5, .6, .7) algorithm that is performed. PMODE is sampled after a chip reset and
should be static while the device is operating.
Auto PACT PROGRAMMING ACTIVE: Used in the Auto-Programming Mode.
Programming (HSO.O) Indicates when programming activity is complete.
Mode PVAL PROGRAM VALID: These signals indicate the success or failure of
(Ports 3 and 4) programming in the Auto Programming Mode and when using this mode
for gang programming. For the Auto Programming Mode this signal is
asserted at Port 3.0. When using this mode for gang programming, all bits
of Port 3 and Port 4 are. asserted to indicate programming validity of the
various slaves. A zero indicates successful programming on PVAL.O. A
zero on PVAL.1 through PVAL.15 indicates a fail. '
SALE SLAVE ALE: Output signal from an 879X in the Auto Programming Mode.
(P2.0) A falling edge on SALE indicates that Ports 3 and 4 contain valid address/
command information for slave 879XBHs that may be attached to the
master.
SPROG SLAVE PROGRAMMING PULSE: Output from an 879X in the Auto
(P2.5) Programming Mode. A falling edge on SPROG indicates that Ports 3 and 4
contain valid data for programming into slave 879XBHs that may be
attached to the master. .
Ports 3 and 4 ADDRESS/COMMAND/DATA BUS: Used by devices in the Auto
Programming Mode to pass command, addresses and data to slaves.
Also used in the Auto Programming Mode as a regular system bus to
access .external memory. Each line should be pulled up to VCC through a
resistor. Also used as PVAL (see above).
Slave SID SLAVE ID NUMBER: Used to assign a pin of Port 3 or 4 to each slave to
Programming (HSI-O, .1, .2, .3) pass programming verification acknowledgement. For example, if gang
Mode programming in the Slave Programming Mode, the slave with SID = 0001
will use Port 3.1 to signal correct or incorrect program verification.
PALE PROGRAMMING ALE INPUT: Accepted by an 879X that is in the Slave
(P2.1) Programming Mode. Indicates that Ports 3 and 4 contain a command/
address.
pROG PROGRAMMING PULSE: Accepted by 879X that is in the Slave
(P2.2) Programming Mode. Used to indicate th'lt Ports 3 and 4 contain the data
to be programmed. A falling edge on PROG signifies data valid and starts
the programming cycle. A rising edge on PROG will halt programming in
the slaves.
PVER PROGRAM VERIFIED: A signal output after a'programming operation by
(P2.0) devices in the Slave Programming Mode. This signal is on Port 2.0 and is
asserted as a logic 1 if the bytes program correctly.
PD~ PROGRAMMING DURATION OVERFLOWED: A signal output by devices
(P2.5) in the Slave Programming Mode. Used to signify that the PROG pulse
applied for a programming operation was I,onger than allowed.
Ports 3 and 4 ADDRESS/COMMAND/DATA BUS: Used to pass commands,
addresses and data to and from slave mode 879X's.
AutoPCCB PVER PROGRAM VERIFIED: A signal output after programming in the Auto
Programming (P2.0) Configuration Byte Programming Mode. The signal is on Port 2.0 and is
Mode. asserted as a logic 1 if the bytes program correctly.
PALE PROGRAMMING ALE INPUT: Used by a device in the Auto Program
(2.1) Configuration Byte Mode to indicate that Port 3 contains the data to be
programmed into the PCCB and CCB.
Figure 33. Programming Mode Pin Definitions
inter 8X9X HARDWARE DESIGN INFORMATION

10.3 Auto Configuration Byte they did not. Programming takes approximately
250 ms. Figure 34 shows a minimum configuration for
Programming Mode Auto Configuration Byte Programming.
The Programming Chip Configuration Byte (PCCB)is
a'non-memory mapped EPROM location. It gets load- Once the CCB and PCCB are programmed, all pro-
ed into the CCR during reset fo~ auto and slave pro- gramming activities and bus operations use the selected
gramming. The Auto Configuration Byte Programming bus width, READY control, bus controls, and READ/
Mode programs the PCCB. WRITE protection until you erase the device. You
must be careful when programming the READ and
The Chip Configuration Byte (CCB) is at location WRITE lock bits in the CCB and PCCB. If you enable
2018H and can be programmed like any other EPROM the,READ and WRITE lock bits in'the CCB or the
location using auto, slave arid run-time programming. PCCB and then reset the device, the array may no long-
However, you can also use the Auto Configuration er be programmed or verified (see Figure 41 in Section
Byte Programming to program the CCB when no other "10.7.1). Therefore, you should program the buswidth,
locations need to be programmed. The CCB' is pro- READY control, and bus controls using the Auto Con-
grammed with the same value as the PCCB. figuration Byte Programming Mode. You should pro-
gram the READ and WRITE lock bits when all pro-
The Auto Configuration Byte Programming Mode is gramming is complete.
entered by following the power-up sequence described
in Section 10.1 with PMODE = ODH, Port 4 = If tb,e PCCB is not programmed, the CCR will be load-
OFFH, and Port 3 = the data to be programmed into ed with OFFFI:I when the device is in the Programming
the PCCB and CCB. When a 0 is placed on PALE, the Mode.
CCB and PCCB are automatically programmed with
the data on Port 3. After programming, PVER is driv- Specific requirements for CCB and PCCB program-
en high if the bytes programmed correctly and low if ming are included in the Auto, Slave, and Run-time
Programming sections.

Vee
BINARY

u '
SWITCH
PO'
PO.S PMOOE = ODH
PO.S
POA P2.2
vpo
r----+-IRESET
vREF 1--....- - - -...
..--~~-INMI SVoe

47 p.F
ANGNO Vee 1+-'---.
Vss l
Vss2 XTALl XTAL2 Pi.l Ho-+-+----+PALE
...........;.;.;r:;.;-....;.;.;:r;;:;.._...1
~PUSH TO
fVPROGRAM

270246-39

NOTES:
1. Tie Port 3 to the value desired to be programmed into CCS, and PCCS.
2. Make all necessary minimum connections for power, ground and clock.

Figure 34. The Auto CCR Programming Mode

2-35
 8X9X HARDWARE DESIGN INFORMATION

10.4 Auto Programming Mode Auto Programming must be done ill 8·bir bus mode. -
For 68L devices you must tie the BUSWIDTH pin to
The Auto Programming Mode 'provides the ability to ground. You do not need to program the/buswidth se-
program the 879X EPROM without using an EPROM lection bit in the PCCB (PCCB.1).For '48L and 64L
programmer. For this mode follow the power-up se- devices there is no BUSWIDTH pin. You must pro-
quence described in Section lO.1 with PMODE = gram PCCB.I using the Auto ,Configuration Byte Pro-
OCH. When RESET rises, the 879XBH and 8798 devic- gramming Mode before programming the array.
es automatically program themselves with the' data
found' at external locations 4000H through 5FFFH. The data in the PCCB takes effect upon reset. If you
The 879XJF programs itself with tile data found at ex- enable either the READ or WRITE lock bits during
ternallocations 4000H through 7FFF. Figure 35 shows Auto Programming but do not reset the device, Auto
a minimum configuration for using an 8K x 8 EPROM , Programming will continue. If you enable either the
to program one 879X in the Auto Programming Mode. READ or WRITE lock bits and then reset the device,
the device will no longer program or verify. You should
The 879X reads a word from external memory, then program these bits when, no more programming will be
the Modified Quick-Pulse Programming™ Algorithm done.
(described later) is used to program the appropriate
EPROM location. Since the erased state of a byte is 10.4.2 GANG PROGRAMMING WITH THE AUTO
OFFH, the Auto Programming Mode will skip loca- PROGRAMMING MODE
tions where,the data to be programmed is OFFH. When
all 8K of the 879XBH and 8798 and all 16K of the An 879X in the Auto Programming Mode can also be
879XJF has been programmed, PACT goes high and used as a programmer for up to 15 other 879XBHs that
the devices outputs a 0 on Port 3.0 (PV AL) if it pro- are configured in the Slave Programming Mode.
grammed correctly and a I if it failed. The 879K acts as the master .. The master programs the
slaves witjl the same data the master is programming
10.4.1. AUTO PROGRAMMING MODE AND THE itself with. The master outputs the necessary slave com-
eeB/peeB mand/data pairs on Ports 3 and 4. It also provides the
Slave ALE (SALE) and Slave PROG (SPROG) signals
In the Auto Programming Mode the CCR is loaded to demultiplex the commands from the data. Figure 36
with the PCCB. The PCCB must correspond to the is a block diagram of a gang programming system using
memory system of the programming setup, including one 879XBH in the Auto Programming Mode. The
the READY and bus control selections. You can pro- Slave Programming Mode is described in the next sec-
gram the PC9B using the Auto c<;mfiguration Byte tion.
Programming Mode (see Section lO.3).

ADDRESS 15

Intel
ADDRESS 8" '15 2764A"2
PORT.

PO'~
po.s PNODE =OCH
PO.S AlE 1--_1--1
po••
+5V

8797BH
lOOK

...........--+--1 RESET

NOTES: ':' 270246-35

'Ports 3 and 4 should have pullups to vee. ,
1. Allow RESET to rise after the voltages to Vee, EA, and Vpp are stable.

Figure 35. The Auto Programming Mode

2-36
intJ 8X9X HARDWARE DESIGN INFORMATION

The master 879X reads a word from the external mem- commands b~ing given to the slaves after each pro-
ory controlled by ALE, RD and. WR. It then drives gramming pulse.
Ports 3 and 4 with a Data Program command using the
appropriate address and alerts the slaves with a falling When programming is complete PACT goes high and
edge on SALE. Next, the data to be programmed is Ports 3 and 4 are driven with all Is if all devices pro-
driven onto Ports 3 and 4 and slave programming be- grammed correctly. Individual bits of Port 3 and 4 will
gins with.a falling edge on SPROG. At the same time, be driven to 0 if the slave with that bit number as an
the master begins to program its own EPROM location SID did not program correctly. The 879X used as the
with the data read in. Intel's Modified 'Quick-Pulse master assigns itself an SID' of O.
Programming™ Algorithm is used, with DataYerify

r
r-----------.,
_1-
I _________ ., I
I I
I
I I
HSLSID = <OFH
i '_ ..I
I

HSLSID=2

HSLSID =I

intel
2764A-2

Vee
1'--------1 C
PO,

PO.4
U
PO.6 PMODE = OCH
PO.5
.
ALE

+5V'
EA 1-----012.75 Voe
8797BH Vpp 1-----012.75 Voe
lOOK
Vpo
VREF
RESET
P2.1
NMI'
BUSWIDTH' P2.2
ANGND
Vee
Vss
Vss
XTAL1 XTAL2

PVAL.O = 0 = PASS

PVAL.l }
,l. =0= FAIL
PVAL.15

270246-36

NOTES: .
'EA and VPP on slaves must be at + 12.75 Vdc. Each slave's PMODE must equal 05H. Ports 3 and 4 should have
pull ups to vee. Minimum configuration connections must also be made for slaves. A 10 MHz clock is recommended for
the slaves.
1..Allow RESET to rise after the voltages to Vee, EA, and VPP are stable.
Figure 36. Gang Programming with the Auto Programming Mode

2-37
inter 8X9X HARDWARE ,DESIGN INFORMATION

10.5 Slave Programming Mode Table 1. Slave Programming

Mode Commands
Any number of 879Xs can be programmed by a master
programmer using the Slave Programming Mode. P4.7, P4.6' Action
0 0 Word Dump
In Slave Programming Mode, the device being' pro- 0 1 pata Verify
grammed uses Port 3, 4 as a commind/data path.
PALE and PROG demultiplex, the commands and
1 .< 0 Data Program Lower 8K
data. PVER, PDO and Ports 3 and 4 pass error infor- 1 1 Data Program Upper 8K
mation to the programmer. There is no 879X depen- (879XJF)
dent limit to the number of devices that can be gang
programmed in the slave mode. DATA PROGRAM COMMAND-After a Data Pro-
gram Command has been sent to the slaves, PROG
It is important to note that the interface to an 879X in must be pulled low to program the data on Ports 3 and
the slave mode is similar to a multiplexed bus. Issuing 4 into the location specified during the command. The .
consecutive PALE pulses without a corresponding falling edge ofPROG indicates data valid and also trig-
PROG pulses will produce unexpected results, as will gers the hardware programming of the word specified.
issuing consecutive PROG pulses without the corre- The slaves will begin programming 48 states after
sponding PALE pulses. PROG falls, and will continue to program the location
until PROG rises.
10.5.1 SLAVE PROGRAMMING COMMANDS After the rising edge of PROG, the slaves automatically
The commands sent to the slaves are 16-bits wide and perform a verification of the address just programmed.
contain two fields. Bits 14 and 15 specify the action The result of this verification is then output on PVER
°
that the slaves are to perform. Bits through 13 specify
the address upon which the action is to take place. On
(Program Verify) and PDO (Program Duration Over-
flowed). Therefore, verification information is available
the 879XJF, P4.6 is both the .least significant bit of the for programming systems that cannot use the Data
"Data Program Upper 8K" command and the most Verify command.
significant bit of tjJ.e address. Commands are sent via
Ports 3 and 4 and are available to cause the slaves to IfPVER and PDO ofa11 slaves are Is after PROG rises
program a word, verify a word, or dump a word (Table then the data program was successful everywhere. If
1). The address part of the command sent to the slaves any slave's PVER is a 0, then the data programmed did
ranges from 2000H to 3FFFH on the 879XBH and the not verify correctly in that device. If any slave's PDO is
8798 lmd from 2000H to 5FFFH on the 879XJF and a 0, then the programming pulse in those devices was
refers to the internal EPROM memory space. The fol- terminated by an internal safety feature rather than the
lowing sections describe each slave programming mode, rising edge of PROG. The safety feature prevents over-
command. programming in the slave mode. Figure 37 shows the
relationship of PALE, PROG, PVER and PDO to the
Command/Data Path on Ports 3 and 4 for the Data
Program Command.

PORTS 3,4 -< ADDRESS/COMMAND ~_----:------

PALE
\ ...._~--I
PROG

PVER VALID 7 \ VALID

PDO VALID / \ VALID

,270,246-37,

Figure 37. Data Program Signalsi" Slave Programming Mode

2-38
 inter 8X9X HARDWARE DESIGN INFORMATION

PALE ~'- _ _ _ --JI

PORTS 3,4-{OATA VERIFY COMMANO) ( VERIFICATION BITS >-
' ' -_ _...J I 270246-38

Figure 38. Data Verify Command Signals

DATA VERIFY COMMAND-When the Data Verify giving each chip being programmed a unique SID. The
Command is sent, the slaves indicate correct or incor- master programmer can then issue a data verify com-
rect verification of the previous Data Program by driv- mand after the data program command. When a verify
ing one bit of Ports 3 and 4. A 1 indiclltes correct verifi- command is seen by the slaves, each will drive one pin
cation, while a 0 indicates incorrect verification. The of Port 3 or 4 with a 1 if the programming verified
SID (Slave ID Number) of each slave determines which correctly or a 0 if programming failed. The SID of each
bit of Ports 3 and 4 is driven. PROG from the program- slave determines which Port 3, 4 bit it is assigned. An
mer governs when the slaves drive the bus. Figure 38 879X in the Auto Programming Mode could be the
shows the relationship of Ports 3 and 4 to PALE and master programmer if 15 or fewer slaves need to be
PROG. programmed (see Gang Programming with the Auto
Programming Mode).
The data verify command is always preceded by a Data
Program Command in a programming system with as 10.5.3 SLAVE PROGRAMMING MODE AND THE
many as 16 slaves. Howev~r, a Data Verify Command CCB/PCCB
does not have to follow every Data Program Com-
mand. . Devices in the Slave Programmng Mode use Ports 3
and 4 as the command/data path. The data bus is not
. WORD DUMP COMMAND-When the Word used. Therefore, you do not need to program either the
Dump Command is issued, the 879X being pro- CCB or the PCCB before starting slave programming.
grammed adds 2000H to the address field of the com-
mand and places the value found at the new address on You can program the CCB during slave mode pro-
Ports 3 and 4. For example, when the slave receives the gramming like any other location. Data programmed
command#0100H, it will place the word found at lo- into the CCB takes effect upon reset. If you enable ei-
cation 2100H on Ports 3 and 4. PROG from the pro- ther the READ or WRITE lock bits in the CCB and do
grammer governs when the slave drives the bus. The not reset the device, slave programming will continue.
signals are the same as shown in Figure 22. If you enable either the READ or WRITE lock bits-
and do reset the device, the device will no longer pro-
Note that this command only works when a single slave gram or verify. You should program the READ and
is attached to the bus, and that there is no restriction on WRITE lock bits using slave programming when the
commands that precede or follow it Word Dump Com- array is fully programmed and verified.
mand.
10.6 Run-Time Programming
10.5.2 GANG PROGRAMMING WITH THE
SLAVE PROGRAMMING MODE Using Run-Time programming, the 879X can program
itself under software control. One byte or word can be
Gang programming of 879Xs can be done using the programmed instead of the whole array. The only addi-
Slave Programming Mode. There is no.879X based lim- tional requirements are that you apply a programming
it on the number of chips that may be hooked to the voltage to Vpp and have the ambient temperature at
same Port 31P0rt 4 data path for gang programming. 25°C. Run-time programming is done with EAat a
TTL high (internal memory enabled).
If more than 16 chips are being gang programmed, the
PVER and PDO outputs of each chip can be used for To run-time program the user writes a byte or word to.
verification. The master programmer can ·issue a' data the location to be programmed. The 879X will continu-
program command and then either watch every chip's ally program that location until another data read or
. error signals, or AND all the signals together to get a data write to the EPROM occurs. The user must con-
system PVER and PDO. o trol the duration of the programming pulse by imple-
menting the Modified Quick-Pulse Programming Algo-
If 16 or fewer 879Xs are to be gang programmed at
rithm (see Section 10.8) in software.
once, a more flexible form of verification is available by
2-39
 I'

intJ 8X9X HARDWARE DESIGN INFORMATION

Figure 39 is an example of code for programming an EPROM. If the program is executing from external
EPROM location while the device is executing internal- memory no, program fetches or pre-fetches ,will occur
ly. Upon entering the PROGRAM routine, the device from internal memory.
retrieves the address and data from the STACK. A
software 'timer is set to expire after one programming
pulse. The 879X starts programming a location by writ- 10.6.1 RUN-TIME PROGRAMMING AND THE
ing to it. The device then goes into a "Jump to SelF' CCB/PCCB
loop while the location is programmed. ("Jump to SelF' For run-time programming, the CCR is loaded with the
is a two byte instruction which can be CALVed from CCB. Run-time programming is done with EA equal to
address 20IAH.) When the software timer interrupt oc- a TTL-high (internal execution) so the internal CCB
curs, the device escapes from the "Jump to SelF' loop, must correspond to the memory system of the applica-
ending the programming pulse. The minimum interrupt tion setup. You can use Auto Configuration Byte Pro-
service routine would remove the 20lAH return ad- gramming or a generic programmer, to program the
dress from the STACK and' return. CCB before using run-.time programming.
. Once you start programming a location, you should not The CCB can ~lso be programmed during Run-Time
perform any program fetches or pre-fetches from the Programming like any other EPROM iocation.
EPROM. The fetches will be done but programming
will stop. Using the "Jump to SelF' prevents this from
, . \ happening because addtess 20lAH is n~t part of the

PROGRAM:
POP temp ;take parameters from the
STACK
POP address_temp
POP data_temp
PUSH temp

PUSHF ;save ourrent status

LDB int_mask, #enable_swt_only ;enable only swt interrups
LDB HSO_COMMAND, #SWTO_ovf ;load swt oommand to interrupt
ADD HSO_TIME,TIMER1, #program_pulse ;when program pulse time
:has elapsed
EI
ST data-temp, [address_temp) :start programming

CALL 201AH :nJump to Self" until

:the program pulse time
:has expired

POPF
RET

EiwtO_expired:
POP 0
RET

Figure 39. Programming the EP,ROM from Internal Memory Execu~lon

2-40
inter 8X9X HARDWARE DESIGN INFORMATION

Dllta programmed into the CCB hikes effect upon reset. on the 879XBH and the 8798 and locations 2000H-
If the WRITE lock bit of the CCB is enabled the array SFFFH on the 879XJF) from inadvertant or unautho-
can no longer be programmed. You should only pro- rized programming. It also prevents writes to the
gnim the WRITE lock bit when no further program- EPROM from upsetting program execution. If write
ming will be done to the array. If the READ lock bit is protection is not enabled, a data write to an internal
enabled the array can still be programmed using run- EPROM location will begin programming that loca-
time programming 1>ut data accesses will only be per- tion, and continue programming the location until a
formed when the program co.unter is between 2000H data access of the internal EPROM is executed. While
and 3FFFH on the 879XBH and the 8798 and between programming, instruction fetches from internal
2000H and SFFFH on the 879XJF. EPROM will not be successful and programming will
stop.

10.7 ROM/EPROM Program Lock READ protection is selected by causing the LOCI bit
in the CCR to take the value O. When READ protec-
Protection mechanisms have been provided on the tion is enabled, the bus controller will only perform a
ROM and EPROM versions of the 8X9X to inhibit data read from the address range 2020H-3FFFH ifthe
unauthorized accesses of internal program memory. slave program counter is' in the range 2000H-3FFFH
However, there must always be ,a way to allow autho- on the 879XBH and the 8798. The bus controller will
rized program memory dumps for testing purposes. only perform a data read from the address range
The following describes 8X9X lock features and the 2020H-SFFFH if the slave program counter is in the
mode provided for authorized memory dumps. range 2000H-SFFAH on 879XJF. Note that since the
slave PC can be many bytes ahead of the CPU program
counter, an instruction that is located after address
10.7.1 LOCK FEATURES
3FFAH may not be allowed to access protected memo-
Write protection is provided for EPROM devices while ry, even though the instruction is itself protected.
READ protection is provided for both ROM and
EPROM devices. ' If the bus controller receives a request to perform a
READ of protected memory, the READ sequence oc-
Write protection is enabled by causing the LOCO bit in curs with indeterminant data being returned to the
the CCR to take the value O. When WRITE protection CPU.
is selected, the bus controller will cycle through the
write sequence, but will not actually drive data to the Figure 41. shows the effects of enabling the READ and
EPROM and will not enable Vpp to the EPROM. This WRITE lock bits.
protects the enti,re EPROM (locations 2000H-3FFFH

CCB.1 CCB.O PCCB.1 PCCB.O

RD WR RD WR Protection
Lock Lock Lock Lock
1 1 1 1 Array is unprotected. ROM Dump Mode and all programming modes
are allowed.
0 1 1 1 Array is read protected. ,Run7time programming and ROM Dump Mode
(with security key verification) are allow,ed. Auto, slave, and auto pees
programming are not allowed.
0 1 0 1 Same as above.
1 0 1 1 Array is write protected. ROM dump mode (with security key
verification) is allowed. Auto, slave, auto pees, and run-time
programming are not allowed.,
1 0 1 0 Same as above.
0 0 1 1 Array is read and write protected. ROM dump mode (with security key
verification) is allowed. Auto, slave, auto pees, and run-time
programming are not allowed.
0 0 0 0 Same as above.

Figure 41

2-41
 8X9X HARDWARE DESIGN IN'FORMATION

Other enhancements were also made. to the 8X9X for Table 2. 8X9XBH Signature Words
program protection. For example, the value of EA :is
latched on reset so that the device cannot be switched . Device Signature Word
from external to internal execution mode .at run-time. 879XBH 896FH
In addition, if READ protection is selected, an NMI 839XBH 896EH
event will cause the device to switch to 'external ol)ly Undefined
809XBH
execution mode. Internal execution can only resume by
879XJF 896BH
resCltting the chip.
839XJF 896AH
809XJF Undefined
10.7.2 ROM DUMP MODE

You can use the security key and ROM dump mode to
. dump the internal ROM/EPROM for testing purposes.
10.10 Erasing the EPROM
Initially, and alter each erasure, all bits of the 879X are
The security key is a 16-byte number. The internal in the "1" statel Data is introduced by selectively pro-
ROM/EPROM must contain the security key at loca- gramming "Os" into the desired bit locations. Although .
tions 2020H-202FH. The user must place the same only "Os': will be programmed, both "Is" and "Os" can
secljrity key at external atldress 4020H -402FH. Before be present in the data w9rd. The only way to change a
doing ROM dump, the device checks that the keys "0" to a "1" is by ultraviolet light erasure.
match.
Erasing begins UpOI) exposure to light with wavelepgths
The ROM dump mode is entered by following the shorter than approximately 4000 Angstroms (A). It
power-up sequence described in Section. 10.1 with should be noted that sunlight and certain types of flu~­
PMODE = 06H. The device first verifies the security rescent lamps have wavelengths in the 3000-4000 A
keys. If the security keys do not match, the device puts range. Constant exposure to room level fluorescent
itself into an endless loop of internal execution. If the lighting could erase the typical 879X in approximately
keys match, the device dumps data to external locations 3 years, while it would take approximately 1 week to
4OOOH-5FFFH and 9000H-91FFH on the 879XBH cause erasure when exposed to direct sunlight. If the
and the 8798 and to exte~nallocations 4000H - 7FFFH 879X is to be exposed to light for extended periods of
and 9OO0H-937FH on the 879XJF. The data starting time, opaque labels must be placed over the EPROM's
at location 9000H will be indeterminate. The data start- window to prevent unintentional erasure.
ing at location 4oo0H will contain the internal
ROM/EPROM, beginning with internal address The recommended erasure procedure for the 879X is
2oooH. exposure to shortwave ultraviolet light which has a
wavelength of 2537A. The integrated dose (i.e., UV in-
tensity X exposure time) for erasure should be a mini-
10.8 Modified Quick-Pulse mum of 15 Wsec/cm 2. The erasure time with this dos-
Programming™Algorithm age is approximately 15 to 20 minutes using an ultravi-
olet lamp with a 12000 /JoW/cm2 power rating. The
The Modified Quick-Pulse Programming Algorithm 879X should be placed within 1 inch of the lamp tubes
calls for each EPROM location to receive 25 separate during erasure. The maximum integrated dose an 879X
100 /Jos (±5 /Jos) program cycles. Verification of correct can be exposed to without damage is 7258 Wsec/cm2 (1
programming is done after the 25 pulses. If the location week @ 12000 /JoW/cm2). Exposure of.the 879X to high
verifies correctly, the next location is programmed. If intensity UV light for long periOds may cause perma-
the location fails to verify, the location has failed. nent damage.
Once all locations are programmed and verified, the
entire EPROM is again verified. 11.0 QUICK REFERENCE
Programming of 879X devices is done with Vpp -
12.75V ±0.25V and Vee = 5.0V ±0.5V. 11.1 Pin Description
On the 48-pin devices the following pins are not bonded
out: Portl, PortO (Analog In) bits 0-3, T2CLK (P2.3),
10.9 Signature Word T2RST (P2.4), P2.6, P2.7, CLKOUT, INST, NMI,
The' 8X9X contains a signature word at location BUSWIDTH. S-DIP packages do not have INST,
2070H. The word can be accessed in the slave mode by CLKOUT, BUSWIDTH or NMI.
. executing a word dump command (see Table 2).

2-42
inter 8X9X HARDWARE DESIGN INFORMATION

PIN DESCRIPTIONS
Symbol Name and Function
Vee Main supply voltage (SV).
Vss Digital circuit ground (OV). Two pins.
VPD RAM standby supply voltage (5V). This voltage must be present during normal operation. In
a Power Down condition (i.e. Vee drops to zero), if RESET is activated before Vee drops
below spec and VPD continues to be held within spec., the top 16 bytes in the Register File
will retain their contents. RESET must be held low during the Power Down and should not
be brought high until Vee is within spec and the oscillator has stabilized. See Section 2.3.
VREF Reference vOltage for the AID converter (5V). VREF is also·the supply voltage to the analog
portion of the AID converter and the logic used to read Port O. See Section 8.
ANGND Reference ground for the AID converter. Should be held at nominally the same potential as
Vss. See Section 8.
Vpp Programming voltage for the EPROM devices. It should be +12.75V when programming
and will float to SV otherwise. The pin should not be above Vee on ROM or GPU devices..
This pin must flo"at in the application circuit on EPROM devices.
XTAL1 Input of the oscillator inverter and of the internal clock generator. See Section 1.S.
XT~L2 Output of the.oscillator inverter. See Section 1.5.
GLKOUT Output of the internal clock generator. The frequency bf GLKOUT is % the oscillator
frequency. It has a.33% duty cycle. See Section 1.S
RESET Reset input to the chip. Input low for at least 10XTAL1 cycles to reset the chip. The
subsequent low-te-high transition re-synchronizes GLKOUT and commences a 10-state-
time sequence in which the PSW is cleared, a byte read from 2018H loads GGR, and a jump
to location 2080H is executed. Input high for normal operation. RESET has an internal
pullup. See Section 13. '.
BUSWIDTH Input for buswidth selection. If GGR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an
8-bit cycle occurs. If GGR bit 1 is a 0, the bus is always an 8-bit bus. If this pin is left
unconnected, itwillrise to Vee. See Sectron 2.7.
NMI A positive transition causes a vector to external memory location OOOOH. External memory
from OOH through OFFH is re$9rved for Intel development systems.
INST Output high during an external memory read indicates the read is an instruction fetch. INST
"
is valid throughout the bus cycle.
EA Input for memory select (External Access). EA equal to a TTL-high caus~s memory _
~ccesses to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM. EA
~al to a TTL-low causes accesses to these locations to be directed ,to off-chip memory.
EA = + 12.SV causes execution to begin in the Programming mode on EPROM devices.
EA has an internal pulldown, so it goes to 0 unless driven otherwise.
ALE/ADV Address Latch Enable or Address Valid output, as selected by GGA. Both pin options __
provide a latch to demultiplex the address from the address/data bus. When the pin is ADV,
it goes inactive high at the end of the bus cycle. ADV can be used as a chip select for
external memory. ALE/ ADV is activated only during external memory accesses. See
Section 2.7.
RD Read signal output to external memory. RD is activated only during external memory reads.

2-43
 8X9XHARDWARE DESIGN INFORMATION

PIN DESCRIPTIONS (Continued)

~

Symbol Name and Function

WR/WRI Write and Write Low output to external memory, as selected by the CCA. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL i~ activated only during external memory writes. See Section 2.7.
SHE/WRH Sus High Enable or Write High output to external memory, as selected by the CCR. aRE =
o selects the bank of memory that is connected to the high byte of the data bus. AO != 0

selects the bank of memory that is connected to the low byte of the data bus. Thus
accesses to a 16-bit wide memory can be to the low byte only (AO = 0, SHE = 1), to the
high byte only (AO = 1, 'SHE # = 0), or both bytes (AO = 0, SHE = 0). If the WRH function
is selected, the pin will go low if the bus cycle is writing to an odd memory location. See
Section 2.7.
READY Ready input to lengthen external memory cycles, for interfacing to slow ,or dynamic memory,
or for bus sharing. If the pin is high, CPU operation continues in a normal manner. If the pin
is low prior to the falling edge of CLKOUT, the Memory Controller goes into a wait mode
until the next positive transition in CLKOUT occurs with READY high. The bus cycle can be
lengthened by up to 1 ,""S. When the external memory is not. being used, READY has no
effect. Internal control of the number of wait states inserted into a bus cycle held not ready
is available through configuration of CCR. READY has a weak internal pullup, so it goes to 1
unless externally pulled low. See Section 2.7.
HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1 , HSI.2, and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. The HSI pins are also used as
ihputs by EPROM devices in Programming mode. See Section 6.
HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1, HSO.2,
HSO.3, HSO.4, and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
See Section 7.
Port 0 8-bit high impedance input-only port. These pins car be used as digital inputs and/or as
analog inputs to the on-chip AID converter: These pins are also a mqde input to EPROM
devices in the Programming mode. See Section 10.
Port 1 8-bit quasi-bidirectional 110 port. See Section 10.
Port 2 8-bit mUlti-functional port. Six of its pins are shared with other functions in the 8X9X, the
remaining 2 are quasi-bidirectional. These pins are also used to input and output control
signals on EPROM devices in Programming Mode. See Section 10.
Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs" These pins are shared with the
multiplexed address/ data bus which has strong internal pullups. Ports 3 and 4 are also u~ed
as a command, address and data path by EPROM devices operating in the programming
mode. See Sections 2.7 and 1 0 . ' .

2-44
inter 8X9X HARDWARE DESIGN INFORMATION

11.2 Pin List 68-Pln 68-Pln 48-Pln 64-Pln

Name
The following is !l list of pins in alphabetical order. PLCC PGA DIP SDIP
Where a pin has two names it has been listed under P1.6 31 47 - 29
both names, except for the system bus pins, ADO-
ADlS, which are listed under Port 3 and Port 4.
P1.7 3,2 46 - 30
P2.0/TXD/PVER 18 60 2 16
P2.1/RXD/PALE 17 61 1 15
68-PIn 68-PIn 48-Pi n 64-Pin P2.2/EXTINT 15 63 47 13
Name
PLCC PGA DIP SDIP P2.3/T2CLK 44 34 - 42
ACHO/PO.O 6 4 ' - 4 P2.4/T2RST 42 36 - 40
P2.5/PWM/PDO 39 39 13 37
ACH1/PO.1 5 5 - 3
ACH2/PO.2 7 3 - 5
P2.6 33 45 - 31
ACH3/PO.3 4 6 - 2
P2.7 38 40 - 36
ACH4/PO.4/MOD.0 P3.0/ADO PVAL 60 18 32 58
11 67 43 9
ACH5/PO.5/MOD.1 10 68 42 8 P3.1/AD1 PVAL 59 19 31 57
ACH6/PO.6/MOD.2 8 2 P3.21 AD2 PVAL 58 20 30 56
40 6
Ad, 7 IPO.7 IMOD.3
P3.3/AD3 PVAL 57 21 29 55
9 1 41 7
ALE/ADV 62 16 P3.4/AD4 PVAL 56 22 28 54
34 60
ANGND 12 66 44 10 P3.51 AD5 PVAL 55 23 27 53
SHE/WRH 41 37 15
P3.61 AD6 PVAL 54 24 26 52
39
SUSWIDTH
CLKOUT
64
65
14
13
-
-
-- P3.7/AD7 PVAL
P4.0/AD8 PVAL
53
52
25
26
25
24
51
50
EA I 2 8 P4.1/AD9 PVAL 51 27 23 49
39 1
EXTINTIP2.2/PROG 15 63 47 13 P4.2/AD10 PVAL 50 28 22 48
HSI.O 24 54 P4.31 AD11 PVAL 49 29 21 47
3 22
HSL1 25 53 4 23 P4.4/AD12 PVAL 48 30 20 46
HSI.2/HSO.4 P4.5/AD13 PVAL 47 31 19 45
26 52 5 24
HSI.3/HSO.5 27 5'1 P4.6/AD14 PVAL ·46 32 18 44
6 25
HSO.O 28 50 7 26
P4.7/AD15 PVAL 45 33 17 43
HSO.1 29 49 8 27 RD 61 17 33 59
HSO.2 34 44 READY 43 35 16 41
9 32
HSO.3 35 43 10 33 RESET 16 62 48 14
HSO.4/HSI.2 RXD/P2.1 17 61 1 15
26 52 5 24
HSO.5/HSI.3 27 51 SALE/PVER/P2.0 18 60 2 16
6 25
SPROG/POO/P2.5 39 39 13 37
INST 63 15 - - TXD/P2.0/SALE 18 60 2 16
NMI 3 7 - - T2CLK/P2.3 44 34 - 42
PWM/P2.5/PDO 39 39 13 37
PALE/P2.1/RXD 17 61 1 15 T2RST/P2.4 42 36 - 40
PROG/P2.2/EXTNT 15 63 47 13 Vpp 37 41 12 35
PVER/P2.0/TXD 18 60 2 16 Vee 1 9 38 64
14 64 46 12
PO.O/ACHO 6 4 - 4 VPD
VREF 13 65 45 11
PO.1/ACH1 5 5 - 3
68 10 11 34
PO.2/ACH2 7 3 - 5 Vss
Vss 36 42 37 63
PO.3/ACH3 4 6 - 2
WR/WRL 40 38 14 38
PO.41 ACH4/MOD.0 11 67 43 9
PO.51 ACH5/MOD.1 68 42 WRH/SHE 41 37 15 39
10 8
PO.61 ACH6/MOD.2 8 2 40 XTAL1 67 11 36 62
6
PO.7 I ACH7 IMOD.3 9 1 41 7 XTAL2 66 12 35 61
P1.0 19 59 - 17
P1.1 20 58 - 18 The following pins are not bonded out in the 48-pin
package:
P1.2 21 57 - 19
P1.3 22 56 - 20
PI.O through Pl.7, PO.O through PO.3, P2.3, P2.4, P2.6,
P1.4 23 55 - 21 P2.7 CLKOUT, INST, NMI, TEST, T2CLK (P2.:3),
P1.5 30 48 - 28 T2RST (P2.4).

2-45
 8X9X HARDWARE DESIGN INFORMATION

1'1.3 Packaging
The.MCS-96 products are available in 48-pin, 64-pin and 68-pin packages, with and without AID, and with and
without on-chip ROM or EPROM. The MCS-96 numbering system shown below this section shows the pinouts for
the 48- and 68-pin packages. The 48-pin version is offered in a Dual-In-Line package while the 68-pin versions come
in a Plastic Leaded Chip Carrier (PLCC), a Pin Grid Array (PGA) or a Type uB" Leadless Chip Carrier.

The MCS®·96 Family Nomenclature

Factory User Programmable
Masked CPU
ROM OTP
EPROM
68·Pin 64·Pin 48·Pin 68-Pln 64~Pln 48·Pin 68-Pin 64-Pin 48-Pi.n 68-Pin 64-Pin 48-Pin
ANALOG 8397BH 8397BH 8395BH 8097BH 8097BH 8095BH 8797BH 8795BH 8797BH 8797JF
8798
8397JF 8397JF 8398 8097JF 8097JF 8098 8798 8797JF 8797BH
NO ANALOG 8396BH 8X9X

Transistor Count MTBF Calculations·

Device Type #MOSGates 8X9XBH 3.8 x 107 Device Hours @ SS·C
839XBH/879XBH 120,000 8X9XBH 1.7 x 107 Device Hours @ 70·C
809XBH 50,000 8X9XJF S.2 X 106 Device Hours @ 55°C
• MTBF data was obtaIned thrOugh calculatIons based upon the actu-
839XJF/879XJF 203,00 al average junction temperatures under stress at 55"C and 70"C
ambient.
809XJF 72,000

. Thermal Characteristics (same for 8X9XBH, 8X9XJF and 8X98)

Package Type 8Ja 8Jc
PGA 35°C/W 10°C/W
PLCC 37"C/W 13°C/W
LCC 28°C/W -
Plastic DIP 38°C/W 19°C/W
Ceramic DIP 26°C/W 6.5°C/W

2-46
 8X9X HARDWARE DESIGN INFORMATION

11.4 Package Diagrams

":
0
CD N 0
ci ci ci ci ci '" i5
RXO/P2.1 RESET
I~
TXO/P2.0 EXTINT/P2.2 ~~~~~~ ::i ~ ~ ~
'"~ ~ ~
% % % % %
~ ~ ~
HSIO VpD ~
u
~
u <> ~ 1;:1 > > x ~ :>
III 1&1
HSII VREr '" '" '"
HSI2/HS04 ANGNO
HSI3/HS05 ACH4/PO.4 ACH5Il'O.5 ADO/P3.0
HSOO ACH5/PO.5 ACH4/PO.4 AD1/P3.1
HSOI ACH7/PO.7 ANGND AD2/P3.:!
HS02 ACH6/PD.$ VREr AD3/P3.3
HS03 EA VPO 14 AD4/P3.4
MCS<R>-96
Vss Vee EXTINT/~2.2 68 PIN AD5/P3.5
Vpp Vss RffiT PLCC AD6/P3.6
PWM/P2.5 XTALI
RXD/P2.1 17 AD7/P3.7
WRL;WR XTAL2
TXD/P2.0 18 AD8/P4.0
WRH/SHE ALE/ADV TOP VIEW
P1.0 LOOKING DOWN ON AD9/P4.1
READY RD COMPONENT SIDE
~1.1 AD10/P4.2
ADI5/P4.7 ADO/P3.0 OF PC BOARD
P1.2 ADI1/P4.3
ADI4/P4.6 AD1/P3.1
P1.3 ADI2/P4.4
ADI3/P4.5 AD2/P3.2
ADI2/P4.4 AD3/P3.3 P1.4 ADI3/P4.5

ADI1/P4.3 AD4/P3.4 HSIO ADI4/P4.6

AD10/P4.2 AD5/P3.5 HSII ADI5/P4.7

AD9/P4.1 AD6/P3.6 HSI2/HS04 T2CLK/P2.3
AD8/P4.0 AD7/P3.7

270246-45

48-Pin Package
270246-46

Pins Facing Down S8-Pin Package (PLCC - Top View)

17 15 13 11 9 7 5 3 1
18 19 16 14 12 10 8 6 4 2 68 ""
2021 6766
MCS<R>-96 1 2 3 4 5 6 7 8 9 1011 121314151617
2223 6564 68 18
68 PIN
2425 GRID ARRAY 6362 67. 19
2627 61 60 66 20
TOP VIEW
2829 5958 65 21
LOOKING DOWN ON
3031 COMPONENT SIDE 5756 64 22
or PC BOARD MCS<R>-96
3233 5554 63 68 PIN 23
34 36 38 40 42 44 46 48 50 53 52 62 LEADLESS CHIP CARRIER 24
TYPE "S"
35 37 39 41 43 45 47 49 51 61 (EPROM ONLY) 25

270246-47 60 26
TOP VIEW
59 LOOKING DOWN ON 27
COMPONENT SIDE
S8-Pin Package 58
OF PC BOARD
28

(Pin Grid Array - Top View) 57 29

56 30
55 31
54 32
53 33
U M
51 50 49 48 47 46 45 4443 42 41 40 39 38 37 36 35

270246-48

S8-Pin Package (LCC - Top View)

2-47
inter 8X9X HARDWARE DESIGN INFORMATION

270246-65

Shrink-DIP Package

2-48
 intJ 8X9X HARDWARE DESIGN INFORMATION

) 11.5 Memory Map

OFFH ....- - - - - - - - - - - - - , 25 5
POWER-DOWN
OFOH RAM 2 40

OEFH
1-----------, INTERNAL
2
39
REGISTER FILE
(RAM) FFFFH

lAH L..._ _ _ _ _ _ _ _ _ _ _..... EXTERNAL MEMORY

26 OR I/o

19H
STACK POINTER STACK POINTER
25 \ 6 OooH
EXTERNAL MEMORY OR I/O 5 FFFH
18H 24
(8X9XBH. 8X98)
17H PWM_CONTROL 23 INTERNAL PROGRAM STORAGE
16H 10Sl 10Cl 22 ROM/EPROM OR EXTERNAL
MEMORY OR I/O (8X9XJF) 4OOOH
15H 10SO lOCO 21
3FFFH
14H 20 INTERNAL PROGRAM
STORAGE ROM/EPROM
13H RESERVED RESERVED 19 OR
12H 18 EXTERNAL MEMORY
2080H
llH SP_STAT SP_CON 17
RESERVED 2030H-207FH
10H 10 PORT 2 10 PORT 2 6
SECURITY KEY 2020H- 202FH
OFH
OEH
10 PORT 1
10 PORT· 0
10 PORT 1
B"'UD_RATE
15
14
\ RESERVED 201CH- 201FH
SELF JUMP OPCOPE (27H FEH) 201AH- 2018H
ODH TlMER2 (HI) 13
RESERVED 2019H
OCH TlMER2 (LO) RESERVED 12
CHIP CONFIGURATION BYTE 2018H
OBH TIMERl (HI) 11
RESERVED 2012H-2017H
OAH
09H
TIMERl (LO)
INLPENDING
WATCHDOG
INLPENDING
10
9
\
INTERRUPT VECTORS
OSH INT_MASK INLMASK 8
2000H
07 H SBUF (RX) SBUF (TX) 7
PORT 4 lFFFH
06 H HSLSTATUS HSO_COMMAND 6
PORT 3 lFFEH
05 H HSLTIME (HI) HSO_TIME (HI) 5
04 H
03 H
HSLTIME (LO)
AD_RESULT (HI)
HSO_TIME (LO)
HSLMODE
4
3
L EXTERNAL MEMORY OR I/O (8X9XBH. 8X98)
XRAM (8X9XJF)

INTERNAL RAM
0100H
OOFFH
02 H AD_RESULT (LO) AD_COMMAND 2 REGISTER FILE
STACK POINTER
01 H RO (HI) RO (HI) 1 SPECIAL FUNCTION REGISTERS
(WHEN ACCESSED AS DATA MEMORY)
00 H RO (LO) RO (LO) 0 OOOOH
(WHEN READ) (WHEN WRITTEN)
270246-49

2-49
inter 8X9X HA~DWARE DESIGN IfI.IFORMATION

11.6 Instruction Summary

Oper- Flags
Mnemonic ands Operation (Note 1) Notes
Z N C V VT ST
AOO/ADDB 2 0 - D+A ... ... ... .... t -
ADD/AODB 3 D,- B + A· ... ... ... .... t -
... ... ... -
...! t
ADDC/ADbcB 2 D-D+A+C
SUB/SUBS 2 D - D-A ... ... ... t -
SUB/SUBB 3 0 - B-A ... ... ... ... t -
... ... ... -
...t t
SUBC/SUBCB 2 0 - D-A+C-1
CMP/CMPB 2 D-A ... ... ... t -
MULIMULU 2 D, D + 2 +-'- D ° A . - - - - - ? 2
MULIMULU 3 D, D + 2 - BOA' - - - - - ? 2
MULB/MULUB 2 D,D + 1 ~ bOA - - - - - ? 3
MULB/MULUB 3 D, D + 1 - BOA - - - - - ? 3
DIVU 2 D - (0, D + 2)/ A, D+ 2 - remainder - - - ... t - 2
DIVUB
DIV
2
2
D -
D -
(D, D + 1)/A,
(D,.D + 2)/ A,
D. +
D+
1
2
-
-
remainder
remainder
-
-
-
-
-- ... ?
t
t
-
-
3

DIVB 2 D .- (D, D + 1)/A, D+ 1 - remainder - - - ? t -

AND/ANDB 2 D - DandA ...... ... 0 0 - -
AND/ANDB 3 D - BandA
- ... 0 0 - -
OR/ORB 2 D - DorA ... ... 0 0 - -
XOR/XORB 2 D - D (excl. or) A ... ... 0 0 - -
LD/LDB 2 O-A - - - - - -
ST/STB 2 A-O - - - - - -
LDBSE 2 O-A;D+1 - SIGN(A) - - - - - - 3,4
LDBZE 2 O-A;D+1-0 - - - - - - 3,4
PUSH 1 SP - SP - 2; (SP) - A - - - - -
POP 1 A - (SP); SP - SP + 2 ,- - - - - -
PUSHF 0 SP - SP - 2; (SP) - PSW; 0 0 0 0 0 0
PSW - OOOOH 1-0
POPF 0 PSW - (SP);SP - SP + 2;
,
1 - ... ... ~ ... ... ... I" ;

SJMP 1 PC +- PC + 11·bit offset - - - - - - 5

WMP 1 PC - PC + t6·bit offset - - - - - - 5
BR [indirect) 1 PC - (A) - - - - - -
SCALL 1 SP - SP - 2; (SP) - PC; - - - - - - 5
PC - PC + 11-bit offset
LCALL 1 SP - SP - 2; (SP) - PC; - - - - - - 5
PC - PC + 16-bit offset
RET 0 PC - (SP);SP - SP + 2 - - - - - -
J (conditional) 1 PC - PC + ~·bit offset (if taken) - - - - ....... - 5
JC 1 JumpifC = l' - - - - - - 5
JNC 1 JumpifC =0 - - - - - - 5
JE 1 JumpifZ =1 - - - - - - 5
, NOTES;
1. If the mnemonic ends in "B", a byte operation is performed, otherwise a word operation is done. Operands D, B, and A
must conform to the alignment ~es for the required operand type. D and B are locations in the Register, File; A can be
located anywhere in memory. . ' _
2. 0, D + 2 are consecutive WORDS in memory; D is DOUBLE-WORD aligned.
3. D, D + 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to a word.
5. Offset is a 2's complement number.

2-50
 '.

8X9X HARDWARE DESIGN INFORMATION

"
Oper- " Flags
Mnemonic Operation (Note 1) Note.
ands Z N C V VT ST
,
JNE 1 JumpifZ = 0 - - ..... - - - 5
JGE 1 Jump if N = 0 - - - - - - 5
JlT 1 JumpifN = 1 - - - - - 5
JGT 1 Jump if N = OandZ = 0 - - - - - - 5
JLE 1 Jump If N = 1 or Z = 1 - - - - - 5
JH 1 JumpifC = 1 andZ = 0 - - - - - -
"
5
JNH 1 JumpifC = OorZ = 1 - - - - - - 5
JV 1 Jump if V = 1 - - - - - - 5
JNV 1 Jump if V = 0 - - - - - - 5
JVT 1 Jump if VT = 1; Clear VT - - - - 0 - 5
JNVT 1 Jump if VT = 0; Clear VT - - - - 0 - 5
JST 1 JumpifST = 1 - - - - - - 5
JNST 1 JumpifST = 0 -,
'- - - - - 5
JBS :3 Jun:tP'if Specified Bit = 1 - '- - - - - 5,6
JBC 3 Jump if Specified Bit = 0 - - - - - - 5,6
OJNZ 1 0 - 0 --1;ifO*Othen
PC - PC + 8-bit offset - - - ..... - - 5
OEC/OECB , 1 0-0-1 ~ ~ ~ ~ t -
NE-G/NEGB 1 0-0-0 ~ ~ ~ ~ t -
INC/INCB 1, 0 - 0+ 1 ~ ~ ~ ~ t -
EXT
EXTB
1
1
0 - p;O + 2 -
0 - 0;0 -Ir 1 -
Sign (0)
Sig'n(O)
~

~
~

~
0
0
0
0
-- -
-
2
3
NOT/NOTB
CLR/CLRB
1
1
o ,- Logical Not (0)
0-0
~

1
~

0
0
0
0
0
-- -
-
SHL/SHLB/SHLL 2 C - msb-----Isb - 0 ~ ? ~ ~ t - 7
SHR/SHRB/SHRL, 2 0 ' - msb-----Isb - C ~ ? -
~ 0 ~ 7
SHRAISHRAB/SHRAL 2 msb - msb--""':-":"'Isb ""'"+ C ~ ~ -
~ 0 ~ 7
SETC 0 C-1 - - 1 - - -
CLRC 9 C-O - -' 0 - - -
CLRVT,
RST
0
0
VT -
~ -
0
2080H
- - - - 0
0 0 0 0 0
-
0 8
01 0 disable All Interrupts (I - 0) - - - - - -
EI 0 Enable All Interrupts (I - 1) - - - - - -
NOP 0 PC-PC+1 - - - - - -
SKIP 0 PC-PC+2 - - - - - -
NORML 2 Le~ shift till msb = 1; 0 - shift count ~ ? 0 - - - 7
TRAP 0 SP - SP - 2; (SP) - PC
PC - (2010H) - - - - - - 9,

NOTES: ,
1. If the mnemonic' ends in "8", a, byte operation is performed, 'otherwise a word operation is done. Operands 0, ,9 and A
must conform to the alignment rules for the required operand type. 0 and 8 are locations in the Register File; A, can be
located anywhere In memory.
5. Offset is a 2's complement number.
6. Specified bit is one of the 2048 bits in the register file.'
7. The "L" (Long) suffix indicates double-word operation.
8. Initiates a Reset by pulling RESET low. Software should re-initialize all the necessary registers with 'code starting at
2080H.
9. The assembler will not accept this mnemonic.

2-51
 , '
8X9X HARDWARE DESIGN INFORMATION " 'I' "

, 11.7 Opcode ,and State Time Listing

INDIRECT@ INDEXED~
DIRECT IMMEDIATE
NORMAL AUTO-fNC. SHORT LONG
"

'8
Iz
:I
a
A.
0
III
8
~
0
U)
~
III ~I g5
III
Q U)
~fa
... lI
U)):
III

~ ~
0 III
aU)
I!: III
~! ~
III
aU)
~;
~):
111
Q
0,
~
0
U)
~; fa ~;
a@
!ell
_5 ~): 5 ~I=
ARITHMETIC INSTRUcnONS
ADD 2 64 3 4 65 4 5 66 3 6111 ~ ,7112 67 4 61115 7112
,
ADD 3 44 4 5 45 5 6 46 4 71\2 4 Sit 3 47 5 71\26 81\3
i\DDB 2 74 3 4 75 3 4 76 3 6111 3 71\2 77 4 6111 ' 5 7/12
ADDB 3 54 4 5 55 4 5 56 4 71\2 4 8113 57 5 7/12 6 81\3
ADOO 2 ..\4 3 4 AS 4 5 Ai> 3 6111 3 71\2 A7 4 6111 5 7/12
.::,~. ", ADDeB 2 B4 3 4 B5 3 4 B6 3 6111 3 71\2 'B7 4 6111 ' 5 71\2
" .,;"\','
SUB, 2 68 3 4 69 . 5 6A 3 6111 3 7112 6B 4 6111 5 7112
SUB j 48, 4 5 49 '5 6 4A 4 7112 4 8/13 4B 5 71\2 6 81\3
SUBB 2 ,78 3 4 79 j 4 7A 3 '6111 3 7/12 7B 4 6111 5 71\2
SUBB 3 58 4 5 59 4 5 SA 4 7/12 4 81\3 5B 5 71\2 6 81\3
SUBC 2 A8 3 4' A9 4 5 AA 3 6111 3 7/12 AB 4 6111 5 7/12
SUBCB 2 :B~ 3 4 B9 3 4 BA 3 6111 3 1112. BB 4: 6111 5 71\2
CMP 2 88 3 4 89 4 5 8A 3 6111 3 7112 8B 4 6111 5 7112
CMPB 2 98 3' 4 99 3 4 9A 3 6111 '3 '\7112 9B 4 6/11 5 7112

MULU 2 6C 3 25 60 4 26 6E 3 27132 3 28/33 6F 4 27132 5 28/33

MULU 3 4C 4 26 40 5 27 4E 4 28/33 4 29/34 4F 5 28/33 6 29/34
MULUB 2 7C 3 17 70 3 i7 7E 3 19/24 3 20;25 7F 4 19/24 5 20/25
MULUB 3 5C 4 18 SO 4 18 5E 4 20/25 4 21126 SF 5 20125 6 21126
MUL 2 ~ 4 29 ~ 5 30 ~, 4 31/36 4 32/37 ~ 5 31136 6 32137
MUL 3 ~ 5 30 ~ 6 31 ~ 5 32137 5 33/38 ~ 6 32137 7 33/38
MULB 2 ~ 4 21 ~ 4 21 ~ 4 23/28 4 24/29 ~ 5 23/28 6 24/29
MUJ.B 3 ~ 5 22 ~ 5 . 22 ~ 5 24/29 5 25/30 ~ 6 24/29 7 25/30
D1VU' 2 '8C 3 25 80 4 26 8E 3 28/32 3 29/33 8F 4 28/32 5 29/33
D1VUB 2 9C 3 17 90 3 17 9E 3 '20/24 3 21i25 9F 4 20124 5 21/25
DIV 2 ~ 4 29 ~ 5 30 ~ 4 32/36 4 33/37 ~ 5 32136 6 33/37
DIVB 2 ~ 4 , 21 ~ 4 21 ~ 4 24/28 4 25/29 ~ 5 24/28 6 25/29
270246-63
NOTES: ,
·Long indexed and ,Indirect + instructions have identical opcodes with Short indexed and Indirect modes, respectively. The
second byte of instructions using any Incjirect or indexed addressing mode )lpecifies the exact mode used. If the second
byte is even, use Indirect or Short indexed. If it is odd, use Indirect + or Long indexed. In all cases the second byte of the
instruction always specifies an even (word) location for the 'address referenced.
(l) Nilimber of state times shown 'for internal/external operands. ,
@ The 'opcodes for signed multiply and divide are the opcodes for the unsigned functions with an "FE" appended as a
prefix,
@ State times shown for 16-bit bus.
inter 8X9X HARDWARE DESIGN INFORMATION .

INDIRECT@) INDEXED@)
DIRECT' IMMEDIATE
NORMAL AUTo-INC. SHORT LONG

·z
W !
ere ere ~I ~I
III III III

I
.~
M
z
:I
II:
III
~
~~
0
~re
Ii)~ i~ ~re
Ii)~ I
LOGICAL INSTRUCTIONS
m ~:I m ~:I
III 1i)F= III 1i)F= III e~
m ~ ~~
AND 2 60 3 4 61 4 5 62 3 6111 3 7112.· 63 4 6111 5 7112
AND 3 40 4 5 41 . 5 . 6 42 4 7112 4 8/13 43 5 7112 6 8/13
AN DB ,2 70 3 4 71 3 4 72 3 6111 3 7/12 73 4 6111 5 7/12
ANDB 3 50 4 5 51 ,4 5 52 4 7/12 4 8/13 53 5 7/12 ·6 8113
OR 2 80 3 4 81 4 5 82 3 6111 3 7/12 83 4 6111 5 7/12
ORB 2 90 3 4 91 3 4 92 3 6111 3 7/12 93 4 6111 5 7/12
XOR 2 84 3 4 85 4 5 86 3 6111 3 7/12 87 4 6111 5 7/12
XORB 2 94 3 4 95 3 4 96 3 6111 3 7/12 97 4 6111 5 7/12
DATA TRANSFER INSTRUCTIONS
LD 2 AO 3 '4 AI 4 5 A2 3 6111 3 7/12 A3 4 ·6111 5 7112
LOB 2 BO 3 4 BI 3 4 B2 3 6/11 3 7/12 B3 4 6111 5 7/12
ST 2 CO 3 4 - - . ' - C2 3 7111 3 8/12 C3 4 7/11 5 8/12
STB 2 C4 3 4 - - - C6 3 7/11 3 8/12 C7 4 7111 5 81-12
LOBSE 2 BC 3 4 BD 3 4 BE 3 6111 3 7112 BF 4 6111 S 7112
LOBZE 2 AC 3 4 AD 3 4 AE 3 ~II 3 7/12 AF 4 6111 5 7112
STACK OPERATIONS (Internal stack)
PUSH I C8 2 8 C9 3 8 CA 2 11115 2 12116 CB 3 11i15 4 12116
POP 1 CC 2 12 - - - CE 2 14/18 2 14/18 CF 3 14/18 4 \4118
PUSHF 0 F2 1 ~
POPF 0 F3 I 9
\ STACK OPERATIONS (external stack)
PUSH I C8 2, 12 C9 3 12 CA 2 15119 2 16120 CB 3 15/19 4 16120
. POP 1 ~C 2 14 - - -CE 2 16120 2 16120 CF 3 16120 4 16120
PUSHF 0 F2 1 12 '
POPF 0 F3 I 13

JUMPS AND CALLS

MNEMONIC OPCODE BYTES STATES MNEMONIC OPCODE BYTES STATES
UMP E7 3' 8 LCALL EF 3 13/1(4)
SJMP 20:27@ 2 8 SCALL 28-2F@ 2 13/1(4)
BRII E3 2 8 RET FO 1 1211(4)
TRAPQ) F7 1 21/24
270246-64
NOTES:
<D Number of state times shown for internal/external operands.
@ The assembler does not accept this mnemonic. .
@ The least $ignificant 3 bits of the opcode are concatenated with the following 8 bits to form an II-bit, 2's complement,
offset for the relative call or jump.
@ State times for stack located internal/external.
@ State times shown for H)-bit bus.

2-53
 8X9X HARDWARE DESIGN INFORMATION

CONDITIONAL JUMPS
All conditional jumps are 2 byte instructions. They require 8 state times if the jump is taken, 4 if it is nol,(8)
MNEMONIC OPCODE MNEMONIC OPCODE MNEMONIC OPCODE MNEMONIC OPCODE
JC OB JE OF dGE 06 JGT 02
JNC 03 JNE 07 JLT OE JLE OA
JH 09 JV 00 JVT OC JST 08
JNH 01 JNV 05 JNVT 04 JNST 00

JUMP ON BIT CLEAR OR BIT SET

These instructions are 3 byte instructions. They require 9 state times if the jump is taken, 5 if it is not.(8)
BIT NUMBER
MNEMONIC 0 1 2 3 4 5 6 7
JBC 30 31 32 33 34 35 36 37
JBS 38 39 3A 3B 3C 30 3E 3F

LOOP CONTROL

MNEMONIC OPCODE BYTES STATE TIMES

OJNZ EO 3 5/9 STATE TIME (NOT TAKEN/TAKEN)(8)

SINGLE REGISTER INSTRUCTIONS

MNEMONIC OPCODE BYTES STATES(S) MNEMONIC OPCODE BYTES STATES(S)
OEC 05 2 4 EXT 06 2 4
OECB 15 2 4 EXTB 16 2 4
NEG " 03 2 4 NOT 02 2 4
NEGB 13 2 4 NOTB 12 2 4
INC 07 2 4 CLR 01 2 4
INCB 17 2 4 CLRB 11 2 4

SHIFT INSTRUCTIONS
INSTR WORD INSTR BYTE INSTR DBLWD
STATE TIMES(S)
MNEMONIC MNEMONIC MNEMONIC
OP B OP B OP B
SHL 09 .3 SHLB 19 3 SHLL 00 3 7 + 1 PER SHIFT(?)
SHR 011 3 SHRB 18 3 SHRL OC 3 7 + 1 PER SHIFT(?)
SHRA OA 3 SHRAB lA 3 SHRAL OE 3 7 + 1 PER SHIFT(?)

SPECIAL CONTROL INSTRUCTIONS

MNEMONIC OPCODE BYTES STATES(S) MNEMONIC OPCODE BYTES STATES(S)
SETC F9 1 4 01 FA 1 4
CLRC F8 1 4 EI FB 1 4
CLRVT FC 1 4 Nap FO 1 4
RST(6) FF 1 166 SKIP 00 2 4

NORMALIZE
MNEMONIC STATE TIMES
NORML 11 + 1 PER SHIFT
NOTES:
6. This instruction takes 2 states to pull RESET low, then holds it low for at least one state time to initiate a reset. The reset
takes 13 states, at which time the program restarts at location 20aOH.
7. Execution will take at least 8 states, even for 0 shift.
8. State times shown for 16·bit bus.
2-54
 8X9X HARDWARE DESIGN INFORMATION

11.8 SFR Summary

AID Result LO (02H) AID Command (02H)

:1
AID CHANNEL NUMBER

STATUS:
Rl.

3
1
2,
CHANNEL II SELECTS WHICH OF THE 8
ANALOG INPUT CHANNELS IS 1'0 BE
CONVERTED TO DIGITAL fORIA.
,

GO INDICATES WHEN THE CONVERSION IS TO

3 0= AID CURRENTLY IDLE BE INITIATED(GO= 1 IAEANS START NOW.
X 1 = CONVERSION IN PROCESS GO = OIAEANS THE CONVERSION IS TO BE
INITIATED BY THE HSO UNIT AT A SPECIFIED TIIAEt.
270246-53
X
AID RESULT:
LEAST SIGNlrlCANT 2 BITS SPCON/SPSTAT (11H)

0 BITI. BITO SPECIfY THE 1A0DE

270246-50
W
R
} 00 =IAODE 0
01=IAODEI
10= 1A0DE 2
11 =IAODE 3
I 2 PEN ENABLE THE PARITY fUNCTION
HSI""':Mode (03H) T
E 3 REN ENABLES THE RECEIVE FUNCTION

I 7 615 41 3 21' I 0 I 4 TB8 PROGRAIAS THE 9TH DATA BIT

R 5 TI IS THE TRANSIAIT INTERRUPT FLAG

L HSI.O MODE E
A
RI IS THE RECEIVE INTERRUPT FLAG
HSI.1 MODE 0 RBS IS THE 9TH DATA RECEIVED
(IF NOT PARITY)
HSI.2 MODE RPE IS THE PARITY ERROR INDICATOR
HSI.3 MODE (IF PARITY ACTIVE)
270246-54
WHERE EACH 2 - BIT MODE CONTROL fiELD
DEfiNES ONE Of 4 POSSIBLE MODES:

00 8 POSITIVE TRANSITIONS Baud Rate Calculations

01 EACH POSITIVE TRANSITION Using XTAL 1:
1o EACH NEGATIVE TRANSITION
11 EVERY TRANSITION M d ' Baud = )(TAU frequency .. B '" 0
(POSITIVE AND NEGATIVE) o eO. Rate 4'(B + 1) ,
270246-51
o . Baud _ XT AL 1 frequency
thers. Rate - 64' (B + 1)

HSO Command (06H) Using T2CLK:

CHANNEL: M d ' Baud - T2CLK frequency. B 0

o eO. Rate - B ,,,,
0-5 HSO.O - HSO.5
BIT: 0]6 HSO.O AND HSO.1 o . Baud _ T~CLK frequency . B
1 HSO.2 AND HSO.3 thers. Rate - .16'B • '" 0
8-8 SOfTWARE TIMERS
2 E RESET TIMER2 . Note that B cannot .equal 0, except wl1en using
3 . f START AID CONVERSION XTALI in other than Mode O.
, INTERRUPT I NO INTERRUPT

SET /CLEAR HSI_Status (06H)

TIMER 2 I TIMER 1
l7 6[5 4J 3 2L lJOJ
X
270246-52
L HSI.O STATUS
HSI.1 STATUS
HSI.2 STATUS
HSI.3 STATUS
WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
BIT INDICATES WHETHER OR NOT AN EVENT HAS
OCCURED ON THIS PIN AND THE UPPER BIT INDICATES
THE CURRENT STATUS Of THE PIN. 270246-55

2-55
inter 8X9.X HARDWARI; DESIGN INFORMATION

lOCO (15H) IOC1 (16H)

HSI.O INPUT ENABLE / i5'iS'AiitE SELECT PWM / SELtCT P2.S

TIMER 2 RESET EACH WRITE EXTERNAL INTERRUPT ACH7 / EXTINT
"
HSI.1 iNPUT ENABLE / DISAI;ILE TIMER 1 OVERFLOW INTERRUPT ENABLE / DISABLE
TIMER 2 EXTERNAL RESET ENABLE / DISABLE TIMER 2 OVERFLOW INTERRUPT ENABLE / DISABLE
HSI.2 INPUT ENABLE / DISAB,LE HSO.4 OUTPUT ENABLE! DISABLE
TIMER 2 RESET SOURCE HSI.O /T2RST SELECT TXD / SELECT P2.0
HSI.3 INPUT ENABLE / DISABLE HSO.5 OUTPUT ENABLE / DISABLE
TIMER 2 CLOCK SOURCE HSI.1 /T2CLK HSI INTERRUPT
FIFO FULL / "'HO"'l'"""D"'"IN"'G'"'R"'E""'GI;;oST"'E"'R-'L""O-'-AD"",E"'D
270246-56
270246-59

lOCO (15H)
Vector Location

I
T2RST - 0 •. - IOCO.5 Vector (High (Low Priority
~~""----T2 RESET Byte) Byte)
, :·-IOCO.3
, ··-IOCO.O Software Trap 2011H 2010H Not Applicable
HSI.O :>'0------- HSI Extint 200FH 200EH 7 (Highest)
•• - IOCO.2 Serial Port 200DH 200CH 6
roO""'-0-'---- HSI Software 200BH 200AH 5
Timers
HSI.1 ~ TIMER2
T2CLK - 0 :. - IOCO.7 CLOCK
HSI.O 2009H 2008H 4
High Speed 2007H 2006H 3
;.- IOCO.4
Outputs
HSI.2 - 0 ""-0-------- HSI HSI Data 2005H 2004H 2
;. - IOCO.6 Available
HSI.3 - 0 '-'0------- HSI AID Conversion 2003H 2002H 1
270246-57 Complete
Timer Overflow 2001H 2000H o (Lowest)
10SO (15H)
IOS1 (16H)
HSO.O CURRENT STATE
HSO.1 CURRENT STATE SOFTWARE TIMER ,0 EXPIRED
HSO.2 CURRENT STATE SOFTWARE TIMER 1 EXPIRED
HSO.3 CURRENT STATE SOFTWARE TIMER 2 EXPIRED
HSO.4 CURRENT STATE
SOFTWARfTIMER 3 EXPIRED
HSO.5 CURRENT STATE TIMER 2 HAS OVERFLOW
CAM QB HOLOING REGISTER IS FULL TIMER 1 HAS OVERFLOW
HSO HOLDING REGISTER IS FULL HSI FIFO IS FULL
270246-58 HSI HOLDING REGISTER DATA AVAILABLE
270246-60

2-56
 8X9X HARDWARE DESIGN INFORMATION

Slave Programming Mode Commands

Chip Configuration
P4.7 P4.6 Action
'1 7 1sI511 ~ 21 ~ ~ Cf.lIP CONFIGURATION REGISTER 0 0 Word Dump
L RESERVED (Set to 0 1 Dilta Verify
1 for
compatibility with future 1 0 Data Program
parts) . 1 1 Reserved
~
BUS WIDTH SELECT
(16 - BIT BUS / ><""8--:-;B""ITr;B"'U"'s)

- WRITE STROBE MODE SELECT

(WR AND BHE/WRL AND WRH)
.
8X9XBH Signature Word
Device Signature Word
ADDRESS VALID STROBE SELECT
879XBH 896FH
(ALE/ ADV)
839XBH 896EH
(iRCO) } INTERNAL READY 809XBH Undefined
(iRC1) CONTROL MODE

(LOCO) } PROGRAM LOCK Port 2 Pin Functions

(LOCI) MODE
Port Function Alternate Function
270246-61
P2.0 Output TXD (Serial Port Transmit)
P2.1 Input RXD (SE!rial Port Receive)
Internal Ready Control P2.2 Input EXTINT (External Interrupt)
IRC1 IRCO Description P2.3 Input T2CLK (Timer 2 Clock)
P2.4 Input T2RST (Timer 2 Reset)
o o Limit to 1 Wait State P2.5 Output PWM (Pulse Width Modulation)
o 1 Limit to 2 Wait States
o Limit to 3 Wait States
Interrupt Pending Register
Disable Internal Ready Control

(LOCATION 09H)
Program Lock Modes
17161514131211101
LOC1 LOCO Protection
0
0
0
1
Read and Write Protected
Read Protected'
II t 1. 1
~~:,~~E,,,
HSO EVENT
0 Write Protected HSI BIT 0
1 No Protection SOFTWARE TIMERS
" - - - - - - - - - - - SERIAL I/O
~-------- EXTERNAL INTERRUPT
Programming Function PMODE Values 270246-62
PM ODE Programming Mode
0-4 Reserved
5 Slave Programming
6-0BH Reserved
OCH Auto Programming Mode
ODH Program Configuration Byte
OEH-OFH Reserved

2-57
 MCS®-96
809XBH, 839XBH, 879XBH
ADVANCED 16-BIT MICROCONTROLLER
. WITH 8- .OR 16-BIT EXTERNAL BUS
• 879XBH: an 809XBH with 8 Kbytes of On-Chip EPROM
• 839XBH: an 809XBH with 8 Kbytes of On-Chip ROM

• 232 Byte Register File

• High Speed 110 Subsystem

• Register-to~Register Architecture
• Full Duplex Serial Port

• 10-Bit A/D Converter with S/H

• Dedicated Baud Rate Generator

• Five 8-Bit I/O Ports

• 6.25 J-ts ~6 x 16 Multiply

• 20 Interrupt Sources
• 6.25 J-ts 32/16 Divide

• Pulse-Width Modulated Output

• 16-Bit Watchdog Timer

• ROM/EPROM Lock
• Four 16-Bit Software Timers

• Run-Time Programmable EPROM

• Two 16-Bit Counter/Timers
The MCS-96 family of 16-bit microcontrollers consists of many members, all of which are designed for high-
speed control functions. The MCS-96 family members produced using Intel's HMOS-III process are described
in this data sheet.
The CPU supports bit, byte, and word operations. Thirty-two bit double-words are supported for a subset of the
instruction set. With a 12 MHz input frequency the 8096BH can do a 16-bit addition in 1.0 p.s and a 16 x 16-bit
multiply or 32/16 divide in 6.25 p.s. Instruction execution times average 1 to 2 p.s in typical applications.
Four high-speed trigger inputs are provided to record the times at which external events occur. Six high-speed
pulse generator outputs are provided to trigger external events at preset times. The high-speed output unit can
s,imultaneously perform software timer functions. Up to four 16-bit software timers can be in operation at once.
The on-chip AID conver~er includes a Sample and Hold, and converts up to 8 multiplexed analog input
channels to 10-bit digital values. With a 12 MHz crystal, each conversion takes 22 p.s. This feature is only
available on the 8X95BHs and 8X97BHs, with the 8X95BHs having 4 multiplexed analog inputs.
Also provided on-chip are a serial port, a Watchdog Timer, and a pulse-width modulated output signal.

PORTO PORT 1 PORT2 HSI HSO

AL T FUNCTIONS
270090-50
Figure 1. MCS®-96 Block Diagram

October 1990
2-58 Order Number: 270090-007
inter 8X9XBH ~OO~!bDrMlD~~OOW

OFfH 255,
POWER-DOWN
RAM
OFOH 240
OEFH 239
INTERNAL
REGISTER FILE
(RAM)
FFFFH
1AH 26
EXTERNAL MEMORY
OR I/O
19H 25
STACK POINTER STACK POINTER 4000H
1SH 24
17H PWM_CONTROL 23 ,INT£RNAL PROGRAM
STORAGE ROM/EPROM
16H IOS1 10Cl 22 OR
15H 10SO lOCO 21 EXTERNAL MEMORY
I
20S0H
14H 20
RESERVED 2072H - 297FH
13H RESERVED RESERVED 19
SIGNATURE WORD 2070H- 2071H
12H 1S
RESERVED 2030H - 206FH
11H SP_STAT SP_CON 17
SECURITY KEY 2020H - 202FH
10H 10 PORT 2 10 PORT 2 16
~ESERVED 201CH-201FH
OFH 10 PORT 1 10 PORT 1 15
SELF JUMP OPCODE (27H FEH) 201AH- 201BH
OEH 10 PORT 0 BAUD_RATE 14
RESERVED 2019H
ODH TIMER2 (HI) 13
CHIP CONFIGURATION BYTE 201SH
OCH TIMER2 (LO) RESERVED 12
RESERVED 2012H - 2017H
OBH TIMERl (HI) 11
OAH TIMER1 (LO) WATCHDOG 10
INTERRUPT VECTORS
09H INLPENDING INT_PENDING
OSH INLMASK INLMASK S 2000H
07H SBUF (RX) SBUF (TX) 7 PORT 4 1FFfH
06H HSLSTATUS HSO_COMMAND PORT 3 1fFEH
OSH HSLTIME (HI) HSO_TlME (HI) EXTERNAL MEMORY
04H
03H
HSLTIME (LO)
AD_RESULT (HI)
HSO_TIME (LO)
HSLMODE
4
L OR I/O

INTERNAL RAM
0100H
OOfFH
02H AD_RESULT (LO) AD_COMMAND REGISTER FILE
STACK POINTER
01H RO (HI) RO (HI) SPECIAL fUNCTION REGISTERS
(WHEN ACCESSED AS DATA MEMORY)
OOH RO (LO) RO (LO) 0 OOOOH

(WHEN READ) , (WHEN WRITTEN)

270090-6

Figure 2. Memory Map

2-59
 8X9XBH

PACKAGING
The 80968H is available in 48-pin, 64-pin, and 68-pin packages, with and without AID, and with arid without
on-chip ROM or EPROM. The 80968H numbering system is shown in Figure 3. Figures 4-9 show the pinouts
for the 48-, 64- and 68-pin packages. The 48-pin version is offered in a Dual-In-Line package while the 68-pin
versions come in a Plastic Leaded Chip Carrier (PLCC), a Pin Grid Array (PGA) or a Type "8" Leadless Chip
Carrier.

Factory Masked User Programmable

CPU
ROM EPROM OTP
68-Pin 64-Pin 48-Pin 68-Pin 64-Pin 48-Pin 68-Pin 64-Pin 48-Pin 68-pin 64-Pin 48-Pin
ANALOG 8397BH 8397BH 8395BH 8097BH 8097BH 8095BH 8797BH 8795BH 8197BH 8797BH
NO ANALOG 8396BH 8096BH
Figure 3. MCS®96 Packaging-8X9XBH
NOTES:
1. 48·pin devic!ls have four Analog Input pins. 3. 68-pin devices have 48 and 64-pin features plus the fol-
2. 64-pin devices have all 48-pin device features plus the lowing:
following: Dynamic Buswidth sizing (8 or 16-bit bus)
Four additional Analog Input channels Dedicated System Clock Output (CLKOWT)
One additional Quasi-Bidirectional 8-bit Parallel Port INST pin for memory expansion
Four additional Port 2 pins with multiplexed features Non-Maskable Interrupt for debugging
. Timer 2 Clock Source pin 4. Package Designators:
Timer 2 Reset pin N=PLCC
Two additional quasi-bidirectional port pins C=Ceramic DIP
A = Ceramic Pin Grid Array
P = Plastic DIP
R = Ceramic LCC
U = Shrink DIP

PGAI PGAI PGAI

PlCC Description PlCC Description PlCC Description
lCC lCC lCC
1 9 ACH7/PO.7/PMOD.3 24 54 AD6/P3.6 47 31 P1.6
2 8 ACH6/PO.6/PMOD.2 25 53 AD7/P3.7 48 30 P1.5
3 7 ACH2/PO.2 26 52 AD8/P4.0 49 29 HSO.1
4 6 ACHO/PO.O 27 51 AD9/P4.1 50 28 HSO.O
5 5 ACH1/PO.1 28 50 AD10/P4.2 51 27 HSO.5/HSI.3
6 A ACH3/PO.3 29 49 AD11/P4.3 52 26 HSO.4/HSI.2
7 3 NMI 30 48 AD12/P4.4 53 25 HSl.l
8 2 EA 31 47 AD13/P4.5 54 24 HSI.O
9 1 VCC 32 46 AD14/P4.6 55 23 Pl.4
10 68 VSS 33 45 AD15/P4.7 56 22 Pl.3
11 67 XTAL1 34 44 T2CLK/P2.3 57 21 Pl.2
12 66 XTAL2 35 43 READY 58 20 Pl.l
13 65 CLKOUT 36 42 T2RST/P2.4 59 19 Pl.0
14 64 BUSWIDTH 37 41 BHE/WRH 60 18 TXD/P2.0/PVERISALE
15 63 INST 38 40 WR/WRL 61 17 RXD/P2.1/PALE
16 62 ALE/ADV 39 39 PWM/P2.5/PDO/SPROG 62 16 RESET
17 61 RD 40 38 P2.7 63 15 EXTINT IP2.2/PROG
18 60 ADO/P3.0 41 37 VPP 64 14 VPD
19 59 AD1/P3.1 42 36 VSS 65 13 VREF
20 \ 58 AD2fP3.2 43 35 HSO.3 66 12 ANGND
21 57 AD3/P3.3 44 34 HSO.2 67 11 ACH4/PO.4/PMOD.0
22 56 AD4/P3.4 45 33 P2.6 68 10 ACH5/PO.5/PMOD.l
23 55 AD5/P3.5 46 32 Pl.7
Figure 4a. PGA, PLCC and LCC Function Pinouts
2-60
 8X9XBH

Description Description
1 EA 33 HSO.3
2 ACH3/PO.3 34 VSS
3 ACH1/PO.1 35 Vpp
4 ACHO/PO.O 36 P2.7
5 ACH2/PO.2 37 PWM/P2.51
6 ACH6/PO.6/PMOD.2 PDO/SPROG
7 ACH7 IPO. 7 IPMOD.3 38 WR/WRL
8 ACH5/PO.5/PMOD.1 39 SHE/WRH
9 ACH4/PO.4/PMOD.0 40 T2RST/P2.4
10 ANGND 41 READY
11 VREF 42 T2CLK/P2.3
12- VPD 43 AD15/P4.7
13 . EXINTIP2.2/PROG 44 AD14/P4.6
14 RESET 45 AD13/P4.5
15 RXD/P2.1/PALE 46 AD12/P4.4
16 TXD/P2.01 47 AD11/P4.3
PVERISALE 48 AD10/P4.2
17 P1.0 49 AD9/P4.1
18 P1.1 50 AD8/P4.0
19 P1.2 51 AD7/P3.7
20 P1.3 52 AD6/P3.6
21 P1.4 53 AD5/P3.5
22 HSI.O 54 AD4/P3.4
23 HSI.1 55 AD3/P3.3
24 HSO.4/HSI.2 56 AD2/P3.2
25 HSO.5/HSI.3 57 AD1/P3.1
26 . HSO.O 58 ADO/P3.0
27 HSO.1 59 RD 270090-56
28 P1.5 60 ALE/ADV
29 P1.6 61 XTAL2 Figure 5. Shrink-DIP Package
30 P1.7 62 XTAL1
31 P2.6 63 Vss
32 HSO.2 64 Vee
Figure 4b. Shrink-DIP Function Pinouts

2-61
inter 8X9XBH

/1 2 3 4 5'6 7 8 9 1011 121314 15 16 17 L

68 18
67 19
...eHS/PO.S 10 ADO/P3.0 20
66
ACH.4/PO.4 11 AOt/P!.1
ANGHD 12 AD2/Pl.2
65 21
VREf 13 ACl/P3.! 64 22
MCS®-96 MCS®-96
VpD ,. A04/P3.4 63 23
68 PIN 68 PIN
E)clINT/P2.2 15 A05/P3.5
62 LEADLESS CHIP CARRIER 24
RESEr 16 PLCC A06/p3.6
RXDjf>2.1 17 A07/P!.7 61 TYPE "B" 25
TXO/P2.D 18 AD8/P4.0 60 (EPRO~ ONLY) . 26
f1.0 51 ADS/P... ,
59 27
Plot TOP VIEW ACID/P"".2 TOP VIEW
58 28
LOOKING DOWN ON A011/P4.3 LOOKING DOWN ON
PI.! AOI2/P ... " 57 COMPONENT SIDE 29
COMPONENT SIDE ADI3/p4.5
Pt." 56 OF PC BOARD. 30
HSIO OF PC BOARD AD14/P4.6
55 31
HSII AOI5/P4.7
HSI2/HS04 44 T2CLK/P2.3 54 32
VU~~Mll~U~~D~~~~gg 53 33
U M
~~~.~Q~~«gQ~~~~n~~r

270090-5
270090-3
Figure 8. 68-Pin Package (LCC - Top View)
Figure 6. 68-Pln Package (PLCC - Top View)

Pins Facing Down RXD/P2.1 RESET

TXD/P2.0 EXTINT/P2.2
17 15 13 11 9 7 5 3 1'-,
HSIO VPD
18 19 16 14 12 10 8 6 4 2 68
HSII VREF ·
2021 6766
MCS<l!>-96 . HSI2/HS04 ANGND'
2223 6564
68 PIN
HSI3/HS05 ACH4/PO.4
2425 GRID ARRAY 6362
HSOO ACH5/PO.5
2627 61 60
TOP VIEW HSOI ACH7/PO.7
2829 5958
LOOKING DOWN ON HS02 ACH6/PO.6
3031 COMPONENT SIDE 5756
OF PC BOARD HS03 EA
3233 5554
34 36 38 40 42 44 46 48 50 53 52
vss Vce
vpp Vss
35 37 39 41 43 45 47 49 51
PWM/P2.5 XTAL1
270090-4
WRL/WR XTAL2

Figure 7. 68-Pin Package WRH/BHE ALE/ADV

(Pin Grid Array - Top View) READY RD
ADI5/P4.7 ADO/P3.0
ADI4/P4.6 AD1/P3.1
ADI3/P4.5 AD2/P3.2
ADI2/P4.4 AD3/P3.3
AD11/P4.3 AD4/P3.4
AD10/P4.2 AD5/P3.5
AD9/P4.1 AD6/P3.6
AD8/P4.0 AD7/P3.7

270090-2

Figure 9. 48-Pin Package

 8X9XBH

PIN DESCRIPTIONS
Symbol Name and Function
Vcc Main supply voltage (5V).
Vss Digital circuit ground (OV). There are two Vss pins, both of which must be connected.
VPD RAM standby supply voltage (5V). This voltage must be present during normal operation. In a Power
Down condition (i.e. Vee drops to zero), if RESET is activated before Vee drops below spec and VPD
continues to be held within spec., the top 16 bytes in the Register File will retain their contents. RESET
must be held low during the Power Down and should not be brought high until Vee is within spec and
the oscillator has stabilized.
VREF Reference voltage for the AID converter (5\1). VREF is also the supply voltage to the analog portion of '
the AID converter. and the logic used to read Port O.
ANGND Reference ground for the AID converter. Must be held at nominally the same potential as Vss.
VPP Programming voltage for the EPROM devices. It should be + 12. 75V for programming and will float to
5V otherwise. The pin should not be above Vee for ROM and CPU devices. This pin must be left
floating in the application circuit for EPROM devices.
XTAL1 Input of the oscillator inverter and of the internal clock generator.
XTAL2 Output of the oscillator inverter:
. CLKOUT*t Output of the internal clock generator. The frequency of CLKOUT is Ya the oscillator frequency. It has a
33% duty cycle.
RESET Reset input to the chip. Input low for a minimum 10 XTAL 1 cycles to reset the chip. The subsequent
low-to-high transition re-synchronizes CLKOUr and commences a 10-state-time sequence in which the
PSW is cleared, a byte read from 2018H loads CCR, and a jump to location 2080H is executed. Input
high/or normal operation. RESET has an internal pullup.
BUSWIDTH*t Input for bus width selection. If CCR bit 1 is a one, this pin selects the bus width for the bus cycle in
progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bitcycle occurs. If
CCR bit 1 is a 0, the bus is always an 8-bit bus. If this pin is left unconnected, it will rise to Vee.
NMI*t A positive transition causes a vector to external memory location 0000f:t. I:xternal memory from OOH
through OFFH is reserved for Intel development systems.
INST*t Output high during an external memory read indicates the read is an instruction fetch. INST is valid
throughout the bus cycle.
EA Input for memory select (External Access). EA equal to a TTL-high causes memory accesses to
locations 2000H through 3FFFH to be directed to on-Chip ROM/EPROM. EA equal to a TTL-low caUses
accesses to these locations to be directed to off-chip memory. EA = + 12.75V causes execution to
, begin in the Programming Mode. EA has an internal pulldown, so it goes to 0 unless driven otherwise.
ALE/ADV Address Latch Enable or Address Valid output, as selected by CCA. Both pin options provide a latch to
demultiplex the address from the address/data bus. When the pin is ADV, it goes inactive high at the
end of the bus cycle. ADV can be used as a chip select for a single external RAM memory. ALE/ ADV is
activated only during external memory accesses.
AD Read signal output to external memory. RD is aqtivated only during external memory reads.
WR/WRI Write and Write Low output to external memory, as selected by the CCR. WR will go low for every
external write, while WRL will go low only for external writes where an even byte is being written.
WR/WRL is activated only during external memory writes. ,
BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCA. BHE = 0 selects
the bank of memory thatis connected to the high byte of the data bus. AO = 0 selects the bank of
memory that is connected to the low byte of the data bus. Thus accesses to a 16-bit wide memory can
be to the low byte only (AO = 0, BHE ~ 1), to the high byte only (AO = 1, BHE = 0), or both bytes
(AO = 0, BHE = 0). If the WRH function is selected, the pin will go low if the bus cycle is writing to an
odd memory location.
"Not available on Shrink· DIP package
tNot available on 48·pin device

2·63
intJ 8X9XBH

PIN DESCRIPTIONS (Continued)

Symbol Name and Function
READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or
" for bus sharing. If the pin is high, CPU operation continues in a normal manner. ,If the pin is low
prior to the falling edge of CLKOUT, the memory controller goes into a wait mode until the next
positive transition in CLKOUr occurs with READY high. The bus cycle can be lengthened by up
to 1 ",s. When the external memory is not being used, READY has no effect. Internal control of
the number of wait states inserted into a bus cycle held not ready is available through
configuration of CCR. READY has a weak internal pullup, so it goes to 1 unless externally pulled
low.
HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2, and HSI.3. Two
of them (HSI.2 and HSI.3) are shared with the HSO Unit. The HSI pins are also used as inputs by
EPROM devices in Programming Mode.
HSO Outputs from High Speed Output Unit. Six HSO"pins are available: HSO.O, HSO.1, HSO.2, HSO.3,
HSO.4, and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
Port 0:1: 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog
inputs to the on-chip AID converter. These pins are also a mode input to EPROM devices in the
Programming Mode.
Port 1t 8-bit quasi-bidirectional I/O port.
Port2t 8-bit multi-functional port. Six of its pins are shared with other functions in the 8096BH, the
remaining 2 are quasi-bidirectional. These pins are also used to input and output control signals,
on EPROM devices in Programming Mode.
Ports 3 and 4 8-bit bi-directionall/O ports with open drain outputs. These pins are shared with the multiplexed
address/data bus which has strong internal pullups. Ports 3 and 4 are also used as a command,
address and data path by EPROM devices operating in the Programming Mode. When used as
ports, pull ups to Vee may be needed,
tNot available on 48-pin device
:rPort 0.0.1.2.3 not available on 48-pin device

2-64
 8X9XBH

AID Result LO (02H) .

~ 1 ,"~"a ""~'"
./0 II1
.
AID Command (02H)

CHANNEL # SELECTS WHICH OF THE 8

ANALOG INPUT CHANNELS IS TO BE
CONVERTED TO DIGITAL FORM.
.
r- SlATUS: : GO INDICATES WHEN THE CONVERSION IS TO

r; I--
3
I-- x
0 = AID CURRENTLY 10LE
1 = CONVERSION IN PROCESS
BE INITIATED (GO = 1 MEANS START NOW,
GO = 0 MEANS THE CONVERSION IS TO BE
INITIATED BY THE HSO UNIT AT A SPECIFIED TIME).
~r-x 270090-24
"6}
.2. AID RESULT:
LEAST SIGNIFICANT 2 BITS

SPCON/SPSTAT (11H)
270090-21

W
O'} BIT!. BITO SPECIFY THE MODE
00 = MODE 0 IO=MODE 2
R .2. 01 = MODE 1 11 = MODE 3
HSLMode (03H) I 2 - PEN ENABLE THE PARITY FUNCTION
~ 3 - REN ENABLES THE RECEIVE FUNCTION
I 7 61 s 41 3 21' 10 1 4 -TB8 PROGRAMS THE 9TH DATA BIT

L HSI.O ~ODE
5 -TI
S-RI
IS THE TRANSMIT INTERRUPT FLAG
IS THE RECEIVE INTERRUPT FLAG
HSI.l ~ODE
"7 -RBB
HSI.2
HSI.3
~ODE

~ODE
- RPE
IS THE 9TH DATA RECEIVED
(IF NOT PARITY)
IS THE PARITY ERROR INDICATOR
(IF PARITY ACTIVE)
WHERE EACH 2 - BIT MODE CONTROL FIELD 270090-26
DEFINES ONE OF 4 POSSIBLE MODES:

00 8 POSITIVE TRANSITIONS
01 EACH POSITIVE TRANSITION
10 EACH NEGATIVE TRANSITION Baud Rate Calculations
II EVERY TRANSITION UBlng XTAL 1:
(POSITIVE AND NEGATIVE) Mod 0: 8aud ~ XTAL 1 frequency. 8 ,. 0
.' e Rate 4"(8 + 1) •
270090-22
Oth . Baud ~ XTAL IIrequency
erB. Rate 64" (8 + 1)
UBlng T2CLK:
HSO Command (06H) M do O' 8aud ~ T2CLK frequency. 8 " 0
o • Rate B '
CHANNEL: • Baud _ T2CLK froquoncy . 8
Ot
o-s HSO.O - HSO.S hera. Rat~ - 16.8 ,"* 0
. BIT: 0]6 HSO.O AND HSO.l
Note that 8 cannot equal 0, except when u81ng XTAL 1 In other
7 HSO.2 AND HSO.3
than Mode O.
8-B SOFTWARE TI~ERS
2 E R£SET TIMER2
3 F START AID CONVERSION

INTERRUPT I NO INTERRUPT Chip Configuration

SET I CLEAR
O. CHIP CONFIGURATION REGISTER
moiER 2/TIMER 1 "'r'T"""'r'T"T'T"'r'
RESERVED (Set to 1 for
compatibility with futUre
port.)
'270090-23 BUS WIDTH SELECT •
(16-BIT BUS/8-BIT BUS)
WRITE STROBE MODE 'SELECT
(WI! AND m
1m AND WI!R)
HSI_Status (06H) ADDRESS VALID STROBE SELECT
(ALE/ ADV)
17 61 5 413 211 101 (IRCO) }'NTERNAL READY CONTROL
'-----(IRC1) MODE
L,HSI.O STATUS (LOCO) )
HSI.I STATUS L - - - - - - ( L O C 1 ) PROGRAM 1.0CK MODE

HSI.2 STATUS 270090'-32

HSI.3 STATUS
WHERE FOR EACH 2-111T STATUS FIELD THE LOWER
BIT INDICATES WHETHER OR NOT AN EVENT HAS
OCCURED ON THIS PIN AND THE UPPER BIT INDICATES
THE CURRENT STATUS OF THE PIN.
270090-25

2-65
inter 8X9XBH

Interrupt Pending/Mask Register

(LOCATION 08H, 09H)

17161514131211101

11 1 .
11 ~::,;~::~2E"
HSO EVENT
HSI BIT 0
SOFTWARE TIMERS
c--_ _ _ _ _ _ _ _ SERIAL I/O
' - - - - - - - - - - - EXTERNAL INTERRUPT
270090-55

PSW Register

lOCO (15H)* IOSO (15H)

HSI.O INPUT ENABLE / DISABLE HSO,O CURRENT STATE

TIMER 2 RESET EACH WRITE HSO.1 CURRENT STATE
HSI.1 INPUT ENABLE / DISABLE HSO.2 CURRENT STATE
TIMER 2 EXTERNAL RESET ENABLE / DISABLE 3 HSO.3 CURRENT STATE
HSI.2 INPUT ENABLE / DISABLE 4 HSO.4 CURRENT STATE
TIMER 2 RESET SOURCE HSI.O / T2RST 5 HSO.5 CURRENT STATE
HSI.3 INPUT ENABLE / DISABLE 6 CAM QB HOLDING REGISTER IS FULL
TIMER 2 CLOCK SOURCE: HSI.1 / f2ciJ( 7 HSO HOLDING REGISTER IS FULL
270090-30 270090-27

lOCO (15H)* IOC1 (16H)

T2RST - - 0 • - - IOCO.5 SELECT PWM / SELECT P2.5

r
~~'-----T2 RESET
EXTERNAL INTERRUPT ACH7 / EXTINT
• - - IOCO.3
• - - IOCO.O TIMER 1 OVERFLOW INTERRUPt ENABLE / DISABLE
HSI.O ~_------- HSI TIMER 2 OVERFLOW INTERRUPT ENABLE / DISABLE
. • - - IOCO.2 HSO.4 OUTPUT ENABLE / DISABLE
~)-------- HSI
HSI.1 ~ TIMER2
SELECT TXD / SELECT P2.0
HSO.5 OUTPUT ENABLE / DISABLE
T2CLK - - 0 :--IOCO.7 CLOCK
• - - IOCO.4 HSI INTERRUPT
""'-0_-----'---..... HSI
HSI.2 - - 0
FIFO FU LL /uHO;-'L:O:D"'INU'G"R"'E"GI;<'ST"'E'iiR'L"O;;:;AD"'E'liD

• -- IOCO.6
""'-0--------- HSI
HSI.3 - - 0
270090-31
270090-29

"See Errata section

2-66
 8X9XBH

Vector Location 1051 (16H)

Vector Priority
(High (Low
SOFTWARE .TlMER 0 EXPIRED
Byte) Byte)
SOFTWARE TIMER 1 EXPIRED
Software Trap 2011H 2010H Not Applicable
SOFTWARE TIMER 2 EXPIRED
Extint ·200FH 200EH 7 (Highest)
Serial Port 200DH 200CH 6 SOFTWARE TIMER :5 EXPIRED
Software 200BH 200AH 5 TIMER 2 HAS OVERFLOW
Timers TIMER 1 HAS OVERFLOW
HSI.O 2009H 2008H 4
HSI FIFO IS FULL
High Speed 2007H 2006H 3
Outputs HSI HOLDING REGISTER DATA AVAILABLE
HSI Data 2005H 2004H 2 270090-28
Available
AID Conversion 2003H 2002H 1
Complete
Timer Overflow 2q01H 2000H o (Lowest)

2-67
 8X9XBH

ELECTRICAL CHARACTERISTICS NOTICE: This data sheet contains' preliminary infor-

ABSOLUTE MAXIMUM RATINGS* mation on new products in production. The specifica-
tions are subject to change without notice.
Ambient Temperature Under Bias .... O°C to +70°C • WARNING: Stressing the device beyond the "Absolute
Storage Temperature .......... - 40°C to + 150°C Maximum Ratings" may cause permanent damage.
Voltage from EA or Vpp These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex-
to VSS or ANGND ........•.... ~O.3V to +13.0V
tended exposure beyond the "Operating Conditions"
Voltage from Any Other Pin to may affect device reliability.
VSS or ANGND .............. - O.3V to + 7.0V·
Average Output Current fro.m Any Pin ....... 10 mA
Power Dissipation .......................... 1.5W
'This includes Vpp on ROM and CPU only devices.

OPERATING CONDITIONS
(All characteristics in this data sheet apply to these operating conditions unless otherwise noted.)
Symbol Parameter Min Max Units
TA Ambient Temperature Under Bias 0 +70 °C
Vee Digital Supply Voltage 4.50 5.50 V
VREF Analog Supply Voltage 4.50 5.50 V
lose Oscillator Frequency 6.0 12 MHz !

Vpo Power-Down Supply Voltage 4.50 5.50 V

NOTE:
ANGND and Vss should be nominally at the same potential.

D.C. CHARACTERISTICS
Symbol Parameter Min Max Units Test Conditions
Icc Vee Supply Current (O'C ,;; TA ,;; 70'C) 240 mA All Outputs
Vee Supply Current (TA = 70'C) 185 mA Disconnected.
lee1
Ipo VPD Supply Current 1 mA Normal operation
and Power· Down.
IREF VREF Supply Current 8 mA
Vil Input Low Voltage -0.3 +0.8 V
VIH Input High Voltage (Except RESET, NMI, XTAL 1) 2.0 Vee +0.5 V
VIH1 Input High Voltage, RESET Rising 2.4 Vee +0.5 V
VIH2 Input High Voltage, RESET Falling (Hysteresis) 2.1 Vee +0.5 V
VIH3 Input High Voltage, NMI, XTAL 1 2.2 Vee +0.5 V
III Input Leakage Current to each pin 01 HSI, P3, P4, and to P2.1. ±10 p.A Vin = oto Vee ,
Ill1 D.C. Input Leakage Current to each pin 01 PO +3 p.A Yin = oto Vee
IIH Input High Current to EA 100 p.A VIH = 2.4V
IlL Input Low Current to each pin 01 P1, -125 p.A Vil = 0.45V
and to P2.6, P2.7.
IIL1 Input Low Current to RESET -0.25 -2 mA Vil = 0.45V
IIL2 Input Low Current P2.2, P2.3, P2.4, READY, BUSWIDTH -50 p.A Vil = 0.45V
VOL Output Low Voltage on Quasi·Bidirectional 0.45 V 1m = 0.8mA
port pins and P3, P4 when used as ports (Note 1)
VOL1 Output Low Voltage on Quasi·Bidirectional 0.75 V IOl = 2.0 mA
port pins and P3, P4 when used as ports (Notes 1, 2, 3)
,
VOl2 Output Low Voltage on Standard Output 0.45 V IOl = 2.0mA
pins, RESET and Bus/Control Pins (Notes 1, 2, 3)

2-68
intJ 8X9XBH

D.C. CHARACTERISTICS (Continued)

Symbol Parameter Min Max Units Test Conditions
VOH Output High Voltage on Quasi-Bidirectional 2.4 V IOH = -20 p.A
pins (Note 1)
VOH1 Output High Voltage on Standard Output 2.4 V IOH = - 200 p.A
pins and Bus/Control pins (Note 1)
IOH3 Output High Current on RESET -50 p.A VOH = 2.4V
Cs Pin Capacitance (Any Pin to Vss) 10 pF fTEST = 1.0 MHz

NOTES:
1. Quasi-bidirectional pins include those on P1, for P2.6 and P2.7. Standard Output Pins include TXD, RXD (Mode 0 only),
PWM, and HSO pins. Bus/Control pins include CLKOUT, ALE, BHE, RD, WR, INSTand ADO-15.
2. Maximum curtent per pin must be externally limited to the following values if VOL is held above 0.45V.
IOl on quasi-bidirectional pins and Ports 3 and 4 when used as ports: 4.0 mA
IOl on standard output pins and RESET: 8.0 mA
IOL on Bus/Control pins: 2.0 mA
3. During normal (non-transient) operation the following limits apply:
Total. IOL on Port 1 must not exceed 8.0 mAo
TotaiiOL on P2.0, P2.6, RESET and all HSO pins must not exceed 15 mA
Total IOl on Port 3 must not exceed 10 mAo
Total IOL on P2.5, P2.7, and Port 4 must not exceed 20 mAo

A.C. CHARACTERISTICS (Test Conditions: Load Capacitance on Output Pins = 80 pF)

TIMING REQUIREMENTS (Other system components must meet these specs.)

Symbol Parameter Min Max Units
TCLYX(2,3) READY Hold after CLKOUT Edge 0(1) ns

hLYV End of ALE/ ADV to READY Valid 2Tosc-70 ns

.- f - - - _ . _ . - - - - - - - - -1------
hLYH End of ALEI fS...DV to READY High 2Tosc+40 4Tosc-80 ns
"- --1 - - . _ - - - -1 - - - - - - - - - - -
TYLYH Non-Ready Time 1000 ns
- - -r - ' - - -
5Tosc-120(5) ns
_TAVDV(4)
. Address Valid to Input Data Valid
--c-.
TRLDV RD Active to Input Data Valid 3Tosc - 100(5) ns
- - -1---- -
TRHDX Data Hold after AD Inactive 0 ns
..- e--
TRHDZ AD Inactive to Input Data Float 0 Tosc-25 ns
.-1-------.----
TAVGV(2,4) Address Valid to BUSWIDTH Valid 2Tosc -125 ns
..---
TLLGX(2,3) BUSWIDTH Hold after ALE/ ADV Low Tosc +40 ns
--=-=,
TLLGV(2,3) ALE/ ADV Low to BUSWIDTH Valid Tosc -75 ns

TRLPV Reset Low to Ports Valid 10Tosc ns

..
NOTES:
1. If the 48-pin or 64-pin device is being used then this timing can be generated by assuming that the CLKOUT falling edge
has occurred at 2Tosc+55 (TLLCH(max) + TCHCL(max)) after the falling edge of ALE.
2. Pins not bonded out on 64-pin devices
3. Pins not bonded out on 48-pin devices.
4. The term "Address Valid" applies to ADO-15, BHE and INST.
5. If wait states are used, add 3Tosc * N where N = number of wait states.

2-69
 8X9XBH

TIMING RESPONSES (MCS-96 devices meet these specs)

Symbol Parameter Min Max Units
FXTAL Oscillator Frequency 6.0 12.0 MHz
Tosc Oscillator Period 83 166 ns
TOHCH XTAL 1 Rising Edge to Clockout Rising Edge 0(4) 120(4) ns
TCHCH(1,4) CLKOUT Period(3) 3Tos0(3) 3Tosc(3) ns
TCHCL(1,4) CLKOUT High Time Tosc-35 Tosc+ 10 ns
TCLLH(1,4) CLKOUT Low to ALE High -30 +15 ns
TLLCH(4) ALEI ADV Low to CLKOUT High(1) Tosc-25 Tosc+45 ns
hHLL ALEI ADV High Time Tosc-30 Tos6+35(5) ns
TAVLL(6) Address Setup to End of ALEI ADV Tosc-50 ns
TRLAZ(7) RD or WR Low to Address Float Typ. = 0 10 ns
hLRL End of ALEI ADV to RD or WR Active Tosc-40 ns
,
TLLAX(7) Address Hold after End of ALEI ADV Tosc-40 ns
TWLWH WR Pulse Width 3Tosc-35(2) ns
TOVWH Output Data Valid to End of WR/WRL/WRH 3Tosc-60(2) ns
TWHOX Output Data Hold after WR/WRL/WRH Tosc-50 ns
TWHLH End of WR/WRL/WRH to ALE/ADv High Tosc-75 ns
TRLRH RD Pulse Width 3Tosc-30(2) ns
TRHLH End of RD to ALEI ADV High Tosc-45 ns
TCLLL(4) CLOCKOUT Low(1) to ALEI ADV Low Tosc-40 Tosc+35 ns
TRHBX(4) RD High to INST(1), SHE, AD8-15 Inactive Tosc-25 Tosc+30 ns
TWHBX(4) WR High to INST(1), SHE, AD8-15 Inactive Tosc-50 Tosc+ 100 ns
THLHH WRL, WRH Low to WRL, WRH High 2Tosc-35 2Tosc+40 ns
TLLHL ALEI ADV Lowto WRL, WRH Low 2Tosc-30 2Tosc+55 ns
TOVHL Output Data Valid to WRL, WRH Low Tosc-60 ns

NOTES:
1. Pins not bonded out on 64-pin devices.
2. If more than' one wait state is desired, add 3Tosc for each additional wait state.
3. CLKOUT is directly generated as a divide by 3 of the oscillator. The period will be 3Tosc ± 10 ns if Tosc is constant and
the rise and fall times on XTAL 1 are less than 10 ns.'
4. CLKOUT, INST, and BHE pins not bonded out on 4S-pin and 64-pin devices.
5. Max spec applies only to ALE. Min spec applies to both ALE and ADV.
6. The term "Address Valid" applies to ADO-15, BRE and INST.
7. The term" Address" in this definition applies to ADO-7 for S-bit cycles, and ADO-15 for 16-bit cycles.
'/

2-70
 an+_r
' III-e- 8X9XBH

WAVEFORM
XTALI
CLOCKOUT
READY

.'. -_ .. -. --_.

AD -------<t~~~~~¢:~::::~~~~~::~~.:-:-:-:-:-:-:-:-:-~.~--
. ,

BHE,INST
~-- ...~--~------~--------~--~~-------------.
TAVLL.J ~I'---TWLWH~
AD8-15 -~(~IL)----<t::::::::::::::V~A~L~IDC:::::::::::~~·E·:-:-:-:-:-:-~-~-~-~-~-:-::-.
.. _----------- ...
270090-47

NOTES:
(1) 8-bit bus only.
(2) 8-bit or 16-bit bus and wrjte strcibe mode selected.
(3) When ADV selected.
(4) 8- or 16-bit bus and no write strobe mode selected.

WAVEFORM-BUSWIDTH PIN*

XTALt
CLKOUT

BUSWIDTH -~-----+----~''f-----;''''--''-------------------------
ALE/ ADV ____"
ADDRESS/DATA------1tJA~D~D~R~O~U~T:>-------_(~D~AT~A~IN~--------
270090-35

*Buswidth is not bonded out on 48- and 64-pin devices.

2-71
 8X9XBH

,
- __ Power Supply Rise Time

r - 5 •5V OC
i - - 4 •5V OC
Vce

9m'iw'~"~'i";m,m'~'~ii"ii'~~i~,~;~,m,,m;,~' ,~
.......
XTAL 0 ••" .
"-

RESET -I ~ Externol to Internal

Release Time
-I-
HSO.O-'HSO.3.
P2.0. P2.5
10 STATE TIMES
PORT3&4
WITH PULLUPS IADDRESS~ ADDRESS I
2018H cce 2080H
PROGRAM
TRLPV =10 XTAL CYCLES FIRST BUS FETCH CYCLE
START
External RESET Low to
Port Valid Time RESET (UNCTION REGISTERS
J
TOTAL 8X9X RESET TIME

270090-57

A.C. CHARACTERISTICS-SERIAL PORT--SHIFT REGISTER MODE

SERIAL PORT TIMING-SHIFT REGISTER MODE

Test Conditions: Load Capacitance = BO pF
Symbol Parameter Min Max Units
TXLXL Serial Port Clock Period BTose ns
TXLXH Serial Port Clock Falling Edge to Rising Edge 4Tose - 50 4Tose + 50 ns
TOVXH Output Data Setup to Clock Rising Edge 3Tose ns
TXHOX Output Data Hold After Clock Rising Edge 2Tose - 70 ns
TXHOV Next Output Data Valid After Clock Rising Edge 2Tose +50 ns
TDVXH Input Data Setup to Clock Rising Edge 2Tose +200 ns
TXHDX . Input Data Hold After Clock Rising Edge 0 ns
_.<-
TXHQZ Last Clock Rising to Output Float 5Tose ns

2-72
 8X9XBH

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE

SERIAL PORT WAVEFORM-SHIFT REGISTER MODE

RXD--"',~~J--",J~~J--",J~~J--"~~,--"~"--'r~"--'r~'r--\r~\r­
(IN)
270090-36

EXTERNAL CLOCK DRIVE

Symbol Parameter Min Max Units
1/TOlOl Oscillator Frequency 6 12 MHz
TOHOX High Time 25 ns

TOlOX Low Time 30 ns

TOlOH Rise Time 15 ns

TOHOl Fall Time 15 ns

EXTERNAL CLOCK DRIVE WAVEFORMS

270090-4B

Ar) external oscillator may encounter as much as a 100 pF load at XTAl 1 when it starts up. This is due to interaction
between the amplifier and its feedback capacitance. Once the external signal meets the VIL and VIH specifications the
capacitance will not exceed 20 pF. '

A.C. TESTING INPUT, OUTPUT WAVEFORM FLOAT WAVEFORM

VlOAO +O.20 V VOH -O.20 v

2.1.~ 2.0> TEST POINTS

0 . 4 5 ' - - / \ 0.8 .
< 2.0:
0.8 " - -
v LOAD
VLOAO -O.20 V
>TI~IN~~~isRENCE<
VOL +O.20·V

270090-51
270090-49 For Timing Purposes a Port Pin is no Longer Floating when a
A.C. Testing inputs are driven at 2.4V for a Logic "1" and 0.45V 200 mV change from Load Voltage Occurs, and Begins to Float
for a Logic "0". Timing measurements are made at 2.0V for a when a 200 mV change from the Loaded VOHIVOL Level occurs
Logie "1" and O.BV for a Logie "0". IOLIiOH ;;, ± 15 mAo

2-73
inter 8X9XBH

Minimum Hardware Configuration Circuits

47 p,r 47 p,r

270090-52 270090-53

2-74
 8X9XBH

AID CONVERTER SPECIFICATIONS

AID Converter operation is verified only on the 8097BH, 8397BH, 809SBH, 839SBH, 8797BH, 879SBH.

The absolute conversion accuracy is dependent on the accuracy of VREF.

Test Conditions: VREF = S.12V, AGND = Vss = OV
Parameter Typical" Minimum Maximum Units·· Notes
Resolution 1024 1024 Levels
1,0 10 Bits
Absolute Error 0 ±4 LSBs
Full Scale Error -O.S ±O.S LSBs·
Zero Offset Error ±O.S LSBs
Non-Linearity 0 ±4 LSBs
Differential Non-Linearity > -1 +2 LSBs
Channel-to-Channel Matching 0 ±1 LSBs
Repeatability ±0.2S LSBs
Temperature Coefficients:
Offset 0.009 LSBI"C
Full Scale 0.009 LSBI"C
Differential Non-Linearity 0.009 LSBrC
Off Isolation -60 dB 1,3
Feedthrough -60 dB 1
Vcc Power Supply Rejection -60 dB 1
Input Resistance 1K SK n
D.C. Input Leakage 0 3.0 fJ-A
Sample Delay 3Tosc - SO 3Tosc + SO ns 2
Sample Time 12Tosc - SO 12Tosc + 50 ns
Sampling Capacitor 2 pF
NOTES:
• These values are expected for most devices at 25'C.
•• An "LSB", as used here, is defined in the glossary which follows and has a value of approximately 5 mY.
1. DC to 100 KHz.
2. For starting the AID with an HSO Command.
3. Multiplexer Break-Before-Make Guaranteed.

2-75

•
inter 8X9XBH

EPROM SPECIFICATIONS

A.C. EPROM PROGRAMMING CHARACTERIST·ICS

Auto. Slave Mode Operating Conditions: Load Capacitance = 150 pF. TA = 25°C ±5°C. Vee. VPD. VREF =
5.0V ± 0.5V. Vss, AGND = OV. Vpp = 12.75V ± 0.25V. EA = 11V ± 2.0V. fose = 6.0 MHz

Run-time Programming Operating Conditions: Fose = 6.0 MHz to 12.0 MHz. Vee. VPD. VREF = 5V ± 0.5V.
TA = 25°C to ±5°C and Vpp = 12.75V ± 0.25V. For run-time prpgramming over a full operating range.
contact the factory.
Symbol Parameter Min Max Units
TAVLL ADDRESS/COMMAND Valid to PALE Low 0 Tose
TLLAX ADDRESS/COMMAND Hold After PALE Low 80 Tose
TDVPL Output Data Setup Before PROG Low 0 Tose
TpLDX Data Hold After PROG Falling 80 Tose
TLLLH ' PALE Pulse Width 180 Tose '
TpLPH PROG Pulse Width 250 Tose 100).LS +
144 Tose
TLHPL PALE High to PROG Low 250 Tose
TpHLL PROG High to Next PALE Low 600 Tose
TpHDX· Data Hold After PROG High 30 Tose
TpHVV PROG High to PVER/PDO Valid 500 Tose
TLLVH PALE Low to PVER/PDO High 100 Tose
TpLDV PROG Low to VERIFICATION/DUMP Data Valid 100 Tose
TSHLL RESET High to First PALE Low (not shown) 2000 Tose

D.C. EPROM PROGRAMMING CHARACTERISTICS

Symbol Parameter Min I Max Units
Ipp Vpp Supply Current (Whenever Programming) I 100 mA
Vpp Programming Supply Voltage 12.75 ±0.25 V
VEA EA Programming Voltage 11 ±2.0 V

NOTE:
Vpp must be within tV of Vee while Vee < 4.5V. Vpp must not have a low impedance path to ground or Vss while
Vee> 4.5V.
/

2-76
 8X9XBH

WAVEFORM-EPROM PROGRAMMING

r,..vLL

PORTS 3,4

PALE--_

PVER VALID VALID

----'

PDO VALID VALID

----' 270090-43

8X9XBH ERRATA Allowing more than seven FIFO entries to occur be·
tween cleared conditions will result in incorrect
Devices covered by this data sheet (see Revision status information for either the eighth or ninth con·
History) have the following errata. secutive entry. This effectively limits the total nUl\"
ber of records to seven.
1. INDEXED, 3 OPERAND MULTIPLY There is one exception that will allow the FIFO to
correctly record eight events. If the first two ,events
The displacement portion of an indexed, three oper·
of a cleared FIFO are separated by greater than 16
and (byte or word) multiply, may not be in the range
state times, the overflow conditions will always
of 200H thru 17FFH inclusive. If you must use these
cause the ninth event to be recorded with incorrect
displacements, execute an indexed, two operand
status information. This is true even if- the event fol·
multiply and a move if necessary.
lowing the first two were only separated by eight
states.
2. HIGH SPEED INPUT FIFO OPERATION
To ensure proper operation (no overflow) of the High 3. RESET AND THE QUASI BIDIRECTIONAL
Speed Input FIFO, it is imperative that any seven PORTS
consecutive FIFO entries be completely cleared be· Because RESET is asynchronous, it is possible to
fore further events occur at the pins. To clear the
apply RESET during writes to the quasi·bidirectional
FIFO, some repetitive variation of the following in·
port pins. If this occurs, the low impedance pullup
structions may be used ...
may not turn on, and only the high impedance pullup
READ.HSI.TASK: 01 : NO INTERRUPTS is turned on. This causes the quasi·bidirectional pins
RELOAD.HREG: JBC IOSI,7,RELOAD.HREG :, WAIT FOR to go to their RESET state (logical one) but will not
: HOLDING do so before expiration of TRLPV max.
: REGISTER TO
: LOAD
STB HSI.STAT, [PTR) + : READ THE
4. SOFTWARE RESET TIMING
: STATUS
The RESET pin will pull down for at least one state
ST HSI.TIME, [PTR) + : 'READ TIME TAG
time. if a software reset instruction executes or the
watchdog timer overflows. Earlier documentation in·
dicated two state times.

2·77
 8X9XBH

5. USING T2CLK AS THE SOURCE FOR TIMER2 Dif,ferences ,between -006 and -005 data sheets.
1. All EPROM programming mode information has
TIMER2 has two selectable clock sources, the been deleted and moved to the 16-Bit Handbook,
T2CLK or HSI.1 pins, selectable by bit IOCO.3. When Hardware Design Information chapter.
using T2CLK as the clock for TIMER2, writing to
lOCO may cause TIMER2 to ,increment. The user , 2. Shrink-DIP package information has been added.
should only write to lOCO once during ir;litializ~tion, , 3. A new RESET timing specification has been add-
and then immediately clear TIMER2 using the HSO ed for olarity.
. command OEH. Effectively, the customer cannot re- 4. Software Reset pin timing information has been
set TIMER2 with bit IOCO.1, and can only use the added.
external reset sources or the HSO command when
using T2CLK as the clock source. 5. HSO IOl specifications have been improved so
that all HSO pins have the same drive capability.
If the HSI.1 pin is the source for TIMER2, only the 6. Port 3 and Port 4 pin descriptions were clarified,
first write to lOCO may cause TIMER2 to increment, indicating the necessity of pullup if the pins are
further writes will not increment TIMER2. used as ports.
7. HSI FIFO overflow description added.
6. RESERVED LOCATION 2019H
Differences between the -005 and the -004 data
The 1990 Architectural Overview recommendeq that sheets.
address 2019H be loaded with OFFH. The recom- 1. The -005 data sheet corresponds to devices
mendation is now 20H. marked with a "0" at the end of the topside
tracking number. The -004 data sheet corre-
sponded to devices which are not marked with a
DATA SHEET REVISION REVIEW "0".
This data sheet (270090-007) is valid for devices 2. Much of the description of device functionality
marked with a "D" at the end of the topside tracking has been deleted. All of this information is al-
number: Data sheets are changed as new device ready in the Embedded controller handbooks in
information becomes available. Verify with your local the MCS-96 8096BH Architectural Overview
Intel sales office that you have the latest version Chapter.
before finalizing a design or ordering devices. 3. The A/D converter specification for Differential
Non-linearity has been changed to be a minimum
The following differences exist between this data of > -1 Isbs to a maximum of +'2 LSBs.
sheet and the previous version (-006). 4. 8X9XBH errata Section. The JBS and JBC on
1. T CCLH changed from Min = - 20 ns, Max = Port 0 errata has been fixed on the latest device
'+25 ns to Min = -30 ns, Max = + 15 ns. stepping.
2. TXHQX changed from Min = 2Tosc - 50 ns to -5. 8X9XBH errata Section. The errata for the 48-pin
Min = 2Tosc - 70 ns. devices has been fixed on the latest device step-
3. TOLOX changed from Min = 25 ns to Min = ping.This errata caused the upper 8 bits on the
30 ns, Address/Data bus to be latched when resetting
into an, 8-bit external memory system.
4. An errata was added changing the recommenda-
tipn for address 2019H from OFFH to 20H. 6. 8X9XBH errata section. An errata existed which
caused the device to be held in RESET for ex-
5. The power supply sequencing section has been tended periods of time with the internal RESET
deleted. The information is in the Hardware De- pin pulled down internally. The condition oc-
sign Information. curred when the XTAL inputs were driven before
6. The method of identifying the clirrent change in- Vcc was stable and within the data sheet specifi-
dicator was added to the differences between the cation. The condition was worse at cold. This er-
~005 and -004 data sheets. rata was not documented in the -004 data sheet.
7. A bug was not documented in the -004 data It has been fixed on the latest device stepping.
, sheet and was fixed before the -005 data. sheet. 7. 8X9XBH errata Section. Errata, 3 and 4 have
Information on the bug was added to the differ- been added to the errata list. These errata exist
ence between the -005 and -004 data sheets: for all steppings of the device.

2·78
 8X9XBH

Differences between the -004 and the -003 data 8. The EPROM programming section figures were
sheets. " corrected to indicate the correct interface to a
1. The bus control figures and bus timing diagrams 2764A-2. A reset circuit was added to these fig-
were modified to more accurately describe their ures and the signal PVAL (Port 3.X and Port 4.X)
operation. In particular the 8-bit bus modes now is now identified as the valid signal for program
reflect the use of Write Strobe Mode. verification in the Auto Programming Mode. Text
was added to this section to reference the re-
2. Additional text was added to the Analog/Digital quirement of using the Auto CQnfiguration Byte
description of the conversion process to clarify Programming Mode for 48-lead devices. Figure
its operation and usefulness. 22A was edited for corrections to the text, and
3. Text was added to the interrupt description sec- now indicates PVER (Port 2.0). The EPROM cir-
tion to indicate the maximum transition speed of cuits were cQrrected to show 6 MHz operation
the input signal relative to the CPU's state tim- for programming devices from internal micro-
ing. A figure was included to graphically demon- code. "
strate the interrupt response timing. 9. The protected memory section was edited to in-
4. The pin descriptions were modified to indicate dicate that the CPU will enter a "JUMP ON
that Vpp must normally float in the application. SELF" condition when ROM/EPROM dump
5. The input low voltage specification (VIU) was mode is complete.
deleted and is covered by the VIL specification. 10. An 8X9XBH ERRATA section was added.
6. A suggested minimum configuration circuit was 11. This REVISION REVIEW was added.
added to the material.
7. The AID Converter Specifications for Differen-
tial Non-Linearity has been corrected to be a
maximum of + 2 LSB's.

2-79
 MCS®-96
809XBH/839XBH/879XBH
EXPRESS
• Extended Temperature Range • Burn-In
( ~. 40°C to + 85°C)

The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-96 family of
microcontroliers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.

The EXPRESS program includes the commercial standard temperature range with burn-in, and an extended
temperature range with or without burn-in.

With the commercial standard temperature range operational characteristics are guaranteed over the temper-
ature range of O°C to + 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of -40°C to + 85°C.

The optionaL burn-in is dynamic, for a minimum time of 160 hours at 125°C with Vee 0= 5.5V ± 0.5V, following
guidelines in MIL-STD-883, Method 1015.

Package types and EXPRESS versions are identified by a one- or two-letter prefix to the device number. The
prefixes are list~d in Table 1.

This data sheet specifies the parameters which deviate from the commercial temperature range option. The
commercial temperature range data sheets are applicable otherwise. .

October 1990
2-80 Order Number: 270433-003
 8X9XBH EXPRESS

OPERATING CONDITIONS
Symbol Parameter Min Max Units
Ambient Temperature Under Bias -40 +85 °C

D.C. CHARACTERISTICS
Symbol Parameter Min Max Units Test Conditions
Icc Vcc Supply Current ( - 40°C S; T A S; + 85°C) 270 mA All Outputs
Disconnected.
ICC1 Vcc Supply Current (TA =. + 85°C) 185 mA

IREF VREF Supply Current 10 mA

IlL Input Low Current to each pin of P1 , -150 p.A VIL = 0.45V
and to P2.6, P2.7.

A.C. CHARACTERISTICS
Symbol Parameter Max Units
AD or WR Low to Address Float 25 ns

PACKAGING
Factory Masked User Programmable
CPU
ROM-
EPROM OTP
68 Pin 64 Pin 48 Pin 68 Pin 64 Pin 48 Pin 68 Pin 64 Pin 48 Pin 68 Pin 64 Pin 48 Pin
ANALOG 8397BH 8397BH 8395BH B097BH 8097BH 8095BH 8797BH 8795BH 8797BH 8797BH
NO ANALOG 8396BH 8096BH
48,pln deVIces have four Analog Input pIns.
64-pin devices have all 48'pin device featur!,s plus the following:
Four additional Analog input channels
One additional quasi·bidirectional 8-bit parallel port
Four additional port 2 pins with multiplexed features
Timer 2 clock source pIn
Timer 2 reset pin
Two additional quasi·bidirectional port pins
68,pln devices have all 48-' and 64-pin features plus the following:
Oynamic buswidth sizing (8. or t 6-bit bus)
Dedicated System Clock Output (CLKOUT)
INST pin for memory expansion
Non·Maskable interrupt for debugging
Package DeSIgnators:
N=PLCC
C = CeramIc DIP
A=Ceramlc Pin Grid Array
P = Plastic DIP
R = Ceramic LCC
U = Shrink DIP
Prefix Designators: •
T = Extended temperature
L = Extended temperature with 160 hours burn·in

2·81
irltef 8X9XBH EXPRESS

DATA SHEET REVISION REVIEW

This data sheet (270433-003) is valid for de.vices
with a "D" at the end .of the topside tracking num-
ber. Data sheets are changed as new device infor-
mation becomes available: Verify with your local
Intel sales office that you have the latest version
before finalizing a design or ordering devices.

The· following differences exist between this data

sheet and the previous version (-002).
1. All information except differences between the
standard and Express data sheets has been re-
moved.
2. Prefix designators for Express products were
added to the packaging section.

Differences between the -002 and the -001 data

sheets.
1, TRLPv-Reset low to ports valid specification
added for clarity.

2-82
 MCS®-96
809XJF,839XJF,879XJF
ADVANCED 16-BIT MICROCONTROLLER·
.WITH 8- OR 16-BIT EXTERNAL BUS
• 879XJF: an 809XJF with 16 Kbytes of On-Chip EPROM
• 839XJF: an 809XJF with 16 Kbytes of On-Chip ROM

• 232 Byte Register File

• High Speed I/O Subsystem

• 256 Bytes XRAM for Code

• Full Duplex Serial Port

• 10-Blt A/D Converter with S/H

• Dedicated, Baud Rate Generator

• Five 8-Bit 110 Ports

• 6.25 J.Ls 16 x 16 Multiply

• 20 Interrupt Sources
• 6.25 J.Ls 32/16 Divide

• Pulse-Width Modulated Output

• 16-Bit Watchdog Timer

• ROM/EPROM Lock
• Four 16-Bit Software Timers

• Run-Time Programmable EPROM (OTP) • Two 16-Bit Counter ITimers

The MCS-96 family of 16-bit microcontroliers consists of many members, all of which are designed for high-
speed cO,ntrol functions. The MCS-96 family members produced using Intel's HMOS-III process are described
in this data sheet.

The CPU supports bit, byte, and word operations. Thirty-two bit double-words are supported for a subset of the,
instruction set. With a 12 MHz input frequency the 8097 JF can do a i6-bit addition in 1.0 p.s and a16 x 16-bit
multiply or 32/16 divide in 6.25 p.s. Instruction execution times average 1 to 2 p.s in typical applications.

Four high-speed trigger inputs are provi,ded to record the times at which external events occur. Six high-speed
pulse generator outputs are provided to trigger external events at preset times. The high-speed output unit can
simultaneously perform software timer functions. Up to four 16-bit software timers can be in operation at once.

The on-chip AID converter includes a Sample and Hold, and converts up to 8 multiplexed analog input
channels to 10-bit digital values. With a 12 MHz crystal, each conversion takes 22 p.s.

Also provided on-chip are a serial port, a Watchdog Timer, and a pulse-width modulated output Signal.

POWER
VREF ANGND

•.-- -- --------- .

CONTROL
SIGNALS

,~-~/
l ~~~:
BUS

: PORT 4
I
,
I

PORT'O PORT 1 PORT2 HSI HSO

AL T FUNCTIONS
270795-1
Figure 1. MCS®·96 Bloc~ Diagram

November 1990
2-83 Order Number. 270795-003
 8X9XJF

OFFH 255,
POWER-DOWN
RAt.!
OFOH 240

OEFH 239
INTERNAL FFFFH
REGISTER rilE
(RAM) EXTERNAL MEMORY
OR I/o

lAH 26 6000H

5FFFH
19H 25 INTERNAL PROGRAM
STACK POINTER STACK POINTER STORAGE ROM/EPROM
18H 24 OR
17H PWM_CONTROL 23 EXTERNAL MEMORY
2080H
ISH 1051 lOCI 22
RE~ERVED 2072H - 207FH
ISH 1050 lOCO 21
SIGNATURE WORD 2070H - 2071H
14H 2Q
RESERVED 2030H - 20SFH
13H RESERVED RESERVED 19
SECURITY KEY 2020H - 202FH
12H 18
RESERVED 201CH - 201FH
llH SP_STAT SP_CON 17
SELF JUMP OPCODE (27H FEH) 201AH - 201BH
10H 10 PORT 2 10 PORT 2 IS
RESERVED 2019H
OFH , 10 PORT 1 10 PORT 1 15
CHIP CONFIGURATION BYTE 2018H
OEH 10 PORT 0 BAUD_RATE 14'
RESERVED 2012H - 2017H
ODH TlMER2 (HI) 13

OCH TlMER2, (LO) RESERVED 12

INTERRUPT VECTORS
OBH TIMER 1 (HI) 11
2000H
OAH TIMERI (LO) WATCHDOG 10
PORT 4 lFFFH
09H INLPENDING INT_PENDING
PORT 3 lFFEH
08H INT_MASK INT_MASK
EXTERNAL MEMORY
07H SBUF (RX) SBUF (TX) OR I/O 01FFH
OSH HSLSTATUS HSO_COMMAND
EXECUTABLE
05H HSLTlME (HI) HSO_ TIME (HI) INTERNAL RAM
(XRAM)
04H HSLTlME (lO) HSO_TIME (LO)
L- 0100H
03H AD_RESULT (HI) HSLMODE OOFFH
INTERNAL RAM
02H AD_RESULT (lO) AD_COMMAND REGISTER rilE
STACK POINTER
01H RO (HI) RO (HI) SPECIAL FUNCTION REGISTERS
(WHEN ACCESSED AS DATA MEMORY)
OOH RO (lO) RO (lO) OOOOH

(WHEN READ) (WHEN WRITTEN)

270795-2

Figure 2. Memory Map

2-84
inter 8X9XJF

PACKAGING
The 8097JF is available in 64·pin and 68·pin packages, with and without on·chip ROM or EPROM. The 8097JF
numbering system is shown in Figure 3. Figures 4-6 show the pinouts for the 64· and 68·pin packages. The
64·pin version is offered in a Shrink·DIP package while the 68·pin versions come in a Plastic Leaded Chip
Carrier (PLCC).

MCS96 PACKAGING 8X9XJF

User Programmable
Factory CPU
Masked ROM EPROM' OTP
68·PinI 64·Pin I 48·Pin 68·Pin I 64·Pin I48·Pin 68·Pin I64·Pin I48·Pin I 64·Pin I48·Pin
68·Pin
8397JF I 8397JF I 8097JF 18097JF I I I 8797JF18797JF I

Package Designators:
N = PLeC
C = Ceramic DIP
A = Ceramic Pin Grid Array
P = Plastic DIP
R = Ceramic LCC
U = Shrink DIP
Figure 3. The 809XJF Family Nomenclature

PLCC Description PLCC Description PLCC Description

9 ACH7 IPO.7 IPMOD.3 54 AD6/P3.6 31 P1.6
8 ACH6/PO.6/PMOD.2 53 AD7/P3.7 30 P1.5
7 ACH2/PO.2 52 AD8/P4.0 29 HSO.1
6 ACHO/PO.O 51 AD9/P4.1 , 28 : HSO.O
5 ACH1/PO.1 50 AD10/P4.2 27 HSO.5/HSI.3
,
4 ACH3/PO.3 49 AD11/P4.3 26 HSO,4/HSI.2
3 NMI 48 AD12/P4,4 25 HSI.1
2 EA 47 AD13/P4.5 24 HSI.O
1 VCC 46 AD14/P4.6 23 P1,4
68 VSS 45 AD15/P4.7 22 P1.3
67 XTAL1 44 T2CLK/P2.3 21 P1.2
66 XTAL2 43 READY 20 P1.1
65 CLKOUT 42 T2RST/P2,4 19 P1.0
64 SUSWIDTH 41 SHE/WRH .. 18 TXD/P2.0/PVERISALE
63 INST 40 WR/WRL . 17 RXD/P2.1/PALE
-
62 ALE/ADV 39 PWM/P2.5/Pi50/SPROG 16 RESET
61 RD 38 P2.7 15 EXTINTIP2.2/PROG
60 ADO/P3.0 37 VPP
-_._-_. 14 VPD
59 AD1/P3.1 36 VSS 13 VREF
,
58 AD2/p3.2 35 HSO.3 12 ANGND
57 AD3/P3.3 34 HSO.2 11 _. ACH4/PO,4/PMOD.O
r----'
56 AD4/P3,4 33 P2.6 10 ACH5/PO.5/PMOD.1
55 AD5/P3.5 32 P1.7
--'--. ----- -
Figure 4. PLCC Function Pinout

2·85
 8X9XJF

SDIP Description SDIP Description SDIP Description

1 EA 23 HSI.1 45 AD13/P4.5
2 ACH3/PO.3 24 HSO.4/HSI.2 46 AD12/P4.4
3 ACH1/PO.1 25 HSO.5/HSI.3 47 AD11/P4.3
4 ACHO/PO.O 26 HSO.O 48 AD10/P4.2
S ACH2/PO.2 27 HSO.1 49 AD9/P4.1
6 ACH6/PO.6/PMOD.2 28 P1.5 50 AD8/P4.0
7 ACH7/PO.7/PMOD.3 29 P1.6 51 AD7/P3.7
8 ACHS/PO.5/PMOD.1 30 P1.7 52 AD6/P3.6
9 ACH4/PO.4/PMOD.0 31 P2.6 53 AD5/P3.5
10 ANGND 32 HSO.2 54 AD4/P3.4
11 VREF 33 HSO.3 55 AD3/P3.3
12 VPD 34 Vss 56 AD2/P3.2
13 EXINTIP2.2/PROG 35 Vpp 57 AD1/P3.1
14 RESET 36 P2.7 58 ADO/P3.0
15 RXD/P2.1/PALE 37 PWM/P2.5/PDO/SP~OG 59 RD
16 TXD/P2.0/PVERISALE 38 WR/WRL 60 ALE/ADV
17 P1.0 39 BHE/WRH 61 XTAL2
18 P1.1 40 T2RST/P2.4 62 XTAL1
19 P1.2 41 READY 63 Vss
20 P1.3 42 T2CLK/P2.3 64 Vee
21 P1.4 43 AD15/P4.7
22 HSI,O 44 AD14/P4.6
Figure 5. SDIP 8X97JF Pin Out

987.5.32 l~D~~M~~~

ACHS/PO 5 10 --------(_ 60 ADO/P! 0

ACH4/PO.4 11
ANGND 12
VREF' 13 ADl/P3.!
Vpo 14
MCS®-96
AD4/P! "
EXTINT/PZ 2 15 68 PIN A05/P3.5
RESET PLCC ADS/Pl.e
RXD/P2,' AD7/P;S.7
TXO/P2.0 18 52 AOS/P4.0
51 A09/P4,1
TOP VIEW 50 A010/P4.2

LOOKING DOWN ON

.
Pl.!
COMPONENT SIDE
OF PC BOARD " AOI3/P4.S
A014/P4.6

HSI2/HS04 26 44 T2CLK/P2 '.5

27 28 29 30 31 3Z 33 343536 37 38 39 40 41 4243

270795-3

Figure 6.. 68-Pin Package (PLCC - Top View)

270795-4

Figure 7. Shrink-DIP Package

2-86
inter 8X9XJF

PIN DESCRIPTtONS
Symbol Name and Function
Vee Main supply voltage' (5V).
Vss DiQital circuit ground (OV). There are two Vss pins, both of which must be connected.
VPD RAM standby supply voltage (5V). This voltage must be present during normal operation.
In a Power Down condition (i.e. Vee drops to zero), if RESET is activate,d before Vee drops
below spec and V PD continues to be held within spec., the top 16 bytes in the Register File
will retain their contents. RESET must be held low during the Power Down and should not
be brought high until Vee is within spec and the oscillator has stabilized.
VREF Reference vQltage for' the A/D converter (5V). VREF is also the supply voltage to the
analog portion of the AID converter and the logic used to re~d Port O.
ANGND Reference ground for the AID converter. Must be held at nominally the same potential as
Vss·
Vpp , Programming voltage for the EPROM pevices. It should be + 12. 75V for programming and
will float to 5V otherwise. It should not be above Vee for ROM or CPU devices. This pin
must be left floating in the application circuit for EPROM devices.
XTAL1 Input of .the oscillator inverter and of the internal clock generator.
XTAL2 Output of the oscillator inverter.
CLKOUT* Output of. the internal clock generator. The frequency of CLKOUT is % the oscillator
frequency. It has a 33% duty cycle.
RESET Reset inPut to the chip. Input low for a minimum of 10 XTAL 1 cycles to reset the chip. The
subsequent low-to-high transition re-synchronizes CLKOUT and commences a 10-state-
time sequence in which the PSW is cleared, a byte read from 2018H .Ioads CCR, and a
jump to location 20BOH is executed. Input high for normal operati.on. RESET has an
internal pull up.
BUSWIDTH* Input for bus width selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-
bit cycle occurs. If CCR bit 1 is a 0, the bus is always an B-bit bus. If this pin is left
unconnected, it will rise to Vee.
NMI* A positive transition causes a vector to external memory location OOOOH. External memory
from OOH through OFFH is reserved for Intel development systems.
INST* Output high during an external memory read indicates the read is an instruction fetch. INST
is valid throughout the bus cycle.
EA Input for memory select (External Access). EA equal to a TTL-high causes memory
accesses to locations 2000H through 5FFF to be directed to on-chip ROM/EPROM. EA .
equal to a TTL-low causes accesses to these locations to be directed to off-chip memory.
EA == + 12.75V causes execution to begin in the Programming Mode. EA has an internal
. pulldown, so it goes to 0 unless driven otherwise. . ,
ALE/ADV Address Latch Enable or Address Valid output, as selected by CCA. Both pin options
a
provide latch to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ADV can be used as a chip select for
a single external RAM memory. ALE/ ADV is activated only during external memory
accesses.
'Not avaIlable on Shrink-DIP package

2-B7
 8X9XJF

PIN DESCRIPTIONS (Continued)

Symbol Name and Function
RD Read signal output to external memory. RD is activated only during external memory
reads.
WR/WRL Write and Write Low output to external memory, as selected by theCCR. WR will go
low for every external write, while WRL will go low only for external writes where an
even byte is being written. WR/WRL is activated only during external memory writes.
SHE/WRH Sus High Enable or Write High output to external memory, as selected by the CCR.
SHE = 0 selects the bank of memory that is connected to the high byte of the data
bus. AO = 0 selects the bank of memory that is connected to the low byte of the
data bus. Thus accesses to a 16-bit wide memory can be to the low byte only tAO =
0, SHE = 1), to the high byte only (AO = 1, SHE = 0), or both bytes (AO = 0, SHE
= 0). If the WRH function is selected, the pin will go low if the bus cycle is writing to
an odd memory location.
READY Ready input to lengt~en external melT)ory cycles, for interfacing to slow or dynamic
memory, or for bus sharing. If the pin is high, CPU operation continues in a normal
manner. If the pin is low prior to the falling edge of CLKOUT, the memory controller
goes into a wait mode until the next positive transition in CLKOUT occurs with
READY high. The bus cycle can be lengthened by up to 1 JLs. When the external
memory is not being used, READY has no effect. Internal control of the number of
wait states inserted into a bus cycle held not ready is available through configuration
of CCA. READY has a weak internal pullup, so it goes to 1 unless externally pulled
low.
HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2, and
HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. The HSI pins are
also used as inputs by EPROM devices in Programming Mode.
HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1,
HSO.2, HSO.3, HSO.4, and HSO.5. Two of them (HSO.4 and HSO.5) are shared with
theHSI Unit.
PortO 8-bit high impedance input-only port. These pins can be used as digital inputs and/or
as analog inputs to the on-chip A/D converter. These pins are also a mode input to
EPROM devices in the Programming Mode.
Port 1 8-bit ql,lasi-bidirectionall/O port.
Port 2 8-bit multi-functional port. Six of its pins are shared with other fl,lnctions in the
8096JF, the remaining 2 are quasi-bidirectional, These pins are also used to input
and output control signals on EPROM devices in Programming Mode.
Ports 3 and 4 8-bit bi-directionalllO ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups. Ports 3 and 4 are
also used as a command, a,ddress and data path by EPROM devices operating in the
Programming Mode. When used as ports, pullups to Vee may be needed.

2-88
 8X9XJF

AID Result LO (02H) AID Command (02H)

-: 1 AID CHANNEL NUMBER

11 1
*
CHANNEL SELECTS WHICH Of THE 8
ANALOG INPUT CHANNELS IS TO BE
CONVERTED TO DIGITAL roRM.

+::
-
3 -
STATUS:
0 = A/O CURRENTLY IDLE
1 = CONVERSION IN PROCESS
: GO INDICATES WHEN THE CONVERSION IS TO
BE INITIATED(GO = 1 MEANS START NOW,
GO = 0 MEANS THE CONVERSION IS TO BE
INITIATED BY THE HSO UNIT AT A SPECIFIED TIME).
270795-9
-_6 } A/O RESULT:
7 LEAST SIGNIFICANT 2 BITS

270795-5
SPCON/SPSTAT(11H)
';} BIT1, BITO SPECIFY THE NODE
W OO=MODEO 10=MODE2
. HSI_Mode (03H)
R r2- 01 = MODE 1 11 = MODE 3
I 2 - PEN ENABLE THE PARITY FUNCTION

17 I 5 41 3 ~ - REN ENABLES THE RECEIVE FUNCTION

6 2 1'1 0 1
4 - TBB PROGRAMS THE 9TH DATA BIT
L HSI.O MODE R 5 - TI IS THE TRANSMIT INTERRUPT FLAG
HSI.l MODE ! rs - RI IS THE RECEIVE INTERRUPT FLAG
HSI.2 MODE o f-;" - RBS IS THE 9TH DATA RECEIVED
HSI.3 MODE ...... (IF NOT PARITY)
/ RPE IS THE PARITY ERROR INDICATOR
WHERE EACH 2 - BIT MODE CONTROL FIELD . (If PARITY ACTIVE)
DEFINES ONE OF 4 POSSIBLE MODES:
270795-10
00 8 POSITIVE TRANSITIONS
01 EACH POSITIVE TRANSITION
10 EACH NEGATIVE TRANSITION.
11 EVERY TRANSITION Baud Rate Calculations
(POSITIVE AND NEGATIVE) Using XTAL 1:
270795-6 Mod o· Baud ~ XTAL !frequency • B '" 0
e . Rate 4'(8 + 1) •
Othe . Baud = XTAL 1 frequency
rs. Rate 64* (B + 1)
HSO Command (06H) Using T2CLK:
ModeO.• Baud - T2CLK frequency. B
Rate - B • '* 0
CHANNEL:
0-5 HSO.O - HSO.5 Baud T2CLK frequency
BIT: 0]6 HSO.O AND HSO.l Others: Rate = 16'8 j B =1= 0
7 HSO.2 AND HSO.3
Note that B cannot equal 0, except when using XTAL 1 In other
8-B SOFTWARE TIMERS
than Modo O.
E RESET TlMER2
F START A / 0 CONVERSION

4 INTERRUPT / NO INTERRUPT
5 SET /CLEAR
Chip Configuration
6 TIMER 2/TIMER 1 1.rl1.r-l""'~""''''..t.,.I0 CHIP CONfiGURATION REGISTER
7 X RESERVED (Set to 1 for
compatibility with future
. 270795-7 ports)
BUS WIDTH SELECT
(16-BIT Bus/s-BIT BUS)
WRITE STROBE MODE SELECT
HSLStatus (06H) (ViR AND I am: m
AND Wlrn)
ADDRESS VALID STROBE SELECT
(ALEi ADV)

HSI.O STATUS (IRCO) }INTERNAL READY CONTROL

'------(IRC1). MODE
'----HSI.l STATUS
' - - - - - - - H S I . 2 STATUS (LOCO) )
' - - - - - - - ( L O C 1 ) PROGRAM LOCK MODE
' - - - - - - - - - H S I . 3 STATUS
270795-11
WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
BIT INDICATES WHETHER OR NOT AN EVENT HAS
OCCUR EO ON THIS PIN AND THE UPPER BIT INDICATES
THE CURRENT STATUS OF THE PIN.
270795-8

2-89
intJ 8X9XJF

Interrupt Pending/Mask Register

(LOCATION 98H, 09H)

17161514131211101

II i ..
I I ~:Z!~~::S~:E"
HSO EVEN;
HSI BIT 0
SOFTWARE TIMERS
L -_ _ _ _ _ _ _ SERIAL I/O
' - - - - - - - - - - - EXTERNAL INTERRUPT
270795-12

P5W Register

lOCO (15H) 1050 (15H)

HSI.O INPUT ENABLE /DISABLE HSO.O CURRENT STATE

TIMER 2 RESET EACH WRITE HSO.l CURRENT STATE
HSI.l INPUT ENABLE / DISABLE HSO.2 CURRENT STATE
TIMER 2 EXTERNAL RESET ENABLE / DISABLE HSO.3 CURRENT STATE
HSI.2 INPUT ENABLE / DISABLE HSO.4 CURRENT STATE
TIMER 2 RESET SOURCE HSI.O / T2RST HSO.5 CURRENT STATE
HSI.3 INPUT ENABLE / DISABLE CAM Q.!! HOLDING REGISTER IS FULL
TIMER 2 CLOCK SOURCE HSl.l /T2CLK 7 HSO HOLDING REGISTER IS FULL
270795-13 270795-15

lOCO (15H) IOC1 (16H)

I
T2RST - - 0 • - . IOCO.5 SELECT PWM / SELECT P2.5
~~---- T2 RESET
EXTERNAL INTERRUPT ACH7 / EXTINT
. • -.10. CO.3
; _. 10CO.O TIMER 1 OVERFLOW INTERRUPT ENABLE / DISABLE
HSI.O ~------- HSI TIMER 2 OVERFLOW INTERRUPT ENABLE / DISABLE
• _. IOCO.2 HSO.4 OUTPUT ENABLE / DISABLE
..c~------- HSI SELECT TXO / SELECT P2.0
HSI.l ~ m.4ER2
T2CLK - - 0 . -. IOCO.7 CLOCK HSO.5 OUTPUT ENABLE / DISABLE

• _. 10COA 7 HSI INTERRUPT

~------- HSI
FIFO FULL / "'HO"'L""O"'"IN""G'""'R"'E""GI""ST""E""R-;L""'O";";AO""'E"'O
HSI.2 - - 0
270795-16
• -. IOCO.6
HSI;3 - - 0 ~-------- HSI
270795-14

2-90
inter 8X9XJF

Vector Location
IOS1'(16H)
Vector Priority
(High (Low
Byte) Byte) SOFTWARE TIMER 0 EXPIRED

Software Trap 2011H 2010H Not Applicable SOFTWARE TIMER 1 EXPIRED

Extint 200FH 200EH 7 (Highest) SOFTWARE TI~ER 2 EXPIRED
Serial Port 200DH 200CH 6 SOFTWARE TIMER 3 EXPIRED
Software 200BH 200AH 5
TIMER 2 HAS OVERFLOW
Timers
HSI,O 2009H 2008H 4 TIMER 1 HAS OVERFLOW
High Speed 2007H 2006H 3 HSI FIFO IS FULL
Outputs HSI HOLDING, REGISTER DATA AVAILABLE
HSI Data 2005H 2004H 2
270795-17
Available
, AID Conversion 2003H 2002H 1
Complete
Timer Overflow 2001H 2000H o (Lowest)

2-91
inter 8X9XJF

ELECTRICAL CHARACTERISTICS NOTICE: This data sheet contains information on

ABSOLUTE MAXIMUM RATINGS* products in the sampling and initial production phases
of development. It is valid for the devices indicated in
Ambient Temperature Under Bias .... O°C to + 70°C the revision history. The specifications are subject to
change without notice. .
Storage Temperature .......... -40°C to + 150°C
Voltage from EA or Vpp • WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
to VSS or ANGND ............ -O.3Vto + 13.0V These are stress ratings only. Operation beyond 'the
Voltage from Any Other Pin to "Operating Conditions~' is not recommended and ex-
VSS or ANGND .............. -O.3V to + 7.0V· tended exposure beyond the "Operating Conditions"
Average Output Current from Any Pin ....... 10 mA may affect device reliability.
Power Dissipation .......................... 1.5W
'This includes Vpp on ROM and CPU only devices.

OPERATING CONDITIONS
(All characteristics specified in this data sheet apply to these operating conditions unless otherwise noted.)

Symbol Parameter Min Max Units

TA Ambient Temperature Under Bias 0 +70 'C
Vee Digital Supply Voltage 4.50 5.50 V
VREF Analog Supply Voltage 4.50 5.50 V
lose Oscillator Frequency 6.0 12 MHz
VPD Power-Down Supply Voltage 4.50 5.50 V

NOTE:
ANGND and Vss should be nominally at the same potential.

D.C. CHARACTERISTICS
Symbol Parameter Min Max Units Test Conditions
lee Vee Supply Current (O'C ,,; TA ,,; 70'C) 300 mA All Outputs
Disconnected.
lecl Vee Supply Current (TA = 70'C) 245 mA
IpD VPD Supply Current 1 mA Normal operation
and Power-Down.
IREF VREF Supply Current 8 mA
VIL Input Low Voltage -0.3 +0.8 V
VIH Input High Voltage (Except RESET, NMI, XTAL 1) 2.0 Vee +0.5 V
VIHl Input High Voltage, RESET Rising 2.4 Vee +0.5 V
VIH2 Input High Voltage, RESET Falling (Hysteresis) 2.1 Vee +0.5 V
VIH3 Input High Voltage, NMI(4), XTAL 1 2.2 Vee +0.5 V
lu Input Leakage Current to each pin 01 HSI, P3, P4, and to P2.1. ±10 p.A Yin = OtoVec
IUl D.C. Input Leakage Current to each pin 01 PO +3 p.A Yin = OtoVee
IIH Input High Current to EA 100 p.A VIH = 2.4V
IlL Input Low Current to each pin 01 P1, -125 p.A VIL = 0.45V
and to P2.6, P2.7.
IILl Input Low Current to RESET -0.25 -2 mA Vil = 0.45V
IIl2 Input Low Current P2.2, P2.3, P2.4, READY, BUSWIDTH -50 p.A Vil = 0.45V
VOL o ' Output Low Voltage on Quasi-Bidirectional 0.45 V IOL = 0.8 mA
port pins and P3, P4 when used as ports (Note 1)
.vOll Output Low Voltage on Quasi-Bidirectional 0.75 V IOL = 2.0 mA
port pins and P3, P4 when used as ports (Notes 1, 2, 3)
VOL2 Output Low Voltage on Standard Output 0.45 V IOL'= 2.0 mA
pins, RESET and Bus/Control Pins (Notes 1, 2, 3)

2-92
 8X9XJF

D.C. CHARACTERISTICS (Continued)

Symbol Parameter Min Max Units Test Conditions
VOH Output High Voltage on Quasi-Bidirectional 2.4 V IOH = -20,...A
pins (Note 1)
VOH1 Output High Voltage on Standard Output 2.4 V IOH = -200,...A
pins and Bus/Control pins . (Note 1)
IOH3 Output High Current on RESET -50 ,...A VOH = 2.4V
Cs Pin Capacitance (Any Pin to Vss) 10 pF fTEST = 1.0 MHz

NOTES:
1. Quasi-bidirectional pins include those on P1, for P2.6 and P2.7. Standard Output Pins include TXD, RXD (Mode 0 only),
PWM, and HSO pins. Bus/Control pins include CLKOUT, ALE, BHE, RD, WR, INST and ADO-15.
2. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V.
IOL on quasi-bidirectional pins and Ports 3 and 4 when used as ports: 4.0 mA
IOL on standard output pins and RESET: 8.0 mA
IOL 6n Bus/Control pins: 2.0 mA
3.During normal (non-transient) operation the following limits apply:
TOlaiioL on Port 1 must not exceed 8.0 mAo
Total IOL on P2.0, P2.6, RESET and all HSO pins must not exceed 15 mAo
TotalloL on Port 3 must not exceed 10 mA.
TotaiiOL on P2.5, P2.7, and Port 4 must not exceed 20 mA.

A.C. CHARACTERISTICS
Test Conditions: Load Capacitance on Output Pins = 80 pF

TIMING REQUIREMENTS (Other system components must meet these specs)

Symbol Parameter M'jn Max Units
TCLYX(3) READY Hold after CLKOUT Edge 0(1) ns

TLLYV End of ALE/ ADV to READY Valid 2Tosc-70 ns

TLLYH End of ALE/ ADV to READY High 2Tosc+40 4Tosc-80 ns

TYLYH Non-Ready Time 1000 ns

TAVDV(2) Address Valid to Input Data Valid 5Tosc -120(4) ns

TRLDV RD Active to Input Data Valid 3Tosc -1 00(4) ns

TRHDX Data Hold after RD Inactive 0 ns

TRHDZ RD Inactive to Input Data Float 0 Tosc-25 ns

TAVGV(2,3) Address Valid to BUSWIDTH Valid 2Tosc -125 ns
TLLGX(3) BUSWIDTH Hold after ALE/ ADV Low Tosc +40 ns
TLLGv(3) ALE/ ADV Low to BUSWIDTH Valid Tosc -100 ns

TRLPV Reset Low to Ports Valid 10Tosc ns

NOTES:
1. If the 64-pin device is being used then this timing can be generated by assuming that the CLKOUT falling edge has
occurred at 2Tosc+55 (TLLCH(max) + TCHCL(max)) after the falling edge of ALE.
2. The term "Address Valid" applies to ADO-15, BHE and INST.
3. Pins not bonded out on 64-pin devices.
4. If wait states are used, add 3Tosc • N where N = number of wait states.
inter 8X9XJF

TIMING RESPONSES (MCS·96 devices meet these specs.)

Symbol Parameter Min Max Units
FXTAL ' Oscillator Frequency 6.0 12.0 MHz

Tosc Oscillator Period 83 166 ns

TOHCH(3) XT AL 1 Rising Edge to Clockout Rising Edge 0 120 ns
TCHCH(3) CLKOUT Period 3Tosc(2) 3Tosb(2) ns
TCHCL(3) CLKOUT High Time Tosc-35 Tosc+ 10 ns
TCLLH(3) CLKOUT Low to ALE High -30 + 15 ns
TLLCH(3) ALE/ ADV Low to CLKOUT High Tosc-25 Tosc+45 ns

hHLL ALE/ ADV High Time Tosc-30 Tosc+35(4) ns

TAVLL(5) Address Setup to End of ALE/ ADV Tosc-50 ns'
TRLAZ(6) RD or WR Low to Address Float Typ. = 0 10 ns

TLLRL End of ALE/ ADV to RD or WR Active Tosc-40 ns

TLLAX(6) Address Hold after End of ALE/ ADV Tosc-40 ns

TWLWH WR Pulse Width 3Tosc-35(1) ns

TaVWH Output Data Valid to End of WR/WRLlWRH 3Tosc-60(1) ns

TWHax Output Data Hold after WR/WRL/WRH . Tosc-' 50 ns

TWHLH End of WR/WRL/WRH to ALE/ ADV High Tosc-75 ns

TRLRH RD Pulse Width 3Tosc-30(1) ns

TRHLH End of RD to ALE/ ADV High Tosc-45 ns

TCLLL(3) CLOCKOUT Low to ALE/ ADV Low Tosc-40 Tosc+35 ns
TRHSX(3) RD High to INST, SHE, AD8·15 Inactive Tosc-25 Tosc+30 ns
TWHSX(3) WR High to INST, SHE, AD8·15 Inactive Tosc-50 Tosc+ 100 ns

THLHH WRL, WRH Low to WRL, WRH High 2Tosc-35 2Tosc+40 ns

hLHL ALE/ ADVlow to WRL, WRH Low 2Tosc-30 2Tosc+ 55 ns

TaVHL Output Data Valid to WRL, WRH Low Tosc-60 ns

NOTES:
1.lf more than one wait state is desired, add 3Tosc for each additional wait state. ,
2. CLKOUT is directly generated as a divide by 3 of the oscillator. The period will be 3Tosc ± 10 ns if Tosc is constant and
the rise and fall times on XTAL 1 are less tnan 10 ns.
3. CLKOUT, INST, and SHE pins not bonded out on 64·lead package.
4. Max spec applies only to ALE. Min spec applies to both ALE and ADV.
5. The term "Address Valid" applies to ADO-15, SHE and INST.
6. The term" Address" in this specification applies to ADO-7 for a·bit cycles, and ADO-15 for 16·bit cycles.

2·94
inter 8X9XJF

WAVEFORM

XTAL1
CLOCKOUT·
READY

,
'.. _--------

,
'~-.

BHE. INST·
~----~--~~----~----------~--~~----------.--.
TAVLL.J ~I.---TWLWH ~
AD8-15 ~(~1L)----<t::::::~::::::V~A~L~IDc:::::::::::~~:E:::::::::::::~:~:~:~:~:::::::
270795-18

NOTES:
(1) 8·bit bus only.
(2) 8·bit or 16·bit bus and write strobe mode selected.
(3) When ADV selected.
(4) /3. or 16·bit bus and no write strobe mode selected.

WAVEFORM--BUSWIDTH PIN*

XTAL1
CLKOUT·
BUSWIDTH· ------+---~~~~~
ALE /ADV _____"
ADDRESS /DATA -------~t~~~J-----------<JD~A~TA~INy-------------
270795-19

• Not available on 64-lead package.

2·95
 :SX9XJF'

- _
_S.SVoe
Power Supply Rls. Time

_4.SVOC
Vee -

XTAL
- r- Stort Time from Po~er Supply Rise to External Output Low

I11111111 11111111111111111111111111111111111111111111111111111111111111111111111111111111111

Ie-----
RESET )I ---1 I-- Release
External to Internal

HSO.O-HSO.3,
P2 .0,P2.5
-- Time

10 STATE TIMES
PORT3&c4
WITH PULLUPS I ADDRESS DATA ADDRESS I
I' - 201BH CCB 20BOH
FIRST BUS FETCH CYCLE PROGRAM
TRLPV = 10XTAL CYCLES START
ExternoI RESET Low to
Port Va lid Time RESET fUNCTION REGISTERS
I
TOTAL 8X9XJF RESET TIME
270795-20

A.C. CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE

SERIAL PORT TIMING-SHIFT REGISTER MODE

Test Conditions: Load Capacitance = 80 pF

/

Symbol Parameter Min Max Units

.
TXLXL Serial Port Clock Peri<;>d 8Tose ns
TXLXH Serial Port Clock Falling Edge to Rising Edge 4Tosc - 50 4Tose + 50 ns
TOVXH Output Data Setup to Clock Rising Edge 3Tosc ns
TXHOX Output Data Hold After Clock Rising Edge 2Tose - 70 ns
TXHOV' Next Output Data Valid After Clock Rising Edge 2Tose +50 ns
-
TOVXH Input Data Setup to Clock Rising Edge 2Tose +200 ns
...
TXHDX Input Data Hold After Clock Rising Edge 0 ns
TXHQZ Last Clock Rising to Output Float 5Tose ns
----_.

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE

SERIAL PORT WAVEFORM-5HIFT REGISTER MODE

r-------------~------------~----------------------------------.

r-TXLXl.-j'
TXD - - -U- .. -U- ---U- _··U ---U- _. -U- _. -U- _.-U-
TQVXH-j 1-.. TXLXH..J r' , TXHOV ~ ..J r-TXHOX \. TXHQZ..J I
(O~;)-<~x:::r=x 2 X 3 X 4 X 5 X 6 X 7" >-
TOVXH-j
RXD --""CCC-.-:::"T-- -
I- -I
-".c,-:--:::",r---"",:-:--::", .
r-TXHOX \
----,.rc: -.C"'.I -----'L": .-.-
(IN) ~_--''\.::.=.:'''' _ _~'''-:. :.C:__'-"'L __ --' "~_:C':::I"" ___ ~'''''--~·''-- ... _---''.~:=CI'- __ ~. 'L:.==r ...__-"c=CI .... ---.J·'L.::::.::I ...~ __
270795-21

2-96
 8X9XJF

EXTERNAL CLOCK DRIVE

Symbol Par~meter Min Max Units
1/TOLOL Oscillator Frequency 6 12 MHz
TOHOX High Time 25 ns
TOLOX Low Time 30 ns
TOLOH Rise Time 15 ns
TOHOL Fall Time 15 ns

EXTERNAL CLOCK DRIVE WAVEFORMS

270795-22

.An external oscillator may encounter. as much as a 100 pF load at XTAL 1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and
VIH specifications the capacitance will not exceed 20 pF.

A.C. TESTING INPUT, OUTPUT WAVEFORM FLOAT WAVEFORM

2 . 4 V 2.0> TEST POINTS

~~8
< O~.x=.
2.0
0.45
270795-23 270795-24
A.G. Testing Inputs are driven at 2.4V for a Logic "1" and 0.45V For Timing Purposes a Port Pin IS no Longer Floating when a
for a Logic "0". Timing measurements are made at 2.0V for a 200 mV change from Load Voltage Occurs, and Begins to Float
Logic "1" and 0.8V for a Logic "0". when a 200 mV change from the Loaded VOHIVOL Level occurs
IOLlloH;;' ± 15 mA.

Minimum Hardware Configuration Circuits

270795-25 270795-26

2-97
 8X9XJF

AID CONVERTER SPECIFICATIONS

The absolute conversion accuracy is dependent on the accuracy of VREF.
Test Conditions: VREF = 5.12V, AGND = Vss = OV
Parameter Typical' Minimum Maximum Units" Notes
Resolution 1024 1024 Levels
10 10 Bits
Absolute Error 0 ±4 LSBs
Full Scale Error -0.5 ±0.5 LSBs
Zero Offset Error ±0.5 LSBs
Non-Linearity 0 ±4 LSBs
Differential Non-Linearity > -1 +2 LSBs
Channel-to-Channel Matching 0 ±1 LSBs
Repeatability ±0.25 LSBs
Temperature Coefficients:
Offset 0.009 LSBrC
Full Scale 0.009 LSBrC
Differential Non-Linearity 0.009 LSBrC
Off Isolation --60 dB 1,3
Feedthrough -60 dB 1
Vee Power Supply Rejection -60 dB 1
Input Resistance 1K 5K n
D.C. Input Leakage 0 3.0 pA
Sample Delay 3Tosc 50 3Tosc + 50 ns 2
Sample Time 12Tosc - 50 12Tosc + 50 ns
Sampling Capacitor 2 pF

NOTES:
• These values are expected for most devices at 25°C.
•• An "LSB", as used here, is defined in the glossary which follows and has a value of approximately 5 mV.
1. DC to 100 KHz.
2. For starting the AID with an HSO Command.
3. Multiplexer Break-Belore-Make Guaranteed.

2-98
intJ 8X9XJF

OTP EPROM SPECIFICATIONS

A.C. EPROM PROGRAMMING CHARACTERISTICS

Auto, Slave Mode Operating Conditions: Load Capacitance = 150 pF, T A = ?5°C ± 5°C, Vee, Vpo, VREF =
5.0V ± 0.5V, Vss, AGND = OV, Vpp = 12.75V ± 0.25V, EA = 11V ± 2.0V, fose = 6.0 MHz

Run-time Operating Conditions: Fose = 6.0 MHz to 12.0 MHz, Vee, Vpo, VREF = 5V ± 0.5V, TA = 25°C to
± 5°C and Vpp = 12.75V ± 0.25V. For run·time programming over a full operating range, contact the factory.
Symbol Parameter , Min Max Units
TAVLL ADDRESS/COMMAND Valid to PALE Low. 0, Tose
TLLAX ADDRESS/COMMAND Hold After PALE Low 80 Tose
TOVPL Output Data Setup Before PROG Low 0 Tose
TpLOX Data Hold After PROG Falling 80 Tose
TLLLH PALE PulseWid,th 180 Tose
TpLPH PROG Pulse Width 250 T08e 100}-tS +
144 Tose
TLHPL PALE High to 'P'ROO Low 250 .- Tose
TpHLL PROG High to Next PALE Low 600 Tose
TpHOX Data Hold After PROG High 30 Tose
TpHVV PROG High to PVER/PDO Valid 500 Tose
TLLVH PAtE Ldwto PVER/PDO High 100 Tose
TpLOY PROG Low to VERIFICATION/DUMP Data Valid 100 Tose
TSHLL RESET High to First PALE Low (not shown) 2000 Tose

D.C. EPROM PROGRAMMING CHARACTERISTICS

Symbol Parameter Min I Max Units
lpp Vpp Supply Current (Whenever Programming) I 100 . mA
Vpp Programming Supply Voltage 12.75 ±0.25 V
VEA EA Programming Voltage 11 ±2.0 V

NOTE:
Vpp must b~ within.1V of Vee while Vee < 4.5V. Vpp must not have a low impedance path to ground (or Vss) while
Vee> 4,5V.

2-99
 8X9X.:JF

WAVEFORM-EPROM PROGRAMMING (OTP)

PORTS 3,4

PALE--_

PROG ---+---..;;;.;;.;..~

PVER VALID
__ _..I VALID

PDO VALID
__ _..I VALID
270795-27

REVISION HISTORY FUNCTIONAL DEVIATIONS

This data sheet (270795-003) is valid for devices Devices covered by this data sheet (see ReviSion
with an "A" at the end of the topside tracking num- History) have the following errata.
ber. Data sheets are changed as new device infor- 1. INDEXED, 30PERANp.MUlTIPlY
mation becomes available. Verify with your local In-
tel sales office that you have the latest version be- The displacement portion of an indexed, three op-
fore finalizing a design or ordering devices. erand (byte or word) multiply may not be in the
. range of 200H thru 17FFH inclusive. If you must
The following differences exist between this data use these displacements, execute an indexed,
sheet and the previous version (-002). two operand multiply and a move if necessary.
1. The reserved location section and th.e power sup- 2. 8X9XJF HIGH SPEED INPUTS
ply sequencing section has been deleted. This The High Speed Input (HSI) peripheral on the
information is in the Hardware Design Informa~ "JF" devices contain three deviations' from the
tion .. original 8X9XBH specification. The first changes
2. The Software Reset Timing bug was removed 'the resolution description. The second deviation
from the Functional DeViations. The RESET pin describes skipped time tag recording. The third
will pull down for at least 2 states if a software modifies theeventl entry loading algorithm.
reset or watchdog timer overflow occurs. NOTE:
"Events" are defined as one or more pin tran-
Differences between the -002 and -001 data sheets. sitions. "Entries" are defined as the recording of
1. The TllGV spec has been changed from Max ± one or more events. The FIFO is defined as emp-
Tose - 75 ns to Max = Tose = 100 ns. ty even if there is an entry in the Holding Register.
2. The TCllH spec has been changed from Min =
-20 ns and Max = +25 ns to Min = -30 ns
and Max = + 15 ns. .
3. The TXHQX spec has been changed from Min =
2 Tose - 50nsto 2Tose - 70 ns.
4, The TOlOX spec has been changed from Min =
25 ns to Min = 30 ns.
5. Added "20" recommendation for reserved ad-
dress 2019H to EPROM specification.
6. Added functional deviations.

2·100
inter 8X9XJF

A. The eight state HSI resolution changes to nine C. The HSI pins. are sampled during an internal
states. Events occurring on the same pin more timing phase. This phase, after some propaga-
frequently than once every nine state times tion time, appears externally as CLKOUT. If
may be lost. Selecting the Eight Positive Tran- the first event to be recorded into an empty
sition Mode limits the resolution to no more FIFO occurs during this CLKOUT period, and
than eight positive transitions per sixteen state the second event' occurs after that period, the
times. Transitions may n6t occur more quickly events will be entered separately with time-
than once per state time. This means tran- tags at least one count apart. If the second
sitions in one state time must stabilize and event enters the FIFO coincident with the
hold a logic level for at least one state time "skipped" time-tag situation (see item 2
before any further transitions occur. above) the time-tags will be at least two
B. A mismatch between the nine state HSI reso- counts apart. If both events occur within the
lution and the eight state hardware timer caus- period of this internal phase, there will be only
es one time-tag value to be skipped every nine one entry recording both events on one time-
timer counts. The effect on FIFO entries is to tag.
receive l:! time tag one count later than expect- 3. RESERVED LOCATION 2019H
ed every nine counts. The 1990 Architectural Overview recommends
that reserved location 2019H be filled with hex
value FFH. The recommendation is now to fill
2019H with hElx value 20H.

2-101
infel®
MCS®-96
809XJF/839XJF1879XJF
Express
• Extended Temperature Range • Burn-In
(-40°C.to +8$OC)

The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-96 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.

The EXPRESS program includesthe commercial standard temperature range with burn-in, and an extended
temperature range with or without burn-in.

With the commercial standard temperature range operational 9haracteristics are guaranteed over the temper-
ature range of O°C to +70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40°C to· + 85°C.

The optional burn-in is dynamic, for a minimum time of 160 hours at 125°C with Vee = 5.5V ± 0.5V, following
guidelines in MIL-STD-883, Method 1015 ..

Package types and EXPRESS versi9ns are identified by a one- or two-letter prefix to the device number. The
prefixes are listed in Table 1.

This data sheet specifies the parameters for the extended temperature rangEl option. The commercial temper-
ature range data sheets are applicable otherwise.

POWER
VREF ANGND

CONTROL
SIGNALS

------
16

.. ---
PORTO PORT 1 PORT 2 HSI HSO
ALT FUNCTIONS
270796-1
MCS®-96 Block Diagram

October 1989
2-102 Order Number: 270796-001
 8X9XJF EXPRESS

ELECTRICAL CHARACTERISTICS NOTICE: This data sheet contains information on

ABSOLUTE MAXIMUM RATINGS* products in the sampling and initial production phases
of development. The specifications are subject to
Ambient Temperature Under Bias. - 40·C to + 85·C change without notice.
Storage Temperature .•.....•.. - 40·C to + 150·C • WARNING: Stressing the device beyond the "Absolute
Voltage from Vpp or EA Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
to Vss or.ANGND ......••.•.. -O.3V to + 13.0V "Operating Conditions" is not recommended and ex-
Voltage from Any Other Pin to tended exposure beyond the "Operating Conditions"
Vss or ANGND .............. -O.3V to + 7.0V· may affect device reliability.
Average Output Current from Any Pin ...•... 10 rnA
Power Dissipation .......•..............•... 1.5W
"This includes Vpp on ROM and CPU devices.

OPERATING CONDITIONS
Symbol Parameter Min . Max Units
TA Ambient Temperature Under Bias -40 +85 °C
Vee Digital Supply Voltage 4.50 5.50 V
,
VREF Analog Supply Voltage 4.50 5.50 V
fose Oscillator Frequeno;;y 6.0 12 MHz
VPO Power-Down Supply Voltage 4.50 5.50 V

NOTE:
ANGND and Vss should be nominally at the same potential.

D.C. CHARACTERISTICS (Under listed operating conditions)

".
Symbol Parameter Min Max Units Test Conditions
lee Vee Supply Current( - 40°C,,; TA ,,; + 85°C) 330 mA All Outputs
245 mA Disconnected.
leel Vee Supply Current(TA = + 85°C)
Ipo VPO Supply Current 1 mA Normal operation
and Power-Down.
IREF VREF Supply Current 10 mA ..
VIL Input Low Voltage (Except RESET) -0.3 +0.8 V
VILl Input Low Voltage, RESET -0.3 +0.7 V
VIH Input High Voltage (Except RESET, NMI, XTAL 1) 2.0 Vee +0.5 V
VIHl Input High Voltage, RESET Rising 2.4 Vee +0.5 V
VIH2 Input High Voltage, RESET Falling Hysteresis 2.1 . Vee +0.5 V
VIH3 Input High Voltage, NMI, XTAL 1 2.3 Vee +0.5 V
III Input Leakage C\lrrent to each pin of HSI, P3, P4, and to P2.1. ±10 ",A Yin = OtoVcc
ILil D.C. Input Leakage Current to each pin of PO +3 ",A Itin = Oto Vee'
IIH Input High Current to EA 100 ",A Viti =2.4V
IlL Input Low Current to each pin of P1, -150 . ",A VIL = 0.45V
and to P2.6, P2.7.
IILl Input Low Current to RESET -0.25 -2 mA VIL = 0.45V
IIL2 Input Low Current P2.2, P2.3, P2.4, READY, BUSWIDTH . -50 ",A VIL= 0.45V
VOL Output Low Voltage on Quasi-Bidirectional 0.45 V IOL = 0.8mA
port pins and P3, P4 when used as ports (Note 1)
VOL1 Output Low Voltage on Quasi-Bidirectional 0.75 V IOL = 2.0mA
port pins and P3, P4 when used as ports (Notes 1, 2, 3)
VOL2 Output Low Voltage on Standard Output 0.45 V' IOL = 2.0mA
pins, RESET and Bus/Control Pins (Notes 1, 2, 3)

2-103
intJ 8X9XJF EXPRESS

D.C. CHARACTERISTICS (Continued) ,

Symbol 'Parameter Min Max Units Test Conditions'
VOH Output High Voltage on Quasi-Bidirectional '2A V IOH = -20 ",A
pins (Note 1)
VOH1 Output High Voltage on Standara Output 2A V tOH = -200 ",A
pins and Bus/Control pins (Note 1)
IOH3 Output High Current on RESET -50 ",A VOH = 2AV
Cs Pin Capacitance (Any Pin to Vss) 10 pF !TEST = 1.0 MHz

NOTES:
1. Quasi-bidirectional pins include ,those on P1, for P2.6 and P2. 7. Standard Output Pins include TXD, RXD (Mode 0 only),
PWM, and HSO pins. Bus/Control pins include CLKOUT, ALE, BHE, RD, WR, INST and ADO-15.
2. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V.
IOl on quasi-bidirectional pins and Ports 3 and 4 when used as ports: 4.0 mA
IOl on standard output pins and RESET: 8.0 mA .
tOl on Bus/Control pins: 2.0 mA
3.During normal (non-transient) operation the following limits apply:
Total IOl on Port 1 must not exceed 8.0.rnA.
TotallOl on P2.0, P2.6, RESET and allHSO pins must not exceed 15 mA.
Total IOl on Port 3 must not exceed 10 mA. .
Total IOl on P2.5, P27, and Port 4 must not exceed 20 mA.

A.C. CHARACTERISTICS (Under listed operating conditions)

Test Conditions: Load Capacitance on Output Pins = 80 pF '
Oscillator Frequency = 10 MHz

TIMING REQUIREMENTS (Other system components must meet these specs)

Symbol Parameter Min Max . Units

TCLYX(3) READY Hold after CLKOUT Edge· 0(1) ns

TLLYV End of ALE/ ADV to READY Valid 2Tosc~70 ns

TLLYH End of ALE/ ADV to RJ:ADY High 2Tosc+40 4Tosc-80 ns

TYLYH ~
Non-Ready Time 1000 ns
TAVDV(2) Address Valid to Input Data Valid 5Tosc-120 ns

TRLDV RD Active to Input Data Valid 3Tosc-100 ns

TRHDX Dat1!- Hold after RD Inactive 0 ns

TRHDZ RD Inactive to Input Data Float 0 Tosc-::-25 ns

,
TAVGV(2,3) Address Valid to BUSWIDTH Valid 2 Tosc -125 ns

TLLGX(3) BUSWIDTH Hold after ALE/ ADV Low Tosc +40 ns

TLLGV(3) ALE/ ADV Low to BUSWIDTH Valid Tosc -:-75 ns

NOTES:, ., .
1, If the 48-pin device is being used then this timing can be generated by assuming that the CLKOUT falling edge has
occurred at 2Tosc+55 (TLLCH(max) + TCHCL(max)) after the falling edge of ALE.
2. The term "Address Valid" applies to ADO-15, BHE and IN~n.
3. Pins not bonded out on 64-pin devices.

2-104
 8X9XJF EXPRESS

A.C. CHARACTERISTICS (Continued)

TIMING RESPONSES (MCS-96 devices meet these specs)

Symbol Parameter Min Max Units
FXTAL Oscillator Frequency 6.0 12.0 MHz
Tosc Oscillii\tor Period 83 166 ns
.. TOHCH XTAL 1 Rising Edge to Clockout Rising Edge 0(4) 120(4) ns
TCHCH(3) CLKOUT Period(3) 3Tosc(2) 3Tosc(2) ns
TCHCL(3) CLKOUT High Time Tosc-35 Tosc+ 10 ns
TCLLH(3) CLKOUT Low to ALE High -20 +25 ns
TLLCH(3) ALEI ADV Low to CLKOUT High Tosc-25 Tosc+45 ns
TLHLL ALEI ADV High Time Tosc-30 Tosc+35(4) ns
TAVLL(5) Address Setup to End of ALEI ADV Tosc-50 ns
TRLAZ(6) RD or WR Low to Address Float 25 ns
TLLRL End of ALEI ADV to RD or WR Active Tosc-40 ns
TLLAX(6) Address Hold after End of ALEI ADV Tosc-40 ns
TWLWH WR Pulse Width 3Tosc-35 ns
TaVWH Output Data Valid to End of WR/WRL/WRH 3Tosc-60 ns
TWHax Output Data Hold after WR/WRL/WRH Tosc-50 ns
TWHLH End of WR/WRLlWRH to ALEI ADV High Tosc-75 ns
TRLRH RD Pulse Width 3Tosc-30 ns
TRHLH End of RD to ALEI ADV High Tosc-45 ns
TCLLL(3) CLOCKOUT Low to ALEI ADV Low Tosc-40 Tosc+35 ns
TRHBX(3) RD High to INST, BHE, AD8-15 Inactive Tosc-25 Tosc+30 ns
TWHBX(3) WR High to INST, BHE, AD8-15 Inactive TosC-50 Tosc+ 100 ns
THLHH WRL, WRH Low to WRL, WRH High 2Tosc-35 2Tosc+40 ns
TLLHL ALEI ADV Low to WRL, WRH Low 2Tosc-30 2Tosc+55 ns
TaVHL Output Data Valid to WRL, WRH Low Tosc-60 ns

NOTES:
1. If more than one wait state is desired, add 3Tosc for each additional wait state.
2. CLKOUT is directly generated as a divide by 3 of the oscillator. The period will be 3Tosc ± 10 ns if Tosc is constant and
the rise and fall times on XTAL 1 are less than 10 ns.
3. Pins not bonded out on 48-pin devices.
4. Max spec applies only to ALE. Min spec applies to both ALE and ADV.
5. The term "Address Valid" applies to ADO-15, BHE and INST.
6. The term" Address" in this definition applies to ADO- 7 for 8-bit cycles, and ADO-15 for 16-bit cycles.

2-105
 ·SX9XJF EXPRESS

Table 1. MCS®·96 Packaging-8X9XJF

Factory User
Masked CPU Programmable
ROM EPROM OTP
68 Pin 64 Pin 48 Pin 68 Pin 64 Pin 48 Pin 68 Pin 64 Pin 48 Pin 68 Pin 64 Pin 48 Pin
Analog 8397JF 8397JF 8097JF 8097JF 8797JF 8797JF
No Analog

PACKAGE DESIGNATORS:
N = PLCC
C = Ceramic DIP
A =;Ceramic Pin Grid Array
P = Plastic DIP
R = Ceramic LCC
U = Shrink DIP

REVISION HISTORY
This is the first data sheet for the 8X9XJF Express devices.

2-106
 EV8097BH fEATURES
• Zero Wait-State 12 MHz Execution Speed
• 24K Bytes of ROMsim
• Flexible Wait-State, Buswidth, Chip-Select Controller
• Concurrent Interrogation of Memory and Registers
• Sixteen Software Breakpoints
.'Two Single-Step Modes
• High-Level Language Support
• Symbolic Debug
• RS-232-C Communication Link

EVALUATION TOOL
Intel's EV8097BH evaluation board provides a hardware environment for code execution and
software debugging at a relatively low cost. The board features the 8097BH 16-bit microcontroller
from the industry standard MCS®-96 family, The board allows you to
take full advantage of the power of the MCS-96, The EV8097BH provides zero wait-state, 12 MHz
execution of a user's code. Plus, its memory (ROMsim) can be reconfigured to match your planned
memory system, allowing for exact analysis of code execution speeds in a particular application.
**IBM pc, XT, AT and DOS are regIstered trademarks of Interndtional Busmess CorporatIOn.

-n+_I®
111'e'-_-
Intel CorporatIon assumes no respopslblhty for the use of any circUitry other than CIrcUItry embodIed In an Intel product. No other ClfCUIt patent
lIcenses are ImplIed InformatlOn con tamed herem supercedes prevlOusly published specifIcations on these deVIces from Intel.
MARCH 1989
© Intel Corporation 1989 Order number: 270739-001
2-107
 , < ' .

Popular features such as'a symb~lic d~bug, sin~le-line assembier, disassembler, single-step program
execution, and sixteen software breakpoints are standard on the EV8097BH. Intel provides a
complete code development environment using assembler (ASM-96) as well as high-level languages
such as Intel's iC;96 or PL/M-96 to accelerate development schedules.
The evaluation board is hosted on an IBM PC~ or BrOS-compatible clone, already a standard
development solution in most of today's engineering environments. The source code for the on-
board monitor (written in ASM-96)is public domain. The program is about lK, and can be\!asily
modified to be included in your t'lrget hardware. In this way, the provided PC ho!\t software can be
used throughout the development phase.

FULL SPEED EXECUTION

The EV8097BH executes your code from on-board ROMsim at 12 MHz with zero wait-states. By
changing crystals on the 8097BH, arty slower execution speed can be evaluated. The boards host
interface timing is not affected by this crystal change,

24K BYTES OF ROMSIM

The board comes with 24K bytes of SRAM to be used as ROMsim for your application code and as
data memory if needeCi. 16K bytes, of this memory are configured as sixteen bits wide and 8K bytes
are configured as eight bits wide. You can therefore evaluate the speed of the part executing from
either buswidth. .

FLEXIBLE MEMORY DECODING

By changing the Programable Logic Device (PLD) on the board, the'memory On the board can be
made to look like the memory system planned for your hardware application. The PLD controls the
buswidth of the 8097BH and the chip-select inputs on the board. It also cO,ntrols the number of wait
states (zero to four) generated by the 8097BH during a memory cycle. These features can all be
selected with 256 byte boundaries of resolution.

CONCURRENT INTERROGATION OF MEMORY AND REGISTERS

The monitor for the EV8097BH allows you to read and modify internal registers and external
memory while your code is running in the board,

SIXTEEN SOFTWARE BREAKPOINTS

There are sixteen breakpoints available which automatically substitute a TRAP instruction for your
instruction at the breakpoint location. The substitution occurs when execution is started. If the code
is halted or a breakpoint is reached, your code is restored in the ROMsim.

TWO STEP MODES

There are two single-step modes available, The first stepping mode locks out all interrupts which
might occur during the step. The second mode enable's interrupts, and treats subroutine calls-and
interrupt routine~ as indivisible instructions.

2-108
HIGH LEVEL LANGUAGE SUPPORT
The host software for the EV8097BH board is able to load absolute object code generated by ASM-96,
iC-96, PL/M-96 or RL-96, all of which are available from Intel.

SYMBOLIC DEBUG
The host has a Single-Line Assembler, and a Disassmbler that recognize symbolics generated by
Intel software tools.

RS-232-C COMMUNICATION LINK

The EV8097BH communicates with the host using an Intel 82510 UART provided on board. This
frees the on-chip UART of the 8097BH for your application.

POWER REQUIREMENTS
The EV8097BH board requirs 5 volts at 450 rnA. If the on-board LED's are disabled, the current
drops to 300 rnA. The board also requires + / - 12 volts at 25 rnA. .

PERSONAL COMPUTER REQUIREMENTS

TJ:.le EV8097BH Evaluation Board is hosted on an IBM PC*, XT*, AT* or BIOS-compatible clone. The
PC must meet the following minimum requirements:
• 512K Bytes of Memory
• One 360K Byte Floppy Disk Drive
• PC-DOS* 3.1 or Later
• A Serial Port (COMI or COM2) at 9600 Baud
• ASM-96, iC-96 or PL/M-96 .
• An ASCII text editor such as AEDIT

P1

.
RS-232 CHIP SELECT
BUFFERS
BUSWlDTH
READY
CPU
LOGIC

P2
Txd ~
Rxd ADDRESS
82510
810321< 810321< 810321<
ANALOG INPUT
ANALOG
DIGITAL
PortO DATA
x16
RAM6'ROM
x16
RAM6'ROM
x8
RAM£PROM
UART
,
-
DIGITAL 110 110 CONTROL
Port 1,2 '---
~ HSO,HSI

Block Diagram of the EV8097BH Board

Pnnted in U.s A /389/l0K/RR SM

MCS®..,96 Instruction Set 3
 MCS®·96
INSTRUCTION SET
OVERVIEW breg. A byte register in the internal register file. When
confusion could exist as to whether this field refers to a
This chapter of the manual gives a description of each source or a destination register it will be prefixed with
instruction recognized by the MCS®-96 architecture. an "S" or a "D",
The instructions are sorted alphabetically by the assem-
bly language mnemonic. baop. A byte operand which is addressed by any of the
address modes.
Additional information including instruction execution
times and a description of the different addressing bitno. A thr~e bit field within an instruction op-code
modes can be found in the following documents: which selects one of the eight bits in a byte.

MCS·96 MACRO ASSEMBLER USER'S GUIDE wreg. A word register in the internal register file. When
Order Number 122048 (Intel systems) confusion could exist as to whether this field refers to a
Order Number 122351 (DOS systems) source register or a ~estination register it will be pre-
fixed with an "S" or a "0".
MCS·96 UTILITIES USER'S GUIDE waop. A word operand which is addressed by any of the
Order Number 122049 (Intel systems)
address modes.
Order Number 122356 (DOS systems)
Lreg. A 32-bit register in the internal register file.
PL/M·96 USER'S GUIDE
Order Number 122134 (Intel systems) caddo An address in the program code.
Order Number 122361 (DOS systems)
Flag Settings. The modification to the flag setting is
C·96 USER'S GUIDE shown for each instruction. A checkmark (,..,) means
Order Number 167632 that the flag is set or cleared as appropriate. A hyphen
means that the flag is not modified. A one or zero (1) or
80C196KC USER'S GUIDE (0) indicates that the flag wiJI be in that stat!! after the
Order Number 270704 instruction. An up arrow (t) indicates that the in-
struction may set' the flag if it is appropriate but wiJI
80C196KB USER'S GUIDE not clear the flag. A down arrow ( J, ) indicates that the
Order Number 270651 flag can be cleared but not set by the instruction. A
question mark (?) indicates that the flag will be left in
MCS·96 ARCHITECTURAL OVERVIEW an indeterminant state after the operation.
Order Number 270250
Generic Jumps and Calls. The assembler for the
The instruction set descriptions in the following sec- MCS-96 family provides for generic jumps and calls.
tions do not always show the effect on the program For all of the conditional jump instructions a "B" can
counter (PC). Unless -otherwise specified, all instruc- be substituted for the "J" and the assembler wiJI gener-
tions increment the PC by the number of bytes in the ate a code sequence which is logically equivalent but
instruction. can reach anywhere in the memory. A JH can only
jump about 128 locations from the current program
A set of acronyms are used to make the instruction set counter; a BH can jump anywhere in memory. In a like
descriptions easier to read, their definitions are listed manner a BR will cause a SJMP or LJMP to be gener-
below: ated as appropriate and a CALL wiJI cause a SCALL
or LCALL to be generated. The assembler user's guide
aa. A two bit field within an opcode which selects the should be consulted for the algorithms used by the as-
basic addressing mode user. This field is only present in sembler to convert these generic instructions into actual
those opcodes which allow address mode options. The machine instructions.
encoding of the field is as follows:
Indirect Shifts. The indirect shift operations use regis-
ters 24 through 255 (l8H-OFFH), since 0-15 are di-
aa Addressing mode
rect operators and registers 16 through 23 are Special
00 Register direct Function Registers. Note that indirect shifts through
SFRs are illegal operations.
01 Immediate
10 Indirect The maximum shift count is 31 (IFH). Count values
above this wiJI be truncated to the 5 least significant
11 Indexed bits.
3-1
 MCS®-96 INSTRUCTION SET

1. ADD (Two Operands) - ADD. WORDS

Operation: The sum of the two word operands is stored into the destination' (leftmost)
operand.
(DESTj" - (DESn + (SRC)

Assembly Language Format: . DST SRC

ADD wreg, waop

Object cOde Format: [ 011001aa 1I waop 1 Iwreg 1

Flags Affected
z 1 N 1 C 1 V 1 VT 1 ST

""'1"'" 1""'1""'1 i 1 -

2. ADD (Three Operands) - ADD WORDS

Operation: The Sum of the second and third word operands is stored into the destination
(leftmost) operand.
(DEST) - (SRC1) + (SRC2)

Assembly Language Format: DST SRC1 SRC2

. ADD D,wreg, Swreg, waop

Object Code Format: [ 0.10001 aa 1I waop 1I Swreg 1I Dwreg 1

ST

3-2
 Mcs/fij..gs INSTRuctiON SEt

3. ADDB (Two Operands) - ADD BYTES . :',' ,.,,. '. ""I,

',',

Operation: Thesum"of the two byte 'operands is stored into the 'destination (leftmost)
operand. .
(DEST) +- (DES'F) + (SRC)

Assembly Language Format: DST SRC

ADDB breg. baop'

,~ 1-, :;,' ~: ' ...

Object Code Format: [ 011101 aa ] [ baop' ] [. br!ilg'] , ! 'n

ST

4. ADDB (Three Operands) ""'7 ADD BYTES . ", "

Operation: The sum of tilesebond and'third byte operands is stored into the destination
(leftmost) operand,' ,
(DEST) +- (SRC1) + (SRC2),

Assembly Language Format: DST SRC1 SRC2

ADDB Dbreg. Sbreg. baop

Object Code Format: [ 010101aa 1[ baop ] [ Sbreg 1[ Dbreg

ST

3-3
inter MCS~.$6 INST~UCTION,SET

5. ADDC - ADD WORDS WITH CARRY

Operation: The sum of the two word operands and the carry flag (0 or 1) is stored into the
destination (leftmost) operand.
(DEST) - (DEST) + (SAC) + C
Assembly Language Format: DST SAC
ADDC wreg, waop

Object Code Format: [ 101001 aa 1[ waop 1[ wreg ]

Flags Affected
Z INlclvlvrlsT
J.1 .... j .... I .... l t l -

6. ADDCB - ADD BYTES WITH CARRY

Operation: The sum .of the two byte operands and the carry flag (0 or 1) is stored into the
destination (leftmost) operand.
(DEST) - (DEST) + (SAC) + C

Assembly Language Format: DST SAC

ADDCB breg, baop

Object Code Format: [ 101101 aa 1[ baop 1( breg ]

Flags Affected.
Z NlclvlvTlsT
J. .... 1 .... 1 .... 1 t 1 -
inter MCS®·96 INSTRUCTION SET

7. AND (Two Operands) - LOGICAL AND WORDS

Operation: . The two word operands are ANDed,. the result having a 1 only in those bit
positions where both operands had a 1, with zeroes in all other bit positions.
The result is stored into the destination (leftmost) operand.
(DEST) - (DEST) AND (SRC)

Assembly Language Format: DST SRC

AND wreg, waop

Object Code Format: [ 011000aa J. [ waop 1[ 'wreg 1

ST

8. AND (Three Operands) - LOGICAL AND WORDS

Operation: The second and third word operands are ANDed, the result having a 1 only in
those bit positions where both operands had a 1, with zeroes in all other bit
positions. The result is stored into the destination (leftmost) operand.
(DEST) - (SRC1) AND (SRC2)

Assembly Language Format: DST SRC1 SRC2

AND Dwreg, Swreg; waop

Object Code Format: [ 010000aa 1[ waop 1[ SWreg 1L Dwreg 1

ST

3-5
 MCS®~96INSTRUCTION SET

9. AN DB (Two Operands) - LOGICAL AND BYTES

Operation: The two byte operands are ANDed, the result having a 1 only in those bit
positions where both operands had a 1, with zeroes in all other bit positions.
The result is stored into the destination (leftmost) operand.
(DEST) ..... (DEST) AND (SRC)

Assembly Language Format: DST SRC

AN DB breg, baop

Object Code Format: [ 011100aa· J [ baop J [ breg J

ST

10. ANDB (Thre~ Operands) - LOGICAL AND BYTES

Operation: The second and third byte operands are ANDed, the result having a 1 only in
those bit positions where both operands had a 1, with zeroes in all other bit
positions. The result is stored into the destination (leftmost) operand.
(DEST) ..... (SRC1) AND (SRC2)

Assembly Language Format: DST SRC1 SRC2

AN DB Dbreg, Sbreg, baop

Object Code Format: [ 010100aa J [ baop J [ Sbreg J [ Dbreg J

Flags Affected
z 1 N 1C 1V I VT1 ST
~ 1~ 10 10 1 -I -

3-6 •
inter MCS®·96 INSTRUCTION SET

11. BMOV - BLOCK MOVE (80C196KB and 80C196KC only)

Operation:' This instruction is used to move a block of word data from one location in
memory to another. The source and destination addresses are calculated
using the indirect with auto-increment addressing modes. A long register ad-
dresses the source and destination pointers which are stored in adjacent word
registers. The number Of transfers Is specified by a word register. The blocks
of data can reside anywhere'in memory, but should not overlap.

COUNT - (CNTREG)
LOOP; SRCPTR - (PTRS)
DSTPTR - (PTRS + 2)
(DSTPTR) - (SACPTR)
(PTRS) - SRCPTR + 2
(PTRS) + 2) - DSTPTR + 2
COUNT - COUNT - 1
if COUNT < > 0 then go to LOOP

PTRSCNTREG
Assembly Language Format: BMOV Lreg, wreg

Object Code Format: [11000001 1 [ wreg 1 [ Lreg 1

Z ST

NOTES:
1. CNTREG does not get decremented during the instruction.
2. It is easy to unintentionally create a very long un-interruptable operation
with this instruction ..
To provide an interruptable version of the BMOV for large blocks, the BMOV
instruction can be used with the DJNZ instruction. This is possible because
the pointers are modified, but CNTREG is not. Consider the example:

LD PTRS, SRC ;Pointer to base of sources table

LD PTRS+2, DST ;Pointer to base of destination table
LD CNTREG, #COUNT ;Number of bytes to move per set
LD CNTSET, #SETS ;Number of sets to move
Move: BMOV PTRS,CNTREG ;Move one set
DJNZ CNTSET, MOVE ;Decrement set counters and move again

3-7 .
 MCS@·96 INSTRUCTION SET

12. BMOVI - INTERRUPTABLE BLOCK MOVE (80Ct96KC only)

Operation: This instruction is used to move a block of word :data from one location in
memory to another and is interruptable. The source and destination addresses
are calculated using the indirect with auto-increment addressing modes. A
long register addresses the source and destination pointers which are stored
in adjacent word registers. The number of transfers is specified by a word
register. The blocks of data can reside a,)ywhere in memory, but should not
overlap.

COUNT .-- (CNTREG)

LOOP: SRCPTR .-- (PTRS)
DSTPTR .-- (PTRS + 2)
(DSTPTR) .-- (SRCPTR)
(PTRS) .-- SRCPTR + 2
(PTRS) + 2) .-- DSTPTR + 2
COUNT .-- COUNT - 1
if COUNT < > 0 then go to LOOP

PTRSCNTREG
Assembly Language Format: BMOVI Lreg, wreg

Object Code Format: [10101101 1 [wreg 1 [ Lreg 1

z ST

NOTES:
1. CNTREG does not get decremented during the instruction. However, if the
BMOVi is interrupted, CNTREG will be updated. Therefore, CNTREG must
be reloaded before starting a BMOVi.
inter MCS®·96 INSTRUCTION SET

13. BR (Indirect) - BRANCH INDIRECT

Operation: The execution continues at the address specified in the operand word regis-
ter.
PC .-- (DEST)

Assembly Language Format: SR [ wreg

Object Code Format: [ 11100011 1[ wreg 1

Flags Affected
zlNlcl,vlvTlsT
-1-1-1-1-1-

14. CLR - CLEAR WORD

Operation: The value of the word operand is set to zero.

(DEST) .-- 0

Assembly Language Format: CLR wreg

Object Code Format: [ 00000001 1[ wreg

z ST

3-9
 MCS®'·96' INStfRI:JCTION SET

15. CLRB - CLEAR BYTE

Operation: The value of the byte operand is set to zero.

(DEST) +- 0

Assembly Language Format: CLRB breg

Object Code Format: [ 00010001 1[ breg 1

Flags Affected
Z /. N / C I V I"\IT I ST
1 I 0 I 01 0 I -,- I -

16. CLRC - CLEAR CARRY FLAG

Operation: The value of the carry flag is set to zero.

C+-O

Assembly Language Format: CLRC

Object Code Format: [. 11111000

Flags Affected
Z I N I C I vi VT r st
- I - I .0 ·1 - I - I -

3-10
inter MCS®·96 INSTRUCTION SET

17. CLRVT - CLEAR OVERFLOW TRAP

Operation: The value of the overflow-trap flag is set to zero.

VT +- 0

Assembly Language format: CLRVT

Object Code Format: [ 11111100

z ST

18. CMP-COMPARE WORDS

Operation: The source (rightmost) word operand is subtracted from' the destination (Ieft~
most) word operand. The flags are altered but the operands remain unaffect-
ed. The carry flag is set as complement of borrow.
. (DEST) - (SRC)

Assembly Language format: DST SRC

CMP wreg, waop

Object Code format: [ 10001 Oaa 1[ waop 1[ wreg

ST

3-11
 MCS®·961NSTRUCTION SET

19. CMPB - COMPARE BYTES

Operation: The source (rightmost) byte operand is subtracted from the destination (left·
most) byte operand. The flags are altered but the operands remain unaffected.
"The carry flag is set as complement of borrow.
(DEST) - (SRC)

Assembly Language Format: DST SRC

CMPB breg, baop

Object Code Format: [ 10011'Oaa 1[ baop 1[ breg

Flags Affected
zlNICIVIVTIST
",1"'1"'1"'1 t 1-

20. CftjlPL - COMPARE LONG (80C196KB and 80C196KC only)

Operation: This instruction is used to compare the magnitudes of two double word (long)
operands. The operands are specified using the direct addressing mode. Five
PSW flags are set following this operation, but the operands are not affected.
DST·SRC

DST SRC
Assembly Language Format: CMPL Lreg, Lreg

Object Code Format: [11000101 1 [ src Lreg 1 [ dst# Lreg 1

ST

3·12
 MCS®·96 INSTRUCTION SET.

21. DEC - DECREMENT WORD

Operation: The value of the word operand is decremented by one.

(OEST) +- (OEST) - 1

Assembly Language Format: OECwreg

Object Code Format: [ 00000101 1[ wreg 1

Flags Affected
ZINlclvlvTlsT
"'.1 "'l"'I"'1 t 1-

22. DECB - DECREMENT BYTE

<V
Operation: The value of the byte operand is decremented by one.
(OEST) +- (OEST).,- 1

Assembly Language Format: OECB breg

Object Code Format: [ 00010101 1[ breg 1

ST

23. 01 - DISABLE INTERRUPTS

Operation: Interrupts are disabled. Interrupt-calls will not occur after this instruction.
Interrupt Enable (PSW.9) +- 0

Assembly Language Format: 01

Object Code Format: [ 11111010

Flags Affected
ZINlclvlvTlsT
-1-1-1-1-1-

3-13
inter MCS®·96INSTRUCrIQN . SET

24. DIV - DIVIDE INTEGERS

Operation: ..This instruction divides the contents of the destination.LONG-INTEGER oper-

and by the contents of the INTE;GER word operand, using signed arithmetic.
The low order word of the destination (Le., the word with the lower address)
will contain the quotient; the high order word will contain the remainder.
(low word DEST) - (DEST) / (SRC)
(high word DEST) - (DEST) MOD (SRC)
The above two statements are performed concurrently.

Assembly Language Format: DST SRC

DIV Ireg, waop

Object Code Format: [ 11111110 1[ 100011aa 1[ waop 1[ Ireq 1

Flags Affected
Z N C V VT ST
- - - ? i ~ 8096BH
- - - ~ i - 80C196KB,80C196KC

25. DiVe - DIVIDE SHORT-INTEGERS

Operation: This instruction"divides the contents of the destination INTEGER operand by

the contents of the source SHORT-INTEGER operand, using signed arithme-
tic. The low order byte oT the destination (I.e. the byte with the lower address)
will contain the quotient; the high order byte will contain the remainder.
(low byte DEST) - (DEST) / (SRC)
(high byte DEST) - (DEST) MOD (SRC) . .,
The above two statements are performed concurrently.

Assembly Language Format: DST SRC

DiVe wreg, baop

Object Code Format: [ 11111110 1[ 100111aa 1[ baop 1[ wreg

Flags Affected
Z N C V VT ST
- - - ? i - 8096BH
- - - ~ i - 80C196KB, 80C196KC

3-14
 MCSIB>-96 INSTRUCTION SET

26. DIVU - DIVIDE WORDS

Operation: This instruction divides the content of the destination DOUBLE-WOAD oper-
and by the contents of the source WOAD operand, using unsigned arithmetic.
The low order word will contain the quotient; the high,order WOAD will contain
the remainder.
(low word DEST) - (DEST) / (SAC)
(high word DEST) - (DEST) MOD (SAC)
The above two statements are performed concurrently.
(

Assembly Language Format: DST SAC

DIVU Ireg, waop

Object Code Format: [ 100011 aa 1[ waop 1[ Ireq 1

z ST

27. DIVUB - DIVIDE BYTES

Operation: This instruction' divides the contents of the destination WOAD operand by ·the
contents of the source BYTE operand, using unsigned arithmetic. The low
order byte of the destination, (Le., the byte with the lower address) will contain
the quotient; the high order byte will contain the remainder.
(lOW byte DEST) - (DEST) I (SAC)
(high byte DEST) - (DEST) MOD (SRC)
The above two statements are performed concurrently.

Assembly Language Format: DST SRC

DIVUB wreg, baop

Object Code Format: 100111aa 1[ baop 1[ wreg 1

z ST

3-15
 MCS®·96INSTRUCTION.SET

28. DJNZ - DECREMENT AND JUMP IF NOT ZERO 1', '

Operation: The value of the .byte operand is decremented by 1.lf the result is not equal to
0, the distance ,from the end of this instruction to the target label is added to
. the program counter, effecting the jump. The offset from the end of this in-
struction to the target label must be in the range of - 128 to + 127. If the
result of the decrement is zero then c(;mtrol passes to the next sequential
instruction.
(COUNT) ~ (COUNT) ~ 1
if (COUNT) < > 0 then
PC ~ PC + disp (sign-extended to 16 bits)
end_if

Assembly·Language Format: DJNZ breg,cadd

Object Code Format: ( 111 00000 1[ breg 1[ disp 1.

Flags Affected
Z 1 N 1 C 1 V 1VT 1ST

-1-1-1-1-1-

29. DJNZW - DECREMENT AND JUMP IF NOT ZERO WORD (80C196KB and
80C196KC only)

Operation: This instruction is the same as the DJNZ except that the count is a word
operand.: A counter word is decremented; if the result is not zero the jump is
taken. The range of the jump is -128 to + 127.

COUNT ~ COUNT ~ - 1
if COUNT < > 0 then
PC ~ PC + disp (sign extended)

Assembly Language Format: DJNZW wreg,cadd

Object Code Format: [11100001 1 [ wreg 1 [disp 1

Z ST

3-16
 MCS@·96 INSTRUCTION SET

30. OPTS - OISPOSABLEPERIPHERAL 'TRANSACTION SERVER

(PTS":'" 80C196KC only)

Operation: The PiS is disabled following the execution of this instruction.

PTS.Disable (PSW.10) +- 0

'" ,~. .
Assembly Language Format: OPTS

Object Code Format: [ 11101100,]

z ST

31. EI- ENABLE INTERRUPTS

OperaJlon: 'Interrupts are erlsbled following the execution of'the next statement. Interrupt-
calls cannot occur immediately folloWing this ,instruction.
Interrupt Enable (PSW.9) +- 1

Assembly Language Format: EI

Object Code Format: [ 11111011]

z ST

-3-17
 inter MCS~·96INSTRUCT:ION.SE:r .

32. EPTS - ENABLEPERtPHERAL' TRANSACTION -SERVER" ,;.

(PTS - 80C196KC o n l y ) ' ". '

. ,Operation: The PTS is enabled following the execution of this. instruction.

PTS Enable (PSW.19) +-. 1 ,

Assembly Language Format: EPTS

Object Code Format: [ 11101101

z ST

1, I '. 33. EXT - SIGN EXTEND INTEGER INTO 'LONG·I~TEGER " :

"\, "

),.',,: "

Op~ratlon: The lo~; Qrder wQrd of the operand is sign-extended throughout the high order
," , worQ ophe operand. " , , ."
if (low word DEST) < BOOOH then
(high word DEST) +- 0
else
(high word DEST) .,...: OFFFFH
enc:Lif

Assembly Language Format: EXT \ Ireg

, .
Object Code Format: [ 00000110 1[ Ireg

Flags Affected
ZINlclvlVTlsT
~ 1~ 10 10 1- I -
 MCS®·96 INSTRUCTION SET

34. EXTB - SIGN EXTEND SHORT-INTEGER INTO INTEGER

Operation: The low order byte of the operand is sign-extended throughout the high order"
byte of the operand.
if (low byte DEST) < SOH then
(high byte DEST) +- 0
else
(high byte DEST) +- OFFH
end_if

Assembly Language Format: EXTB wreg

Object Code Format: [ 00010110 I[ wreg I

Flags Affected
zlNlclVIVTIST
,;1,;1010"1-1-

35. INC -INCREMENT WORD

Operation: The value of the word operand is incremented by 1.

(DEST) +- (DEST) + 1

Assembly Language Format: INC wreg

Object Code Format: [ 00000111 I[ wreg I

FI,gs Affected
z 1N I" c 1V 1VT 1ST
,,;J,;I,;I,;I i 1-

3-19
 MCS®-96 INSTRUCTION SET

36. INCB -INCREMENT BYTE

Operation: The value of the byte operand is incremented by 1.

(DEST) - (DEST) + 1

Assembly Language Format: INCB breg

Object Code Format: [ 00010111 1 [ breg

ST

37. IDLPD - IDLE/POWERDOWN (80C196KB and 80C196KC only)

powe~down modes. Select-

Operation: This instruction is used for entry into the idle and
ing IDLE or POWER DOWN is done using the key operand .. If the operand is
not a legal key, the part executes a reset sequence. The bus controller will
complete any prefetch cycle in progress before the CPU stops or resets.

if KEY = 1 then enter IDLE

=
else if KEY 2 then enter
POWERDOWN
else execute reset.

Assembly Language Format: IDLPD #key (key is a-bit value)

Object Code Format: [111101101 [ key 1

Flags Affected
Z N V VT C x I ST
Legal Key:
Illegal Key:
- - -
0 0 0
-
0
-0 X
X
-
0
-
0
( - = Unchanged)

3-20
inter MCS®·96 INStRUCTION SET

38. JBC - JUMP IF BIT CLEAR

Operation: The specified bit is tested. If it is clear (Le., 0), the distance from the end of this
instruction to the target label is added to the program counter, effecting,the
jump. The offset from the end of this instruction to the target label must be in
the range of -128 to + 127. If the bit is set (Le., 1), control passes to the next
sequential instruction.
if (specified bit) = 0 then
PC +- PC + disp (sign-extened to 16 bits)

Assembly Language Format: JE;lC breg,bitno,cadd

Object Code Format: [ 0011 Obbb 1 [ breg 1 [ disp 1

where bbb is the bit number within the specified register.

z ST

3-21
 MC$®-.96 INSTRUCTION SET

39.~ JBS - JUMP IF BIT SET

Operation: The specified bit is tested. If it is set (i.e., 1),Jhe distance from the end of this
instruction to the target label is added to the program counter, effecting the
jump. The offset from the end of this instruction to the target I.abel must be in
the range of -128 to + 127. If the bit is clear (i.e., 0), control passes to the
next sequential instruction.
if (specified bit) = 1 then
PC +- PC +disp (sign-extended to 16 bits)

Assembly Language Format: JBS breg,bitno,cadd

Object Code Format: [ 00111 bbb )[ breg I [ disp I

where bbb is the bit number within the specified register.

z ST

40. JC - JUMP IF CARRY FLAG IS SET

Operation: If the carry flag is set (i.e., 1), the distance from the end of this instruction to
the target label is added to the program counter, effecting the jump. The offset
from the end of this instruction to the target label must be in the range of
-128 to + 127. If the carry flag is clear (i.e., 0), control passes to the next
sequential instruction.
if C = 1 then
PC +- PC + disp (sign-extended to 16 bits)

Assembly Language Format: JC cadd

, Object Code Format: [ 11011011 I[ disp

ST

3-22
 MCS®·96 INSTRUCTION SET

41. JE-JUMP IF EQUAL

Operation: If the zero flag is set (i.e., 1), the distance from the' end of this instruction to the
target label is added to the program counter, effecting the Jump. The offset
from the end of this instruction to the target label must be in the range of
-128 to + 127. If the zero flag is clear (i.e., 0), control passes to the next
,sequential instruction.
ifZ=1then
PC +- PC + qisp (sign-extended to 16 bits)

Assembly Language Format: JE cadd

Object Code Format: 11011111] [ disp ]

Z ST

42. JGE-JUMP IF SIGNED GREATER THAN OR EQUAL

Operation: If the negative flag is clear (i.e., 0), the distance from the end of this instruction
, to the target label is added to the program counter, effecting the jump. The
offset from the end of this instruction to the target label must be in the range
of --:,128 to + 127. If the negative flag is set (Le., 1), control passes to the next
. sequential instruction.
ifN = o then
PC +- PC +- disp (sign-extended to 16 bits)

Assembly Language Format: JGE cadd

Object Code Format: [ 11010110 ] [ disp

Z ST

('

3·23
 MCS®·96 INSTRUCTION:SET

43. JGT-JUMP IF. SIGNED GREATER THAN

Operation: If both the negative flag and the zero flag are clear (Le., 0), the distarice from
the end of this instruction to the target label is added to the program counter,
effecting the jump. The offset from the end of this instruction to the target
label must be in the range of - 128 to + 127. If either the negative flag or the
zero flag are set (Le., 1,) control passes to the next sequential instruction.
if N = 0 AND Z = 0 then
PC ~ PC + disp (sign-extended to 16 bits)

Assembly Language Format: JGT cadd

Object Code Format: [ 11010010 1[ disp

.2 ST

'-

44. JH - JUMP IF HIGHER (UNSIGNED)

Operation: If the carry flag is set (Le., 1), but the zero flag is not, the distance from the end
of this instruction to the target label is added to the program counter, effecting
the jump. The offset from the end of this instruction to the target label must be
in the range of -128 to + 127. If either the carry flag is clear or the zero flag is
set, control passes to the next sequential instruction.
if C = 1 AND Z = 0 then
PC ~ PC + disp (sign-extended to 16 bits)

Assembly Language Format: JH cadd

Object Code Format: [ 11011001 1[ disp

Z ST

3-24
 MCS®·96 INSTRUCTION SET

4,5. JLE - JUMP IF SIGNED LESS THAN OR EQUAL

Operation: If either the negative flag or the zero flag are set (Le., 1), the distance from the
end of this instruction to' the target label is added to the program counter,
effecting the jump. The offset from the end of this instruction to the target
label must be in the range of - 128 to + 127. If both the negative flag and the
zero flag are clear (Le., 0), control passes to the next sequential instruction.
if N = 1 OR Z = 1 then
PC +,- PC + disp (sign-extended to 16 bits)

Assembly Language Format: JLE cadd

Object Code Format: [ 11011010 I[ disp I

Flags Affected
1N 1C 1V VT 1ST
, Z·
-1-1-1- -1-

46. JLT - JUMP IF SIGNED LESS THAN

Operation: If the negative flag is set (Le.; 1), the distance from the end of this instruction
to the target label is added to th.e program counter, effecting the jump. The
offset from the end of this instruction to the target label must be in the range
of -128 to+ 127. If the nl'lgative flag is clear (Le., 0), control passes to the
next sequential instruction.
ifN=1then
PC -- PC + disp (sign-extended to 16 bits)

Assembly Language Format: JLT cadd

Object Code Format: [ 11011110 I[ disp I

Flags Affected
zlNICIVIVTIST
-1-1'-1-1-1-

3-25
 MCS®·96 INSTRUCTION SET

47. JNC-JUMP IF CARRY FLAG IS CLEAR

Operation: If the carry flag is clear (i.e., 0), the distance from the end of this instruction to
the target label is added to the program counter, effecting the jump. The offset
from the end of this instruction to the target label must be in the range of
-128 to + 127. If the carry flag is set (Le., 1), control passes to the next
sequential instructiQn. .
if C = 0 then
PC - PC + disp (sign-extended to 16 bits)

Assembly Language Format: JNC cadd

Object Code Format: [ 11010011 1[ disp 1

Flags Affected
zlNICIVIVTIST

-1-1-1-1-1-

48. JNE - JUMP IF NOT EQUAL

Operation: If the zero flag is clear (i.e., 0), the distance from the end of this instruction to
the target label is added to the program counter, effecting the jump. The offset
from the end of this instruction to the target label must be in the range of
-128 to + 127. If tbe zero flag is set (Le., 1), control passes to the next
sequential instruction.
if Z = 0 then
PC - PC + disp (sign-extended to 16 bits)

Assembly Language Format: JNE cadd

Object Code Format: [ 11010111 [disp 1

? . ST

3-26
inter MCS®-96 INSTRUCTION SET

49. JNH - JUMP iF NOT HIGHER (UNSIGNED)

Operation: If either the carry flag is clear (i.e., 0), or the zero flag is set (Le., 1), the
distance from the end of this instruction to the target label is added to program
counter, effecting the jump. The offset from the end of this instruction to the
target label must be in the range of - 128 to + 127. If the carry flag is set (Le.,
1) and the zero flag is not, control passes to the next sequential instruction.
if C = 0 OR Z = 1 then
PC +- PC + disp(sign-extended to 16 bits)
Assembly Language Format: JNH cadd

- Object Code Format: [ 11010001 I[ disp

Z ST

50. JNST - JUMP IF STICKY BIT IS CLEAR

Operation: If the sticky bit flag is clear (Le., 0), the distance from the end of this instruction
to the target label is added to the program counter, effecting the jump. The
offset from the end of this instruction to the target label must be in the range
of -128 to + 127. If the sticky bit flag is set (Le., 1), control passes to the next
sequential instruction.
if ST = 0 then
PC +- PC + disp (sign-extended to 16 bits)

Assembly Language Format: JNST cadd

Object Code Format: [ 11010000 I[ disp

Z ST

3-27
 MCS®·96 INSTRUCTION SET

51. JNV - JUMP IF OVERFLOW FLAG IS CLEAR·

Operation: If the overflow flag is clear (Le., 0), the distance from the end of this instruction
to the target label is added to the program counter, effecting the jump. The
offset from the end of this instruction to the target label must be in the range
of -128 to +127. If the overflow flag is set (Le., 1), control passes to next
sequential instruction.
ifV=Othen
PC -- PC + disp (sign-extended to 16 bits)

Assembly Language Format: JNV c~dd

ObjectCodeFormat: [/11010101 ] [ disp ]

Flags Affected
zlNlclvlVTlsT

-1-1-1-1-1-

52. JNVT - JUMP IF OVERFLOW TRAP IS CLEAR

Operation: If the overflow trap flag is clear (Le., 0), the distance from the end of this
instruction to the target label is added to the program counter, effecting the
jump. The offset from the end of this instruction to the.target label must be in
the range of -128 to +127. if the overflow trap flag is set (Le., 1), control
passes to the next sequential instruction. The VT flag is cleared.
if VT = 0 then
PC -- PC + disp (sign-extended to 16 bits)

Assembly Language Format: JNVT cadd

Object Code Format: [ 11010100 j[ disp

ST

3-26
 MCS®·96 INSTRUCTION SE.T

53. JST - JUMP IF STICKY BIT IS SET

Operation: If the sticky bit flag is set (Le., 1), the distance from the end of this instruction
to the target label is added to the program counter, effecting the jump. The
offset from the erid of this instruction to the target label must be in the range
of -128 to + 127. If the sticky bit flag is clear (i,e., 0), control passes to the
next sequential instruction.
if ST= 1 then
PC +- PC + disp (sign-extended to 16 bits)

Assembly Language Format: JST cadd

Object Code Format: [ 11011000 1[ disp 1

z ST

54. JV - JUMP IF OVERFLOW FLAG IS SET

Operation: If the overflow is set (Le., 1), the distance from the end of this instruction to the
target label is added to the. program counter, effecting the jump. The offset
from the end of this instruction to the target label must be in the range of
-128 to + 127. If the overflow flag is clear (Le., 0), control passes to the next
sequential instruction.
if V = 1 then
PC +- PC + disp (sign-extended to. 16 bits)

Assembly Language Format: JV cadd

Object Code Format: [ 11011101 1[ disp

z ST

3-29
 MCS®~96 INStRUCtiON SET

55. JVT - JUMP IF OVERFLOW TRAP IS SET

Operation: If the overflow trap flag is set (Le., 1), the distance from the end of this instruc-
tion to the target label is added to the program counter, effecting the jump.
The offset from the end of this instruction to the target label must be in the
range of -128 to + 127. If the overflow trap flag is clear (Le., 0), control
passes to the next sequential instruction. The VT flag is cleared.
if VT = 1 then
PC - PC + disp (sign-extended to 16 bits)

Assembly Language Format: JVT cadd

Object Code Format: [ 11011100 1[ disp 1

Flags Affected
ZINlclvlvTlsT
-1~1-1-lol-

56. LCALL - LONG CALL

Operation: The contents of the program counter (the return address) is pushed onto the
stack. Then the distance from the end of this instruction to the target label is
added to the program counter, effecting the call. The operand may be any
address in the entire address space.
SP - SP - 2
(SP) - PC
Pc. - PC + disp

Assembly Language Format: LCALL cadd

Object Code Format: 11101111 1[ disp-Iow 1[ disp-hi 1

Flags Affected
z I NI C I V I vrl ST
-\-\-I,-I-J-'

3-30
 MCS®-96 INSTRUCTION SET

57. LD-LOAD WORD

Operation: The value of the source (rightmost) word operand is stored into the destination
(leftmost) operand.
(OEST) - (SRC)

Assembly Language Format: OST SRC

LO wreg, waop

ObjeC~1COde Format: 101000aa 1[ waop 1[ wreg 1

z ST

58. LDB - LOAD BYTE

Operation: The value of the source (rightmost) byte operand is stored into the destination
(leftmost) operand.
(OEST) - (SRC)

Assembly Language Format: OST SRC

LOB breg, baop

Object Code Format: [ 1011 OOaa 1[ baop 1[ breg 1

Flags Affected
zlNICIVIVTIST
-1-1-1-1-1-

3·31
 MCS®-96 INSTRUCTIONS!:T j
,~

59. LDBSE --LoAD INTEGER WITH SHORT-INTEGER

Operation: The value of the source (rightmost) byte operand is sign-extended and stored
into the destination (leftmost) word operand.
(low byte DEST) +- (SAC)
if (SAC) < 80H then
(high byte DEST) +- 0
else
(high byte DEST) +- OFFH
end_if

Assembly Language Format: DST SAC

LDBSE wreg. baop

Object Code Format: [ 101111 aa 1[ baop 1[ wreg

Flags Affected
Z1N 1c 1V 1VT 1ST
-1-1-1-1-1-

60. LDBZE - LOAD WOAD WITH BYTE

Operation: The value of the source (rightmost) byte operand is zero-exte,nded and stored
into the destination (leftmost) word operand.
(low byte DEST) +- (SAC)
(high byte DEST) +- 0

Assembly Language Format: DST SAC

LDBZE wreg.' baop

Object Code Format: [ 101011aa 1[ baop 1[ wreg 1

Flags Affected
zlNlclvlVTlsT
-1-1-1-1-1-

3-32
 MCS®-96 INSTRUCTION SET

&1. LJMP - LONG JUMP

Operation: The distance from the end of this instruction to the target label is added to the
program counter, effecting the jump. The operand may be any address in the
.entire address space.
PC::: - PC+ disp

Assembly Language Format: LJMP cadd

Object Code Format: [ 11100111 I[ disp-Iow I[ disp-hi I

z ST

62.· MUL (Two Operands) - MULTIPLY INTEGERS

Operation: The two INTEGER operands are multiplied using signed arithmetic and the 32-
bit result is stored into the destin/!,tion (leftmost) LONG·INTEGER operand.
The sticky bit flag is undefined after the instruction is executed.
(DEST) - (DEST)· (SRC)

Assembly Language Format: DST SRC

MUL Ireg, waop

Object Code Format: 11111110 I[ 011011 aa I[ waop I[ Ireg I

z ST
?

3-33
inter MCS®·96 INSTRUCTION SET

63. MUL (Three Operands) - MULTIPLY INTEGERS

Operation: The second and third INTEGERoperands are multiplied. using Signed arithme-
tic and the 32-bit result is stored into the destination (leftmost) LONG INTE-
GER operand. The sticky bit flag is undefined after the instruction is executed.
(DEST) - (SRC1) • (SRC2)

Assembly Language Format: DST SRC1 SRC2

MUL Ireg, wreg, waop

Object Code Format: [ 11111110 1[ 010011aa 1[ waop 1[ wreg 1[ Ireg 1

z ST
?

.
64. MULB (Two Operands) - MULTIPLY SHORT-INTEGERS

Operation: The two SHORT-INTEGER operands are multiplied using signed arithmetic
and the 16-bit result is stored into the destination (leftmost) INTEGER oper-
and. The sticky bit flag is undefined after the instruction is executed.
(DEST) - (DEST)' (SRC)

Assembly Language Format: DST SRC

MULB wreg, baop

Object Code Format: [ 11111110 1 [' 011111aa, 1[ baop ] [ wreg 1

z ST
?

3-34
inter MCS®·96 INSTRUCTION SET

65. MULB (Three Operands) - MULTIPLV' SHORT·INTEGERS

Operation: The second and third SHORT-INTEGER operands are multiplied using signed
arithmetic and the 16-bit result is stored into the destination (leftmost) INTE-
GER operand. The sticky bit flag is undefined after the instruction is executed.
(DEST) +- (SRC1)· (SRC2)

Assembly Language Format: DST SRC1 SRC2

MULB wreg, breg baop

Object Code Format: [ 11111110 1[ 010111aa 1[ baop 1[ breg 1[ wreg 1

z ST
?

66. MULU (Two Operands) -..: Ml,!LTIPLV WORDS

Operation: The two WORD operands are multiplied using unsigned arithmetic and the 32-
bit result is stored into the destination (leftmost) DOUBLE-WORD operand.
The sticky bit flag is undefined after the instruction is executed.
(DEST) +- (DEST)' (SRC)

Assembly Language Format: DST SRC

MULU Ireg, waop

Object Code Format: [ 011011 aa 1[ waop 1[ Ireg 1

Flags Affected
z 1N 1C 1v·1 VT 1ST
-1-1-1-1-1 ?
inter MCS\ID~96 IN.STRUCTION seT

67. MULU (Three Operands) -:- MULTIPLY WORDS

Operation: The second and third WOAD operands are multiplied using unsigned arithme-
tic and the 32-bit result is stored into the destination (leftmost) DOUBLE-
WOAD operand. The sticky bit flag is undefined after the instruction is execut-
ed.
(DEST) ~ (SAC1) • (SAC2)

Assembly Language Format: DST SAC1 SRC2

MULU Ireg, wreg, waop

Object Code Format: [ 010011 aa 1[ waop 1[ wreg 1[ Ireg 1

Flags Affected
zlNlclvlVTIST
-1-1-1-1-1 ?

68. MULUB (Two Operands) - MULTIPLY BYTES

Operation: The two BYTE operands are multiplied using unsigned arithmetic and the
. WORD result is stored into the destination (leftmost) operand. The sticky bit
flag is undefined after the instruction is executed.
(DEST) ~ (DEST)' (SAC)

Assembly Language Format: DST SRC

MULUB wreg, baop

Object Code Format: [ 011111 aa 1[ baop 1[ wreg 1

z ST
?

3-36
inter MCS®-96 INSTRUCTION SET

69. MULUB (Three Operands) - MULTIPLY BYTES'

Operation: The second and third BYTE operands are multiplied using unsigned arithmetic
and the WORD result is stored into the destination (leftmost) operand. The
sticky bit flag is undefined after the instruction is executed.
(DEST) +- (SRC1)' (SRC2)

Assembly Language Format: DST SRC1 SRC2

MULUB wreg, breg, baop

Object Code Format: [ 010111 aa 1[ baop 1[ breg 1[ wreg

z ST
?

70. NEG - NEGATE INTEGER

Operation: The value of the INTEGER operand is negated.

(DEST) +- - (DEST)

Assembly Language Format: NEG . wreg

Object Code Format: [ 00000011 1 [wreg 1,

Flags Affected
z I N I C I V I VT I ST
,...1,...1,...1,...1 i 1-

3·37
,
 MCS®·96 INSTRUCTION SET

71. NEGB - NEGATE SHORT-INTEGER.

Operation: Thevalue·of the SHORT·INTEGER operand is negated.

(OEST) . - - (OEST)

Assembly Language Format: NEGB breg

Object Code Format: [ 00010011 1 [ breg

ST

72. NOP - NO OPERATION

Operation: Nothing is done. Control passes to the next sequential instruction.

Assembly Language Format: NOP

Object Code Format: [ 11111101

z ST
inter MCS@·96 INSTRUCTION SET

73. NORML - NORMALIZE LONG-INTEGER

. Operation: The LONG-INTEGER operand is normalized; i.e., it is shifted to the left until its
most significant bit is 1. If the most significant bit is still 0 after 31 shifts, the
process stops and the zero flag is set. The number of shifts actually performed
is stored in the second operand.
(COUNT) +- 0
do while (MSB(DEST) = 0) AND ((COUNT) < 31)
(DEST) +- (DEST) • 2
(COUNT) +- (COUNT) + 1
end_while

Assembly Language Format: NORML Ireg,breg .

Object Code Format: [ 00001111 I[ breg I[ Ireg I

Flags Affected
z1N 1C 1V 1VT 1ST
"-17101-1-1-

74. NOT - COMPLEMENT WORD

Operation: The value of the WORD operand is complemented: each 1 is replaced with a
0, and each 0 with a 1.
(DEST) +- NOT (DEST)

Assembly Language Format: NOT wreg

Object Code Format: [ 00?00010 I[ wr.eg

ST

3-39
 Mc:S@-96 INSTRUCr.ON SET

7S~· NOTS - COMPLEMENT BYTE ". ,,'

Operation: The vaule of the BYTE operand is complemented: ~ach 1 is replaced with a 0,
and each 0 with a 1.
. (DEST) ..- .NOT (DEST)

Assembly Language Format: NOTB breg

Object Code Format: [ 00010010 I[ breg

ST

76. OR ~ LOGI~AL OR WORDS

Operation: The sc;>urce (rightmost) WORD is ORed with the destination (leftmost) WORD
operand. Each bit is set to 1 if the corresponding bit in either the source
operand or the destination operand is 1. The result replaces the original desti-
nation operand.
(DJ:ST) ..- (DEST) OR (SRC)

Assembly Language Format: DST' SRC

OR wi-eg, waop

Object Code Format: [ 100000aa I [waop I [ wreg I

ST

3-40
inter MCS®-96 INSTRUCTION SET

77. ORB - LOGICAL OR BYTES

Operation: The source (rightmost) BYTE operand is ORed with the destination (leftmost)
BYTE operand. Each bit is set to 1 if the corresponding bit in either the source
operand or the destination operand was 1. The result replaces the original
destination operand.
(DEST) - (DEST) OR (SRC)

Assembly Language Format: ORB breg,baop

Object Code Format: [ 1001 OOaa 1[ baop 1[ breg 1

Flags Affected
ZINlclvlvTlsT
"'1"'10101-1-

78. POP - POP WORD

Operatlo~: The word on top of the stack is popped and placed at the destination operand.
(DEST) - (SP)
SP - SP + 2

Assembly Language Format: POP waop

Object Code Format: [ 110011 aa 1[ waop

z ST

3-41
intJ MCS®-96 INSTRUCTION SET

79.POPA - POP ALL (80C196KB and 80C196KC only)

Operation: This instruction is used instead of POPF to support the 8 additional interrupts.
It is similar to POPF, but pops two words instead of one. The first word is
popped into the INT...,.MASK1/WSR register pair, while the second word is
popped into the PSW/INT_MASK register pair. As a result of this instruction
the SP is incremented by 4. Interrupts cannot occur between this instruction
. and the one following it.
INT_MASK1 IWSR +- (SP)
SP +- SP + 2
PSW/INT_MASK +- (SP)
SP +- SP + 2

Assembly Language Format: POPA

Object Code Format: [11110101 1

(", = changed)

80. POPF - POP F.LAGS

Operation: The word on top of the stack is popped and placed in the PSW. Interrupt calls
cannot occur immediately following this instrl,lction.
(PSW) +- (SP)
SP +- SP + 2

Assembly Language Format: POPF

Object Code Format: [ 11110011

Flags Affected
z I N I c I V I VT I ST
", I ", I ", I ", I ", I ",

3-42
 MCS®·9E$ INSTRUCTION SET

81. PUSH - PUSH WORD

Operation: The specified operand is pushed onto the stack.

SP +- SP - 2
(SP) +- (DEST)

Assembly Language Format: PUSH waop

Object Code Format: [ 11001 Oaa 1[ waop

z ST

82. PUSHA - PUSH ALL (80C196KB, 80C196KC and 80C196KR only)

Operation: This instruction is used instead of PUSHF to support the 8 additional inter-
.rupts. It is similar to PUSHF, but pushes two words instead of one. The first
word pushed is the same as for the PUSHF instruction, PSW/INT_MASK.
The second word pushed is formed by the INT_MASK1/WSR register pair.
As a result of this instruction the PSW, INT_MASK, and INT_MASK1 regis-
ters are cleared, and the SP is decremented by 4. Interrupts are disabled in
two ways by this instruction since both PSW.9 and the interrupt masks are
cleared. Interrupts cannot occur between this instruction and the one following
it.
SP +- SP - 2
(SP) +- PSW/INT_MASK
PSW/INT_MASK +- 0
SP +- SP - 2
(SP) +- INT_MASK1/WSR
INT_MASK1 +- 0

Assembly Language Format: PUSHA

Object Code Format: [11110100 1

z ST
o o

3-43
inter MCS®·96 INSTRUCTION SET

83. PUSHF - PUSH FLAGS

Operation: The PSW is pushed on top of the stack, and then set to aU zeroes. This implies
that all interrupts are disabled. Interrupt-calls cannot occur immediately follow-
ing this instruction.
SP ~ SP - 2
(SP) ~ PSW
PSW ~ 0

Assembly Language Format: PUSHF

Object Code Format: [ 11110010

z ST
.0 o

84. RET - RETURN FROM SUBROUTINE

Operation: The PC is popped off the top of the stack.

PC ~ (SP)
SP ~ SP + 2

Assembly Language Format: RET

Object Code Format: [ 11110000

z ST

3-44
inter MCS®-96 INSTRUCTION SET

85. RST - RESET SYSTEM

Operation: The PSW is initialized to zero, and the PC is initialized to 2080H. The 1/0
registers are set to their initial value. Executing this i,nstruction will cause a
pulse to appear on the reset pin.
PSW +- 0
PC' +- 2080H

Assembly Language Format: RST

Object Code Format: [ 11111111 1

Flags Affected
z I N I C I V I VT I ST
01010101010

86. SCALL - SHORT CALL

Operation: The contents of the program counter (the return address) is pushed onto the
stack. Then the distance from the end of this instruction to the target label is
added to the program counter, effecting the call. The offset from .the end of
this instruction to the target label must be in the range of -1024 to + 1023
inclusive.
SP +- SP - 2
(SP) +- PC
PC +- PC + disp (sign-extended to 16 bits)

Assembly Language Format: SCALL cadd

Object Code Format: [ 00101xxx I [ disp-Iow I

where xxx holds the three high-order bits of displacement.

z ST

3-45
inter MC~®·96 I~STRUqT'ON SET

87. SETC-SET CARRY FLAG

Opera~ion: The carry flag is set.

C-1

Assembly Language Format: SETC

Object Code Format: 11111001

z ST

88. SHL - SHIFT WORD LEFT

Operation: The destination (leftmost) word operand is shifted left as many times as speci-
fied by the count (rightmost) operand. The count may be specified either as an
immediate value in the range of 0 to 15 (OFH) inclusive, or as the content of
any register above 15H. Details on indirect shifts can be found in the Over-
view. The right bits of the result are filled with zeroes. The last bit shifted out is
saved in the carry flag.'
Temp _ (COUNT)
do while Temp < > 0
C - High order bit of (DEST)
(DEST) - (DEST) • 2
. Temp - Temp-1
end_while

Assembly Language Format: SHL wreg,#count

or
SHL wreg,breg

Object Code Format: [ 00001001 1[ cntlbreg 1[ wreg 1

Flags Affected
ZINlclvlVTIST
,..., I ? I,..., I ,..., I t 1-

3-46
inter MCS®-96 INSTRUCTION SET

89.. SHLB - SHIFT BYTE LEFT

Operation: The destination (leftmost) byte operand is shifted left as many times as speci-
fied by the count (rightmost) operand. The count may be specified either as an
immediate value in the range of 0 to 15 (OFH) inclusive, or as the content of
any register above 15H. Details on indirect shifts can be found in the Over-
view. The right bits of the result are filled with zeroes. The last bit shifted out is
saved in the carry flag.
Temp +- (COUNT)
do while Temp < > 0
C +- High order bit of (DESn
(DEST) +- (DEST) • 2
TEMP +- Temp - 1
end_while

Assembly Language Format: SHLB breg, # count

or
SHLB br~g,breg

Object Code Format: [ 00011001 1[ cnt/breg 1[ brag 1

ST

3-47
 MC$@~96 fNSTRUCTION SET

90. SHLL - SHIFT DOUBLE..'WORD LEFT

Operation: The destination (leftmost) double-word' operand is Shifted left as many times
as specified by the count (rightmost) operand. The count may be specified
either as an immediate value in the range of 0 to 15 (OFH) inclusive, or as the
content of any register above 15H. Details on indirect shifts can be found in
the Overview. The right bits of the result are filled with zeroes. The last bit
shifted out is saved in the carry flag.
Temp - (COUNT)
do while Temp < > 0
C - High order bit of (DEST)
(DEST) - (DEST)' ,2
Temp - Temp - 1
end_while

Assembly Language Format: SHLL Ireg, # count

or
SHLL Ireg, breg

Object Code Format: [ 00001101 ] [ cnt/breg 1[ Ireg ]

ST

;3-48
 MCS®·96 INSTRUCTION SET

91. SHR - LOGICAL RIGHT SHIFT WORD

Operation: The destination (leftmost) word operand is shifted right as many times as
specified by the count (rightmost) operand. The count may be specified either
as an immediate value in the range of 0 to 15 (OFH) inclusive, or as the
content of any register above 15H. Details on indirect shifts can be found in
the OVerview. The left bits of the result are filled with zeroes. The last bit
shifted out is saved to the carry. The sticky bit flag is cleared at the beginning
of the instruction, and set if at any time during the shift a 1 is shifted first into
the carry flag, and a further shift cycle occurs.
Temp - (COUNT)
do while Temp < > 0
C - Low order bit of (DEST)
(DEST) - (DEST) / 2 where / is unsigned division
Temp - Temp - l'
end_while

Assembly Language Format: SHR wreg, # count

or
SHR wreg,breg

Object Code Format: [ 00001000 1[ cnt/breg 1[ wreg 1

3-49
 ,. " v
MCS~-96 INSTRUCTION SET

92. SHRA - ARITHMETIC RIGHT SHIFT WORD

Operation: The destination (leftmost) word operand is shifted right as many times as
. specified by the count (rightmost) operand. The count may be specified either
as an immediate value' in the range ·of o· to 15 (OFH) inclusive, or as the
content of any register above 15H. Details on indirect shifts can be found in
the Overview: If the original high order bit value was 0, zeroes are shifted in. If
the value was 1, ones are shifted in. The last bit shifted out is saved in the
carry. The sticky bit flag is cleared at the beginning of the instruction, and set if
at any time during the shift a 1 is shifted first into the carry flag, and a further
shift cycle occurs.
Temp ..- (COUNT)
do while Temp < > 0
C ..- Low order bit of (DEST)
(DEST) ..- (DEST) / 2 where / is signed division
Temp ..- Temp - 1
end_while

Assembly Language Format: SHRA wreg, #count

or
SHRA wreg,breg

Object Code Format: [ 00001010 1[ cntlbreg 1[ wreg 1

3-50
intJ MCS®·96 INSTRUCTION SET

93. SHRAB - ARITHMETIC RIGHT SHIFT BYTE

Operation: The destination (leftmost) byte operand is shifted right as many times as spec-
ified by the count (rightmost) operand. The count may be specified either as
an immerliate vdlue in the range of 0 to 15 (OFH) inclusive, or as the content of
any register above 15H. Details on indirect shifts can be found in the Over-
. view. If the original high order bit value was 0, zeroes are shifted in. If that
value was 1, ones are shifted in. The last bit shifted out is saved in the carry.
The sticky bit flag is cleared at the beginning of the instruction, and set if at
anytime during the shift a 1 is shifted first into the carry flag, and a further shift
cycle occurs.
Temp - (COUNT)
do while Temp < > 0
C, = Low order bit of (DEST)
(DEST) - (DEST) / 2 where / is signed division
Temp - Temp - 1
end_while

Assembly Language Format: SHRAB breg, #count

or
SHRAB breg,breg

Object Code Format: [ 00011010 1[ cntlbreg 1[ breg 1

3-51
 MCS®·96 INSTRUCTION SET

94. SHRAJ,. - ARITHMETIC RIGHT SHIFT DOUBLE-WORD

Operation: The destination (leftmost) double-word operand is shifted right as many times
as specified by the count (rightmost) operand. The count may be specified
either as an immediate value in the range of 0 to 15 (OFH) inclusive, or as the
content of any register above 15H. Details on indirect shifts can be found in
the Overview. If the original high order bit value was 0, zeroes are shifted in. If
the value was 1, ones are shifted in. The sticky bit is cleared at the beginning
of the instruction, and set if at any time during the shift a 1 is shifted first into
the carry flag, and a further shift cycle occurs.
Temp+- (COUNT)
do while Temp < > 0
C +- Low order bit of (DEST)
(DEST) +- (DEST) I 2 where I is signed division
Temp +- Temp - 1
end_while

Assembly Language Format: SHRAL Ireg,#count

or
SHRAL Ireg,breg

Object Code Format: [ 00001110 1[ cntlbreg 1[ ireg 1

3-52
inter MCS®·96 INSTRUCTION SET

95. SHRB - LOGICAL RIGHT SHIFT'BYTE

Operation: . The destination (leftmost) byte operand is shifted right as many times as spec-
ified by the count (rightmost) operand, The count may be specified either as
an immediate value 'in the range of 0 to 15 (OFH) inclusive, or as the content of
any register above 15H. Details on indirect shifts can be found in the Over-
view. The left bits of the result are filled with zeroes. The last bit shifted out is
saved in the carry. The sticky bit flag is cleared at the beginning of the instruc-
tion, and set if at any time during the shift a 1 is shifted first into the carry flag,
and a further shift cycle occurs.
Temp +- (COUNT)
do while Temp < > 0
C +- Low order bit of (DEST)
(DEST) +- (DEST) / 2 where / is unsigned division
Temp +- Temp - 1
end_while

Assembly Language Format: SHRB breg, #count

or
SHRB breg,breg

Object Code Format: 00011000 I[ cntlbreg I[ breg I

Flags Affected
ZINlclvlvTlsT
~101~101-1~

3-53
inter MCS®·96 INSTRUCTION SET

96. SHRL - LOGICAL RIGHT SHIFT DOUBLE.:WORD

Operation: The destination (leftmost) double-word operand is shifted right as many times
as specified by the count (rightmost) operand .. The count may be specified
either. as an immediate value lin the range of 0 to 15 (OFH) inclusive, or as the
content.of any register above 15H. Details on indirect shifts can be found in
the Overview. The .left· ;bits of the, result are filled with zeroes. The last bit
shifted out is saved in the c<\rry. The sticky bit flag is cleared at the beginning
of the instruction, and set if at any time during the shift a 1 is shifted first into
the carry flag, and a .further shift cycle occurs. .
Temp . - (COUNT)
do while Temp < > 0
C . - Low order bit of (DEST)
(DSET) . - (DEST) I 2 where I is unsigned division
Temp . - Temp - 1
end_while

Assembly Language Format: SHRL Ireg,#count

or
SHRL Ireg,breg

Object Code Format: [ 00001100 J [ cnt/breg J [ Ireg· J

Flags Affected
zlNlclvlvTIST
..-101..-101-1..-

3-54
intJ MCS®·96 INSTRUCTION SET

97. SJMP-SHORT JUMP

Operation: The distance from the end of this instruction to the target label is added to the
program counter, effecting the jump. The offset from the end of this instruction
to the label must be in the range of -1024 to + 1023 inclusive.
PC ~ PC + disp (sign-extended to 16 bits)

Assembly Language Format: SJMP cadd

Object Code Format: [ 00100xxx 1 [ disp-Iow 1

where xxx holds the three high order bits of the displacement.

Flags Affected
z 1 N 1 C 1 V 1VT 1ST
-1-1-1-1-1-

98. SKIP - TWO BYTE NO·OPERATION

Operation: Nothing is done. This is actually a two-byte NOP where the second byte can
b~ any value, and is simply ignored. Control passes to the next sequential
instruction.

Assembly Language Format: SKIP breg

Object Code Format: [ 00000000 1[ breg

z ST

3-55
 MCS®~96 INSTRUCTION SET

99. ST - STORE WORD

Operation: The value of the leftmost word operand is stored into the rightmost operand.
(DEST) - (SRC)

Assembly Language Format: SAC DST

ST wreg, waop

Object Code Format: [ 110000aa 1[ waop 1[ wreg 1

z ST

100. STB - STORE BYTE

Operation: The value of the leftmost byte operand is stored into the rightmost operand.
(DEST) - (SRC)

Assembly Language Format: SRC DST

STB breg, baop

Object Code Format: [ 110001 aa 1[ baop 1[ breg 1

z ST

3·56
 1
MCS®·96 INSTRUCTION SET

101. SUB (Two Operands) - SUBTRACT WORDS

Operation: The source (rightmost) word operand is subtracted from the destination (left-
most) wOrd operand, and the result is stored in the destination. The carry flag
is set as complement of borrow.
(DEST) - (DEST) - (SRC)

Assembly Language Format: DST SRC

SUB wreg, waop

Object Code Format: [ 01101 Oaa ] [ waop ] [ wreg ]

ST

102. SUB (Three Operands)....;. SUBTRACT WORDS

Operation: The source (rightmost) word operand is subtracted from the second word
operand, and the result is stored in the destination (the leftmost operand). The
carry flag is set as complement of borrow.
(DEST) - (SRC1) - (SRC2)

Assembly Language Format: DST SRC1 SRC2,

SUB wreg, wreg, waop

Object Code Format: [ 010010aa ] [ waop ] [ Sweg] [ Dwreg ]

ST

3-57
inter MCS®·96 INSTRUCTION SET

103. SUBB (Two Operands) - SUBTRACT BYTES

Operation: The source (rightmost) byte is subtracted from the destination (leftmost) byte
operand, and the result is stored in the destination. The carry flag is set as
complement of borrow.
(DEST) +- (DEST) - (SRC)

Assembly Language Format: DST SRC

SUSS breg. baop

Object Code Format: [ 011110aa 1[ baop 1[ breg 1

Flags Affected
ZINICIVIVTIST
,...1,...1,...1,...1 t 1 -

104. SUBB (Three Operands) - SUBTRACT BYTES

Operation: The source (rightmost) byte operand.is subtracted from the second byte oper-
and. and the result is stored in the destination (the leftmost operand). The
carry flag is set as complement of borrow.
(DEST) +- (SRC1) - (SRC2)

Assembly Language Format: DST SRC1 SRC2

SUSS breg. Sbreg baop

Object Code Format: [ 010110aa 1[ baop 1[ Sbreg 1[ Dbreg 1

ST

3-58
inter MCS®-96 INSTRUCTION SET

105. SUBC - SUBTRACT WORDS WITH BORROW

Operation: 'The source (rightmost) word operand is subtracted from the destination (Ieft-
, most) word operand. If the carry flag was clear, 1 is subtracted from the above
result. The result replaces the orignal destination operand. The carry flag is
set as complement of borrow.
(DEST) +- (DEST) - (SRC) - (1-C)

Assembly Language Format: DST SRC

SUBC wreg, waop

Object Code Format: [ 101010aa 1[ waop 1[ wreg 1

Flags Affected
z 1 N 1 C 1 V 1 VT 1 ST
i 1,...1,...1,...1 t 1 -

106. SUBCB - SUBTRACT BYTES WITH BORROW

Operation: The source (rightmost) byte operand is subtracted from the destination (left-
most) byte operand. If the carry flag was clear, 1 is subtracted from the above
result. The result replaces the original destination operand. The carry flag is
set as complement of borrow.
(DEST) +- (DEST) - (SRC) - (1-C)

Assembly Language Format: DST SRC

SUBCB breg, baop

Object Code Format: [ 10111 Oaa 1[ baop 1[ breg 1

ST

3-59
inter MCS®·96 INSTRUCTION SET

107. TIJMP - TABLE INDIRECT JUMP (80C196KC and 80C196KRonly)

Operation: The execution continues at an address selected· out of a table of addresses.

TBASE .is a word register which contains the 1S-bit address of the beginning
of the table. INDEX is a word register containing the 1S-bit address of a byte
which contains the index into the table. INDEX-MASK is ANDed with the
index. The index must be between 0 and 128.
ADDRESS CALCULATION
[INDEX] AND INDEX_MASK = OFFSET
(2 • OFFSET) + [TBASE] = DEST X-

Assembly Language Format: TBASE [lNDEX1.#INDEX-MASK

TIJMP wreg, wreg # byte
[INDEX] [TBASE]

Object Code Format: [ 11100010 1 [ wreg 1 [ # byte 1 [ wreg 1

z ST

3-S0
intJ MCS®·96 INSTRUCTION SET

108. TRAP - SOFTWARE TRAP

Operation: This instruction causes an interrupt-call which is vectored through location

2010H. The operation of this instruction is not effected by the state of the
interrupt enable flag in the PSW (I). Interrupt-calls cannot occur immediately
following this instruction. This instruction is intended for use by Intel provided
development tools. These tools will not support user-application of this in-
struction ..
SP +- SP - 2
(SP) +- PC
PC +- (2010H)

Assembly Language Format: This instruction is not supported by revision 1.2 of the 8096 assembly lan-
guage.

Object Code Format: [ 11110111

z ST

109. XOR - LOGICAL EXCLUSIVE·OR WORDS

Operation: The source (rightmost) word operand is XORed with the destination (leftmost)
word operand. Each bit is set to 1 if the corresponding bit. in either the source
operand or the destination operand was 1, but not both. The result replaces
the original destination operand.
(OEST) +- (OEST) XOR (SRC)

Assembly Language Format: OST SRC

XOR wreg, waop

Object Code Format: [ 100001aa 1 [ waop 1 [ wreg 1

Flags Affected
ZINlclvlvTlsT
"]"[0[01-1-

3-61
inter MCS®·96 INSTRUCTION SET

110. XCH - EXCHANGE WORD (80C196KC only)

Operation: The value of the source (rightmost) word operand is exchanged with the desti-
'nation (leftmost) operand.
(DEST) - (SRC)

Assembly Language Format: DST SRC

XCH wreg, waop

Object Code Format: [ 00000100 1[ waop 1[ 'wreg

[ 00001011 1
I , Flags Affected . I
I~I:I~I~I:I:I

111. XCHB - EXCHANGE BYTE (80C196KC only)

Operation: The value of the source (rightmost) byte operand is exchanged with the desti-
nation (leftmost) operand. .
(DEST) - (SRC)

Assembly Language Format: DST SRC

XCHB breg, baop

Object Code Format: 00010100 1[ baop 1[ breg 1

00011011 1
Flags Affected
z I N J C J V 1VT 1ST
-1-1-1-1-1-

3-62
intJ MCS®·96 INSTRUCTION SET

112. XORB - LOGICAL EXCLUSIVE·OR BYTES

Operation: The source (rightmost) byte operand is XORed with the destination (leftmost)
byte operand. Each bit is set to 1 if the corresponding bit in either the source
operand or the destination operand was 1, but not both. The result replaces
the original destination operand.
(DEST) ~ (DEST) XOR (SRC)

Assembly Language Format: DST SRC

XORB breg, baop

Object Code Format: [ 100101aa I[ baop I[ breg I

ST

3·63
80C196KB User's Guide 4
and Data Sheets
 November 1990

80C196KB
User's Guide

Order Number: 270651-003

4-1
 80C196KB USER'S GUIDE
CONTENTS PAGE CONTENTS PAGE

1.0 CPU OPERATION .................... 4-4 '6.0 Pulse Width Modulation Output
1.1 Memory Controller ................. 4-5 (D/A) ................................. 4-36
1.2 CPU Control ....................... 4-5 6.1 Analog Outputs ................... 4-38
1.3 InternalTiming ..................... 4-5 7.0 TIMERS . ............................ 4-39
2.0 MEMORY SPACE .................... 4-7 7.1 Timer1 ........................... 4-39
2.1 Register File ....................... 4-7 7.2 Timer2 ........................... 4-39
2.2 Special Function Registers ......... 4-7 7.3 Sampling on External Timer
Pins ............................... 4-39
2.3 Reserved Memory Spaces ........ 4-11
7.4 Timer Interrupts .................. 4-40
2.4 Internal ROM and EPROM ........ 4-11
2.5 System Bus ...................... 4-12 8.0 HIGH SPEED INPUTS., ............. 4-41
8.1 HSI Modes ....................... 4-42
3.0 SOFTWARE OVERViEW ............ 4-12
8.2 HSI Status ........................ 4-42
3.1 Operand Types ................... 4-12
8.3 HSI Interrupts ..................... 4-43
3.2 Operand Addressing .............. 4-13
8.4 HSllnput Sampling ............... 4-43
3.3 Program Status Word ............. 4-15
8.5 Initializing the HSI ................. 4-43
3.4 Instruction Set .................... 4-17
3.5 80C196KB Instruction Set 9.0 HIGH SPEED OUTPUTS ............ 4-43
Additions and Differences .......... 4-25 9.1 HSO Interrupts and Software
3.6 Software Standards and Timers ............................. 4-44
Conventions ....................... 4~25 9.2 HSO CAM ........................ 4-45
3.7 Software Protection Hints ......... 4-26 9.3 HSO Status ....................... 4-46
4.0 PERIPHERAL OVERVIEW .......... 4-26 9.4 Clearing the HSO and Locked
Entries ............................. 4-46
4.1 Pulse Width Modulation Output
(D/A) .............................. 4-27 9.5 HSO Precautions ....... " ........ 4-47
4.2 Timers ........................... 4-27 9.6 PWM USing the HSO, ............. 4-47
4.3 High Speed Inputs (HSI) .......... 4-27 9.7 HSO Output Timing ............... 4-48
4.4 High Speed Outputs (HSO) ....... 4-27 10.0 SERIAL PORT ..................... 4-48
4.5 Serial Port ........................ 4-27 10.1 Serial Port Status and Control ... 4-50
4.6 AID Converter .................... 4-29 10.2 Serial Port Interrupts ............. 4-52
4.7110 Ports ......................... 4-29 10.3 Serial Port Modes ............... 4-52
4.8 Watchdog Timer .................. 4-29 10.4 Multiprocessor
Communications ................... 4-54
5.0 INTERRUPTS ....................... 4-30
5.1 Interrupt Control .................. 4-32 11.0 AID CONVERTER ................. 4-54

5.2 Interrupt Priorities ................. 4-32 , 11.1 AID Conversion Process ........ 4-56

5.3 Critical Regions ................... 4-34 11.2 AID Interface Suggestions ...... 4-56

5.4 Interrupt Timing ................... 4-34 11.3 The AID Transfer Function ...... 4-57

5.5 Interrupt Summary ....... , ........ 4-35 11.4 AID Glossary of Terms .......... 4-61

4-2
 80C196KB USER'S GUIDE
CONTENTS PAGE CONTENT~ PAGE
12.0110 PORTS ........................ 4-63 15.0 EXTERNAL MEMORY
12.,1 Input Ports ...... : ................4-63 INTERFACING ....................... 4-74
12.2 Quasi-Bidirectional Ports ........ 4-63 15.1 Bus Operation ................... 4-74 ,
12.3 Output Por~s ............' ......... 4-65 15.2 Chip Configuration Register ...... 4-75
12.4 Ports 3 and 4/ ADG-15 .......... 4-66 " 15.3 Bus Width ................... , .. , 4-78
15.4 HOLD/HLDA Protocol ....... ,., .4-79
13.0 MINIMUM HARDWARE 15.5 AC Timing Explanations ..... ·.... 4-81
CONSiDERATIONS ...... , ............ 4-67
15.6 Memory System Examples ...... 4-86
13.1 Power Supply ................... 4-67
15.7 I/O Port Reconstruction ......... 4-88
13.2 Noise Protection Tips ............ 4-67
13.3 Oscillator and Internal Timings ... 4-67 16.0 USING THE EPROM ... , ........... 4-88
13.4 Reset and Reset Status ......... 4-68 16.1 Power-Up and Power-Down ..... 4-88
13.5 Minimum Hardware 16.2 Reserved Locations ............. 4-89
Connections ....................... 4-71 16.3 Programming Pulse Width
Register (PPW) ..........' ...... , ... 4-90
14.0 SPECIAL MODES OF
OPERATION ..... , ................... 4-72 16.4 Auto Configuration Byte
Programming Mode ................ 4-91
14.1 Idle Mode ....................... 4-72
16.5 Auto Progr.amming Mode ........ 4-91
14.2 Powerdown Mode .... ~ .......... 4-72
16.6 Slave Programming Mode ....... 4-93
14.3 ONCE and Test Modes .......... 4-73
16.7 Run-Time Programming ......... 4-95
16.8 ROM/EPROM Memory Protection
Options ............................ 4-96
16.9 Algorithms ..................... , 4-97

4-3
 80C196KB USER'S GUIDE

The 80C196KB family is a CHMOS branch of the , There ,are many members of the 80C196KB family, so
MCS@-96 family. Other members of the MCS~96 fami- , to provide easier reading this manual will refer to the
ly. incljlde the 8096BH and 8098. All of.. the MCS-96 80C196KB family generically as the 8OC196KB.
components share a common instruction set and ~rchi­ Where information applies only to specific components
tecture. However the CHMOS components have en- it will be clearly indicated.
hancements to provide higher performance at lower
power consumptions. To further decrease power usage, The 80CI96KB can be separated into four sections for
these parts can be placed into idle and powerdown the, purpose of des~ribing its oper~tion. A block dia-
I!loi;les. gram is shown in Figure I-I. There is the CPU and
architecture, the instruction set, the peripherals and the
MCS-96 family members are all high-performance mi- bus unit. Each of the sections will be sub-divided as the
crocontrollers with a 16-bit CPU and at least 230 bytes discussion progresses. Let us first examine the CPU.
of on-chip RAM. They are register-to-register ma-
chines, so no accumulator is needed, and most opera-
tions can be quickly performed from or to any of the 1.0 CPU OPERATION
registers. In addition, the register operations can con-
trol the many peripherals which are available on the' The major components of the CPU on the 80C196KB
chips. These peripherals include a serial port, A/D con- are the Register File and the Register/Arithmetic Log-
verter, PWM output, up to 48 I/O lines and a High- ic Unit (RALU). Communication with the outside
Speed I/O subsystem which has 2 16·bit timer/coun- world is done through either the Special Function Reg-
ters, an 8-level input capture FIFO and an 8-entry pro- isters (SFRs) or the Memory Controller. The RALU
grammable output generator. does not use an accumulator. Instead, it operates di-
rectly on the 256-byte register space made up of the
Typical applications for MCS-96 products are closed- Register File and the SFRs. Efficient 110 operations
loop control and mid-range digital signal processing. are possible by directly controlling the I/O through the
Mc;S-96 products are being ,used in moderns, motor SFRs. The main benefits of this structure are the ability
controls, printers, engine controls, photocopiers, anti- to quickly change context, absence of accumulator bot-
lock brakes, air conditioner temperature controls, disk tleneck, and fast throughput and I/O times.
drives, and medical instrumentation.

v EF ANGND

.--------------------.
....._-_
r-~--~~ :CrPU______•
,
... ,:,
,,,
, CONTROL
SIGNALS

PORT 3

l ~f~:
BUS
'--- ....
/
PORT 4
1+---1--

AID ALTERNATE
FUNCTIONS HSO
270651-1

Figure 1-1. 80C196KB Block Diagram

4-4
 80C196KB USER'S GUIDE

The CPU on the 80C196KB is 16 bits wide and con- REGISTERI ALU (RALU)
nects to the interrupt controller and the memory con-
troller by a 16-bit bus. In addition, there is an 8-bit bus Most calculations performed by the 80C196KB take
which transfers instruction bytes from the memory con- place in the RALU. The RALU, shown in Figure 1-2,
.troller to the CPU. An extension of the 16-bit bus con- contains a 17-bit ALU, the Program Status Word
nects the CPU to the peripheral devices. (PSW), the Program Counter (PC), a loop counter, and
three temporary registers. All of the registers are 16-
bits or 17-bits (16+ sign extension) wide. Some of the
1.1 Memory Controller registers have the ability to perform simple operations
to off-load the ALU. .
The RALU talks to the memory, except for the loca-
tions in the register file and SFR space, throug1). the A separate incrementor is used for the Program Coun-
memory controller. Within the memory controller is a ter (PC) as it accesses operands. However, PC changes
bus controller, a four byte queue and a Slave Program due to jump,s, calls, returns and inrerrupts must be han-
Counter (Slave PC). Both the internal ROMIEPROM dled through the ALU. Two of the temporary registers
bus and the external·memory bus are driven by the bus have their own shift logic. These registers are used for
controller. Memory access requests to the bus control- the operations which require logical shifts, including
ler can come from either the RALU or the· queue, with Normalize, Multiply, and Divide. The "Lower Word"
queue accesses having priority. Requests from the and "Upper Word" are used together for the 32-bit
queue are always for instruction at the address in the instructions and as temporary registers for many in-
slave PC. structions. Repetitive shifts are counted by the 6-bit
"Loop Counter".
By having program fetches from memory referenced to
the slave PC, the processor saves time as addresses sel- A third temporary register stores the second operand of
dom have to be sent to the memory controller. If the two operand instructions. This includes the multiplier
address sequence changes because of a jump, interrupt, during multiplications and the divisor during divisions.
call or return, the slave PC is loaded with a new value, To perform subtractions, the outp~t of this register can
the queue· is flushed, and· processing continues. be complemented before being placed into the "B" in-
put of the ALU.
Execution speed is increased by using a queue since it
usually keeps the next instruction byte available. The Several constants, such as 0, 1 and 2 are stored in the
instruction execution times shown in Section 3 show RALU to speed. up certain calculations. (e.g. making a
the normal execution times with no wait states added 2's complement number or performing an increment or
and the 16-bit bus selected. Reloading the slave PC and decrement instruction.) In addition, single bit masks for
fetching the first byte of the new instruction stream bit test instructions ate generated in the constant regis-
takes 4 state times. This is reflected in the jump taken! ter based on the 3-bit Bit Select register.
not-taken times shown in the table.

When debugging code using a logic analyzer, one must 1.3 Internal Timing
be aware of the queue. It is not possible to determine
when an instruction will begin executing by simply The 80C196KB requires an input clock on XTALI to
watching when it is fetched, since the queue is filled in function. Since XTALI and XTAL2 are the input and
advance of instruction execution. output of an inverter a crystal can be used to generate
the clock. Details of the circuit and suggestions for its
use can be found in Section 13:
1.2 CPU Control
Internal operation of the 80C196KB is based on the
A microcode engine controls the CPU, allowing it to crystal or external oscillator frequency divided by 2.
perform operations with any byte, word or double word Every 2 oscillator periods is referred to as one "state
in the 256 byte register space. Instructions to the CPU time", the basic time measurement for all 80C196KB
are taken from the queue and stored temporarily in the operations. With a 12 MHz oscillator, a state time is
instruction register. The microcode engine decodes the 167 nanoseconds. With an 8 MHz oscillator, a state
instructions .and generates the correct sequence of time is 250 nanoseconds, the same as an 8096BH run-
events to have the RALU p~rform the desired function. ning with a 12 MHz oscillator. Since the 80C196KB
Figure 1-2 shows the memory controller, RALU, in- will be run at many frequencies, the times given
struction register and the control unit. throughout this chapter will be in state times or
"states", unless otherwise specified. A clock out

4-5
 l
Memory
"TI
Bus
C

;1
!"
H
Upper word
register
w/shifter

~I
Lower word

DI
:::I
H register
w/shifter
CD
o
...o
Do i;:IIi;
IH
Register Processor
i: Status
CD File OJ
3 Word
.j>. c:
m -<0 and U)
rn
0 Special ::D
0
:::J
Function cii
::::
0
Registers
c;)

.
~ M
CPU
i' E
~ Control
and Status
o
rn
CD
6" ALU Signals
n
~
C

..
iii"
CD
DI
3
16
CPU BUSES
8
270651-2
inter 80C196KB USER'S GUIDE

(CLKOUT) signal, shown in Figure 1-3, is provided as 2.1 Register File

an indication of the internal machine state. Details on
timing relationships can be found in Section 13. Locations OOH through OFFH contain the Register File
and Special Function Registers, (SFRs). The RALU
can operate on any of these 256 internal register loca-
tions, but code can not be executed from them. If an
PHASE1~ attempt to execute instructions from locations OOOH
,
through OFFH is made, the instructions will be fetched
from external memory. This section of external memo-
PHASE2~ ry is reserved for use by Intel development tools
,
, The internal RAM from location OlSH (24 decimal) to
CLKOUT~ OFFH is the Register File. It contains 232 bytes of
270651-3, RAM which can be accessed as bytes (8 bits), words
(16 bits), or double-words (32 bits). Since each of these
Figure 1·3. Internal Clock Waveforms locations can be used by the RALU, there are essential-
ly 232 "accumulators". This memory region, as well as
the status of the majority of the chip, is kept intact
2.0 MEMORY SPACE while the chip is in the Powerdown Mode. Details on
Powerdown Mode are discussed in Section 14.
The addressable memory space on the 80C196KB con-
sists of 64K bytes, most of which is available to the user Locations 18H and 19H contain the stack pointer.
for program or data memory. Locations which have These are not SFRs and may be used as standard RAM
special purposes are OOOOH through OOFFH and if stack operations are not being performed. Since the
1FFEH through 2080H. All other locations can be stack pointer is in this area, the RALU can easily oper-
used for either program or data storage or for memory ate on it. The stack pointer must be initialized by the
mapped peripherals. A memory map is shown in Figure user program and can point anywhere in the 64K mem-
2-1. ory space. Operations to the stack cause it to build
down, so the stack pointer should be initialized to 2
bytes' above the highest stack location, and must be
OFFFFH word aligned.
EXTERNAL MEMORY OR I/O
4000H
INTERNAL ROM/EPROM OR
EXTERNAL MEMORY' 2.2 Special Function Registers
2080H
RESERVED Locations OOH through 17H are the 1/0 control regis-
2040H ters or SFRs. All of the peripheral devices on the
UPPER 8 INTERRUPT VECTORS 80C196KB (except Ports 3 and 4) are controlled
(NEW ON 80C196KB)
through these registers. As shown in Figure 2-2, three
2030H
SFR windows are provided on the 80C196KB.
ROM/EPROM SECURITY KEY
2020H
RESERVED
Switching between the -windows is done using the Win-
2019H dow Select Register (WSR) at location 14H in all of the
CHIP CONFIGURATION BYTE windows. The PUSHA and POPA instructions push
2018H and pop the WSR so it is easy to change between win-
RESERVED dows. Only three values may be written to the WSR, 0,
2014H 14 and 15. Other values are reserved for use in future
a
LOWER INTERRUPT VECTORS parts, and will cause unpredictable operation.
PLUS 2 SPECIAL INTERRUPTS
2000H
Window 0, the register window selected with WSR = 0,
PORT 3 AND PORT 4
1FFEH
is a superset of the one used on the 8096BH. As depict·
EXTERNAL MEMORY OR I/O
ed in Figure 2-3, it has 24 registers, some of which have
0100H different functions when read than when written. Reg-
INTERNAL DATA MEMORY· REGISTER FILE isters which are new to the 80Cl96KB or have changed
(STACK POINTER. RAM AND SFRS) functions from the 8096 are indicated in the figure.
EXTERNAL PROGRAM CODE MEMORY
OOOOH

Figure 2·1. 80C196KB Memory Map

4-7
 80C196KB USER'S GUIDE

Listed registers
are present in
all three windows

16H 16H 16H

WSR WSR WSR
14H 14H 14H
INT MASKlIPENDl INT MASK1/PENDl INT MASK1/PENDl
12H 12H 12H
10H 10H 10H
OEH OEH OEH
TIMER2 T2CAPTURE T2CAPTURE
OCH OCH OCH
OAH OAH OAH
INT MASK/PEND INT MASK/PEND INT MASK/PEND
08H 08H 08H
06H 06H 06H
04H 04H 04H
02H 02H 02H
ZERO REG ZERO REG ZERO REG
OOH OOH OOH
READ/WRITE PROGRAMMING WRITE/READ
,WSR ~ 0 WSR ~ 14 WSR ~ 15

Figure 2-2. Multiple Register Windows

19H 19H
STACK POINTER STACK POINTER
18H 18H
17H 'IOS2 17H PWM_CONTROL
16H 10Sl 16H 10Cl
15H 10SO 15H lOCO
14H 'WSR 14H 'WSR
13H 'INT MASK 1 13H 'INT MASK 1
12H 'INT PEND 1 12H 'INT PEND 1
llH 'SP_STAT llH 'SP_CON
10H PORT2 10H PORT2 10H RESERVED"
OFH PORTl OFH PORn OFH RESERVED"
OEH PORTO OEH BAUD RATE OEH RESERVED"
ODH TIMER2 (HI) ODH TIMER2(HI) ODH 'T2 CAPTURE (HI)
OCH TIMER2 (LO) OCH TIMER2 (LO) OCH 'T2 CAPTURE (LO)
OBH TIMERl (HI) OBH 'IOC2
WSR ~ 15
OAH TIMERl (LO) OAH WATCHDOG
09H INT_PEND 09H INT_PEND OTHER SFRS IN WSR 15 BECOME
08H INT MASK OSH INT MASK READABLE IF THEY WERE WRITABLE
IN WSR ~ 0, AND WRITABLE IF THEY
07H SBUF(RX) 07H SBUF(TX) WERE READABLE IN WSR ~ 0
06H HSI STATUS 06H HSO COMMAND
05H HSI TIME (HI) 05H HSO TIME (HI)
04H HSI_TIME (LO) 04H HSO TIME (LO) 04H PPW
03H AD_RESULT (HI) 03H HSI_MODE WSR ~ 14
02H AD_RESULT (LO) 02H AD_COMMAND
01H ZERO REG (HI) 01H ZERO REG (HI) 'NEW OR CHANG~D REGISTER
OOH ZERO REG (LO) ,OOH ZERO REG (LO) FUNCTION FROM S096BH
"RESERVED REGISTERS SHOULD NOT
WHEN READ WHEN WRITTEN
WSR ~ 0 BE WRITTEN OR READ

Figure 2-3. Special Function Registers

4-8
inter 80C196KB USER'S GUIDE

Register Description
RO Zero Register - Always ~eads as a zero, useful for a base when indexing and as a
constant for calculations and compares.
AD_RESULT AID Result Hi/low - low and high order results of the AID converter
AD_COMMAND AID Command Register - Controls the AID
HSI_MODE HSI Mode Register - Sets the mode of the High Speed Input unit.
HSI TIME HSI Time Hillo - Contains the time at which the High Speed Input unit was triggered.
HSO_TIME HSO Time Hi/lo - Sets the time or count for the High Speed Output to execute the
command in the Command Register.
HSO_COMMAND HSO Command Register - Determines what will happen at the. time loaded into the
HSO Time registers. '
HSI_STATUS HSI Status Registers - Indicates which HSI pins were detected at the time in the HSI
Time registers and the current state of the pins. In Window 15 - Writes to pin
detected bits, but not current state bits.
SBUF(TX) Transmit buffer for the serial port, holds contents to be outputted. last written value
is readable in Window 15.
SBUF(RX) Receive buffer for the serial port, holds the byte just received by the serial port.
Writable in Window 15.
INT_MASK Interrupt Mask Register - Enables or disables the individual interrupts.
INT_PEND Interrupt Pending Register - Indicates that an interrupt signal has occurred on one of
the sources and has not been serviced. (also INT_PENDING)
WATCHDOG Watchdog Ti,mer Register - Written periodically to hold off automatic reset every 64K
state times. Returns upper byte of WDT counter in Window 15.
TIMER1 Timer 1 Hi/lo - Timer1 high arid low bytes.
TIMER2 Timer 2 Hillo - Timer2 high and low bytes.
10PORTO Port 0 Register - levels on pins of Port O. Reserved in Window 15.
BAUD_RATE Register which determines the baud rate, this register is loaded sequentially.
Reserved in Window 15.
IOPORT1 Port 1 Register - Used to read or write to Port 1. Reserved in Window 15
IOPORT2 Port 2 Register - Used to read or write to Port 2. Reserved in Window 15
SP_STAT Serial Port Status - Indicates the status of the serial port.
SP_CON Serial Port Control - Used to set the mode of the serial port.
10SO 1/0 Status Register 0 - Contains information on the HSO status. Writes to HSO pins
in Window ,15.
IOS1 1/0 Status Register 1 - Contains information on the status of the timers and of the'
HSI.
lOCO I/O Control Register 0 - Controls alternate functions of HSI pins, Timer 2 reset
sources and Timer 2 clock sources.
IOC1 1/0 Control Register 1 - Controls alternate functions of Port 2 pins, timer interrupts
and HSI interrupts.
PWM CONTROL Pulse Width Modulation Control Register - Sets the duration of the PWM pulse.
INT_PEND1 Interrupt Pending register for the 8 new interrupt vectors (also INT_PENDING1)
INT MASK1 Interrupt Mask register for the 8 new interrupt vectors
IOC2 1/0 Control Register 2 - Controls new 80C196KB features
IOS2 I/O Status Register 2 - Contains information on HSO events
WSR Window Select Register - Selects register window
Figure 2-4. Special Function Register Description

4-9
inter 80C196KB USER'S GUIDE

Programming control and test operations are done in in Window IS. (Timer2 was read-only on the 8096.)
Window 14. Registers in this window that are not la- Registers which can be read and written in Window 0
beled should be considered reserved and should not be can also be read and written in Window IS.
either read or written.
Figure 2-4 contains brief descriptions of the SFR regis-
In register Window IS (WSR= IS), the operation of ters. Detailed descriptions are contained in the section
the SFRs is changed, so that those which were read- which discusses the peripheral controlled by the regis-
only in Window 0 space are write-only and vice versa. ter. Figure 2-5 contain.s a description of the alternate
The only major exception to this is that Timer2 is read/ function in Window IS.
write in Window 0, and T2 Capture is read/write

AD_COMMAND (02H) , - Read the last written command

AD_RESULT (02H, 03H) - Write a value into the result register
HSI_MODE (03H) ~ Read the value in HSI_MODE
HSI_TIME (04H, OSH) - Write to FIFO Holding register
HSO_TIME (04H, 05H) - Read the last value placed in the holding register
HSI_STATUS (06H) - Write to status bits but not to HSI pin bits. (Pin bits are I, 3, 5, 7)
HSO_COMMAND (06H) - Read the last value placed in the holding register
SBUF(RX) (07H) - Write a value into the recc:;ive buffer
SBUF(TX) (07H) - Read the last value written to the transmit buffer
WATCHDOG (OAH) - Read the value in the upper byte of the WDT
TIMER I (OAH, OBH) - Write a value to Timerl
TIMER2 (OCH, ODH) - ReadIWrite the Timer2 capture register.
(Timer2 read/write is done with WSR = 0)
IOC2 (OBH) - Last written value is readable, except bit 7 (Note I)
BAUD_RATE (OEH) - No function, cannot be read
PORTO (OEH) - No function, no output drivers on the pins
SP_STAT(llH) - Set the status bits, TI and RI can be set, but it will not cause an interrupt
SP_CON (IIH) - Read the current control byte
IOS0 (ISH) - Writing to this register controls the HSO pins. Bits 6 and 7 are inactive for
writes.
lOCO (ISH) - Last writtc:n value is readable, except bit I (Note I)
IOS1 (l6H) - Writing to this register will set the status bits, but not cause interrupts. Bits
6 and 7 are not functional.
lOCI (16H) - Last written value is readable
IOS2 (17H) - Writing to this register will set the status bits, but not cause interrupts.
'PWM_CONTROL (17H) - Read the duty cycle value writtc:n to PWM_CONTROL
NOTE:
1. IOC2.7 (CAM CLEAR) and IOCO.1 (T2RST) are not latched and will read as a 1 (precharged bus).
Being able to write to the read-only registers and vice-versa provides a lot of flexibility. One of the most useful
advantages is the ability to set the timers and HSO lines for initial conditions other than zero.

Figure 2-5. Alternate SFR .Function In Window 15

4-10
 80C196KBUSER'S GUIDE

Within the SFR space are several registers and bit loca- change the contents of this location. Refer to Section
tions labeled "RESERVED". These locations should 15.2 for more information about bus contention during
never be written or read. A reserved bit location should CCB fetch.
always be written with 0 to maintain compatibility with
future parts. Values read from these locations may
change from part to part or over temperature and volt- FFFFH
EXTERNAL MEMORY
age. Registers and bits which are not labeled should be ORIIO
treated as reserved registers and bits. Note that the de- 4000H
fault state of internal registers is 0, while that for exter- INTERNAL PROGRAM
nal memory is 1. This is because SFR functions are STORAGE ROMIEPROM
typically disabled with a zero, while external memory is OR
EXTERNAL MEMORY 20BOH
typically erased to all Is.
RESERVED 2074H-207FH
VOLTAGE LEVELS 2072H-2073H
Caution must be taken when using the SFRs as sources
of operations or as base or index registers for indirect or SIGNATURE WORD 2070H-2071H

indexed operations. It is possible to get undesired re- RESERVED 2040H-206FH

sults, since external events can change SFRs and some INTERRUPT VECTORS 2030H-203FH

SFRs clear when read. The potential for an SFR to SECURITY KEY 2020H-202FH
~hange value must be taken into account when operat- RESERVED 2019H-201 FH
mg on these registers. This is particularly important CHIP CONFIGURATION BYTE 201BH
when high level languages are used as they may not RESERVED 2015H-2017H
always make allowances for SFR-type registers. SFRs PPW 2014H
can be operated on as bytes or words unless otherwise INTERRUPT VECTORS 2000H-2013H
specified.
Figure 2·6. Reserved Memory Spaces
2.3 Reserved Memory Spaces Resetting the 80CI96KB causes instructions to be
Locations IFFEH and IFFFH are used for Ports 3 and fetched starting from location 2080H. This location was
4 respectively, allowing easy reconstruction of these chosen to allow a system to have up to 8K of RAM
ports if external memory is used. Ari example of recon- continuous with the register file. Further information
structing the I/O ports is given in Section 15. If ports 3 on reset can be found in Section 13.
and 4 are not going to be reconstructed and internal
ROM/EPROM is not used, these locations can be
treated as any other external memory location. 2.4 Internal ROM and EPROM
When a ROM part is ordered, or an EPROM part is
Many reserved and special locations are in the memory
programmed, the internal memory locations 2080H
area between 2000H and 2080H. In this area the 18
through 3FFFH are user specified, as are the interrupt
interrupt vectors, chip configuration byte, and security
vectors, Chip Configuration Register and Security Key
key are located. Figure 2-6 shows the locations and
in locations 2000H through 207FH. Location 2014H
functions of these registers. The interrupts, chip config-
contains the PPW (Programming Pulse Width) regis-
uration, and security key registers are discussed in Sec-
ter. The PPW is used solely to program 87CI96KB
tions 5: 16, and 17 respectively. With one exception, all
EPROM devices and is a reserved location on ROM
unspecified addresses in locations 2000H through
and ROMless devices.
207FH, including those marked "Reserved" are re-
served by Intel for use in testing or future products.
Instruction and data fetches from the internal ROM or
They must be filled with the Hex value FFH to insure
EPROM occur only if the part has ROM or EPROM
compatibility with future devices. Location 2019H
EA is tied high, and the address is between 2000H and
should contain 20H to prevent possible bus contention
3FFFH. At all other times data is accessed from either
during the CCB fetch cycle. NOTE: 1. This exception
the internal RAM space or external memory and in-
applies only to systems with a 16-bit bus and external
structions are fetched from external memory. The EA
program memory. 2. Previously designed systems
pin is latched on RESET rising. Information on pro-
which do not experience bus contention don't need to
gramming EPROMs can be found in Section 16.

4-11
 80C196KB USER'S GUIDE

The 80CI96KB provides a ROM/EPROM lopk feature These are the same as the names for the general. data
to allow the program to be locked against reading registers used in the 8086. It is important to note that in.
and/or writing the internal program memory. In order the 80C 196KB these are not dedicated registers but
to maintain security, code can not be executed out of merely the symbolic names assigned by the program-
the last three locations of internal ROM/EPROM if mer to an eight byte region within the on-board register
the lock is enabled. Details on this feature are in Sec- file.
tion 17.

3.1 Operand Types

2.5 System Bus
The MCS-96 architecture supports a variety of data
There are several modes of system bus operation on the types likely to be uS,eful in a control application. To
80C196KB. The standard bus mode uses a 16-bit multi- avoid confusion, the name of an operand type is capital-
plexed address/data bus. Other bus modes include an ized. A "BYTE" is an unsigned eight bit variable; a
8-bit mode and a mode in which the bus size can dy-. "byte" is an eight bit unit of data of any type.
namically be switched between 8-bits and 16-bits.

Hold/Hold Acknowledge (HOLD/HLDA) and Ready BYTES

signals are available to create a variety of memory sys- BYTES are unsigned 8-bit variables which can take on
tems. The READY line extends the width of the RD the values between 0 and 255. Arithmetic and relational
(read) and WR (write) pulses to allow access of slow operators can be applied to BYTE operands but the
memories. Multiple processor systems with shared result must· be interpreted in modulo 256 arithmetic.
memory can be designed using HOLD/HLDA to keep Logical operations on BYTES are applied bitwise. Bits
the 80CI96KB off the bus. Details on the System Bus within BYTES are labeled from 0 to 7, with 0 being the
are in Section 15. least significant bit.

3.0 SOFTWARE OVERVIEW WORDS

This section provides information on writing programs ,WORDS are unsigned 16-bit variables which can take
to execute in the 80C196KB. Additional information on the values between 0 and 65535 .. Arithmetic al).d
can be found in the following documents: relational operators can be applied to WORD operands
but the result must be interpreted modulo 65536. Logi-
MCS®-96 MACRO ASSEMBLER USER'S GUIDE cal operations on WORDS are applied bitwise.. Bits
Order Number 122048 (Intel Systems) within wor,ds are labeled from 0 to 15 with 0 being the
Order Number 122351 (DOS Systems) least significant bit. WORDS must be aligned at even
byte boundaries in the MCS-96 address space. The least
MCS®-96 UTILITIES USER'S GUIDE significant byte of the WORD is in the even byte ad-
Order Number 122049 (Intel Systems) dress and the most significant byte is in the next higher
Order Number 122356 (DOS Systems) (odd) address. The address of a word is the address of
its least significant byte. Word operations to odd ad-
PL/M-96 USER'S GUIDE dresses are not guaranteed to operate in a consistent
Order Number 122134 (Intel Systems) manner.
Order Number 122361 (DOS Systems)

C-96 USER'S GUIDE SHORT-INTEGERS

Order Number 167632 (DOS Systems) SHORT-INTEGERS are 8-bit signed variables which
can' take on the, values' between -128 and + 127,
Throughout this chapter short sections of code are used Arithmetic operations which generate results outside of
to illustrate the operation of the device. For these sec- the range of a SHORT-INTEGER will set the overflow
tions it is assumed that the following set of temporary indicators in the program status word. The actual nu-
registers has· been declared: meric result returned will be the same as the equivalent
AX, 13X, CX, and DX are 16-bit registers. operation on BYTE variables.
AL is the low byte of AX, AH is the high byte.
BL is the low byte of BX
CL is the low byte of CX
DL is the low byte of DX

4-12
inter 8OC196KB USER'S GUIDE

INTEGERS LONG-INTEGERS can also be normalized. For these

operations a LONG-INTEGER variable must reside in
INTEGERS are 16-bit signed variables which can take the onboard register file of the 80Cl96KB and be
on the values. between -32,768 and +32,767. Arith- aligned at an address which is evenly divisible by 4. A
metic operations which generate results outside of the LONG-INTEGER is addressed by the address of its
range of an.INTEGERwill set the overflow indioators least significant byte.
in the program status word. The actual numeric result
returned will be the same as the equivalent operation on LONG-INTEGER operations which are not directly
WORD variables. INTEGERS conform to the same supported can be easily implemented with two INTE-
alignment and addressing rules as do WORDS. GER operations. For consistency with Intel provided
software, the user should adopt the conventions for ad- .
dressing LONG operands which are discussed in Sec-
BITS tion 3.6. .
BITS are single-bit operands which can take on the
Boolean'values of true and false. In addition to the nor-
mal support for bits as components of BYTE and 3.2 Operand Addressing
WORD operands, the 80Cl96KB provides for the di- Operands are accessed within the address space of the
rect testing of any bit in the intemal register file. The 8OC196KB with one of six basic addressing modes.
MCS-96 architecture requires that bits be addressed as Some of the details of how these addressing modes
components of BYTES or WORDS, it does not support work are hidden by the assembly language. If the pro-
the direct addressing of bits that can occur in the MCS- grammer is to take full advantage of the architecture, it
51 architecture. is important that these details be understood. This sec-
tion will describe the addressing modes as they are han-
dled by the hardware. At the end of this section the
addressing modes will be described as they are seen
DOUBLE-WORDS are unsigned 32-bit variables through the assembly language. The six basic address
which can take on the values between 0 and modes which will be described are termed register-di-
4,294,967,295. The MCS-96 architecture provides di- o rect, indirect, indirect with auto-increment, immediate,
rect support for this operand type for shifts, as the divi- short-indexed, and long-indexed. Several other useful
dend in a 32-by-16 divide and the product of a 16-by-16 addressing operations can be achieved by combining
multiply, and for double-word comparisons; For these these basic addressing modes with specific registers
operations a DOUBLE-WORD variable must reside in such as the ZERO register or the stack pointer.
the on-board register file of the 80C196KB and be
aligned at an address which is evenly divisible by 4. A
DOUBLE-WORD operand is addressed by the address REGISTER-DIRECT REFERENCES
of its least significant byte. DOUBLE-WORD opera- The register-direct mode is used to directly access a
tions .which are not directly supported can be easily register from the 256 byte on-board register file. The
implemented with two WORD operations. For consist- register is selected by an 8-bit field within the instruc-
ency with Intel provided software the user should adopt tion and the register address must conform to the oper-
the conventions for addressing DOUBLE-WORD op- and type's alignment rules. Depending on the instruc-
erands which are discussed in Section 3.5. tion, up to three registers .can take part in the calcula-
tion.
LONG-INTEGERS

LONG-INTEGERS are 32-bit signed variables which Examples

can take on the values between -2,147,483,648 and ADD AX,BX,CX
+ 2,147,483,647. The MCS-96 architecture provides di- AX:=BX+CX.
MUL AX,BX AX:=AX*BX
rect support for this data type for shifts, as the dividend
in a 32-by-16 divide and the product of a 16-by-16 mul-
INCB CL CL:=CL+l
tiply, and for double-word comparisons.
inter 80C196KBUSER'S'GUIDE

INDIRECT REFERENCES

The indirect mode is used to access an operand by plac- file. The register which contains the indirect address is
ing its address in a WORD variable in the register file. selected by an eightbiffield within the instruction. An
The calculated address must conform to the alignment instruction can contain only one indirect reference and
rules for the operand type. Note that the indirect ad- the remainil!g operands of the instruction (if any) must
dress can refer to an operand anywhere within the ad- be register-direct ,references.
dress space of the 80C196KB, including the register

Examples
LD AX, [AX] AX:=MEM_WORD(AX)
ADDB AL,BL, [CX] AL:=BL+MEM_BYTE(CX)
POP [AX] MEM_WORD(AX) :=MEM_WORD(SP) ; SP:=SP+2

INDIRECT WITH AUTO-INCREMENT REFERENCES

This addressing mode is the same as the indirect mode SHORT-INTEGERS the indirect address variable will
except that the WORD variable which contains the In- be incremented by one'. If the instruction operates on
direct address is incremented after it is used to address WORDS or INTEGERS the indirect address ,variable
the operand. If the instruction oper~tes, on BYTES or will be incremented by two.

Examples
LD AX, [BX]+ AX:=MEM_WORD(BX) ; BX:=BX+2
ADDB AL,BL,[CX]+ AL:=BL+MEM_BYTE(CX) ; CX:=CX+1.
PUSH [AX]+ SP:=SP-2 ;
MEM_WORD(SP) :=MEM~WORD(AX)
AX:=AX+2

IMMEDIATE REFERENCES

This addressing mode allows an operand to be taken INTEGER operands the field is 16 bits wide. An in-
directly from ,a field in the instruction. For operations struction can contain only one immediate 'reference and
on BYTE or SHORT-INTEGER operands this field is the remaining operand(s) must be register-direct refer-
eight bits wide. For operations on WORD or ences.

Examples
ADD AX,#340 AX:=AX+340
PUSH #1234H SP:=SP-2; MEM_WORD(SP) :=1234H
DIVB AX,#lO AL:=AX/10; AH:=AX MOD 10

SHORT-INDEXED REFERENCES

In this addressing mode an eight bit field in the instruc- Sil1.ce the eight bit field ~ign-extended,theeffective
is
tion selects a WORD variable in the register file which address can be up to 128 bytes before the address in the
contains an address. A second eight bit field in the in- WORD variable and up to 127 bytes after it. An in-
struction stream is sign-extended and summed with the struction can contain only one short-indexed reference
WORD variable to form the address of the operand and the remaining operand(s) must be register-direct
which will take part in the calculation. references.

Examples
LD AX,12[BX] AX:=MEM_WORD(BX+12)
MULB AX,BL,3[CX] AX:=BL*MEM_BYTE(CX+3)

4-14
 80C196KB USER'S GUIDE

LONG-INDEXED REFERENCES

This addressing mode is like the short-indexed mode struction can contain only one long-indexed reference
except that a 16-bit field is taken from the instruction and the remaining operand(s) must be register-direct
and added to the WORD variable to form the address references.
of the operand. No sign extension is necessary. An in-

Examples
AND AX,BX,TABLE[CX] AX:=BX AND MEM_WORD(TABLE+CX)
ST AX, TABLE [BX] MEM_WORD(TABLE+BX) :=AX
ADDB AL,BL,LOOKUP[CX] AL:=BL+MEM_BYTE(LOOKUP+CX)

ZERO REGISTER ADDRESSING

The first two bytes in the register file are fixed at zero variable in a long-indexed reference. This combination
by the 80CI96KB hardware. In addition to providing a of register selection and address mode allows any loca-
fixed source of the constant zero for calculations and tion in memory to be addressed directly.
comparisons, this register can be used as the WORD

Examples
ADD AX,1234[0] AX:=AX+MEM_WORD(1234)
POP 5678[0] MEM_WORD(5678) :=MEM_WORD(SP)
SP:=SP+2

STACK POINTER REGISTER ADDRESSING

The system stack pointer in the 80CI96KB is accessed accessed by using the stack pointer as the WORD vari-
as register 18H of the internal register file. In addition able in an indirect reference. In a similar fashion, the
to providing for convenient manipulation of the stack stack pointer can be used in the short-indexed mode to
pointer, this also facilitates the accessing of operands in access data wi thin the stack.
the stack. The top of the stack, for example, can be

Examples
PUSH [SP] DUPLICATE TOP_OF_STACK
LD AX,2!SP] AX:=NEXT_TO_TOP

ASSEMBLY LANGUAGE ADDRESSING MODES These features of the assembly language simplify the
programming task and should be used wherever possi-
The MCS-96 assembly language simplifies the choice of ble.
addressing modes to be used in several respects:
Direct Addressing. The assembly language will choose
between register-direct addressing and long-indexed 3.3 Program Status Word
with the ZERO register depending on where the oper-
and is in memory. The user can simply refer to an oper- The program status word (PSW) is a collection of Boo-
and by its symboliq name: if the operand is in the regis- lean flags which retain information concerning the state
ter file, a register-direct reference will be used, if the of the user's program. There are two bytes in the PSW;
operand is elsewhere in memory, a long-indexed refer- the actual status word and the low byte of the interrupt
ence will be generated. mask. Figure 3-1 shows the status bits of the PSW. The
P8W can be saved in the system stack with a single
Indexed Addressing. The assembly language will operation (PUSHF) .and restored in a like manner
choose between short and long indexing depending on (POPF). Only the interrupt section of the PSW can be
the value of the index expression. If the value can be accessed directly. There is no SFR for the PSW status
expressed in eight bits then short indexing will be used, bits.
if it cannot be expressed in eight bits then long indexing
will be used.
4-15
intJ 80C196KB USER'S GUIDE

CONDITION FLAGS VT: The oVerflow Trap (lag is set when the V flag is
set, but it is only cleared by the CLRVT, JVT and
The PSW bits on the 80CI96KB are set as follows: JNVT instructions. The operation of the VT flag
allows for the testing for a possible overflow con-
dition at the end of a sequence of related arithme-
tic operations. This is normally more efficient
than testing the V flag after each instruction.
Figure 3·1. PSW Register C: The Carry flag is set to indicate the state of the
arithmetic carry from the most significant bit of
Z: The Z (Zero) flag is set to indicate that the opera- the ALU for an arithmetic operation, or the state
tion generated a result equal to zero. For the add-
of the last bit shifted out of an operand for a shift.
with-carry (ADDC) and subtract-with-borrow
Arithmetic Borrow after a subtract operation is
(SUBC) operations the Z flag is cleared if the re-
the complement of the C flag (i.e. if the operation
sult is non-zero but is never set. These two in- generated a borrow then C=O.)
structions are normally used in conjunction with
the ADD and SUB instructions to perform multi- X: Reserved. Should always be cleared when writing
ple precision arithmetic. The operation of the Z to the PSW for compatibility with future prod-
flag for these instructions leaves it indicating the ucts.
proper result for the entire multiple precision cal- I: The global Interrupt disable bit disables all inter-
culation. rupts when cleared except NMI, TRAP, and un-
N: The Negative flag is set to indicate that the opera- implemented opcode.
tion generated a negative result. Note that the N ST: The ST (STicky bit) flag is set to indicate that
flag will be in the algebraically correct state even during a right .shift a 1 has been shifted first into
if an overflow occurs. For shift operations, includ- the C flag and then. been shifted out. The ST flag
ing the normalize operation and all three forms is undefined after a multiply operation. The ST
(SHL, SHR, SHRA) of byte, word and double flag can be used along with the C flag to control
word shifts, the N flag will be set to the same rounding after a right shift. Consider multiplying
value as the most significant bit of the result. This two eight bit quantities and then scaling the result
will be true even if the shift count is O. down to 12 bits:
V: The oVerflow flag is set to indicate that the opera-
tion generated a result which is outside the range MULUB AX,CL,DL ;AX:=CL*DL
for the destination data type. For the SHL, SHLB SHR AX,#4 ;Shift right 4
and SHLL instructions, the V flag will be set if the places
most significant bit of the operand changes at any
time during the shift. For divide operations, the If the C flag is set after the shift, it indicates that the
following conditions are used to determine if the V - bits shifted off the end of the operand were greater-than
flag is set: or equal-to one half the least significant bit (LSB) of the
result. If the C flag is clear after the shift, it indicates
For the that the bits shifted off the end of the operand were less
operation: V is set if Quotient is:
than half the LSB of the result. Without the ST flag,
UNSIGNED the rounding decision must be made on the basis of the
BYTE DIVIDE> 255 (OFFH) C flag alone. (Normally the result would be rounded up
if the C flag is set.) The ST flag allows a finer resolution
UNSIGNED in the rounding decision: .
WORD DIVIDE> 65535 (OFFFFH)

SIGNED < -l27(8lH) C ST Value of the Bits Shifted Off

BYTE or 0 0 Value = 0
DIVIDE > l27(7FH)
0 1 o < Value < % LSB
SIGNED < -32767 (800lH) 1 0 Value = %LSB
WORD or
DIVIDE > 32767 (7FFFH) 1 1 Value> %LSB
Figure 3·2. Rounding Alternatives

Imprecise rounding can be a major source of error in a

numerical calculation; use of the ST flag improves the
options available to the programmer.

4-16
inter 80C196KB USER'S GUIDE

INTERRUPT FLAGS WORDS can be converted to DOUBLE-WORDS by

simply clearing the upper WORD of the DOUBLE-
The, lower eight bits of the PSW individually mask the WORD (CLR) and INTEGERS can be converted to
lowest 8 sources of interrupt to the 80C196KB. These LONGS with the EXT (sign extend) instruction.
mask bits can be accessed as an eight bit byte (INT_
MASK-address 8) in the on-board register file. A sep- The MCS-96 instructions for addition, subtraction, and
arate register (INT_MASKI-address 13Hj contains comparison do not distinguish between unsigned words
the control bits for the higher 8 interrupts. A logical 'I' and signed integers. Conditional jumps are provided to
in these bit positions enables the servicing of the corre- allow the user to treat the results of these operations as
sponding interrupt. Bit 9 in the PSW is the global inter- either signed or unsigned quantities. As-an example, the
rupt disable. If this bit is cleared then interrupts will be CMPB (compare byte) instruction is used to compare
locked out. Note that the interrupts are collected in the both signed and unsigned eight bit quantities. A JH
INT_PEND -registers even if they are locked out. Exe- (jump if higher) could be used following th~ compare if
cution of the corresponding service routines will pro- unsigned operands were involved or a JGT (jump if
ceed according to their priority when they become en- greater-than) if signed operands were involved.
abled. Further information on the interrupt structure of
the 80C196KB can be found in Section 5. Tables 3-1 and 3-2 summarize the operation of each of
the instructions. Complete descriptions of each instruc-
tion and its timings can be found in the MCS-96 family
3.4 Instruction Set Instruction Set chapter.

The MCS-96 instruction set contains a full set of arith- The execution times for the instruction set are given in
metic and logical operations for the 8-bit data types Figure 3-3. These times are given for a 16-bit bus with
BYTE and SHORT INTEGER and for the 16-bit data no wait states. On-chip EPROM/ROM space is a 16-
types WORD and INTEGER. The DOUBLE-WORD bit, zero wait state bus. When executing from an 8-bit
and LONG data types (32 bits) are supported for the external memory system or adding wait states, the CPU
products of 16-by-16 multiplies and the dividends of becomes bus limited and must solt)etimes wait for the
32-by~ 16 divides, for shift operations, and for 32-bit prefetch queue. The performance penalty for an 8-bit
compares. The remaining operations on 32-bit variables external bus is difficult to measure, but has shown to be
can be implemented by combinations of 16-bit opera- between 10 and 30 percent based on the instruction
tions .. As an example the sequence: mix. The best way to measure code performance is to
actually benchmark the code and time it using an emu-
ADD AX,CX lator or with TIMER!.
ADDC BX,DX
The indirect and indexed instruction timings are given
performs a 32-bit addition, and the sequence for two memory spaces: SFR/Internal RAM space (0-
OFFH), and a memory controller reference (IOOH-
SUB AX,CX OFFFFH). Any instruction that uses an operand that is
SUBC BX,DX referenced through the memory controller (ex. Add
rl,5000H(01) takes 2-3 states longer than if the oper-
performs a 32-bit subtraction. Operations on REAL and was in the SFRIInternal RAM space. Any data
(i.e. floating point) variables are not supported directly access to on-chip ROM/EPROM is considered to be a
by the hardware but are supported by the floating point memory _controller reference.
library for the 80Cl96KB (FPAL-96) which imple-
ments a single precision subset of draft 10 of the IEEE Flag Settings. The modification to the flag setting is
standard for floating point arithmetic. The performance shown for each instruction. A checkmark (,....) means
of this software is significantly improved by the that the flag is set or cleared as appropriate. A hyphen
80CI96KB NORML instruction which normalizes a means that the flag is not modified. A one or zero (I) or
32-bit variable and by the existence of the ST flag in the (0) indicates'that the flag will be in that state after the
PSW. instruction. An up arrow (t) indicates that the in-
struction may set the flag if it is appropriate but will
In addition to the operations on the various data types, not clear the flag. A down arrow ( ,J, ) indicates that the
the 80CI96KB supports conversions between these flag can be cleared but not set by the instruction. A
types. LDBZE (load byte zero extended) converts a question mark (?) indicates that the flag will be left in
BYTE to a WORD and LDBSE (load byte sign extend- an indeterminant state after the operation.
ed) converts a SHORT-INTEGER into an INTEGER.

4-17
 80C196KB USER'S GUIDE

Table 3-1A.lnstruction Summary

Flags
Mnemonic Operands Operation (Note 1) Notes
Z N C V VT ST
ADD lAD DB 2 D - D+A ", ", ", ", i -
ADD/ADDB 3 D - B+A ", ", ", ", i -

AODC/AOOCB 2 O-O+A+C ! ", ", ", i -

SUB/SUBB 2 0 - O-A -", ", ", ", i -

SUB/SUBB 3 0 - B-A ", ", ", ", i -
SUBC/SUBCB 2 0-0-'-A+C-1 ! ", ",- ", i -
CMP/CMPB 2 O-A ", ", ", ",
i -
MUL/MULU 2 0,0 + 2 - 0 xA - - - - - - 2
MUL/MULU 3 0,0 + 2 - BxA - - - - - - 2
MULB/MULUB 2 0,0 + 1 - 0 xA - - - - - - 3
MULB/MULUB 3 0,0 + 1 - BxA - - - - - - 3
OIVU 2 o- (0,0 + 2) I A,O + 2 - , remainder - - - ", i - 2
OIVUB ,2 o- (0,0 + 1) IA,O + 1 - remainder - - - ", i - 3
OIV 2 o- (0,0 + 2) I A,O + 2 - remainder - - - ", i -
DIVB 2 o- (O,D + 1) IA,O + 1 - remainder - - - ", i -
ANO/ANOB 2 D - OANOA ", ", 0 0 - -

ANO/ANOB 3 o +- BANDA ", ", 0 0 - -

OR/ORB 2 0 - DORA ", ", 0 0 - -

XOR/XORB 2 o- D (ecx!. or) A ", ", 0 0 - -

LD/LOB 2 O-A - - - - - -
ST/STB 2 A-O - - - - - -
LOBSE 2 0-A;0+1 - SIGN(A) - - - - - - 3,4
LOBZE 2 0-A;0+1 - 0 - - - - - - 3,4
PUSH 1 SP - SP ....: 2; (SP) - A - - - - - -
POP 1 A - (SP); SP + 2 - - ,- - - -
PUSHF 0 SP - SP - 2; (SP) - PSW; 0, 0 0 0 0 0
PSW - OOOOH; I - 0
POPF 0 PSW - (SP); SP - SP + 2; I+-", ", ", ", ", ", ",

SJMP 1 PC +- PC + 11-bit offset - - - - - ' - 5

LJMP 1 PC - PC -+ 16·bit offset - - - - - - 5
BR [indirect]
SCALL
1
1
PC -
SP -
(A)
SP - 2;
-
-
-
-
-
-
-
-
-
-
-
- 5
(SP) - PC; PC - PC + 11-bit offset
LCALL 1 SP - SP - 2; (SP) - PC; - - - - - - 5
PC - PC + 16-bit offset

4-18
intJ 80C196KB USER'S GUIDE

Table 3-16. Instruction Summary

Flags
Mnemonic Operands Operation (Note 1) Notes
Z N C V VT ST
RET 0 PC - (SP); SP - SP +2 - - - - - -
J (conditional) 1 PC - PC + a-bit offset (if taken) - - - - - - 5
JC 1 Jump ifC = 1 - - - - - - 5
JNC 1 jump ifC = 0 - - - - - - 5
JE 1 jump if Z=1 - - - - - - 5
JNE 1 Jump if Z = 0 - - - - - - 5
JGE 1 Jump if N = 0 - - - - - - 5
JLT 1 Jump if N = 1 - - - - - - 5
JGT 1 Jump if N = 0 and Z = 0 - - - - - - 5
JLE 1 Jump if N = 1 or Z = 1 - - - - - - 5
JH 1 Jump if C = 1 and Z = 0 - - - - - - 5
JNH 1 Jump if C = 0 or Z = 1 - - - - - - 5
JV 1 Jump if V = 1 - - - - - - 5
JNV 1 Jump if V = 0 - - - - - - 5
JVT 1 Jump if VT = 1; Clear VT - - - - 0 - 5
JNVT 1 Jump if VT = 0; Clear VT - - - - 0 - 5
JST 1 Jump if ST = 1 - - - - - - 5
JNST 1 Jump ifST = 0 - - - - - - 5
JBS 3 Jump if Specified Bit = 1 - - - - - - 5,6
JBC 3 Jump if Specified Bit = 0 - - - - - - 5,6
DJNZI 1 P - D -1; - - - - - - 5
DJNZW If D * 0 then PC - PC + a-bit offset 10
DEC/DECB 1 D - D-1
,.. ,.. ,.. ,.. i -
NEGINEGB 1 D - O-D
,.. ,.. ,.. ,.. i -

INC/INCB 1 D - D + 1
,.. ,.. ,.. ,.. i -
EXT 1 D - D; D + 2 - Sign (D)
,.. ,.. 0 0 - - 2
EXTB 1 D - D; D + 1 - Sign (D)
,.. ,.. 0 0 - - 3
NOTINOTB 1 D - Logical Not (D) ,.. ,.. 0 0 - -
CLR/CLRB 1 D-O 1 0 0 0 - -
SHL/SHLB/SHLL 2 C - msb - - - - - Isb - 0
,.. ,.. ,.. ,.. i - 7
SHRISHRB/SHRL 2 o- msb - - - - - Isb - C
,.. ,.. ,.. 0 - ,.. 7
SHRA/SHRAB/SHRAL 2 msb - msb - - - - - Isb - C
,.. ,.. ,.. 0 - ,.. 7
SETC 0 C-1 - - 1 - - -
CLRC 0 C-O - - 0 - - -

4-19
 80C196KB USER'S GUIDE

Table 3-1C.lnstruc;:tion Summary

Mnemonic Operands Operation (Note 1), "Flags ,Notes

Z N C V VT ST
CLRVT 0 VT - 0
- - - - 0 -
RST 0 PC - 2080H 0 0 0 0 0 0 8
DI 0 Disable All Interupts (I - 0) - - - - - -
EI 0 Enable All Interupts (I - 1) - - - - - -

Nap 0 PC-PC+1 - - - ,- - -

SKIP 0 PC-PC+2 - - - - - -
NORML 2 Left shift till msb = 1; D - shift count ~ ~ 0 - - - 7
TRAP 0 SP- SP - 2; - - - - - - 9
, (SP) - PC; PC - (2010H)
PUSHA 1 SP - SP-2; (SP) - PSW; 0 0 0 0 0 0
PSW - OOOOH; SP - SP-2;
(SP) - IMASK1/WSR; IMASK1 - OOH
paPA 1 IMASK1/WSR - (SP); SP - SP+2 ~ ~ ~ ~ ~, ~

PSW - (SP); SP - SP+2

IDLPD 1 IDLE MODE IF KEY = 1; - - - - - -
POWER DOWN MODE IF KEY = 2;
CHIP RESET OTHERWISE
CMPL 2 D-A ~ ~ ~ ~ t -

BMOV 2 [PTR_HI] + - [PTR_LOW] + ; - - - - - -

UNTIL COUNT = 0

NOTES: '
1. If the mnemonic ends in "B" a byte operation is performed, otherwise a word operation is done. Operands D, B, and A
must conform to the alignment rules for the required operand type. D and B are locations in the Register File; A can be
located arlywhere in memory.
2. D,D + 2 are consecutive WORDS in memory; D is DOUBLE-WORD aligned.
3. D,D + 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to word.
5. Offset is a 2's complement number.
6. Specified bit is one of the 2048 bits in the register file.
7. The "L" (Long) suffix indicates double-word operation. .
8. Initiates a Reset by pulling RESET low. Software should re-initialize all the necessary registers with code starting at
2080H.
9. The assembler will not accept this mnemonic.
10. The DJNZW instruction is not guaranteed to work. See Functional Deviations section.

4-20
intJ 80C196KB USER'S GUIDE

Table 3-2A. Instruction Length (in Bytes)/Opcode

INDIRECT INDEXED
MNEMONIC DIRECT IMMED
NORMAL*(1) A-INC'(1) SHQRT*(1) LONG*(1)
ADD (3-ap) 4/44 5/45 4/46 4/46 5/47 6/47
SUB (3-ap) 4/48 5/49 4/4A 4/4A 5/4B 6/4B
ADD (2-ap) 3/64 4/65 3/66 3/66 4/67 5/67
SUB (2-ap) 3/68 4/69 3/6A 3/6A 4/6B 5/6B
ADDC 3/A4 4/A5 3/A6 3/A6 4/A7 5/A7
SUBC 3/A8 4/A9 3/AA 3/AA 4/AB 5/AB
CMP 3/88 4/89 3/AB 3/AB 4/8B 5/8B
ADDB (3-ap) 4/54 4/55 4/56 4/56 5/57 6/57
SUBB (3-ap) 4/58 4/59 4/5A 4/5A 5/5B 6/5B
ADDB (2-ap) 3174 3175 3176 3176 4/77 5/77
SUBB (2-ap) . 3178 3179 317A 3/7A 417B 517B
ADDCB 3/B4 3/B5 3/B6 3/B6 4/B7 5/B7
SUBCB 3/B8 3/B9 3/BA 3/BA 4/BB 5/BB
CMPB 3/98 3/99 3/9A 3/f)A 4/9B 5/9B
MUL (3-ap) 5/(2) 6/(2) 5/(2) 5/(2) 6/(2) 7/(2)
MULU (3-ap) 4/4C 5/4D 4/4E 4/4E 5/4F 6/4F
MUL (2-ap) 4/(2) 5/(2) 4/(2) 4/(2) 5/(2) 6/(2)
MULU (2-ap) 3/6C 4/6D 3/6E 3/6E 4/6F 5/6F
DIV 4/(2) 5/(2) 4/(2) 4/(2) 5/(2) 6/(2)
DIVU 3/8C 4/8D 3/8E 3/8E 4/8F 5/8F
MULB (3-ap) 5/(2) 5/(2) 5/(2) 5/(2) 6/(2) 7/(2)
MULUB (3-ap) 4/5C 4/5D 4/5E 4/5E 5/5F 6/5F
MULB (2-ap) 4/(2) 4/(2) 4/(2) 4/(2) 5/(2) 6/(2)
(
MULUB (2-ap) 3/7C 317D 317E 3/7E 4/7F 517F
DIVB 4/(2) 4/(2) 4/(2) 4/(2) 5/,(2) 6/(2)
DIVUB 3/9C 3/9D 3/9E 3/9E 4/9F ' 5/9F'
AND (3-ap) 4/40 5/41 4/42 4/42 5/43 6/43
AND (2-ap) 3/60 4/61 3/62 3/62 4/63 5/63
OR (2-ap) 3/80 4/81 3/82 3/82 4/83 5/83
XOR 3/84 4/85 3/86 3/86 4/87 5/87
. ANDB (3-ap) 4/50 4/51 4/52 4/52 5/53 5/53
ANDB (2-ap) 3/70 3/71 3172 3172 4173 4173
ORB (2-ap) 3/90 3/91 3/92 3/92 4/93 5/93
XORB 3/94 3/95 3/96 3/96 4/97 5/97
PUSH 2/C8 3/C9 2/CA 2/CA 3/CB 4/CB
POP 2/CC - 2/CE 2/CE 3/CF 4/CF

NOTES:
1. Indirect and indirect + share the same opcodes, as do short and long indexed opcodes. If the second byte is even, use
indirect or short indexed. If odd, use indirect or long indexed.
2. The opcodes for signed multiply and divide are the unsigned opcode with an "FE" prefix.

4-21
inter 80C196KB USER'S GUIDE

Table 3-28. Instruction Length (in Bytes)/Opcode

INDIRECT INDEXEr;>
MNEMONIC DIRECT IMMED
NORMAL A-INC SHORT LONG
LO 3/AO 4/A1 3/A2 3/A2 4/A3 5/A3
LOB 3/BO 3/B1 3/B2 3/B2 "
4/B3 5/B3
ST 3/CO - 3/C2 3/C2 4/C3 5/C3
STB 3/C4 - 3/C6 3/C6 4/C7 5/C7
LOBSE 3/BC 3/BO 3/BE ·3/BE 4/BF 5/BF
LBSZE 3/AC 3/AO 3/AE 3/AE 4/AF 5/AF

Mnemonic Length/Opcode Mnemonic Length/Opcode

PUSHF 1/F2 OJNZ 3/EO
POPF 1/F3 OJNZW 3/E1(4)
PUSHA 1/F4 NORML ' 3/0F
POPA 1/F5 SHRL 3/0C
SHLL 3/00
TRAP 1/F7 SHRAL 3/0E
LCALL 3/EF SHR 3/0S
SCALL 2/2S-2F(3) SHRB 3/1S
RET 1/FO SHL 3/09
LJMP 3/E7 SHLB 3/19
SJMP 2/20-27(3) SHRA 3/0A
BR[) 2/E3 SHRAB 3/1A

JNST 1/00 CLRC 1/FS

JST 1/0S SETC 1/F9
JNH 1/01 01 1/FA
JH 1/09 EI 1/FB
JGT 1/02 CLRVT 1/FC
JLE 1/0A NOP 1/FO
JNC 1/B3 RST 1/FF
JC 1/0S SKIP 2/00
JNVT 1/04 10LPO 1/F6
JVT 1/0C BMOV 3/c'1
JNV 1/05
JV 1/00
JGE 1/06
JLT 1/0E
JNE 1/07
JE 1/0F
JBC 3/30-37
JBS 3/3S-3F
NOTES:
3, The 3 least significant bits of the opcode are concatenated with the 8 bits to form an 11·bit, 2's complement offset.
4, The DJNZW instruction is not guaranteed to work. See Functional Deviations section.

4·22
 80C196KB USER'S GUIDE

Table 3.3A. Instruction Execution State Times (1)

INDIRECT INDEXED
MNEMONIC DIRECT IMMED
NORMAL' A-INC' SHORT' LONG'
ADD (3-op) 5 6 7/10 8/11 7/10 8/11
SUB (3-op) 5 6 7/10 8/11 7/10 8/11
ADD (2-op) 4 5 6/8 7/9 6/8 7/9
SUB (2-op) 4 5 6/8 7/9 6/8 7/9.
ADDC 4 5 6/8 7/9 6/8 7/9
SUBC 4 5 6/8 719 6/8 7/9
CMP 4 5 6/8 7/9 6/8 7/9
ADDB (3·op) 5 5 7/10 8/11 7/10 8/11
SUBB (3-op) 5 5 7/10 8/11 7/10 8/11
ADDB (2-op) 4 4 6/8 7/9 6/8 7/9
SUBB (2-op) 4 4 6/8 7/9 6/8 7/9
ADDCB 4 4 6/8 7/9 6/8 7/9
SUBCB 4 4 6/8 7/9 6/8 7/9
CMPB 4 4 6/8 7/9 6/8 7/9
MUL (3-op) 16 17 18/21 19/22 19/22 20/23
I
MULU (3-op) 14 1.5 16/19 17/19 17/20 18/21
MUL (2-op) 16 17 18/21 19/22 19/22 20/23
MULU (2-op) 14 15 16/19 17/19 17/20 18/21
DIV 26 27 28/31 29/32 29/32 30/33
DIVU 24 25 26/29 27/30 27/30 28/31
MULB (3-op) 12 12 14/17 13/15 15/18 16/19
MULUB (3·op) 10 10 12/15 12/16 12/16 14/17
MULB (2-op) 12 12 14/17 15/18 15/18 16/19
MULUB (2-op) 10 10 12/15 13/15 12/16 14/17
DIVB 18 18 20/23 21/24 21/24 22/25
DIVUB 16 16 18/21 19/22 19/22 20/23
AND (3-op) 5 6 7/10 8/11 7/10 8/11
AND (2-op) 4 5 6/8 7/9 6/8 7/9
OR (2·op) 4 5 6/8 7/9 6/8 7/9
XOR 4 5 6/8 7/9 6/8 7/9
AN DB (3-op) 5 5 7/10 8/11 7/10 8/1t
AN DB (2-op) 4 4 6/8 7/9 6/8 7/9
ORB (2-op) 4 4 6/8 7/9 6/8 7/9
XORB 4 4 6/8 7/9 6/8 719
LD, LOB 4,4 5,4 5/8 6/8 6/9 7/10
ST,STB 4,4 - 5/8 6/9 6/9 7/10
,
LDBSE 4 4 5/8 6/8 6/9 7/10
LDBZE 4 4 5/8 6/8 6/9 7/10
BMOV internal/internal: 6 + 8 per word
external/internal: 6 + 11 per word
external/external: 6+ 14 per word
PUSH (int stack) 6 7 9/12 10/13 10/13 11/14
POP (int stack) 8 - 10/12 11/13 11/13 12/14
PUSH (ext stack) 8 9 11/14 12/15 12/15 13/16
POP (ext stack) 11 - 13/15 14/16 14/16 15/17
"Times for operands as: SFRs and Internal RAM (0-1 FFH)/memory controller (200H-OFFFFH)

NOTE:
1. Execution times for memory controller references may be one to two states higher depending on the number of bytes in
the prefetch queue. Internal stack is 200H-1FFH and external stack is 200H-OFFFFH.
4-23
 80C196KB.USER'S GUIDE

Table 3.3B. Instruction Execution State Times

MNEMONIC MNEMONIC
PUSHF (int stack) 6 PUSHF (ext stack) 8·
POPF (int stack) 7 POPF (ext stack) 10
PUSHA (int stack) 12 PUSHA (ext stack) 18
POPA (int stack) 12 POPA (ext stack) 18
TRAP (int stack) 16 TRAP (ext stack) 18
LCALL (int stack) 11 LCALL (ext stack) 13
SCALL (int stack) 11 SCALL (ext stack) 13
RET (int stack) 11 RET (ext stack) 14
CMPL 7 OEC/OECB 3
CLR/CLRB 3 EXT/EXTB 4
NOT/NOTB 3 INC/INCB 3
NEG/NEGB 3
LJMP 7
SJMP 7
BR [indirect] 7
JNST,JST 4/8 jump not taken/jump taken
JNH,JH 4/8 jump not taken/jump taken
JGT,JLE 4/8 jump not taken/jump taken
JNC, JC 4/8 jump not taken/jump taken
JNVT, JVT 4/8 jump not taken/jump taken
JNV, JV 4/8 jump not taken/jump taken
JGE, JLT 4/8 jump not taken/jump taken
JNE, JE 4/8 jump not taken/jump taken
JBC,JBS 5/9 jump not taken/jump taken
OJNZ 5/9 jump not tak~n/jump taken
OJNZW (Note 1) 5/9 jump not taken/jump taken
. NORML 8 + 1 per shift (9 for 0 shift)
SHRL 7 + 1 per shift (8 for 0 shift)
SHLL 7 + 1 per shift (8 for 0 shift)
SHRAL 7 + 1 per shift (8 for 0 shift)
SHR/SHRB 6 + 1 per shift (7 for 0 shift)
SHL/SHLB 6 + 1 per shift (7 for 0 shift)
SHR,A./SHRAB 6 + 1 per shift (7 for 0 shift)
CLRC 2
SETC 2
01 2
EI 2
CLRVT 2
NOP 2
RST 15 (includes fetch of configuration byte)
SKIP 3
10LPO 8/25 (proper key/improper key)

NOTE:
1. The DJNZW instruction is not guaranteed to work. See Functional Deviations section.

4-24
inter 80C196KB USER'S GUIDE

3.5 80C196KB Instruction Set language and PLM-96 environment and it offers com-
patibility between these environments. Another advan-
Addl~ions and Differences
tage is that it allows the user access to the same floating
For users already familiar with the 8096BH, there are point arithmetics library that PLM-96 uses to operate
six instructions added to the standard MCS-96 instruc- on REAL variables.
tion set to form the 80C 196KB instruction set. All of
the former instructions perform the same function, ex- REGISTER UTILIZATION
cept as indicated in the next section. The new instruc-
tions and their descriptions are listed below: The MCS-96 architecture provides a 256 byte register
PUSHA - PUSHes the PSW, INT_MASK, file. Some of these registers are used to control register-
IMASK1, and WSR mapped I/O devices and for other special functions
POPA - POPs the PSW, INT_MASK, IMASK1, such as the ZERO register and the stack pointer. The
and WSR remaining bytes in the register file, some 230 of them,
are available for allocation by the programmer. If these
IDLPD - Sets the part into IDLE or Powerdown registers are to be used effectively, some overall strategy
mode for their aUocation must be adopted. PLM-96 adopts
CMPL , - Compare 2 long direct values the simple and effective strategy of allocating the eight
BMOV - Block move using 2 auto-incrementing bytes between addresses lCH and 23H as temporary
storage. The starting address of this region is caUed
pointers and a counter
PLMREG. The remaining area in the register file is
DJNZW - Decrement Jump Not Zero using a Word treated as a segment of memory which is allocated as
counter (Not functional on current step- required.
ping.)·

ADDRESSING 32-BIT OPERANDS

INSTRUCTION DIFFERENCES
These operands are formed from two adjacent 16-bit
Instruction times on the 80C 196KB are shorter than words in memory. The least significant word of the
those on the 8096 for many instructions. For example a double word is always in lower address, even when the
16X 16 unsigned multiply has been reduced from 25 to data is in the stack (which means that the most signifi-
'14 states. In addition, many zero and one operand in- cant word must be pushed into the stack first). A dou;
structions and most instructions using external data ble word is addressed by the address onts least signifi-
take one or two fewer state times. cant byte. Note that the hardware supports some opera-
tions on double words. For these operations the double
Indexed and indirect operations relative.to the stack word must be in the internal register file and must have
pointer (SP) work differently on the 80Cl96KBthan an address which is evenly divisible by four. .
on the 8096BH. On the 8096BH, the address is calcu-
lated based on the un-updated version of the stack
pointer. The 80CI96KB use~ the updated version. The SUBROUTINE LINKAGE
offset for POP[SP] and POP nn[SP] instructions may
need to be changed by a count of 2. Parameters are passed to subroutines in the stack. Pa-
rameters are pushed into the stack in the order that
they are encountered in the scanning of the source text.
Eight-bit parameters (BYTES 01: SHORT-INTE-
3.6 Software Standards and GERS) are pushed into the stack with the high order
Conventions byte undefined. Thirty-two bit parameters (LONG-IN-
For a software project of any size it is a good idea to TEGERS, DOUBLE-WORDS, and REALS) are
modularize the program and to establish' standards pushed onto the stack as two 16-bit values; the most
which control the communication between these mod- significant half of the parameter is pushed into the
ules. The nature of these standards will vary with the stack first.
needs of the final application. A common component of
aU of these standards, however, must be the mechanism As an .example, consider the following, PLM-96 proce-
for passing parameters to procedures and returning re- dure:
sults from procedures. In the absence of some overrid-
ing consideration which prevents their use, it is suggest- example_procedure: PROCEDURE
ed that the user conform to the conventions adopted by (param I ,param2,param3);
the PLM-96 programming language for procedure link- DECLARE paraml BYTE,
age. It is a very usable standard for both the assembly param2 DWORD,
param3 WORD;

4-25
inter 80C196KB USER'S GUIDE

When this procedure is entered at run time the stack It is recommended that unused areas. of code be filled
will contain the parameters. in. the following order: with NOPs and periodiC jumpst!J an error routine or
RST (reset chip) instructions. This is particularly im-
portant in the code around lookup tables, since if look-
?????? : param1 up tables are executed uncj.esired results will occur.
high word of param2 Wherever space allows, el;lch table should be surround-
ed by 7 NOPs (the longest 80Cl96KB instruction has 7
low word of param2 bytes) and a RST or jump to error routine instruction.
param3 Since RST is a one-byte instruction, the NOPs are not
needed if RSTs are used instead of jumps to an error
return address +- Staci<.::...pointer routine. This will help to ensure a speedy recovery
Figure 3-5. Stack Image should the processor have a glitch in the program flow.

If a procedure returns a value to the calling code (as The Watchdog Timer (WDT) further protects against
opposed to modifying more global variables) then the software and hardware errors. W:hen using the WDT to
result is returned in the variable PLMREG. PLMREG protect software it is desirable to reset it from only one
is viewed as either an 8-, 16- or 32-bit variable depend- place in code, lessening the chance of an undesired
ing on the type of the procedure. WDT reset. The section of code that resets the WDT
should monitor the other code sections for proper oper-
The standard calling convention adopted by PLM-96 ation. This can be done by checking variables to make
has several key features: sure they are within reasonable values. Simpl'y using a
software timer to reset the WDT every 10 milliseconds
a) Procedures can always assume that the eight bytes of , will provide protection only for catastrophic failures.
register file memory starting at PLMREG can be
used as temporaries within the body of the proce-
dure. 4.0 PERIPHERAL OVERVIEW
b) Code which calls a procedure must assume that the
eight bytes of register file memory starting at There are five major peripherals on the 80C196KB: the
PLMREG are modified by the procedure. pulse-width-modulated output· (PWM), Timer! and
.c) The Program Status Word (PSW-see Section 3.3) is Timer2, High Speed I/O Unit, Serial Port and A/D
not saved and restored by procedures so the calling Converter. With the exception of the high speed I/O
code must assume that the condition flags (Z, N, V, unit (HSIO), each of the peripherals is a single unit that
VT, C, and ST) are modified by the procedure. can be discussed without further separation.
d) Function results from procedures are always re: Four individual sections make up the HSIOand work
turned in the variable PLMREG. together to form a very flexible' timer/counter based
I/O system. Included in the HSIO are a 16-bit timer
PLM-96 allows the definition of INTERRUPT proce- (Timer!), a 16-bit up/down counter (Timer2), a pro-
dures which are executed when a predefined interrupt grammable high speed input unit (HSI), and a pro-
occurs. These procedures do not conform to the rules of grammable high speed output unit (HSO). With very
a normal procedure. Parameters cannot be passed to little CPU overhead the HSIO can measure pulse
these procedures and they cannot return results. Since widths, generate waveforms, and create periodic inter-
they can execute essentially at any time (hence the term rupts. Depending on the application, it can perform the
interrupt), these procedures must save the PSW and work of up to 18· timer/counters and capture/compare
PLMREG when they are entered and restore these val- registers.
ues before they exit.
A brief'description of the peripheral functions and in-
terractions is included in this section. It provides over-
3.7 Software Protection Hints view information prior to the detailed discussions in the
following sections. All of the details on control bits and
Several features to assist in recovery from hardware precautions are in the individual sections for each pe-
and software errors are available on the 80C196KB. ripheral starting with Section 5.
Protection is also provided against executing unimple-
mented opcodes by the unimplemented opcode inter-
rupt. In addition, the hardware reset instruction (RST)
can cause a reset if the program counter goes out of
bounds. This instruction· has an opcode of OFFH, so if
the processor reads in bus lines which have been pulled
high it will reset itself.

4-26
 inter 80C196KB USER'S GUIDE

4.1 Pulse Width Modulation Output HSI_TIME register. When the time register is read
(D/A) , the next FIFO location is loaded into the holding regis-
ter.
Digital to analog conversion can be done with the Pulse
Width Modulation output. The output waveform is a Three forms of HSI interrupts can be generated: when a
variable duty cycle pulse which repeats every 256 state value moves from the FIFO into the holding register;
times or 512 state times if the prescaler is enabled. when the FIFO (independent of the holding register)
Changes in the duty cycle are made by writing to the has 4 or more events stored; and when the FIFO has 6
PWM register. There are several types of motors which or more events stored. This flexibility allows optimiza-
require a PWM waveform for most efficient operation. tion of the HSI for the' expected frequency of interrupts.
Additionally, if this waveform is integrated it will pro-
duce a DC level which can' be changed in 256 steps by Independent of the HSI operation, the state of the HSI
varying the duty cycle. Details on the PWM are in Sec- pins is indicated by 4 bits of the HSI_STATUS regis-
tion 6. ter. Also independent of the HSI operation is the HSI.O
pin interrupt, which can be used as an extra external
interrupt even if the pin is not enabled to the HSI unit.
4.2 Timers
Two 16-bit timers are available for use on the 4.4 High Speed Outputs (HSO)
80C 196KB. The first is designated "Timer!", the sec-
ond "Timer2". Timer! is used to synchronize events to The High Speed Output (HSO) unit can generate events
real time, while Timer2 is clocked externally and syn- at specified times or counts based on Timer! or Timer2
chronizes events to external occurrences. The timers with minimal CPU overhead. A block diagram of the
are the time bases for the High Speed Input (HSI) and HSO unit is shown in Figure 4-4. Up to 8 pending
High Speed Output (HSO) units and can be considered events can be stored in the CAM (Content Addressable
an integral part of the HSI/O. Details on the timers are Memory) of the HSO unit at one time. Commands are
in Section 7. placed into the HSO unit by first writing to HSO_
COMMAND with the event to occur, and then to
Timer! is a free-running timer 'which is incremented HSO_TIME with the timer match value.
every eight state times, just as it is on the 8096BH.
Timer! can cause an interrupt when it overflows. Fourteen different types of events can be triggered by
the HSO: 8 external and 6 internal. There are two inter-
Timer2 counts transitions, both positive and negative, rupt vectors associated with the HSO, one for external
on its input which can be either the T2CLK pin or the events, and one for internal events. External events con:
HSI.I pin. Timer2 can be read and written and can be sist of switching one or more of the 6 HSO pins
reset by hardware, software or the HSO unit. It can be (HSO.O-HSO.5). Internal events include setting up 4
used as an up/down counter based on Port 2.6 and it's Software Timers, resetting Timer2, and starting an A/
value can be captured into the T2CAPture register. In- D conversion. The software timers are flags that can be
terrupts can be generated on capture events and if set by the HSO and optionally cause interrupts. Details
Timer2 crosses the OFFFFH/OOOOH boundary or the on the HSO Unit are in Section 9.
7FFFH/8000H boundary in either direction.

4.5 Serial Port

4.3 High Speed Inputs (HSI)
The serial port on the 80CI96KB is functionally co~­
The High Speed Input (HSI) unit can capture the value patible with the serial port on the MCS-51 and MCS-96
of Timer! when an event takes place on one of four families of microcontrollers. One synchronous and
input pins (HSI.O-HSI.3). Four types of events can trig- three asynchronous modes are available. The asynchro-
ger a capture: rising edges only, falling edges only, ris- nous modes are full duplex, meaning they can transmit
ing or falling edges, or every eighth rising edge. A block and receive at the same time. Double buffering is pro-
diagram of this unit is shown in Figure 4-3. Details on vided for the receiver so that a second byte can be re-
, the HSI unit are in Section 8. ceived before the first byte has been read. The transmit-
ter is also double buffered, allowing bytes to be written
When events occur, the Timer! value gets stored in the while transmission is still in progress.
FIFO along with 4 status bits which indicate the input
line(s) that caused the event. The next event ready to be The Serial Port STATus (SP_STAT) register contains
unloaded from the FIFO is placed in the HSI Holding bits to indicate receive overrun, parity, and framing er-
Register, so a total of 8 pieces of data can be stored in rors, and transmit and receive interrupts. Details on the
the FIFO. Data is taken off the FIFO by reading the Serial Port are in Section 10.
HSI_ST ATUS register, followed by reading the

4-27
inter 80C196KB USER'S GUIDE

HSI Trigger Options

FIFO

~ HITO~O
INTERRUPT

CONTROL
Be LOGIC 11 6l l
TI ER
I
-r- LOTOHI 4 7x20 BIT
FIFO
-IH'iOR."LOl-
I I
J1I1J1.I1.IUUUU
EVERY EIGHTH POSITIVE
TRANSITION

270651 ~18

270651-19

Figure 4·3. HSI Block Diagram

16-BIT 16-BIT

• T2RST
XTAL1/16
(P2.4)
CONTROL
LOGIC

~----~--24--------~

-..------16 - - - . I
16

HIGH SPEED OUTPUT CONTROLS

6 PINS
4 SOFTWARE TIMERS
2 INTERRUPTS
INITIATE AID CONVERSION
BUS RESET TIMER2

270651-8

Figure 4·4. HSO Block Diagram

4·28
inter 80C196KB USER'S GUIDE

MODES OF OPERATION input at a time using successive approximation with a

result equal to the ratio of the input voltage divided by
Mode 0 is a synchronous mode which is commonly the analog supply voltage. If the ratio is 1.00, then the
used for shift register based 1/0 expansion. Sets of 8 result will be all ones. A conversion can be started by
bits are shifted in or out of the 80C 196KB with a data writing to the AID_Command register or by an HSO
signal and a cIock signal. Command. Details on the AID converter are in Section
II.
Mode I is the standard asynchronous communications
mode: the data frame used in this mode consists of 10
bits: a start bit (0).8 data bits (LSB first), and a stop bit 4.7 I/O Ports
(1). Parity can be enabled to send an even parity bit
instead of the 8th data bit and to check parity on'recep- There are five 8-bit 1/0 ports on the 80CI96KB. Some
tion. of these ports are input only, some are output only,
some are bidirectional and some have multiple func-
Modes 2 and 3 are 9-bit modes commonly used for tions. In addition to these ports, the HSI/O pins can be
multi-processor communications. The data frame used used as standard 1/0 pins if their timer related features
in these modes consist of a start bit (0). 9 data bits (LSB are not needed.
first), and a stop bit (1). When transmitting, the 9th
data bit can be set to a one to indicate an address or Port 0 is an input port which is also the analog input
other global transmission. Devices in Mode 2 will be for the AID converter. Port 1 is a quasi-bidirectional
interrupted only if this bit is set. Devices in Mode 3 will port and the 3MSBs of Port I are multiplexed with the
be interrupted upon any reception. This provides an HOLD/HLDA functions. Port 2 contains three types
easy way to have selective reception on a data link. of port lines: quasi-bidirectional, input and output. Its
Mode 3 can also be used to send and receive 8 bits of input and o,utput· lines are shared with other functions
data plus even parity. such as serial- port receive and transmit and Timer2
clock and reset. Ports 3 and 4 are open-drain bidirec-
tional ports which share their pins with the addressl
BAUD RATES data bus.
Baud rates are generated in" an independent 15-bit Quasi-bidirectional pins can be used as input and out-
counter based on either the T2CLK pin or XTAL 1 pin. put pins without the need for a data direction register.
Common baud rates can be easily generated with stan- They output a strong low value and a weak high value.
dard crystal frequencies. A maximum baud rate of 750 The weak high value can be externally pulled low pro-
Kbaud is available in the asynchronous modes with viding an input function. A detailed explanation of
12MHz on XTALI. The synchronous mode has a max- these ports' can be found in Section 12.
imum rate of 3.0 Mbaud with a 12 MHz clock.

4.8 Watchdog Timer

4.6 A/D Converter
The Watchdog Timer (WDT) provides a means to re-
The 80CI96KB's Analog interface consists of a sample- cover gracefully from a software upset. When the
and-hold, an 8-channel multiplexer, and a 10-bit suc- watchdog is enabled it will initiate a hardware reset
cessive approximation analog-to-digital converter. unless the software clears it every 64K state times.
Hardware resets on the 80CI96KB cause the RESET
Analog signals can be sampled by any of the 8 analog input pin to be pulled low, pro~iding a reset signal to
input pins (ACHO through ACH7) which are shared other components on the board. The WDT is indepen-
with Port O. An AID conversion is performed on one dent of the other timers on the 80C196KB.

4-29
inter 80C196KBUSER'S GUI~E

5.0 INTERRUPTS Special Interrupts

Twenty-eight (28) sources 'of interrupts are available on Three special interrupts are available on the
the 80C196KB. These sources are gathered into 15 vec- 80C196KB: NMI, TRAP and Unimplemented opcode.
tors plus special vectors for NMI, the TRAP instruc- The external NMI pin generates an unmaskable inter-
tion, and Unimplemented Opcodes. Figure 5-1 shows rupt for implementation of critical interrupt routines.
the routing of the interrupt sources into their vectors as The TRAP instruction is useful in the development of
well as the control bits which enable some of the custom software debuggers or generation of software
sources. interrupts. The unimplemented opcode interrupt gener-
ates an interrupt when unimplemented opcodes are exe-

SOURCES VECTORS
NON - MASKABLE INTERRUPT - - - - - - - - - NMI

TIMER 2 CAPTURE TIMER 2 CAPTURE

4TH FIFO ENTRY - - - - - - - - - HSI FIFO 4

UNIMPLEMENTED OPCODE - - - - - - - - - UNIMPLEMENTED OPCODE

TRAP INSTRUCTION SOFTWARE TRAP

EXTINT (P2.2) EXTINT1

PORT 0.7 ---_e~IOC1.1

- EXTINT

TJ FLAG ......... TI FLAG (NEW)

/'~------ SERIAL PORT
RI FLAG - - - . . : ; ; . ; . . . - - - - RI FLAG (NEW)

SWTO - 3 ------r--- SOFTWARE TIMER

RESET TIMER 2 - - - - - - 1
START AID -----~

HSI.O PIN - - - - - - - - - HSI.O PIN

HSO PINS 0 - 5 - - - - - - - - - HIGH SPEED OUTPUT

HSI FIFO IS FULL - - - - . . . , . . - - - - HSI FIFO FULL (NEW)

HSI HOLDING REGISTER LOADED ---_e~IOC1.7

- HSI DATA AVAILABLE

AID CONVERSION COMPLETE AID CONVERSION COMPLETE

TIMER 2 OVERFLOW - - - . . . . , . - -____- TIMER 2 OVERFLOW (NEW)
L.:w-fIOC1.3
TIMER 1 OVERFLOW ---=r-r---
. . . ._-- TIMER OVERFLOW
IOC1.2
270651-9

Figure 5-1. 80C196KB Interrupt Sources

4-30
inter 80C196KB USER'S GUIDE

cuted. This provides software recovery from random The programmer must initialize the interrupt vector ta-
execution during hardware and software failures. Al- ble with the starting addresses of the appropriate inter-
though available for customer use, these interrupts may rupt service routines. It is suggested that any unused
be used in Intel development tools or evaluation boards. interrupts be vectored to an error handling routine. In a
debug environment, it may be desirable to have the rou-
tine lock into a jump to self loop which would be easily
NMI traceable with emulation tools. More sophisticated rou-
NMI, the external Non-Maskable Interrupt, is the tines may be appropriate for production code recover-
ies. "
highest priority interrupt. It vectors indirectly through
location 203EH. For design symmetry, a mask bit ex-
ists in INT_MASKI for the NM[ To prevent acci-
INTERRUPT SOURCES
dental masking of an NMI, the bit does not function
arid will not stop an NMI from occurring. For future
compatibility, the NMI mask bit must be set to zero.

NMI on the 8096 vectored directly to location {)()()()H,

so for the 80Cl96KB to be compatible with 8096 soft-
ware, which uses the NMI, location 203EH must be
loaded with OOOOH. The NMI interrupt vector and in-
terrupt vector location is used by some Intel develop-
ment tools. For example, the EV8OCl96KB evaluation
board uses the NMI to process serial communication
interrupts' from' the host. The NMI interrupt routine
executes monitor commands passed from the host. 80C196KB
28 Sources
The NMI interrupt is sampled during PHI or 18 Vectors
CLKOUT low and is latched internally. If the pin is
held high, multiple interrupts will not occur.

TRAP VECTOR STATUS

270651-10
Opcode OF7H, the TRAP instruction, causes an indi-
rect vector through location 201OH. The TRAP in- Figure 5-2. 80C196KB Interrupt Structure
struction provides a single instruction interrupt useful
Block Diagram
in designing software debuggers. The TRAP instruc-
tion prevents the acknowledgement of interrupts until
after execution of the next instruction. Five registers control the operation of the interrupt sys-
tem: INT_PEND, INT_PENDI, INT_MASK and
INT_MASKl and the PSW which contains a global
Unimplemented Opcode disable bit. A block diagram of the system is shown in
Figure 5-2. The transition detector looks for 0 to 1 tran-
Opcodes which are not implemented on the 80Cl96KB sitions on any of the sources. External sources have, a
will cause an indirect vector through location 2012H. maximum transition speed of one edge every state time.
User code or hardware which may have failed and run Sampling will be guaranteed if the level on the interrupt
into an unimplemented opcode can software recover line is held for at least one state time. If the interrupt
through this interrupt. The DJNZW instruction is not line is not held for at least one state time, the interrupt
supported on the 80Cl96KB but remains a valid op- may not be detecled.
code, therefore, no interrupt will occur.

.4-31
 80C196KB USER'S GUIDE

5.1 Interrupt Control format of these registers-is the same as that of the Inter-
rupt Pending Register shown in Figure 5-3;'
Interrupt Pending Register The INT_MASKand INT--,MASKI registers can be
read or written as byte registers. A one in any bit posi-
When the hardware detects one of the sixteen inter- tion will enable the corresponding interrupt source and
rupts it sets the corresp~mding bit in one o( two pending a zero will disable the source. The hardware will save
interrupt registers (INT_PEND-09H and INT_ any interrupts that occur by setting bits in the pending'
PENDl-12H). When the interrupt vector is taken, the register, even if t,he interrupt mask bit is cleared. The
pending bit is cleared. These registers, the formats of INT-,-MASK register is the lower eight hits of the
which are shown in Figure 5-3, can be read or modified PSW so the PUSHF and POPF instructions save and
as byte registers. They can ,be read to determine which restore the INT_MASK register as well as the global
of the interrupts are pending at any given time or modi- interrupt lockout and .the, arithmetic flags. Both the
fied to either clear pending interrupts or generate inter- INT_MASK and INT_MASKI registers can be
rupts under software control. Any software which saved with the PUSHA and POPA Instructions.
modifies the INT_PEND registers should ensure that
the entire operation is inseparable. The easiest way to
do this is to use the logical instructions in the two or Global Disable
three operand format, for example:
The processing of all interrupts except the NMI, TRAP
ANDB INT_PEND,#llllllOlB and unimplemented opcode interrupts can be disabled
; Clears the AID Interrupt by clearing the I bit in the PSW. Setting the I bit will
ORB INT_PEND,#OOOOOOlOB enable interrupts that have mask register bits which are
; Sets the AID Interrupt set. The I bit is controlled by the EI (Enable Interrupts)
and DI (Disable Interrupts) instructions. Note that the
Caution must be used when writing to the pending reg- I bit only controls the actual servicing of interrupts.
ister to' clear interrupts. If the interrupt has 'already Interrupts that occur during periods of lockout will be
been acknowledged when the bit is cleared, a 5 state held in the pending register and serviced on a: priori-
time "partial" interrupt cycle will occur. This is be- tized basis when the lockout period ends.
cause the 80CI96KB will have to fetch the next instruc-
tion of the normal instructionflQw, instead of proceed-
ing with the interrupt processing. The effect on the pro- 5.2 Interrupt Priorities
gram will be essentially that of an extra two NOP~
This can be prevented by clearing the bits using a 2 The priority encoder looks at all of the interrupts which
operand immediate logical, as the SOC196KB holds off are both pending and enabled, and selects the one with
acknowledging interrupts during these "read/modify/ the highest priority. The priorities are shown in Figure
write" instructions. 5-4 (IS is highest, 0 is lowest). The interrupt generator
then forces a call to the location in the indicated vector
location. This location would be the starting location of
Interrupt Mask Register the Interrupt Service Routine (ISR).
Individual interrupts can be enabled or disabled by set-
ting or clearing bits in the interrupt mask registers
(INT_MASK-OSH and INT_MASKl-I3H). The

7 6 5 4 3 2 1 0
12H IPEND1: FIFO EXT T2 T2
NMI HSI4 RI TI
13H IMASK1: FULL INT1 OVF CAP

7 6 5 4 3 2 1 0
09H IPEND: EXT SER SOFT HSI.O HSO HSI AID TIMER
08H IMASK: INT PORT TIMER PIN PIN DATA DONE OVF
Figure 5-3. Interrupt Mask and Pending Registers

4-32
inter 80C196KB USER'S GUIDE

Note that location 200CH in the interrupt vector table

Vector would have to be loaded with the label serial_io_isr
Number Source Priority
Location and the interrupt be enabled for this routine to execute.
INT15 NMI 203EH 15
There is an interesting chain of instruction side-effects
INT14 HSI FIFO Full 203CH 14 which makes this (or any other) 80Cl96KB interrupt
INn3 EXTINT1 203AH 13' service routine execute properly:
A) After the interrupt controller decides to process an
INT12 TIMER2 Overflow 2038H 12
interrupt, it executes a "CALL", using the location
INT11 TIMER? Capture 2036H 11 from the corresponding interrupt vector table entry
as the destination. The return address is pushed
INT10 4th Entry into HSI FIFO 2034H 10 onto the stack. Another interrupt cannQt be serviced
INT09 RI 2032H 9 until after the first instruction following the inter-
rupt call is executed.
INT08 TI 2030H 8
B) The PUSHA instruction, which is now guaran-
SPECIAL Unimplemented Opcode 2012H N/A teed to execute, saves the PSW, INT_MASK,
INT_MASKI, and the WSR on the stack as two
SPECIAL Trap 2010H N/A
words, and clears them. An interrupt cannot be
INT07 EXTINT 200EH 7 serviced immediately following a PUSHA instruc-
tion. (If INT_MASKI and the WSR register are
INT06 Serial Port 200CH 6 not used, or 8096BH code is being executed,
INT05 Software Timer 200AH 5 PUSHF, which saves only the PSW and
INT_MASK, can be used in place of PUSHA).
INT04 HSI.O Pin 2008H 4
C) LD INT_MASK, which is guaranteed to execute,
INT03 High Speed Outputs 2006H 3 enables those interrupts that are allowed to inter-
rupt this ISR. This allows the software to establish
INT02 HSI Data Available 2004H 2
its own priorities independent of the hardware.
INT01 AID Conversion Complete 2002H 1 D) The ~I instruction reenllbles the processing of inter-
INTOO Timer Overflow 2000H 0 rupts'with the new priorities.
E) At the end of the ISR, the POPA instruction re-
Figure 5·4. 80C196KB Interrupt Priorities
stores the PSW, INT_MASK, INT_MASKI, and
WSR to their original state when the interrupt oc-
This priority selection controls the order in which curred. Interrupts cannot occur immediately follow-
pending interrupts are passed to the software via inter- ing a POPA instruction so the RET instruction is
rupt calls. The software can then implement its own guaranteed to execute. This prevents the stack from
priority structure by controlling the mask registers overflowing if interrupts are ocq.lrring at high fre-
(INT_MASK and INT_MASKI). To see how this is quency. (If INT_MASKI and the WSR are not
done, consider the case of a serial 1/0 service routine being used, or 8096BH code is being executed,
which must run at a priority level which is lower than POPF, which restores only the PSW and
the HSI data available interrupt but higher than any INT_MASK, can be used in place of POPA.)
other source. The "preamble" and exit code for this
interrupt service routine would look like this:

serial_io_isr:
'PUSHA ; Save the PSW, INT_MASK
; INT_MASKl,' and WSR
LDB INT_MASK,#OOOOOIOOB

I
EI ; Enable interrupts again

S,rvi" th,int,rrupt

POPA Restore
RET

4-33
 80C196KB' USER,'S GUIDE

Notice that the "preamble" and exit code for the inter- if interrupts are disabled. Depending on system config-
rupt service routine does not include any code for sav- urations, several other SFRs might also need to be
ing or restoring registers. This is because it has been changed in a! single instruction for the same reason.
assumed that the interrupt service routine has been al-
located its own private set of registers from the on- When variables must be modified without interruption"
board register file. The availability of some 230 bytes of and a single instruction can not be used, the program-
register storage makes this quite practical. mer must create what is termed a critical region in
which it is safe to modify the variable. One way to do
this is to simply disable interrupts with a D I instruc'
5.3 Critical Regions tion, perform the modification, and then re-enable in-
terrupts with an EI instruction. The problem with this
Interrupt service routines must sometimes share data approach is that it leaves the interrupts enabled even if
with other routines. Whenever the programmer is cod- they were not enabled at the start. A better solution is
ing those sections of code which access these shared to enter the critical region with a PUSHF instruction
pieces of data, great care must be taken to ensure that which saves the PSW and also clears the interrupt en-
the integrity of the data is maintained. Consider clear- able flags. The region can then be terminated with a
ing a bit in the interrupt pending register as part of a POPF instruction whic\I returns the interrupt enable to
non-interrupt routine: the state it was in before the code sequence. It should be
noted that some system configurations might require
LDB AL, INT _PEND more protection to form a critical region. An example
ANDB AL,#blLmask is a system in which more than one processor has ac-
STB AL,INT_PEND cess to a common resource such as memory or external
I/O devices.
This code works if no other routines are operating con-
currently, but will cause occasional but serious prob-
lems if used in, a concurrent environment. (All pro- 5.4 Interrupt Timing
grams which make use of interrupts must be considered
to be part of a concurrent environment.) To demon- The 80Cl96KB can be interrupted from four different
strate this problem, assume that the INT_PEND reg- external sources; NMI, P2.2, HSI.O an!i PO.7. All exter-
ister contains OOOOlll1B and bit 3 (HSO event inter- nal interrupts are sampled during PHI or CLKOUT
rupt pending) is to be reset. The code does work for this low and are latched internally. Holding levels on exter-
data pattern but what happens if an HSI interrupt oc- nal interrupts for at least one state, time will ensure
curs somewhere between the LDB and the STB instruc- recognition of the interrupts.
tions? Before the LDB instruction INT_PEND con-
tains 00001111B and after the LDB instruction so does The external interrupts on the 80C196KB, although
AL. If the HSI interrupt service routine executes at this sampled during PHI, are edge triggered interrupts as
point then INT_PEND will change to OOOOIOI1B. opposed to level triggered. Edge triggered interrupts
The ANDB changes AL to 00OO0l11B and the STB will generate only one interrupt if the input is held
changes INT_PEND to OOOOOIIIB. It should be high. On the other hand, level triggered interrupts will
OOOOOOIIB. This code sequence has managed to gener- generate multiple interrupts when held high.'
ate a false HSI interrupt The same basic process can
generate an amazing assortment of problems and head- Interrupts are not always acknowledged immediately.
aches. These problems can be avoided by assuring mu- If the interrupt signal does not, occur prior to 4 state-
tual exclusion which basically means that if more than times before the end of an instruction, the interrupt
one routine can change a variable, then the program- may not be acknowledged until after the next instruc.
mer must ensure exclusive access to the variable during tionhas been executed. This.is because an instruction is
the entire operation on the variable. fetched and prepared for execlltion a few state times
before it is actually executed.
In many cases the instruction set of the 80Cl96KB al-
lows the variable to be modified with a single instruc- There are 6 instructions which always inhibit interrupts
tion. The code in the above example can be implement- from being acknowledged until after the next instruc-
ed with a single instruction. tion has been executed. These instructions are:
EI, DI - Enabkand disable all interrupts by tog-
ANDB gling the global disable bit (PSW.9).
Instructions are indivisible so mutual exclusion is en- PUSHF - PUSH Flags pushes the PSW/IN:r_
sured in this case. Changes to the INT_PEND or MASK pair then clears it, leaving both
INT_PENDI register must be made as a single in- INT_MASK and PSW.9 clear.
struction, since bits can be changed in'this register even

4-34
inter 80C196KB USER'S GUIDE

POPF - POP Flags pops the PSW lINT_MASK following EI. The 01, PUSHF, POPF, PUSHA, POPA
pair off the stack and TRAP instructions will also cause the same situa-
PUSHA - PUSH All does a PUSHF, then pushes tion. Typically these instructions would only effect la-
, the INT_MASK l/WSR pair and clears' tency when one interrupt routine is already in process"
INT_MASKl as these instructions are seldom used at other times.
POPA - POP All pops the INT_MASKl/WSR
pair and then does a POPF
5.5 Interrupt Summary
Interrupts can also not occur immediately after execu- Many of the interrupt vectors on the 8096BH were
tion of: shared by multiple interrupts. The interrupts which
Unimplemented Opcodes were shared on the 8096BH are: Transmit Interrupt,
TRAP - The software trap instruction Receive Interrupt, HSI FIFO Full, Timer2 Overflow
and EXTINT. On the 80C196KB, each of these inter-
SIGND - The signed prefix for multiply and divide rupts have their own interrupt vectors. The source of
instructions the interrupt vectors are typically programmed through
control registers. These registers can be read in Win-
When an interrupt is acknowledged the interrupt pend- dow 15 to determine the source of any interrupt. Inter-
ing bit is cleared, and a call is forced to the location rupt sources with two possible interrupt vectors, serial
indicated by the specified interrupt vector. This call oc- receive interrupt sharing serial port and receive inter-
curs after the completion of the instruction in process, rupt vectors for example, should be configured for only
except as noted above. The procedure of getting the one interrupt vector.
vector and forcing the call requires 16 state times. If the
stack is in external RAM an additional 2 state times are Interrupts with separate vectors include: NMI, TRAP,
required. Unimplemented Opcode, Timer2 Capture, 4th Entry
into HSI FIFO, Software timer, HSI.O Pin, High Speed
The maximum number of state times required from the Outputs, and AID conversion Complete. The NMI,
time an interrupt is generated (not acknowledged) until TRAP and Unimplemented Opcode interrupts were
the 80CI96KB begins executing code at the desired lo- covered in section 5.0.
cation is the time of the longest instruction, NORML
(Normalize - 39 state times), plus the 4 state times
prior to the end of the previous instruction, plus the EXTINT and PO.7
response time (16(internal stack) or 18(external stack)
state tillles). Therefore, the maximum response time is The 80CI96KB has two external interrupt vectors;
61 (39 + 4 + 18) state times. This does not include the EXTINT (200EH) and EXTINTI (203AH). The
10 state times' required for PUSHF if it is used as the EXTINT vector has two alternate sources selectable by
first instruction in the interrupt routine or additional IOCI.I, the external interrupt pin (Port 2.2) and Port
latency caused by having the interrupt masked or dis- 0.7, The external interrupt pin is the only source for the
abled. Refer to Figure 5-5, Interrupt Response Time, to EXTINTI interrupt vector. The external interrupt pin
visualize an example of worst case scenario. should not be programmed to interrupt through both
vectors. Both external interrupt sources are rising edge
Interrupt latency time can be reduced by careful selec- triggered,
tion of instructions in areas of code where interrupts
are expected. Using 'El'followed immediately by a
long instruction (e.g. MUL, NORML, etc.) will in-
crease the maximum latency by 4 state times, as an
interrupt cannot occur between EI and the instruction

STATE TIMES 432 3 9 - - - - ·- 1 6 - - - . . - - 2 - - - . . . . - 6--.

EXECUTION 'PUSHF' ~
INTERRUPT ROUTINE
EXTINT~
PENDING
BIT
..J SET
RESPONSE TIME f-I.---------
270651-11

Figure 5-5. Interrupt Response Time

4-35
 80C196KB USER'S GUIDE

Serial Port Interrupts are individually enabled by setting bits 2 and 3 oflOC1:
bit 2 for Timer!, and bit 3 for Timer2. Which timer
The serial port generates one of three possible inter- actually caused the interrupt can be determined by bits
rupts: Transmit interrupt TI(2030H), Receive Interrupt 4 and 5 of 10SI: bit 4 for Timer2 and 5 for Timer!. On
RI(2032H) and SERIAL(200CH). Refer to section 10 the 80CI96KB Timer2 overflow(OH or 8000H) has a
for information on the serial port interrupts. The separate interrupt vector through location 2038H.
8096BH shared the TI and RI interrupts on the SERI-
AL interrupt vector. On the 80C196KB, these inter-
rupts share both the serial interrupt vector and have Timer2 Capture
their own interrupt vectors. Ideally, the transmit and The 80CI96KB can generate an interrupt in response
receive interrupts should be programmed as separate to a Timer2 capture triggered by a rising edge on P2.7.
interrUpt vectors while disabling the SERIAL inter- Timer2 Capture vectors through location 2036H.
rupt. For 8096BH compatibility, the interrupts can still
use the SERIAL interrupt vector.
High Speed Outputs
HSI FIFO FULL and HSI DATA AVAILABLE The High Speed Outputs interrupt can be generated in
response to a programmed HSO command which caus-
HSI FIFO FULL and HSI DATA AVAILABLE in-
es an external event. HSO commands which set or clear
terrupts shared the HSI DATA AVAILABLE inter- the High Speed Output pins are considered external
rupt vector on the 8096BH. The source of the HS,I events. Status Register IOS2 indicates which HSO
DATA AVAILABLE interrupt is controlled by the
events have occured and can be used to arbitrate which
setting of 1/0 Control Register I ,(IOC 1.7). Setting HSO command caused the interrupt. The High Speed
IOC1.7 to zero will generate an interrupt when a time Output 'interrupt vectors indirectly through location
value is loaded into the holding register. Setting the bit 2006H. For more information on High Speed Outputs,
to one generates an interrupt when the FIFO, indepen-
refer to Section 9.
dent of the holding register, has six entries in it.

On the 80C196KB, separate interrupt vectors are avail- Software Timers

able for the HSI FIFO FULL(203CH) and HSI DATA
AV AILABLE(2004H) interrupts. The interrupts HSO commands which create internal events can inter-
should be programmed for separate interrupt vector lo- rupt through the Software Timer interrupt vector. In-
cations. Refer to Section 8 for more information on the ternal events include triggering an AID conversion, re-
High Speed Inputs. setting Timer2 and software timers. Status registers
IOS2 and 10SI can be used to determine which internal
HSO event has occured. Location 200AH is the inter-
rupt vector for the Software Timer interrupt. Refer to
Section 9 for more information on software timers and
The HSI FIFO can generate an interrupt when the HSI the HSO.
has four or more entries in the FIFO. The HSI FIFO_
4 interrupt vectors through location 2034H.· Refer to
Section 8 for more information on the High Speed In- AID Conversion Complete
puts.
The AID Conversion Complete interrupt can generate
an interrupt in response to a completed AID conver-
HSI.O External Interrupt sion. The interrupt vectors indirectly through location
2002H. Refer to section II for more information on the
The rising edge on HSI.O pin can be used as an external AID Converter.
interrupt. The HSI.O pin is sampled during PHI or
CLKOUT low. Sampling is guaranteed if the pin is
held for at least one state time. The interrupt vectors
through location 2008H. The pin does not need to be
6.0 Pulse Width Modulation Output
enabled to the HSI FIFO in order to generate the inter- (D/A)
rupt.
Digital to analog conversion can be done with the Pulse
Width Modulation output; a block diagram of the cir-
Timer2 and Timer1 overflow cuit is shown in Figure 6-1. The 8-bih:ounter is incre-
mented every state time. When it equals 0, the PWM
Timer2 and Timer! can interrupt on overflow. These output is set to a one. When the counter matches the
interrupts shared the same interrupt vector TIMER value in the PWM register, the output is switch!!d low.
OVERFLOW(2000H) on the 8096BH. The interrupts When the counter overflows, the output is once again
switched high. A typical output waveform is shown in

4-36
intJ 80C196KB USER'S GUIDE

Figure 6-2. Note that when the PWM register equals

00, the output is always low. Additionally, the PWM
register will only be reloaded from the temporary latch
when the counter overflows. This means the compare
circuit will not recognize a new value' until the counter
has expired preventing missed PWM edges.

The 80C196KB PWM unit has a prescaler bit (divide

by 2) which is enabled by setting IOC2.2 = 1. The
PWM frequencies are shown in Figure 6-3. The output
waveform is a variable duty cycle pulse which 'repeats
every 256 or 512 state times (42.75 J-Ls or 85.5 J-Ls at
12 MHz). Changes in the duty cycle are made by writ- PWM
ing to the PWM register at location 17H. The value OUTPUT
programmed into the PWM register can be read in
Window 15 (WSR = 15). There are several types of mo-
tors which require a PWM waveform for more efficient
operation. Additionally, if this waveform is integrated
it will produce a DC level which can be changed in 256 STATE TIME CLOCK
steps by varying the duty cycle. as described in the next F(XTAL1 )/2
section.
270651-12
XTAL1 = 8MHz 10MHz 12 MHz • Duty Cycle Programmable In 256 Steps
IOC2.2 = 0 15.6 KHz 19.6 KHz 23.6 KHz Figure 6-1. PWM Block Diagram
IOC2.2 = 1 7.8 KHz 9.8 KHz 11.8 KHz
Figure 6-3. PWM Frequencies

The PWM output shares a pin with Port 2, pin 5 so

that these two features cannot be used at the same time.
IOCI.O equal to 1 selects the PWM function instead of
the standard port function.

DUTY PWM CONTROL

CYCLE REGISTER VALUE OUTPUT WAVEFORM
HI
0% 00
LO

10% 25
~~Jl~____~n~____~n~_____
HI
50% 128
LO

90% 230 HI
LO
-1 u u
HI
99.6% 255
LO
270651-13

Figure 6-2. Typical PWM Outputs

4-37
 80C196KB USER~S GUIDE

6.1 Analog Outputs drift, a highly accurate 8-bit 0 to A converter can be

made using either the HSO or the PWM output. Figure
Analog outputs can be generated by two methods, ei- 6-5 shows two typical circuits. If the HSO is used the
ther by using the PWM output or the HSO. See Section , accuracy could be theoretically extended to l6-bits,
9.7 for information on generating a PWM with the however the temperature and noise .related problems
High Speed Output Unit. Either device will generate a would be extremely hard to handle.
rectangular pulse train that varies in duty cycle and
period. If a smooth analog signal is desired as an out- When driving some circuits it may be desirable to use
put, the rectangular waveform must be filtered. unfiltered Pulse Width Modulation. This is particularly
true for motor drive circuits. The PWM output can
In most cases this filtering is best done after the signal generate these waveforms if a fixed period on the order
is buffered to make it swing from 0 to 5 volts since both of 64 f-ts is acceptable. If this is not the case then the
of the outputs are guaranteed only to low current lev- HSO unit can be used. The HSO can generate a vari-
els. A block diagram of the type of circuit nee,!led is . able waveform with a duty cycle variable in up to 65536
shown in Figure 6-4. By proper selection of compo- steps and a period of up to 87.5 milliseconds. Both of
nents, accounting for temperature and power supply these outputs produce CHMOS levels.

BUFFER
'80C196KB TO MAKE FILTER
(PASSIVE POWER
HSO OUTPUT
OR SWING
OR
ACnVE)
AMP I---- ANALOG
OUTPUT
PWM RAIL (OpnONAL)
TO (OPnONAL)
RAIL

270651-14

Figure 6-4. 01 A Buffer Block Diagram

Vcc

* 1/2 VQ3001 P
6

270' 7 S.1K
PWM----~VV~---- __ . .____~~__--~t-----ANALOG
8 OUT

270651-15

80C196KB
HSO R HIGH ANALOG
OR ~_----"'Nw----_----_IIMPEDANCE .....- - - OUTPUT
PWM AMP
c

270651-16

Figure 6-5. Buffer Circuits for 01 A

4-38
 80C196KB USER'S GUIDE

7.0 TIMERS Capture Register

The value in Timer2 can be captured into the

7.1 Timer1 T2CAPture register by a rising edge on P2. 7. The edge
must be held for at least one state time as discussed in
Timer! is a 16-bit free-running timer which is incre- the next section. T2CAP is located at OCH in Window
mented every eight state times. An interrupt can be 15. The interrupt generated by a capture vectors
generated in response to an overflow. It is read through through location 2036H.
location OAH in Window 0 and written in Window 15.
Figure 7-1 shows a block diagram of the timers.
Fast Increment Mode
Care must be taken when writing to it if the High Speed Timer2 can be programmed to run in fast increment
I/O (HSIO) Subsystem is being used. HSO time entries mode to count transitions every state time. Setting
in the CAM depend on exact matches with Timer!. IOC2.0 programs Timer2 in the Fast Increment mode.
Writes to Timer! should be taken into account in soft- In this mode, the events programmed on the HSO unit
ware to ensure events in the HSO CAM are not missed with Timer2 as a reference will not execute properly
or occur in an order which may be unexpected. Chang- since the HSO requires eight state times to compare
ing Timer! with incoming events on the High Speed every location in the HSO CAM. With Timer2 as a
Input lines may corrupt relative references between reference for the HSO unit, Timer2 transitioning every
captured inputs. Further information on the High state time may cause programmed HSO events to be
Speed Outputs and High Speed Inputs can be found in missed. For this reason, Timer2 should not be used as a
Sections 8 and 9 respectively. reference for the HSO if transitions occur faster than
once every eight state times.
7.2 Timer2 Timer2 should not be RESET in the fast increment
Timer2 on the 80Cl96KB can be used as an external mode. All Timer2 resets are synchronized to an eight
reference for the HSO unit, an up/down counter, an state time clock. If Timer2 is reset when clocking faster
external event capture or as an extra counter. Timer2 is than once every 8 states, it may' reset on a different
clocked externally using either the T2CLK pin (P2.3) count.
or the HSI.l pin depending on the state of IOCO.7.
Timer 2 counts both positive and negative transitions. Up/Down Counter Mode
The maximum transition speed is once per state time in
the Fast Increment mode, and once every 8 states oth- Timer2 can be made to count up or down based on the
erwise. CLKOUT cannot be used directly to clock Port 2.6 pin if IOC2.1 = 1. However, caution must be
Timer2. It must first be divided by 2. Timer2 can be used when this feature is working in conjunction with
read and written through location OCH in Window O. the HSO. If Timer2 does not complete a full cycle it is
Figure 7-1 shows a block diagram of the timers. possible to have events in the CAM which never match
the timer. These events would stay in the CAM until
Timer2 can be reset by hardware, software or the HSO the CAM is cleared or the chip is reset.
unit. Either T2RST (P2.4) or HSl.O can reset Timer2
externally depending on the setting of IOCO.S. Figure
7-2 shows the configuration and input pins of Timer2. 7.3 Sampling on External Timer Pins
Figure 7-3 shows the reset and clocking options for
Timer2. The appropriate control registers can be, read The T2UP/DN, T2CLK, T2RST, and T2CAP pins are
in Window 15 to determine the programmed modes. sampled during PHI. PHI roughly corresponds to
However,.IOCO.l(T2RST) is not latched and will read CLKOUT low externally. For valid sampling, the in-
al. puts should be present 30 risec prior to the rising edge
of CLKOUT or it may not be sampled until the next
Caution should be used when writing to the timers if CLKOUT. If the T2UP/DN signal changes and be-
they are used as a reference to the High Speed Output comes stable before, or, at the same time that the
Unit. Programmed HSO commands could be missed if T2CLK signal changes, the count will go into the new
the timers do not count continuously in one direction. direction.
High Speed Ol:ltput events based on Timer2 must be
carefully programmed when using Timer2 as an
up/down counter or is reset externally. Programmed
events could be missed or occur in the wrong order.
Refer to section 9' for more information on using the
timers with the High Speed Output Unit.

4-39
 80C196KB USER'S GUIDE

[J~[J+--------:--P2.7

....---P2.6

1+---T2CLK

1+---HSI.l

'----------T2RST

270651-5

Figure 7-1. Timer Block Diagram

Bit = 1 Bit = 0
IOCO.1 Reset Timer2 each write No action
IOCO.3 Enable external reset Disable
IOCO.5 HSI.O is ext. reset source T2RST is reset source
lOCO.? HSI.1 is T2 clock source T2CLK is clock source
IOC1.3 Enable Timer2 overflow int. Disable overflow interrupt
IOC2.0 Enable fast increment Disable fast increment
IOC2.1 Enable downcount feature Disable downcount
P2.6 Count down if IOC2.1 = 1 Count up
IOC2.5 Interrupt on ?FFFH/SOOOH Interrupt on OFFFFH/OOOOH
P2.? Capture Timer2 into
T2CAPture on rising edge
Figure 7-2. Timer2 Configuration and Control Pins
7.4 Timer Interrupts
Both Timer! and Timer2 can trigger a timer overflow
interrupt and set a flag in the I/O Status Register I
(lOS I). Timerl overflow is controlled oy setting
IOC1.2 and the interrupt status is indicated in IOSI.5.
The TIMER OVERFLOW interrupt is enabled by set-
ting INT_MASK.O.
A Timer2 overflow condition interrupts through loca-
tion 2000H by setting IOCI.3 and setting INT_
MASK.O. Alternatively, Timer2 overflow can interrupt
through location 2038H by setting INT_MASKI.3.
The status of the. Timer2 overflow interrupt is indicated
in IOSI.4.

IOCO.5 270651-17
Interrupts can be generated if Timer2 crosses the
OFFFFH/OOOOH boundary or the 7FFFH/8000H
Figure 7-3. Timer2 Clock and Reset Options boundary in either direction. Byhaving two interrupt
points it is possible to have 'interrupts enabled even if

4-40
 80C196KB USER'S GUIDE

Timer2 is counting up and down centered around one timer interrupts are controlled by the Interrupt Mask
of the interrupt points. The boundaries used to control Register bit O. In all cases, setting a bit enables a func-
the Timer2 interrupt is determined by the setting of tion, while clearing a bit disables it.
IOC2.5. When set, Timer2 will interrupt on the
7FFFH/8000H boundary, otherwise, the OFFFFH/
OOOOH boundary interrupts. 8.0 HIGH SPEED INPUTS
A T2CAPTURE interrupt is enabled by setting INT_ The High Speed Input Unit (HSI) can record the time
MASK 1.3. The interrupt will vector through location an event occurs with respect to Timer!. There are 4
2036H. lines (HSI.O through HSI.3) which can be used in this
mode and up to a total of 8 events can be recorded.
Caution must be used when examining the flags, as any HSI.2 and HSI.3 are bidirectional pins which can also
access (including Compare and Jump on Bit) of 10SI be used as HSO.4 and HSO.5. The I/O Control Regis-
clears bits 0 through 5 including the software timer ters (lOCO and lOCI) determine the functions of these
flags. It is, therefore, recommended to copy the byte to pins. The values programmed into lOCO and lOCI can
a temporary register before testing bits. Writing to be read in Window IS. A block diagram of the HSI unit
10SI in Window 15 will set the status bits but not cause is shown in Figure 8-1.
interrupts. The general enabling and disabling of the

HSI Trigger Options

FIFO
~ HITOLO
-r- LOTOHI
INTERRUPT

CONTROL
& LOGIC 111 T
sliR I
--IHiOR L'Ol-
I I 4 7x20 BIT
..n.nn.n.n.n.n.
EVERY EIGHTH POSITIVE
FIFO

TRANSITION

270651-18 HSLSTATUS '

270651-19

Figure 8-1. High Speed Input Unit

HSI Status Register (HSI_Status)

17 6 15 4 I 3 I 2 I 1 I 0 I 06H '

I C HSI.O STATUS
HSI.l STATUS
HSI.2 STATUS
HSI.3 STATUS
WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
BIT (STATUS BIT) INDICATES WHETHER OR NOT AN EVENT
HAS OCCURED ON THIS PIN AND THE UPPER BIT (INPUT BIT)
INDICATES THE CURRENT INPUT LEVEL OF THE PIN.
270651-22

Figure 8-2. HSI Status Register Diagram

4-41
 80C196KB USER'S GUIDE

When an HSI event occurs, a 7 X 20 FIFO stores the 16

bits of Timer!, and the 4 bits indicating which pins T2RST - - 0 • - - IOCO.S

I
recorded events associated with that time tag. There- ~~""'----T2 RESET
fore, if multiple pins are being used as HSI inputs, soft- • - - IOCO.3
ware must check each status bits when processing on • - - IOCO.O
HSI event. MuItiplepins can recognize events with the HSI.O ~_------HSI
same time tag. It can take up to 8 state times for this ••• IOCO.2
information to reach the holding register. For this rea-
son, 8 state times must elapse between consecutive ro~-------HSI
reads of HSI_TIME. When the FIFO is full, one addi- HSI.l .~ TIMER2
tional event, for a total of 8 events, can be stored by T2CLK - - 0 ,l_ - IOCO.7 CLOCK
considering the holding register part of the FIFO. If the .-- IOCO.4
FIFO and holding register are full, any additional
events will not be recorded.
HSI.2 - - 0 "-0------- HSI
• - - IOCO.6
HSI.3 ~"-o------- HSI
8.1 HSI Modes 270651-21

There are 4 possible modes of operation for each of the Figure 8·4. lOCO Control of HSI Pin Functions
HSI pins. The HSI_MODE register at location 03H
controls which pins wiIllook for what type of events. In 8.2 HSI Status
Window 15, reading the register will read back the pro-
grammed HSI mode. The 8-bit register is set up as Bits 6 and 7 of the I/O Status Register 1 (lOS I-see
shown in Figure 8-3. Figure 8-5) indicate the status of the HSI FIFO. If bit 7
is set, the HSI holding-register is loaded. The FIFO
mayor may not contain 1-5 events. If bit 6 is set, the
03H
FIFO contains 6 entries. If the FIFO fills, future events
will not be recorded. Reading 10SI clears bits 0-5, so
keep an image of the register and test the image to
retain all 6 bits.

' - - - - - - - - HSI.2 MODE

Reading the HSI holding register must be done in ·a
certain order. The HSI_STATUS Register (Figure 8-
' - - - - - - - - - - HSI.3 MODE 2) is read first to obtain the status and input bits. Sec-
WHERE EACH 2 - BIT MODE CONTROL FIELD ond, the HSI_TIME Register (04H) is read to obtain
DEFINES ONE OF 4 POSSIBLE MODES: the time tag. Reading HSI_TIME unloads one level of
00 8 POSITIVE TRANSITIONS
the FIFO. If the HSI_TIME is read before
01 EACH POSITIVE TRANSITION HSI_STATUS, the contents of HSI_STATUS associ-
10 EACH NEGATIVE TRANSITION ated with that HSI_TIME tag are lost.
11 EVERY TRANSITION
(POSITIVE AND NEGATIVE)
270651-20
SOFTWARE TIMER 0 EXPIRED
Figure 8·3. HSI Mode Register 1 SOFTWARE TIMER 1 EXPIRED
SOFTWARE TIMER 2 EXPIRED
The maximum input speed is 1 event every 8 state times
except when the 8 transition mode is used, in which SOFTWARE TIMER 3 EXPIRED
case it is 1 transition per state time. TIMER 2 HAS OVERFLOW

The HSI pins can be individually enabled and disabled TIMER 1 HAS OVERFLOW
using bits in lOCO as shown in Figure 8-4. If the pin is HSI FIFO IS FULL
disabled, transitions are not entered in the FIFO. How-
HSI HOLDING REGISTER DATA AVAILABLE
ever, the input bits of the HSI_STATUS register (Fig-
ure 8-2) are always valid regardless of whether the pin 16H
is enabled to the FIFO. This allows the HSI pins to be 270651-23
used as general purpose input pins.
Figure 8·5. 110 Status Register 1

4-42
 80C196Ka USER'S GUIDE

If the HSI_TIME register is read without the holding The HSI.O pin can g~nerate an interrupt on the rising
register being loaded, the returned value will be indeter- edge even if its not enabled to the HSI FIFO. An inter-
minate. Under the same conditions, the four bits in rupt generated by this pin vectors through location
HSI_STATUS indicating which events have occurred 2008H.
will also be indeterminate. The four HSI_STATUS
bits which indicate the current state of the pins will
always return the correct value. 8.4 HSI Input Sampling
It should be noted that many of the Status register con- The HSI pins are sampled internally once each state
ditions are changed by a reset, see section 13. Writing time. Any value on these pins must remain stable for at
to HSI_TIME in window 15 will write to the HSI least 1 ful1 state time to guarantee that it is recognized:
FIFO holding register. Writing to HSI_STATUS in The actual sampling occurs during PHI or during
Window 15 will set the status bits but will not affect the CLKOUT low. The HSI inputs should be valid at least
input bits. 30 nsec before the rising of CLKOUT. Otherwise, the
HSI input may be sampled in the next CLKOUT.
Therefore, if information is to be synchronized to the
8.3 HSI Interrupts HSI it should be latched on the rising edge of
CLKOUT.
Interrupts can be generated by the HSI unit in three
ways: when a value moves from the FIFO into the
holding register; when the FIFO (independent of the 8.5 Initializing the HSI
holding register) has 4 or more event stored; when the
FIFO has 6 or more events. To start the HSI, the fol1owing steps and the sequence
must be observed; 1) flush the FIFO, 2) enable the HSI
The HSI DATA AVAILABLE and HSI FIFO FULL interrupts, and 3) initialize and enable the HSI pins.
interrupts are shared on the 8096BH. The source for The following section of code can be used to flush the
the HSI DATA AVAILABLE interrupt is controlled FIFO:
by IOC1.7. When IOC1.7 is cleared, the HSI will gen-
erate an interrupt when the holding register is loaded. reflush: 1d 0, HSLT1ME ;c1ear an event
The interrupt indicates at least one HSI event has oc- skipO ;wai t 8 state times
curred and is ready to be processed. The interrupt vec- skipO
tors through location 2004H. The interrupt is enabled j bs 10S1, 7, reflush
by setting INT_MASK.2. The generation of a HSI
DATA AVAILABLE interrupt will set IOS1.7. The Enabling the HSI pins before enabling the interrupts
HSI FIFO FULL interrupt will vector through HSI can cause a FIFO lockout condition. For example, if
DATA AVAILABLE if IOC1.7 is set. On the the HSI pins were enabled first, an event could get
80C196KB, the HSI FIFO FULL has a separate inter- loaded into the holding register before the HS1_
rupt vector at location 203CH. DAT A~VAILABLE interrupt is enabled. If this
happens, no HSI_DA TA_A VAILABLE interrupts
A HSI FIFO FULL interrupt occurs when the HSI will ever occur.
FIFO has six or more entries loaded independent of the
holding register. Since all interrupts are rising edge trig-
gered, the processor will not be reinterrupted until the 9.0 HIGH SPEED OUTPUTS
FIFO first contains 5 or less records, then contains six
or more. The HSI FIFO FULL interrupt mask bit is The High Speed Output unit (HSO) trigger events at
INT_MASK1.6. The occurrence of a HSI FIFO specific times with minimal CPU overhead. Events are
FULL interrupt is indicated by IOS1.6. Earlier warning generated by writing commands to the HSO_COM-
of a impending FIFO ful1 condition can be achieved by MAND register and the relative time at which the
the HSI FIFO 4th Entry interrupt. events are to occur into the HSO_TIME register. In
Window IS, these registers will read the last value pro-
The HSI_FIFO_4 interrupt generates an interrupt grammed in the holding register. The programmable
when four or more events are stored in the HSI FIFO events include: starting an AID conversion, resetting
independent of the holding register. The interrupt is Timer2, setting 4 software flags, and switching 6 output
enabled by setting INT_MASK 1.2. The HSI_ lines (HSO.O through HSO.5). The focinat of the
FIFO_4 vectors indirectly through location 2034H. HSO_COMMAND register is.shown in Figure 9-1.
There is no status flag associated with the HSI_ Commands OCH and ODH are reserved for use on fu-
FIFO_4 interrupt since it has its own independent in- ture products. Up to eight events can be pending\at one
terrupt vector.. time and interrupts can be generated whenever any of
these events are triggered. HSO.4 and HSO.5 are bi-

4-43
 80C196KB USER'S.GUIDE

7 6 5 4 3 I 2 I 1 I 0
HSO_ CAM TMR2/ SET/ INT/
CHANNEL 06H
COMMAND LOCK TMR1 CLEAR lNT

CAM Lock - Locks event in CAM if this is enabled by IOC2.6 (ENA_LOCK)

TMR/TMRI - Events Based on Timer2lBased on Timer! If 0
SET/CLEAR - Set HSO pin/Clear HSO pin if 0
INT/INT - Cause interrupt/No interrupt if 0
CHANNEL: 0-5: HSO pins 0-5 separately
(in Hex) 6: HSO pins 0 and I together
7: HSO pins 2 and 3 together
8-B: Software Timers 0-3
C-D: Unflagged Events (Do not use for future compatibility)
E: Reset Timer2
F: Start A to D Conversion

Figure 9·1. HSO Command Register

directional pins which are multiplexed with HSI.2 and HSO Interrupt Status
HSI.3 respectively. Bits 4 and 6 of 110 Control Regis-
ter 1 (IOC1.4, IOC1.6) enable HSO.4 and HSO.5 as Register IOS2 at location 17H displays the HSO events
outputs. The Control Registers can be read in Window which have occurred. IOS2 is shown in Figure 9-2. The
15 to determine the programmed modes for the HSO. events displayed are HSO.O through HSO.5, Timer2
However, the IOC2.7(CAM CLEAR) bit is not latched Reset and start of an A/D conversion. IOS2 is cleared
and will read as a one. Entries can be locked in the when accessed, therefore, the register should be saved
CAM to generate periodic events or waveforms. in an image register if more than one bit is being tested.
The status register is useful in determining which
events have caused an HSO generated interrupt. Writ-
9.1 HSO Interrupts and Software ing to this regIster in Window 15 will set the status bits
Timers but not cause interrupts. In Window 15, writing to
IOS2 can set the High Speed Output lines to an initial
The IISO unit can generate two types of interrupts. The value. Refer to Section 2.2 for more information on
High Speed Output execution interrupt can be generat- Window 15.
ed (if enabled) for HSO commands which change one
or more of the six output pins. The other HSO inter-
rupt is the interrupt which can be generated by any
other HSO command, (e.g. triggering the A/D, reset-
ting Timer2 or generating a software time delay).

IOS2: 7 6 5 4 3 2 1 0
START T2
HSO.5 HSO.4 HSO.3 HSO.2 HSO.1 HSO.O
AID RESET

17H
read Indicates which HSO event occcured
START A/D: HSO_CMD 15, start A/D
T2RESET: HSO_CMD 14, Timer2 Reset
HSO.0-5: Output pins HSO.O through HSO.5

Figure 9·2. I/O Status Register 2

4-44
 80C196KB USER'S GUIDE

SOFTWARE TIMERS 9.2 HSOCAM

The HSO can be programmed to generate interrupts at A block diagram of the HSO unit is shown in Figure 9-
preset times. Up to four such "Software Timers" can be 3. The Content Addressable Memory (CAM) file is the
in operation at a time. As each preprogrammed time is center of control. One CAM register is compared with
reached, the HSO unit sets a Software Timer Flag. If the timer values every state time, taking 8 state times to
the interrupt bit in the HSO command register was set compare all CAM registers with the timers. This de-
then a Software Timer Interrupt will also be generated. fines the time resolution of the HSO to be 8 state times
The interrupt service routine can then examine I/O (1.33 microseconds at an oscillator frequency of 12
Status register 1 (IOS1) to determine which software MHz).
timer expired and caused the interrupt. When the HSO
resets Timer2 or starts an A/D conversion, it can also Each CAM register is 24 bits wide. Sixteen bits specify
be programmed to generate a software timer interrupt. the time at which the action is to be carried out, one bit
for the lock bit and 7 bits specify both the nature of the
If more than one software timer interrupt occurs in the action and whether Timer! or Timer2 is the reference.
same time frame, multiple status bits will be set. Each The format of the command to the HSO unit is shown
read or test of any bit in 10SI (see Figure 9-5) will clear in Figure 9-1. Note that bit 5 is ignored for command
bits 0 through 5. Be certain to save the byte before channels 8 through OFH.
testing it unless you are only concerned with I bit. See
also Section 11.5. To enter a command into the CAM file, write the 8-bit
"Command Tag" into location 0006H followed by the
time the action is to be carried out into word address
0004H. The typical code w~)Uld be:

LDB HSO_COMMAND,#what_to_do
ADD HSO_TIME,Timerl.#when_to_do_it

16-81T 16-81T

XTAL1/16
CONTROL
LOGIC

16

HIGH SPEED 'OUTPUT CONTROLS

6 PINS .
4 SOFTWARE TIMERS
2 INTERRUPTS
INITIATE AID CONVERSION
RESET TIMER2
270651-24

Figure 9-3_ High Speed Output Unit

4-:45
 80C196KB USER'S GUIDE

16H
HSO.O CURRENT STATE SOFTWARE TIMER a EXPIRED
HSO.l CURRENT STATE SOFTWARE TIMER 1 EXPIRED
HSO.2 CURRENT STATE SOFTWARE TIMER 2 EXPI~ED

HSO.3 CURRENT STATE SOFTWARE TIMER 3 EXPIRED

HSO.4CURRENT STATE TIMER 2 HAS OVERFLOW
HSO.5 CURRENT STATE TIMER 1 HAS OVERFLOW
CAM Q!l HOLDING REGISTER IS FULL HSI FIFO IS FULL
HSO HOLDING REGISTER IS FULL HSI HOLDING REGISTER DATA AVAILABLE
270651-25 270651-26

Figure 9·4. 1/0 Status Register 0 Figure 9·5.110 Status Register 1 (IOS1) ,

Writing the time value loads the HSO Holding Register this register in Window 15. The format for 1/0 Status
with both the time and the last written command tag. Register 0 is shown in Figure 9-4.
The command does not actually enter the CAM file
until an empty CAM register becomes available. The expiration of software timer 0 through 4, and the
overflow of Timerl and Timer2 are indicated in 10S1.
Commands in the holding register will not execute even The status bits can be set in Window 15 but not cause
if their time tag is reached. Commands must be in the interrupts .. The register is shown in Figure 9-5.
CAM to execute. Commands in the holding register
can also be overwritten. Since it can take up to 8 state Whenever the processor reads this register all of the
times for a command to move from the holding register time-related flags (bits 5 through 0) are cleared. This
to the CAM, 8 states must be allowed between succes· applies not only to explicit reads such as:
sive writes to the CAM.
LDB AL,IOSl
To provide proper synchronization, the minimum time
that should be loaded to Timerl is Timerl + 2. Small- but also to implicit reads such as:
er values may cause the Timer match to occur 65,636
counts later than expected. A similar restriction applies JBS IOSl,3,somewhere_else
if Timer2 is used.
which jumps to somewhere_else if bit 3 of lOS I is set.
Care must be taken when writing the command tag for In most cases this situation can best be handled by hav-
the HSO, because an interrupt can occur between writ- ing a byte in the register file which maintains an image
ing the command tag and loading the time value. If the of the register. Any time a hardware timer interrupt or
interrupt service routine writes to the HSO, t,he com- a HSO, software timer interrupt occurs the byte can be
mand tag used in the interrupt routine will overwrite updated:
the command tag from the main routine. One way of
avoiding this problem would be to disable interrupts ORB IOSl_image,IOSl
when writing to the HSO unit.
leaving lOS I_image containing all the flags that were
set before plus all the new flags that were read and
9.3 HSO Status cleared from 10S1. Any other routine which needs to
sample the flags can safely check lOS I_image. Note
Before writing to the HSO, it is desirable to ensure that , that if these routines need to clear the flags that they
the Holding Register is empty. If it is not, writing to the have acted Qn, then the modification of IOSI_image
HSO will overwrite the value in the Holding Register. must be done from inside a critical region.
I/O Status Register 0 (IOSO) bits 6 and 7 indicate the
status of the HSO unit. If IOSO.6 equals 0, the holding
register is empty and at least one CAM register is emp- 9.4 Clearing the HSO and Locked
ty. If IOSO.7 equals 0, the holding register is empty. Entries
The programmer should carefully decide which of these
two flags is the best to use for each application. This All 8 CAM locations of the HSO are compared before
register also shows the current status of the HSO.O any action is taken. This allows a pending external
through HSO.5. The HSO pins can be set by writing to

4-46
inter 80C196KB USER'S GUIDE

event to be cancelled by simply writing the opposite be carefully done. The user should ensure writing to
event to the CAM. However, onc.e an entry is placed in Timer! will not cause programmed HSO events to be
the CAM, it cannot be removed until e.ither the speci- missed or occur in the wrong order. rhe same precau-
fied timer matches the written value , a chip reset oc- tion applies' to Timer2.
curs or IOC2.7 is set. IOC2.7 is the CAM clear bit
which clears all entries in the CAM. The HSO'requires at least eight state times to compare
each entry in the CAM. Therefore, the fast increment
Internal events cannot be cleared by writing an oppo- mode for Timer2 cannot be used as a reference for the
site event. This includes events on HSO channels 8 HSO if transitions occur faster then once every eight
through F. The only method for clearing these events state times.
are by a reset or setting IOC2.7.
Referencing events when Timer2 is being us~d as an
up/down counter could cause events to occur m oppo-
HSO LOCKED ENTRIES site order or be missed entirely. Additionally, locked
The CAM Lock bit (HSO_Command.7) can be set to entries could possibly occur several times if Timer2 is
keep commands in the CAM, otherwise the commands oscillating around the time tag for an entry.
will clear from the CAM as soon as they cause an
event. This feature allows for generation periodic events When using Timer2 as the HSO reference, caution
based on Timer2 and must be enabled by setting must be taken that Timer2 is not reset prior to the
IOC2.6. To clear locked events from the CAM, the en- highest value for a Timer2 match in. the C~M. If t?at
tire CAM can be cleared by writing a one to the CAM match is never reached, the event will remam pendmg
clear bit IOC2. 7. A chip reset will also clear the CAM. in the CAM until the part is reset or CAM is cleared.

Locked entries are useful in applications requiring peri-

odic or repetitive events to occur. Timer2 used as an 9.6 PWM Using the HSO
HSO reference can generate periodic events with the The HSO unit can generate PWM waveforms with very
use of the HSO T2RST command. HSO events pro-
little CPU overhead using Timer2 as a reference. A
grammed with a HSO time less then the Timer2 reset PWM is generated by programming an HSO line to a
time will occur repeatedly as Timer2 resets. Recurrent high and a T2RST to occur at the same time. An HSO
software tasks can be scheduled by locking software
low time is programmed on the CAM to generate t~e
timers commands into the High Speed Output Unit. duty cycle of the PWM. A repetitive PWM waveform IS
Continuous sampling of the A/D converter can be ac-
generated by locking the commands into the CAM. Re-
compished by programming a locked HSO A/D co~­ programming of the duty cycle or PWM frequency can
version command. One of the most useful features IS
be accomplished by generating a software interrupt and
the generation of multiple PWM's on the High Speed reprogramming the HSO high, HSO low and T2RST
Output lines. Locked entries provide the ability to pro- commands.
gram periodic events while minimizing the software
overhead. Section 9.6 describes the generation of four Multiple PWMs can be programmed using Timer2 as a
PWMs using locked entries. reference and locked CAM entries. Up to four PWM's
can be generated by locking a PWM(High) and
Individual external events setting or clearing an HSO PWM(low) into the CAM for each HSO.O through
pin can by cancelled by writing the opposite event to HSO.3. Timer2 is used as a reference and set to zero by
the CAM. The HSO events do not occur until the timer programming a T2RST command at the same time an
reference has changed state. An event programmed to HSO command sets all the lines high. Two CAM en-
set and clear an HSO event at the same time will cancel tries program the four PWM (high) times by setting
each other out. Locked entries can correspondingly be
HSO.O/HSO.! and HSO.2/HSO.3 high with the same
cancelled using this method. However, the entries re- command. Four entries in the CAM set each of the
main in the HSO CAM and can quickly fill up the HSO lines low. One entry is used to reset Timer2. This
available eight locations. As an alternative, all entries in method uses a total of seven CAM entries with little or
the HSO CAM can be cleared by setting IOC2.7.
no software overhead. The PWMs can change their
duty cycle by reprogramming the CAM with different
HSO levels.
9.5 HSO Precautions
Timer! is incremented once every 8 state-times. When Changing the duty cycle for each PWM requires the
it is being used as the reference timer for an HSO com- flushing of the CAM and reprogramming of all seven
mand, the comparator has a chance to look at all. 8 entries in the CAM. The 80C196KB can flush the en-
CAM registers before Tinier! changes its value. Wnt- tire CAM by setting bit 7 in the IOC2 register (location
ing to Timer!, which is allowed in Window 15, should 16H). Each HSO(high) and HSO(low) times should be

4-47
inter 80C196KB USER'S GUIDE

reprogrammed in addition to the Timer2 reset com· er changes every eight state times during Phase!. From
mand. This method provides for up to four PWM's an external perspective the HSO pin should change just
with no software overhead except when reprogramming prior to the falling edge of CLKOUT and be stable by
the duty cycle of any particular PWM. The code to its rising edge. Information from the HSO, can be
generate these PWMs is shown in Figure 9·6. latched on the CLKOUT rising edge. Internal events
also occur when the reference timer increments. '
9.7 HSO Output Timing
Changes in the HSO lines are synchronized to either 10.0 SERIAL PC>EtT
Timerl or Timer2. All of the external HSO lines due to
change at a certain value of a timer will change just The serial port on the 80C196KB has one synchronous
after the incrementing of the timer. Internally, the tim· and 3 asynchronous modes. The asynchronous modes

$include (reg196.inc)
**********************************************************
*
·, * GENERATION OF FOUR PWM'S USING LOCKED ENTRIES *
*
·,, * Timer2 is used as a reference and is clocked
externally by T2CLK. The High Speed outputs are
*
· * *
; * used as PWMs by programming each individual *
; * PWM(low) and PWM(High) time as a locked entry. *
·, * The period of the PWM is programmed by resetting *
; * timer2 and setting all the HSO lines high at the *
; * same time. The PWMs are reprogrammed by *
·,, * clearing the HSO CAM and reloading new values
for the PWM period and duty cycle.
*
· * *
*
**********************************************************
RSEG at 60h
pwmOtiml: dsw 1
pwmltiml: dsw 1
pwm2timl: dsw 1
pwm3timl: dsw 1
PWM_period: dsw 1
temp: dsw 1
cseg at 2080h
ld sp.#OdOh initialize stack pointer
Id PWM_period.#OfOOOh intialize pwm period
ld pwmOtiml.#2000h initialize pwm 0-3 duty cycle
ld pwmltiml.#4000h
Id pwm2timl.#6000h
Id pwm3timl.#8000h
Idb ioc2.#40h Enable locked entries
Idb iocO.#Oh Enable t2clk for timer2 clock,
source
'call pwm_program program pwm's on CAM
here: sjmp here loop forever

Figure 9·6. Generating Four PWMs Using Locked Entries

4·48
 80C196KB USER'S GUIDE

pwm_program:
Idb ioc2,#OcOh flush entire cam
Idb hso_command,#Oceh program timer2 reset time
Id hso_time,PWM_period
nop delay eight state times before
nop next load
nop'
nop
Idb hso_command,#Oe6h HSO OIl high, locked, timer2 as
reference
Id hso_time,PWM_period set hso_high on t2rst
nop
nop
nop
nop
Idb hso_command,#Oe7h ; HSO 2/3 high, locked, timer2
; as referenoe
Id hso_time,PWM_period ;'set hso_high on t2rst
nop
nop
nop
nop
Idb hso_command,#OcOh set HSO.O low. locked, timer2
as reference
Id hso_time,pwmOtiml HSO.O time low
nop
nop
nop
nop
Idb hso_cbmmand,#Oclh set HSO.l low, locked, timer2
reference
Id hso_time,pwmltiml HSO.l time low
nop
nop
nop
nop
Idb hso_command,#Oc2h set HSO.2 low, 10cked,timer2
as refe,rence
Id hso_time,pwm2timl HSO.2 time low
nop
nop
nop
nop
Idb hso_command,#Oc3h set HSO.3 low, 10oked,timer2
as reference
Id hso_time,pwm3timl HSO.3 time low
ret
end

Figure 9·6. Generating Four PWMs Using Locked Entries (Continued)

4·49
 80C196KBUSER'SGUIDE

are full duplex, meaning they can transmit and receive reading it accesses SP_STAT. The upper 3 bits of
at the same time. The receiv~r is double buffered so that SP_CON must be written as Os for future compatibil-
the reception of a second byte can begin before the first ity. On the SOCI96KB the SP_STAT register contains
byte has been read. The transmitter on the SOCI96KB new bits to indicate receive Overrun Error (OE), Fram-
is also double buffered allowing continuous transmis- ing Error (FE), and Transmitter Empty (TXE). The
sions. The port is functionally compatible with the seri- bits which were also present on the S096BH are the
al port on the MCS-51 family of microcontrollers, al- Transmit Interrupt (TI) bit, the Receive Interrupt (RI)
though the software controlling the ports is different. bit, and the Received Bit. S (RBS) or Receive Parity
Error (RPE) bit. SP_STAT is read-only in Window 0
Data to and from the serial port is transferred th~ough and is shown in Figure 10-1.
SBUF(RX) and SBUF(TX), both located at 07H.
SBUF(TX) holds data ready for transmission and In all modes, the RI flag is set after the last data bit is
SBUF(RX) contains data received by the serial port. sampled, approximately in the middle of a bit time.
SBUF(TX) and SBUF(RX) can be read and can be Data is held in the receive shift register until the last
written in Window 15. data bit is received, then the data byte is loaded into
SBUF (RX). The receiver on the SOCI96KB also
Mode 0, the synchronous shift register mode, is de- checks Jor a valid stop bit. If a stop bit is not found
signed to expand I/O over a serial line. Mode I is the within the appropriate time, the Framing Error (FE)
standard S bit data asynchronous mode used for normal bit is set.
serial communications. Modes 2 and 3 are 9 bit data
asynchronous modes typically used for interprocessor Since the receiver is double-buffered, reception on a
communications. Mode 2 provides monitoring of a second data byte can begin before the first byte is read.
communication line for a I in the 9th bit position before However, if data in the shift register is loaded into
causing an interrupt. Mode 3 causes interrupts indepen- SBUF (RX) before the previous byte is read, the Over-
dant of the 9th bit value. flow Error (OE) bit is set. Regardless, the data in SBUF
(RX) will always be the latest byte received; it will nev-
er be a combination of the two bytes. The RI, FE, and
10.1 Serial Port Status and Control OE flags are cleared when SP_STAT is read. Howev-
er, RI does not have to be cleared for the serial port to
Control of the serial port is done through the Serial receive data.
Port Control (SP_CON) register shown in Figure 10-
J. Writing to location llH accesses SP....,.CON while

~-:--~-:--~-:--~T-:-8-+I-R-:-N-+-P-:-N-+--~-2-+--;-1~1 11H
TBS - Sets the ninth data bit for transmission. Cleared after each transmission. Not valid
if parity is enabled.
REN . - Enables the receiver
PEN - Enables the Parity function (even ~arity)
M2, MI - Sets the mode. ModeO = 00, Model = 01, Mode2 = 10, Mode3 = 11

7 6 5 4 3 2 1 0
RBS/ RI TI FE TXE OE X X 11H
RPE
RB8 - Set if the 9th data bit is high on reception (parity disabled)
Rf'E - Set if parity is enabled and a parity error occurred
RI - Set after the last data bit is sampled
TI - Set at the beginning of'the STOP bit transmission
FE - Set if no STOP bit is found at the end of a reception
TXE - Set if two bytes can be transmitted
OE .:..-. Set if the receiver buffer is overwritten

Figure 10-1. Serial Port ContrOl and Status Registers

4·50
inter 80C196KB USER'S GUIDE

The Transmitter Empty (TXE) bit is set if the transmit BAUD RATES
buffer is empty and ready to take up to two characters.
TXE gets cleared as soon as a byte is written to SBUF. Baud rates are generated based on either the T2CLK
Two bytes may be written consecutively to SBUF if pin or XT AL 1 pin. The values used are different than
TXE is set. One byte may be written if TI alone is set. those used for the S096BH because the 80C196KB uses
By definition, if TXE has just been set, a transmission a divide-by-2 clock instead of a divide-by-3 clock to
has completed and TI will be set. The TI bit is reset generate the internal timings. Baud rates are calculated
when the CPU reads the SP_STAT registers. using the following formulas where BAUD_REG is
the value loaded into the baud rate register:
The TBS bit is cleared after each transmission and both
TI and RI are cleared when SP_STAT reacj. The RI Asynchronous Modes 1, 2 and 3:
and TI status bits can be set by writing to SP_STAT in
window 15 but they will not cause an interrupt. Read- BAUD_REG = XTAL1 -lOR T2CLK
ing of SP_CON in Window 15 will read the last value Baud Rate * 16 Baud Rate' 8
written. Whenever the TXD pin is used for the serial
port it must be enabled by setting IOp.5 to a 1. I/O
control register 1 can be read in window 15 to deter- Synchronous Mode 0:
mine the setting.
BAUD_REG = B XT;L 1, - 1 OR T2CLK
aud ate' 2 Baud Rate
STARTING TRANSMISSIONS AND RECEPTIONS

In Mode 0, if REN = 0, writing to SBUF (TX) will The most significant bit in the baud register value is set
start a transmission. Causing a rising edge on REN, or to a one to select XT AL 1 as the source. If it is a zero
clearing RI with REN = 1, will start a reception. Set- the T2CLK pin becomes the source. The following ta-
ting REN = 0 will stop a reception in progress and ble shows some typical baud rate values.
inhibit further receptions. To avoid a partial or com-
plete undesired reception, REN must be set to zero be- BAUD RATES AND BAUD REGISTER VALUES
fore RI is cleared. This can be handled in an interrupt
environment by using software flags or in straight-line Baud XTAL 1 Frequency
code by using the Interrupt Pending register to signal Rate
8.0 MHz 10.0 MHz 12.0 MHz
the completion of a reception.
300 1666/ -0.02 2082/0.02 2499/0.00
In the asynchronous modes, writing to SBUF (TX) 1200 416/ -0.08 520/-0.03 624/0.00
starts a transmission. A falling edge on RXD will begin 2400 207/0.16 259/0.16 312/-0.16
a reception if REN is set to 1. New data placed in , 4800 103/0.16 129/0.16 155/0.16
SBUF (TX) is held and will not be transmitted until the 9600 51 /0.16 64/0.16 77 / 0.16
end of the stop bit has been sent. 19.2K 25/0.16 32/1.40 38/0.16
In all modes, the RI flag is set after the last data bit is Baud Register Value I % Error
sampled approximately in the middle of the bit time.
Also fdr all modes, the TI flag is set after the last data A maximum baud rate of 750 Kbaud is available in the
bit (either 8th or 9th) is sent, also in the middle of the asynchronous modes with 12 MHz on XTAL). The
bit time. The flags clear when SP_STAT is read, but synchronous mode has a maximum rate of 3.0 Mbaud
do not have to be clear for the port to receive or trans- with a 12 MHz clock. Location OEH is the Baud Regis-
mit. The serial port mterrupt bit is set as a logical OR ter. It is loaded sequentially in two bytes, with the low
of the RI and TI bits. Note that changing modes will byte being loaded first. This register may not be loaded
reset the Serial Port and abort any transmission or re- with zero in serial port Mode O.
ception in progress on the channel. '

4-51
inter 80C196KBUSER'S GUIDE

10.2 Serial Port Interrupts mode the TXD pin outputs a set of 8 pulses while the
RXP pin either transmits or .receivesdata. Data is
TlJe. serial port generates one of three possible inter- transferred 8 bits at a time with the LSB first. A dia-
rupts: Transmit Interrupt TI(2030H), Receive Inter- gram··of the relative timing.of these signals is shown in
rupt RI(2032H) and SERIAL(200CH). When the RI Figure 10-2. Note that this is the only. mode which uses
bit gets set an interrupt is generated through either RXD as an output.
200CH or 2032H depending on which interrupt is en-
abled. INT_MASK 1.1 controls the serial port receive
interrupt through location 2032H and INT_MASK.6 Mode 0 Timings
controls serial port interrupts through location 200CH. In Mode 0, the TXD pin sends but a clock train, while
The 8096BH shared the TI and RI interrupts on the the RXD pin transmits or receives the data. Figure 10-
SERIAL interrupt vector. On the 80C196KB, these in- 2 shows the waveforms and timing.
terrupts share both the serial interrupt vector and have
their own interrupt vectors. In this mode the serial port expands the I/O capability
of the 80C196KB by simply adding shift registers. A
When the TI bit is set it can cause an interrupt through schematic of a typical circuit is shown in Figure 10-3.
the vectors at locations 200CH or 2030. Interrupt This circuit inverts the data coming in, so it must be
through location 2030 is determined by INT_ reinverted in software.
MASK 1.0. Interrupts through the serial interrupt is
controlled by the same bit as the RI interrupt(INT_
MASK.6). The user should not mask off the serial port MODE 1
interrupt when using the double-buffered feature of the
transmitter, .as it could cause a missed count in the Mode 1 is the standard asynchronous communications
number of bytes being transmitted. mode. The data frame used in this mode is shown in
Figure 10-4. It consists of 10 bits; a start bit (0), 8 data
bits (LSB first), and a stop bit (l). If parity is enabled
10.3 Serial Port Modes by setting SPCON.2, an even parity bit is sent instead
of the 8th data bit and parity is checked on reception.
MODE 0
Mode 0 is a synchronous mode which is commonly
used for shift register based I/O expansion. In this

RXD(OUT) -,..( DO I 01 I 02 I 03 I D4' I 05 I D6 I 07 t--

DO 01 02 03 D4 05 D6 07
RXD(IN)

EXPANDED:

RXO(OUT) ----{=JDO~==x::rl-: __......:D:.;1~ ___ x:: 02

DO 01
RXO(IN) ~r-1---IDI--....,f:rr-:--
270651-28

Figure 10-2. Mode 0 Timing

4-52
inter 80C196KB USER'S GUIDE

CLOCK 1NHI8IT

..-------=-----4 PX.X
DATA
~_""'-"""-----4 RXD

CLOCK
1.----+----.....-..;...--1 TXD
INPUTS
OUTPUTS .80C196KB
SERIAL IN A

ENABLE
a>-----I PX.X

270651-29

Figure 10-3. Typical Shift Register Circuit

·.STOP

270651-30

STOP

PROGRAMMABLE 9TH BIT - - _....

It·BIT FRAME
270651-31

Figure 10-4. Serial Port Frames, Mode 1,2, and 3

The transmit and receive functions are controlled by port will holt! off transmission until the stop bit is com-
separate shift clocks. The transmit shift clock starts plete. RI is set when 8 data bits are received, not when
when the baud rate generator is initialized, the receive the stop bit is received. Note that when the serial port
shift clock is reset when a 'I to 0' transition (start bit) is status register is read both TI and RI are cleared.
received. The transmit clock may therefore not be in
sync with the receive clock, although they will both be Caution should be. used when using the serial port to
at the same frequency. connect more than two devices in half-duplex, (i.e. one
wire for transmit and receive). If the receiving proces-
The TI (Transmit Interrupt) and RI (Receive Inter· sor does not wait for one bit time after RI is set before
rupt) flags are set to indicate when operations are' com· starting to transmit, the stop bit on the link could be
plete. TI,is set when the last data bit of the message has corrupted. This could cause a problem for other devices
been sent, not when the stop bit is sent. If an attempt to listening on the link. .
send another byte is made before the stop bit is sent the

4·53
inter 80C196KB USER'S GUIDE

MODE 2 bit is set. Two types of frames are used: address frames
which have the 9th bit set and data frames which have
Mode 2 is the asynchronous 9th bit recognition mode. the 9th bit cleared. When the master processor wants to
This mode is commonly used with Mode 3 for multi- transmit a block of data to one of several slaves, it first
processor communications. Figure 10-4 shows the data sends out an address frame which identifies the target
frame used in this mode. It consists of a start bit (0), 9 slave. Slaves in Mode 2 will not be interrupted by a data
data bits (LSB first), and a stop bit (I). When transmit- frame, but an address frame will interrupt all slaves.
ting, the 9th bit can be set to a one by setting the TB8 Each slave can examine, the received byte and see if it is
bit in the control register before writing to SBUF (TX). being addressed. The addressed slave switches to Mode
The TB8 bit is cleared on every transmission, so it must 3 to receive the coming data frames, while the slaves
be set prior to writing to SBUF (TX). During recep- that were not addressed stay in Mode 2 continue exe-
tion, the serial port interrupt and the Receive Interrupt cuting.
will not occur unless the 9th bit being received is set.
This provides an easy way to have selective reception
on a data link. Parity cannot be enabled in this Il'\ode. 11;0 AID CONVERTER
Analog Inputs to the 80CI96KB System are handled
MODE 3 by the AID converter System. As shown in Figure
11-4, the converter system has an 8 channel multiplex-
Mode 3 is the asynchronous 9th bit mode. The data er, a sample-and-hold, and a 10 bit successive approxi-
frame for this mode is identical to that of Mode 2. The mation AID converter. Conversions can be performed
transmission differences between Mode 3 and Mode 2 on one of eight channels, the inputs of which share pins
are that parity can be enabled (PEN = I) and cause the with port O. A conversion can be done in as little as 91
9th data bit to take the even parity value. The TB8 bit state t.irites.
can still be used if parity is not enabled (PEN = 0).
When in Mode 3, a reception always causes an inter- Conversions are started by loading the AD_COM-
rupt, regardless of the state of the 9th bit. The 9th bit is MAND register at location 02H with the channel num-
stored if PEN = 0 and can be read in bit RB8. If ber. The conversion can be started immediately by set-
PEN = I then RBS becomes the Receive Parity Error ting the GO bit to a one. If it is cleared the conversion
(RPE) flag. will start when the HSO unit triggers it. The AID com-
mand register must be written to for each conversion,
Mode 2 and 3 Timings even if the HSO is used as the trigger. The result of
the conversion is read in the AD_RESULT(High)
Modes 2 and 3 operate in a manner similar to that of and AD_RESULT(Low) registers. The AD_RE-
Mode 1. The only difference is that 'the data is now SULT(High) contains the most significant eight bits of
made up of 9 bits, so II-bit packages are transmitted the conversion. The AD_RESULT(Low) register con-
and received. This means that 1'1 and RI,will be set on tains the remaining two bits and the AID channel num-
the 9th data bit rather than the 8th. T.he 9th bit' can be ber and AID status. The format for the AD_COM-
used for parity or multiple processor communications. MAND register is shown in Figure 11-1. In Window
15, reading the AD_COMMAND register will read
the last command written. Writing to the AD_RE-
10.4 Multiprocessor Communications SULT register will write a value into the result register.

Mode 2 and 3 are provided for multiprocessor commu-

nications. In Mode 2 if the received 9th data bit is zero, 02H
the RI bit is not set and will not cause an interrupt. In
Mode 3, the RI bit is set and always causes an interrupt
regardless of the value in the 9th bit. The way to use
this feature in multiprocessor systems is described be-
low.
ml:
1
CHANNEL # SELE,CTS WHICH OF THE 8 .
ANALOG INPUT CHANNELS IS TO BE
CONVERTED TO DIGITAL FORM. '

GO INDICATES WHEN THE CONVERSION IS TO

The master processor is set to Mode 3 so it always gets BE INITIATED (GO = 1 MEANS START NOW,
GO = 0 MEANS THE CONVERSION IS TO BE
interrupts from serial receptions. The slaves are set in INITIATED BY THE HSO UNIT AT A SPECIFIED TIME).
Mode 2 so they only have receive interrupts if the 9th 270651-33

Figure 11·1. AID Command Register

4~54
inter 80C196KB USER'S GUIDE

The AID converter can cause an interrupt through the started. The upper byte of the result register contains
vector at location 2002H when 'it completes a conver- the most significant 8 bits of the conversion. The lower
sion. It is also possible to use a polling method by b~te format is shown in Figure 11-2.
checking the Status (S) bit in the lower byte of the
AD_RESULT register, also at location 02H. The At high crystal frequencies, more time is needed to al-
status bit will be a 1 while a conversion is in progress. It low the comparator to settle. For this reason IOC2.4 is
takes 8 state times to set this bit after a conversion is provided to adjust the speed of the AID conversion by
disablinglenabling a clock prescaler.

A summary of the conversion time for the two options

is shown below. The numbers represent the number of
state times required for conversion, e.g., 91 states is
A/D CHANNEL NUMBER 22.7 /ks with, an 8 MHz XTALl (providing a 250 ns
state time.)
STATUS:
0= A/D CURRENTLY IDLE
X
=
1 CONVERSION IN PROCESS Clock Prescaler On Clock Prescaler Off
IOC2.4 = 0 IOC2.4 = 1
5 ,X
158 States 91 States
6 } A/D RESULT: 26.33 /ks @ 12 MHz 22.75 /ks @ 8 MHz.
LEAST SIGN I,ICANT 2 BITS
7 Figure 11-3. AID Conversion Times
270651-32

Figure 11-2. AID Result Lo Register

'vREF

8 TO 1 SAMPLE
ANALOG AND
MULTIPLEXER HOLD

CHANNEL

START
CONVE~SION
HSO COMMAND "F"
270651-34

Figure 11-4. AID Conve~ter Block Diagram

4-55
 ; :,
80C196KB USER'S GUIDE \,' :

11.1 AID Conversion Process The total number of state times required for a 'conver-
sion is determil'led,by the setting of IOC2.4' clock pre-
The conversion process is initiated by the execution of scaler bit. With the bit set the conversion time is 91
HSO command OFH, or by writing a one to the GO Bit states and 158 states when'the bit is cleared.
in'the AID Control Register. Either activity causes a
start conversion signal to be sent to the 'AID converter
control logic. If an HSO Command was used, the con- 11.2 AID Interface Suggestions
version process will begin when Timer! 'increments. (
This aids applications attempting to approach spectral- The external interface circuitry to an analog input is
ly pure -sampling, since successive samples spaced by highly dependent upon the application, and can impact
equal Timerl' delays will occur with a variance of about converter characteristics. In the external circuit's de-
±50 ns (assuming a stable clock on XTALI). Howev- sign, important factors such as input pin leakage, sam-
er, conversions initiated by writing a one to the AD- ple capacitor size and multiplexer series resistance from
CON register GO Bit will start within three state times the input pin to the sample capacitor must bel consid-
after the instruction has completed, execution resulting ered.
in a variance of about 0.50 p.s (XTALI = 12 MHz).
For the 80C196KB, these factors are idealized in Fig-
Once the A/D unit receives a start conversion signal, ure 11-5. The external input circuit mllst be able to
there is a one state time delay before sampling (Sample charge a sample capacitor (Cs) t.hrough a ,series resist-
Delay) while the successive approximation register is ance (RI) to an accurate voltage -given a D.C. leakage
reset and tlte proper multiplexer channel is selected. (IL)' On the 80C196KB; Cs is around 2 pF, RI is
After the sample delay, the mUltiplexer output is con- around 5 Kn. and IL is specmed as 3 p.A maximum. In
nected to the sample capacitor and remains connected determining the necessary source impedance Rs, the
for 8 state times in fast mode or 15 state times for slow value of VBIAS is not ,important.
mode (Sample Time). After this 8/15 state time "sam-
ple window" closes, the input to the sample capacitor is

~~
disconnected from the multiplexer so that changes on
the input pin will not alter the stored charge while the
conversion is in progress. The comparator is then auto-
zeroed and the conversion begins. The sample delay
and sample time uncertainties are each approximately
± 50 ns, independent of clock speed.
VB1A!i.
To perform the actual analog-to-digital conversion the
80CI96KB implements a successive approximation al- 270651-35
gorithm. The converter hardware consists of a 256-re-
sistor ladder, a comparator, coupling capacitors and a Figure 11 ~5. Idealized AID Sampling Circuitry
lO-bit successive approximation register (SAR) with
logic that guides the process. The resistor ladder pro- External circuits with source impedances of I Kn. or
vides 20 mV steps (VREF = 5.12V), while capacitive Jess will be able to maintaln an input voltage within a
coupling creates 5 m V steps within the 20 m V ladder tolerance of about ±0.61 LSB (1.0 Kn. X 3.0 p.A=
voltages. Therefore, 1024 internal reference voltages are 3.0 mY) given the D.C. leakage. Source impedances
available for comparison' against the analog input to above 2 Kn. can result in an external error 'of at least
generate a lO-bit conversion result. one LSB due, to the voltage drop caused by the 3 p.A
leakagll. I.!l addition, source impedances above 25 Kn.
A successive approximation conv~i!>n is performed by may degrade converter accuracy, as a result of the inter-
comparing a sequence of reference voltages, to the ana- nal'sample capacitor not being-fully charged during the
log input, in a binary search for the reference 'Voltage I p.s (12 MHz clock) sample window.,
that most clo.sely matches the input. The 'I. full scale
reference voltage is the rtrst tested. This corresponds to If large source impedances degrade converter accUracy
a 1O.bit 'result where the most signmcant bit is zero, because the sample capacitor'is not charged during the
and all other bits are one~ (Oll1.l1ll.11b). If the ana- sample time, an external capacitor connected to the pin
log input was'less than the test voltage, bit 10 of the compensates for this. Since the sample capacitor is
SAR is left it zero, and a new test v<i\tage, of 1/4 full scal~ 2 pF, a 0;005, p.F ~pacitor (2048* 2 pF) will charge
(00 I I.l111.11 b) is tried. If this test voltage was lower the sample capacitor ~ an a~urate input voltage of
than the analog input, bit 9 of the SAR is set and bit 8 ±O.5 LSB. An external capacitor does not compensate
is cleared for the Jilext test (010 1.1111.11 b). This binary for the voltage drop across the 'source resistance, but
search continues until 10 tests have occurred, at which charges the sample, capacitor fully during the sample
time the valid IO-bit conversion result resides in the time.' "
SAR where it ~an be read by software.

4-56
 80C196KB USER'S GUIDE

,Placing an external capacitor on each analog input will ANGND must be connected even if the AID converter
- also reduce the sensitivity to noise, as the capacitor is not being used. Remember that Port 0 receives its
combines with series resistance in the external circuit to power from the VREF and ANGND pins even when it
form a low-pass filter, In practice, one should include a is used as digital 1/0.
small series resistance prior to the external capacitor on
the analog input pin and choose the largest capacitor
value practical, given the frequency of the signal being 11.3 The AID Transfer Function
converted, This provides a low-pass filter on the input,
while the resistor will also limit input current during The conversion result is a to-bit ratiometric representa-
over-voltage conditions. tion of the input voltage, so the numerical value ob-
tained from the conversion will be:
Figure 11-6 shows a simple analog interface, circUit
based upon the discussion above. The circuit in the fig- INT [1023 x (VIN - ANGND)/(VREF - ANGND)l.
ure also provides limited protection against over-volt-
age conditions on the analog input. Should the input This produces a stair-stepped transfer function when
voltage inappropriately drop significantly below the output code is plotted versus input voltage (see Fig-
ground, diode D2 will forward bias at about 0.8 DCV. ure 11-7). The resulting digital codes can be taken as '
Since the specification of the' pin has an absolute maxi- simple ratiometric information, or they provide infor-
mum low voltage of -0.3V, this will leave about O.SV , mation about absolute voltages or relative voltage
across the 2700 resistor, or about 2 mA of current. changes on the inputs, The more demanding the appli-
This should limit the current to a safe amount. cation is on the AID converter, the more important it
is to fully understand the converter's operation, For
However, before any circuit is used in an actual applica- simple applications, kpowing the absolute error of the
tion, it should be thoroughly analyzed for applicability to converter is sufficient. However, closing a servo-loop
the specific problem at hand. with' analog inputs necessitates a detailed understand-
ing of an AID converter's operation apd errors.

The errors' inherent in an analog-to-digital conversion

VREF
process are many: quantizing error, zero offset, full-
01 scale error, differential non-linearity, and non-linearity.
These are "transfer function" errors related to the AID
FROM USER CIRCUIT."'>..:--4--"VI.f'v-...
~
.lJ ANALOG
INPUT PIN converter. In addit\on, converter temperature drift,
02 Vee rejection, sample-hold feedthrough, multiplexer
off-isolation, channel-to-channel matching and random
noise should be considered. Fqrtunately, one "Absolute
ANGNO Error" specification is available which describes the
270651-36 sum total of all deviations between the actual conver-
sion process and an ideal converter, However, the vari-
Figure 11-6. Suggested AID Input Circuit 'ous sub-components of error are important in many
applications. These error components are described in
ANALOG REFERENCES
Section I1.'S and in the text below where ideal and actu-
al converters are compared.
Reference supply levels strongly influence the absolute
accuracy of the conversion. For this reason, it is recom- An unavoidable error simply results from the conver-
mended,that the ANGND pin be tied to the two Vss sion of a continuous voltage to an integer digital repre-
pillS at the power supply. Bypass capacitors should also sentation. This error is called quantizing error, and is
be used betwe~n "REF and ANGND. ANGND should always ±O.S LSB. Quantizing error is the only error
be within about a tenth of a volt of Vss. VREF should seen in a perfect A/D,converter. and is obviously pres-
be well regulated and used only for the AID converter. ent in actual converters. Figure 11-7 shows the transfer
The VREF supply can be between 4.SV and 5.SV and function for an ideal 3-bit AID converter (i.e. the Ideal
needs .to be able to source around SmA. See Section 13 Characteristic). .
for the minimum hardware connections.
Note that in Figure H-7 the Ideal Characteristic pos-
Note that if only ratiometric information is desired, sesses unique qualities: it's first code transition occurs
VREF can be connected to Vee. In addition, VREF and when the input voltage is O.S LSB; it's full-scale code
transition occurs when the input voltage equals the full-

4-57
 7

FINAL CODE TRANSITION OCCURS

WHEN THE APPLIED VOLTAGE IS •
(
EQUAL TO (Vref - 1 (/2 (LSB».

."

..
ci
r::
CD
CD
0
.... 4 ....0
~ ~
0: Q ;:J!:
CD THE VOLTAGE CHANGE ID
oj>. !!!. BETWEEN ADJACENT CODE c:
Q, » TRANSITIONS (THE "CODE (J)
m
<X> '-
c .3 WIDTH") IS= 1 LSB •
:lJ
0 ene;)
..
:::r
1»-

..
I»
()
CD
::l. 2
c:
6
m
til
:::!:
()

H .
FIRST CODE TRANSITION OCCURSJ
WHEN THE APPLIED VOLTAGE IS
- EQUAL TO 1/2 LSB.
------------------

O~--J---_r------_,--------,_------_r--------r_------_.--~--_,--------,
1/2 2 .3 4 5 6 61/2 7 8

INPUT VOLTAGE (LSBs)

270651-37
 7

- --1 FULL SCALE ERROR

t
6 IDEAL
CHARACTERISTIC

5 ABSOLUTE ERROR
'TI
c"
c:
~ ACTUAL
CD CHARACTERISTIC
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270651-38
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INPUT VOLTAGE (LSBs) 270651-39

 80C196KB USER'S GUIDE

scale 'reference minus L5 LSB; and it's code widths are Undesired signals come from three main sources, First,
all exactly one LSR Th~se' qualities result in a digitiza- noise on V cc-Vcc Rejection, Second, input signal
tion without offset, full-scale or linearity errors, In oth- changes on the channel being converted after the sam-
er words, a perfect conversion. ple window has closed-Feed through, Third, signals
applied to' channels not selected by the multiplexer-
Figure 11-8 shows an Actual Characteristic of a hypo- Off-Isolation.
thetical 3-bit converter, which is not perfect, When the
Ideal Characteristic is overlaid with the imperfect char- Finally, multiplexer on-channel resistances differ slight-
acteristic, the actual converter is seen to exhibit errors ly from one channel to the next causing Channel-to-
in the location of the first and final code transitions and Channel Matching errors, and random noise in general
cod~ widths, The deviation of the first code transition results in Repeatability errors,
from ideal is called "zero offset", and the deviation of
the final code transition from ideal is "full-scale error".
The deviation of the code widths from ideal causes two 1'1.4 AID Glossary of Terms
types of errors. Differential Non-Linearity and Non-
Linearity. Differential Non-Linearity is a local linearity Figures 11-7, 11-8, and 11-9 display many of these
error measurement, whereas Non-Linearity is an over- terms, Refer to AP-406 'MCS-96 Analog Acquisition
all linearity error measure, Primer' for additional information on the AID terms.

Differential Non-Linearity is the degree to which actual ABSOLUTE ERROR-The maximum difference be-
code widths differ from the ideal one LSB width, It tween corresponding actual and ideal code transitions,
gives the user a measure of how' much the input voltage Absolute Error accounts for all deviations of an actual
may have changed in order to produce a one count converter from an ideal converter,
change in the conversion result, Non-Linearity is the
worst case deviation of code transitions from the corre- ACTUAL CHARACTERISTIC-The characteristic of
sponding code transitions of the Ideal Characteristic, an actual converter. The characteristic of a given con-
Non-Linearity describes how much Differential Non- verter may vary over temperature, supply voltage, and
Linearities could add up to produce an overall maxi- frequency conditions, An Actual Characteristic rarely
mum departure from a linear eharacteristic. If the Dif- has ideal first and last transition locations or ideal code
ferential Non-Linearity errors are too large, it is possi- widths, It may even vary over multiple conversion un-
ble for an AID converter to miss codes or exhibit non- der the same conditions,
monotonicity, Neither behavior is desirable in a closed-
loop system, A converter has no missed codes if there BREAK-BEFORE-MAKE-The property of a multi-
exists for each output code a unique input voltage range plexer which guarantees' that a previously selected
that produces that code only. A converter is monotonic channel will be deselected befdre a new channel is se-
if every subsequent code change represents an input lected. (e,g, the converter will not short inputs
voltage change in the same direction, ' together,)

Differential Non-Linearity and Non-Linearity are CHANNEL-TO-CHANNEL MATCHING-The dif-

quantified by measuring the Terminal Based Linearity ference between corresponding code transitions of actu-
Errors, A Terminal Based Characteristic results when al characteristics taken from different channels under
an Actual Characteristic is shifted and rotated to elimi- the same temperature, voltage and frequency condi-
nate zero offset and full-scale error (see Figure 11-9), tions.
The Tenninal Based Characteristic is similar to the Ac-
tual Characteristic that would be seen if zero offset and CHARACTERISTIC-A graph of input voltage ver-
full-scale error were externally trimmed away, In prac- sus the resultant output code for an AID converter. It
tice, this is done by using input circuits which include describes the transfer function of the AID converter,
gain and offset trimming, In addition, VREF on the
80C 196KB could also be closely regulated and trimmed CODE-The digital value output by the converter,
within the specified range to affect full-scale error,
CODE CENTER-The voltage corresponding to the
Other factors that affect a real AID Converter system midpoint between two adjacent code transitions.
include sensitivity to temperature, failure to completely
reject all unwanted signals, mUltiplexer channel dissim- CODE TRANSITION-The point at which the con-
ilarities and random noise, Fortunately these effects are verter changes from an output code of Q, to a code of
small. Q + L The input voltage corresponding to a code tran-
sition is defined to be that voltage which is equally like-
Temperature sensitivities are described by the rate at ly to produce either of two adjacent codes, '
which typiCal specifications change with a change in
temperature. CODE WIDTH-The voltage corresponding to the
difference between two adjacent code transitions,
4-61
intJ 80C196KB USER'S'GUIDE

CROSSTALK-See "Off-Isolation". REPEATABILITY-The difference between corre-

sponding code transitions from different actual charac.
D.C. INPUT LEAKAG&-Leakage current to ground teristics taken from the same converter on the same
from an analog input pin. channel at the same temperature, voltage and frequency
conditions.
DIFFERENTIAL NON-LINEARITY-The differ-
ence between the ideal and actual code widths of the RESOLUTION-The number of input voltage levels
terminal based characteristic of a converter. that the converter can unambiguously distinguish be-
tween. Also defines the number of useful bits of infor-
FEEDTHROUGH-Attenuation of a voltage a'pplied mation which the converter can return.
on the selected channel of the AID converter after the
sample window closes, SAMPLE DELAY-The delay from rect;iving the start
conversion signal to when the sample window opens.
FULL SCALE ERROR-The difference between the
expected and actual input voltage corresponding to the SAMPLE DELAY UNCERTAINTY-The variation
full scale code transition. in the Sample Delay,

IDEAL CHARACTERISTIC-A characteristic with SAMPLE TIME-The time that the sample window is
its first code transition at VIN = 0.5 LSB, its last code open.
transition at VIN (= (VREF 1.5 LSB) and all code
widths equal to one LSB. SAMPLE TIME UNCERTAINTY-The variation in
the sample time.
INPUT RESISTANCE-The effective series resistance
from the analog input pin to the sample capacitor. SAMPLE WINDOW-Begins when the sample capac-
-itor is attached to a selected channel and ends when the
LSB-LEAST SIGNIFICANT BIT: The voltage value sample capacitor is disconnected from the selected
corresponding to the full scale voltage divided by 2n , channel.
where n is the number of bits of resolution of the con-
verter. For a lO-bit converter with a reference voltage SUCCESSIVE APPROXIMATION-An AID con-
of 5.12 volts, one LSB is 5.0 mY. Note that this is version methOd which uses a binary search to arrive at
different than digital LSBs, since an uncertainty of two the best digital representation of an analog input.
LSBs, when referring to an AID converter, equals
10 mY. (This has been confused with an uncertainty of TEMPERATURE COEFFICIENTS-Change in the
two digital bits, which would mean four counts, or stated variable per degree centigrade temperature
20 mV.) . change. Temperature coefficients are added to the typi-
cal values of a specification to see the effect of tempera-
MONOTONIC-The property of successive approxi- ture drift.
mation converters which guarantees that increasing in-
put voltages produce adjacent codes of increasing value, TERMINAL BASED CHARACTERISTIC-An Ac-
and that decreasing input voltages produce adjacent tual Characteristic which has been rotated and translat-
codes of decreasing value. ed to remove zero offset and full-scale error.

NO MISSED CODES-For each and every output Vee REJECTION-Attenuation of noise on the Vee
code, there exists a unique input voltage range which line to the AID converter. .
produces that code only. ,
ZERO OFFSET-The difference between the expected
NON-LINEARITY-The maximum deviation of code and actual input voltage corresponding to the first code
transitions of the terminal based characteristic from the transition.
corresponding code transitions of the ideal characteris-
tics.

OFF-ISOLATION-Attenuation of a voltage applied

on a deselected channel of the AID converter. (Also
referred to as Crosstalk.)

4-62
intJ 80C196KB USER'S GUIDE

12.0 1/0 PORTS In addition to acting as a digital input, each line of Port
o can be selected to be the input of the A/D converter
There are five 8-bit I/O ports on the 80C196KB. Some as .discussed in Section 11. The capacitance on these
of these ports, are input only, some are output only, pins is approximately 1 pF and will instantaneously in-
some are bidirectional and some have alternate func- crease by around 2 pF when the pin is being sampled by
tions. in addition to these ports, the HSI/O unit pro- the A/D converter.
vides extra I/O lines if the timer related features of
these lines are not needed. Port 0 pins are special in that they may individually be
used as digital inputs and analog inputs at the same
Port 0 is an input port which is also used as the analog time. A Port 0 pin being used as a digital input acts as
input for the A/D converter. Port 0 is read at location the high impedance input ports just described. Howev-
OEH. Port 1 is a quasi-bidirectional port and is read or er, Port 0 pins being used as analog inputs are 'required
written to through location OFH. The three most signif- to provide current to the internal sample capacitor
icant bits of Port 1 are the control signals for .'the when a conversion begins. This means that the input
HOLD/HLDA bus port pins. Polt 2 contains three characteristics of .a pin will change if a conversion is
types of port lines: quasi-bidirectional, input and out- being done on that pin. In either case, if Port 0 is to be
put. Port2 is read or written from location IOH. The used as analog or digital I/O, it will be necessary to
ports cannot be read or written in Window 15. The provide power to this port through the VREF pin and
input and output lines are shared with other functions ANGNDpins.
in the 80C196KB as shown in Figure 12-1. Ports 3 and
4 are open-drain bidirectional ports which share their Port 0 is only sampled when the SFR is read to reduce
pins with the address/data bus. On EPROM and ROM the noise in the A/D converter. The data must be stable
parts, Port 3 and 4 are read and written through loca- one state time before the SFR is read.
tion IFFEH.

ALTERNATE CONTROL
PIN FUNC.
FUNCTION REG.
2.0 Output TXO (Serial Port Transmit) IOC1.S
2.1 Input RXO (Serial Port Receive) SPCON.3
P2.2 Input EXTINT IOC1.1
2.3. Input T2CLK (Timer2 Clock & Saud) lOCO.?
2.4 Input T2RST (Timer2 Reset) IOCO.S
2.5 Output PWM Output IOC1.0 BUS
2.6 OBO' Timer2 up/down select IOC2.1
2.? OBb' Timer2 Capture N/A
'OBO = Quasi-bidirectional,
Figure 12-1. Port 2 Multiple Functions
SAMPLE
270651-76
While discussing the characteristics of the I/O pins
some approximate current or voltage specifications will NOTE:
be given. The exact specifications are available in the '01 and 02 are ESO Protection Devices
latest version of the data sheet that corresponds to the
part being used. Figure 12·2. Input Port Structure

12.1 Input Ports 12.2 Quasi·Bidirectional Ports

Input ports and pins can only be read. There are' no Port 1 and Port 2 have quasi-bidirectional I/O pins.
output drivers on these pins. The input leakage of these When used as inputs the data on these pins must be
pins is in the microamp range. The specific values 'can stable one state time prior to reading the SFR. This
be found in the data sheet for the deyice being consid- timing is also valid for the input-only pins of Port 2 and
ered. Figure 12-2 shows the input port structure. is similar to the HSI in that the sample occurs during
,PHI or during CLKOUT low. When used as outputs,
The high impedance input pins on the 80Cl96KB have the quasi-bidirectional pins will change state shortly af-
an input leakage of a few microamps and are pre\fomi- ter CLKOUT falls. If the change waS'from '0' to a 'I'
nantly capacitive loads on the order of 10 pF.
4-63
 80C196KB USER'S GUIDE

Vee Vee Vee

, Q
FROMPORTc;>-~----------------'-----~-1t-~~
LATCH

INPUT .....::r--~X
DATA~

READ
PORT PIN u--~
270651-40
CHMOS Configuration. pFET 1 is turned on for 2 ose. periods after Q makes a O-to-1 transition. During this time, pFET 1
also turns on pFET 3 through the inverter to form a lateh which holds the 1. pFET 2 is also on.

Figure 12-3. CHMOS Quasi-Bidirectional Port Circuit

the low impedance pullup will remain on for one state turns on for two oscillator periods. P2 remains on until
time after the change. a zero is written to the pin. P3 is used as a latch, so it is
turned on whenever the pin is above the threshold value
Port I, Port 2.6 and· Port 2.7 are quasi-bidirectional (around 2 volts). '
ports. When the processor writes to the pins of a quasi-
bidirectional port it actually writes into a register which To reduce the amount of cutrent which flows when the
in turn drives the port pin. When the processor reads pin is externally pulled low, P3 is turned off when the
these ports, it senses the status of the pin directly. If a pin voltage drops below the threshold. The current re-
port pin is to be used as an input then the software quired to pull the pin from a high to a low is at its
should write a one to its associated SFR bit, this will maximum just prior to the pull-up turning off. An ex-
cause the low-impedance pull-down device to turn off ternal driver'can switch these pins easily. The maxi-
and leave the pin pulled up with a relatively high im- mum current required occurs at the threshold voltage
pedance pullup deviCe which can be easily driven down and is approximately 700 microamps.
,by the device driving the input.
When the Port 1 pins are used as their alternate func-
If some pins of a port are to be used as inputs and some tions (HOLD, HLDA, and BREQ), the pins act like a
are to be used as outputs the programmer should be standard output port.
careful when writing to the port.

Particular care should be exercised when using XOR HARDWARE CONNECTION HINTS
opcodes or any opcode which is a read-modify-write
When using the quasi-bidirectional ports as inputs tied
instruction. It is possible for a Quasi-Bidirectional Pin to switches, series resistors may be needed if the ports
to be written as a one, but read back as a zero if an
will be written to internally after the part is initialized.
external device (i.e., a transistor base) is pulling the pin
The amount of current sourced to ground from each
below VIH. pin is typically 7 rnA or more. Therefore, if all 8 pins
are tied to ground, 56 rnA will be sourced. This is
Quasi-bidirectional pins can be used as input and out- equivalent to instantaneously doubling the power used
put pins without the need for a data di,rection register.
by the chip and may cause noise in some applications.
They output a strong low value and a weak high value.
The weak high value can be externally pulled low pro-
This potential problem can be solved in hardware or
viding an input function. Figure 12-3 shows the config-
software. In software, never write a zero to a pin being
uration of a CHMOS quasi-bidirectional port. '- usee! as an input.
Outputting a 0 on a quasi-bidirectional. pin turns on the In hardware, a LK resistor in series with each pin will
strong pull-down and turns off all of th,e pull-ups.
limit current to a reasonable value without impeding
When a 1 is output the pull-down is turned off and 3 the ability to override the high impedance p).llll,lp. If all
pull-ups (strong-PI, weak-P3, very weak-P2) are turned
8 pins are tied together a 1200 resistor would be rea-
on. Each time, a, pin switches from 0 to 1 transistor PI
sonable. The problem is not quite as severe when the

4-64
infef 80C196KB USER'S GUIDE

inputs are tied to electronic devices instead of switches, the voltage present on the port pin. The second case can
as most external pulldowns will not hold 20 rnA to 0.0 be taken care of in the software fairly easily:
volts.
LDB AL, IOPORTl
Writing to a Quasi-Bidirectional Port with electronic XORB AL, #OlOB
devices attached to' the pins requires special attention. ORB AL, #OOlB
Consider using P1.0 as an input and trying to toggle STB AL, IOPORTl
P 1.1 as an output:
A software solution to both cases is to keep a byte in
ORB IOPORT1, #OOOOOOOlB Set PLO RAM as an image of the data to be output to the port;
for input any time the software wants to modify the data on the
XORB IOPORT1, #OOOOOOlOB Complement port it can then modify the image byte and copy it to
Pl.l the port.

The first instruction will work as expected but two If a switch is used on a long line connected to a quasi-
problems can occur when the second instruction exe- bidirectional pin, a pullup resistor is recommended to
cutes. The first is that even though P 1.1 is being driven reduce the possibility of noise glitches and to decrease
high by the 80C 196KB it is possible that it is being held the rise time of the line. On extremely long lines that
low externally. This typically happens when the port are handling slow signals, a capacitor may be helpful in
pin drives the base of an NPN transistor which in turn addition to the resistor to reduce noise.
drives whatever there is in the outside world which
needs to be toggled. The base of the transistor will
clamp the port pin to the transistor's Vbe above 12.3 Output Ports
ground, typically 0.7V. The 80C196KB will input this
value asa zero even if a one has been written to the port Output pins include the bus control lines, the HSO
pin. When this happens the XORB instruction will al- lines, and some of Port 2. These pins can only be used
ways write a one to the port pin's SFR and the pin will as outputs as there are no input buffers connected to
not toggle. them. The output pins are output before the rising edge
of PHI and is valid some time during PHI. Externally,
The second problem, which is related to the first, is that PHI corresponds to CLKOUT low. It is not possible to
if P1.0 happens to be driven to a zero when Port 1 is use immediate logical instructions such as XOR to tog-
read by the XORB instruction, then the XORB will gle these pins.
write a zero to P1.0 and it will no longer be useable as
an input. The control outputs and HSO pins have output buffers
with the same output characteristics as those of the bus
The first situation can best be solved by the external pins. Included in the category of control outputs are:
driver design. A series resistor between the port pin and TXD, RXD (in Mode 0), PWM, CLKOUT, ALE~
the base of the transistor often works by bringing up BHE, RD, and WR. The bus pins have 3 states: output
high, output low, and high impedance. Figure 12-4
shows the internal configuration of an output pin.

BUS o Q

LATCH

IE
ALT. - - - 4 - - - - - 1
FUNCT.

BUS PORT FCN SELECT RESET

270651-77

Figure 12·4. Output Port

4-65
 /ilOC196KB USER'S GUIDE

12;4 Ports 3 and 4/ADO-15 be used as inputs. Reading Port 3 and 4 from a previ-
ously written zero condition is as follows ...
These pins have two functions. They are either bidirec-
tional ports with open-drain outputs or System Bus LD intregA, #OFFFFH setup port
pins which the memory controller uses when it is ac- change mode
cessing off-chip memory. If the EA line is low, the pins pattern
always act as the System Bus. Otherwise they act as bus
pins only during a memory access. If these pins are ST intregA, lFFEH register -+
being used ·as ports and bus pins, ones must be written ., Port 3' and 4
to them prior to bus operations. LD II: ST not
needed if
Accessing Port 3 and 4 as I/O is easily done from inter- previously
nal registers. Since the LD and ST instructions require written as ones
the use of internal registers, it may be necessary to first
move the port information .into an internal location be- LD intr,egB, lFFEH register +-
fore utilizing the data. If the data is already internal, ,Port 3 and 4
the LD is unnecessary. For instance, to write a word
value to Port 3 and 4 ... Note that while the format of the LD and ST instruc-
tions are sirrtilar, the source and destination directions
LD intreg, portdata ,register +- change.
data
not needed if When acting as the system bus the pins have strong
already drivers to both Vee and V ss. These drivers are used
internal whenever data is being output on the system bus.and
are not used when data is being output by Ports 3 and
ST intreg, IFFEH register -+ 4. The pins, external input buffers and pulldowns are
Port 3 and 4 shared between the bus and the ports. The ports use
different output buffers which are configured as open-
To read Port 3 and 4 requires that "ones" be written to drain, and require external pull up resistors. (open-drain
the port registers to first setup the input port configura- is the MOS version of open-collector.) The port pins
tion circuit. Note that the ports are reset to this input and their system bus functions are shown in Figure
condition, but if zeroes have been written to the port, 12-5.
then ones must be re-written to any pins which are to

BUS D Q
P3/4
LATCH

IE
ADDR~__~______~
DATA

PIN--+--+--+-+---__I-CI<
PORT BUS SAMPLE RESET
BUS PORT FCN SELECT
270651-41

Figure 12-5. Port 3, 4/ADO-15 Pins

inter 80C196KB USER'S GUIDE

Ports 3 and 4 on the 80CI96KB are open drain ports. follow good design and board layout techniques to keep
There is no pullup when these pins are used as I/O noise to a minimum. Liberal use of decoupling caps,
ports. A diagram of the output buffers connected to Vee and ground planes, and transient absorbers can all
Ports 3 and 4 and the bus pins is shown in Figure 12-5. be of great help. It is much easier to design a board
with these features then to search for random noise on
When Ports 3 and 4 are to be used as inputs, or as bus a poorly designed PC board. For more information on
pins, they must first be written with a 'I'. This will put noise, refer to Applications Note AP-125, 'Designing
the ports in a high impedance mode. When they are Microcontroller Systems for Noisy Environments' in
used as outputs, a pullup resistor must be used external- the Embedded Control Application Handbook.
ly. A 15K pullup resistor will source a maximum of
0.33 milliamps, so it would be a reasonable value to
choose if no other circuits with pullups were connected 13.3 Oscillator arid Internal Timings
to the pin.
ON-CHIP OSCILLATOR
Ports 3 and 4, are addressed as off-chip memory-
m;:tpped I/O. The port pins will change state shortly The on-chip oscillator circuitry for the 80C196KB, as
after the falling edge ofCLKOUT. When these pins are shown in Figure 13.1, consists of a crystal-controlled,
used as Ports 3 and 4 they are open drains, their struc- positive reactance oscillator. In this application, the
ture is different when they are used as part of the bus. crystal is operated in its fundamental response mode as
an inductive reactance in parallel resonance with capac-
Port 3 and 4 can be reconstructed as I/O ports from the itance external to the crystal.
Address/Data bus. Refer to Section 15.7 for details. I

13.0 MINIMUM HARDWARE Vee

CONSIDERATIONS ,----------1--+ To internal
circuitry

The 80C 196KB requires several external connections to

opera,te ,correctly. Power and ground must be connect- Rf
ed, al clock source must be generated, and a reset circuit
must be present. We will look at each of these areas in XTAL1
detail.

13.1. Power Supply

Power to the 80C196KB flows'through 5 pins. Vee
supplies the positive voltage to the digital portion of the
chip while VREF supplies the A/D converter and PortO Vss
with a positive voltage. These two pins need to be con- 270651-42
nected to a 5 volt power supply. When using the A/D
converter, it is desirable to connect VREF to a separate Figure 13-1. On-Chip Oscillator Circuitry
power supply, or at least a separate trace to minimize
the noise in the A/D converter. The feedback resistor, Rf, consists of paralleled n-chan-
nel and p-channel FETs controlled by the PD (power-
The four common return pins, VSSl, VSS2, Vss3, and down) bit. R,f acts as an open when in Powerdown
Angd, must all be nominally at 0 volts. Even if the Mode. Both XTALl and XTAL2 also have ESD pro-
A/D converter is not being used, VREF and Angd must tection on the pins Which is not shown in the figure.
still be connected for PortO to function.
The crystal specifications and capacitance values in
Figure 13-2 are not critical. 20 pF is adequate for any
13.2 Noise Protection Tips frequency above I MHz with good quality ,crystals. Ce-
ramic resonators can be used instead of a crystal in cost
Due to the fast rise and fall times of high speed CMOS sensitive applications. For ceramic resonators, the man,-
logic, noise glitches on the power supply lines and out- ufacturer .should be contacted for values of the capaci-
puts at the chip are not uncommon. The 80C196KB is tors.
no exception to this rule. So it is extremely important to

4-67
intJ 80Ct96KB USER'S GUIDE

INTERNAL TIMINGS

TO INTERNAL Internal operation of the chip is based on the oscillator

CIRCUITS
Rf frequency divided by two, giving the basic time unit,
known as a 'state time'. With a 12 Mhz crystal, a state
time is 167 nS. Since the 80CI96KB can operate at
many frequencies, the times given throughout this over-
XTALI XTAL2 view will be in state times.
QUARTZ CRYSTAL
OR CERAMIC
---1=:::t.--1DI----J
Two non-overlapping internal phases are created by the
RESONATOR 20~PF clock generator: phase 1 and phase 2 as shown in Fig-
ure 13-4. CLKOUT is generated by the rising edge of
phase I and phase 2. This is not the same as the
8096BH, which uses a three phase clock. Changing
270651-43 from a three phase clock to a two phase one speeds up
operation for a set oscillator frequency. Consult the lat-
Figure 13-2. External Crystal Connections est data sheet for AC timing specifications.

To driv~ the 80CI96KB with an external clock source,

apply the external clock signal to XTALl and let
XTAL2 float. An example of this circuit is shown in PHASE1~
Figure 13-3. The required voltage levels on XTALl are
specified in the data sheet. The signal on XTALl must
be clean with good solid levels. PHASE2~
" ,

It is important that the minimum high and low times ,

are met to avoid having the XTAL I pin in the tran- CLKOUT~
sition range for long periods of time. The longer the 270651-44
signal is in the transition region, the higher the proba-
bility that an external noise glitch could be seen by the Figure 13-4. Internal Clock Phases
clock generator circuitry. Noise glitches on the
,80C196KB internal c10ckilines will cause unreliable op-
eration. 13.4 Reset and Reset Status
Reset starts the 80CI96KB off in a known state. To
DIVIOER CIRCUITRY reset the chip, the RESET pin must be held low for at
least four state times after the power supply is within
tolerance and the oscillator has stabilized. As soon as
Vce
the RESET pin is pulled low, the I/O and control pins
are asynchronously driven to their reset condition.

After, the RESET pin is brought high, a ten state reset

sequence occurs as shown in Figure 13-5. During this
time the CCB (Chip Configuration Byte) is read from
location 2018H and stored in the CCR (Chip Configu-
-----------
Vee
----------- ------- ration Register). The EA (External Access) pin quali-
fies whether the CCB is read from external or internal
XTAL1 XTAL2
memory. Figure 13-6 'gives the reset status of all the
5K FLOAT pins and Special Function Registers.

270651-78

Figure 13-3. External Clock Drive

4·68
 l
8OC196KB Reset Sequence
RESET
PIN /.l1l
CASE I.
"II PHI 00
C)
~
...r::
....CD
CASE II.
o...
PHI ~
Cf
~
?'
::D INTERNAL
RESET I
\.
;\_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
"c:
m

-
Q) CD UJ
<D- III
CD
0+-- ----, m
eCDn
.D
ALE /117 'I n~ ___ ::D
cii
C)
r::
S
CD
:I
n
CD
~ 1- .r C
m.
COli FIG. > 2081H
D~~! ( 2018H >---C) ( 2080H >--CJ( OR >---C)
PHASES AND RESET BYTE 2082H
SYNCHRONISED
270651-45
 80C196KB USER'S GUIDE

WATCHDOG TIMER RST INSTRUCTION

There are three ways in which the 80Cl96KB can reset Executing II RST instruction will also reset the
itself. The watchdog timer will reset the 80C 196KB if it 80C196KB. The opcode for the RST instruction is
is not cleared in 64K state times. The watchdog timer is OFFH. By putting pullups on the Addr/data bus, unim-
enabled the first time it is cleared. To clear the watch- plemented areas of memory will read OFFH and cause
dog, write a 'IE' followed immediately by an 'EI' to the 80Cl96KB to be reset.
location OAH. Once enabled, the watchdog can only be
disabled by a reset. .
,-

Pin Multiplexed Value of the Register Name Value

Name Port Pins Pin on Reset AD_RESULT 7FFOH
RESET Mid-sized Pullup
HSI_STATUS xOxOxOx08
ALE Weak Pull up
S8UF(RX) OOH
RD Weak Pullup
INT_MASK 000000008
8HE Weak Pullup
INT_PENDING 000000008
WR \ Weak Pullup
TIMER1 OOOOH
INST Weak Pullup
TIMER2 OOOOH
EA Undefined Input • IOPORT1 111111118
READY Undefined Input • IOPORT2 110000018
NMI Undefined Input • SP_STAT ISP_CON 000010118
8USWIDTH Undefined Input • IMASK1 000000008
CLKOUT Phase 2 of Clock
IPEND1 000000008
System 8us P3.0-P4.7 Weak Pullups
WSR XXXXOOO08
ACHO-7 PO.0-PO.7 Undefined Input • HSI_MODE 111111118
PORT1 P1.0-P1.7 Weak Pullups
IOG2 XOOOOOO08
TXD P2.0 Weak Pullup
lOCO 000000X08
RXD P2.1 Undefined Input •
IOC1 001000018
EXTINT P2.2 Undefined Input • PWM_CONTROL OOH
T2CLK P2.3 Undefined Input • IOPORT3 111111118
T2RST P2.4 Undefined Input •
IOPORT4 111111118
PWM P2.5 Weak Pulldown
10SO 000000008
- P2.6-P2.7 Weak Pullups
IOS1 000000008
HSI0-HSI1 Undefined Input,'
IOS2 000000008
HSI2/HS04 Undefined Input •
'These pins must be driven and not left floating.
HSI3/HS05 Undefined Input •
HSOO-HS03 Weak Pull down

Figure 13·6. Chip Reset Status

4-70
 80C196KB USER'S GUIDE

RESET CIRCUITS is only asserted for four state times. If this is done, it is
possible for the 80CI96KB to start running before oth-
The si~plest way to reset an 80CI96KB is to insert a er chips in the system are out of reset. Software must
capacitor between the RESET pin and Vss. The take this condition into account. A capacitor cannot be
80CI96KB has an internal pullup which has a value connected directly to RESET if it is to drive the reset
between 6K and 50K ohms. A 5 uF or greater capaci- pins of other chips in the circuit. The capacitor may
tor should provide sufficient reset time as long as Vcc keep the voltage on the pin from going below guaran-
rises quickly. teed VIL for circuits connected to the RESET pin. Fig-
ure 13-8 shows an example of a system reset circuit.
, Figure 13-7 shows what the RESET pin looks like in-
ternally. The RESET pin functions' as an input and as
an output to reset an entire system with a watchdog 13.5 Minimum Hardware Connections
timer overflow, or by executing a RST instruction. For
a system reset application, the reset circuit should be a Figure 13-9 shows the minimum connections needed to
one-shot with an open collector output. The reset pulse get the 80CI96KB up and running. It is important to
may have to be lengthened and buffered since RESET tie all unused inputs to Vee or V ss. If these pins are

80C196KB CHIP . RESET

RESET PIN

WATCHDOG TIMER
OVERFLOW
RESET INSTRUCTION
(OFFH)
270651-46

Figure 13-7. Reset Pin

80C196KB
OPTIONAL OTHER
CIRCUITRY
Vee RESET 1-......-1 ONE-SHOT
74LS123

(1 ) ,

270651-47

NOTE:
. 1. The diode will provide a faster eycle time repetitive power-on-resets.

Figure 13'-8. System Reset Circuit

4-71
 80C196KB USER'S GUIDE

r
20pF 20pF

q,
"5V +5V

vee VREF
1 p.F
VSS1 ANGND

VSS2

VSS3
.. BUSWIDTH
+5V

READY
Vpp
RESET
5p.F .l: BUS
CONTROL

RXD ADO-AD15
EXTINT
T2CLK PO.O- PO.7
T2RST
HSI.O- HSI.3 EA
NMI

80C196KB
270651-48

NOTE:
'Must be driven high or low.
"VSS3 was formerly the CDE pin. The CDE function is no longer available. This pin must be connectd to V$s.

Figure 13·9. 80C196KB Minimum Hardware Connections

left floating, they can float to a mid voltage level and the CPU out of the Idle Mode, the CPU vectors to the
draw excessive current. Some pins such as NMI or corresponding interrupt service routine and begins exe~
EXTINT may generate spurious interrupts if left un- cuting. The CPU returns from the interrupt service
connected. routine to the next instruction following the 'IDLPD
# l' instruction that put the CPU in the Idle Mode.,

14.0 SPECIAL MODES OF In the Idle Mode, the system bus control pins (ALE,
OPERATION RD, WR, INST, and BHE), go to their inactive states.
Ports 3 and 4 will retain the value present in their data
The 80C196KB has Idle and Powerdown Modes to re- latches if being used as I/O ports. If these ports are the
duce the amount of current consumed by the chip. The ADDR/DATA bus, the pins will float.
80CI96KB also has an ONCE (ON-Circuit-Emulation)
Mode to isolate itself from the rest of the components It is important to note the Watchdog Timer continues
in the system. to run in the Idle Mode if it is enabled. So the chip
must be awakened every 64K state times to clear the
14.1 Idle Mode Watchdog or the chip will reset.

The Idle Mode is entered by executing the instruction

'IDLPD # I'. In the Idle Mode, the CPU stops execut- 14.2 Powerdown Mode
ing. The CPU clocks are frozen at logic ~tate zero, but The Powerdown Mode is entered by executing the in-
the peripheral clocks continue to be active. CLKOUT struction, 'IDLPD #2'. In the Powel-down Mode, all
continues to be active. Power consumption in the Idle internal clocks are frozen at logic state zero and the
Mode is reduced to about 40% of the active Mode. oscillator is shut off. All 232 bytes of registers and rnPst
peripherals hold their values if Vee is maintained.
The CPU exits the Idle Mode by any enabled interrupt Power is reduced to the device leakage arid}s in the qA
source or a hardware reset .. Since all of the peripherals range. The 87CI96KB (EPROM part) will consume
are running, the interrupt can be generated by the HSI, more power if the EPROM window is not covered<
HSO, A/D, serial port, etc. When an interrupt brings

4-72
 inter 80C196KB USER'S GUIDE

XTAL1

CLKOUT

PHl
,,
INTERNAL'
POWERDOWN :
i---+--;"--;~S ------;.-+--i
r-I

SIGNAL ;"1--;---i---i---i---'

Vpp :

TIMEOUT .,..:---------------'~S r-1

270651-49

Figure 14·1. Power Up and Power Down Sequence

In Powerdown, the bus control pins go to their Inactive If the external interrupt brings the chip Qut of Power-
states. All of the"output pins will assume the value in down, the corresponding bit will be set in the interrupt
their data latches. Ports 3 and 4 will continue to act as pending register. If the interrupt is unmasked, the part
ports in the .single chip mode or will float if acting as will immediately execute the interrupt service routine,
the ADDR/DATA bus. and return to the instruction following the IDLPD in-
struction that put the 'chip into Powerdown. If the in-
To pr~vent accidental entry into the Powerdown Mode, terrupt is masked, the chip will start at the instruction
this feature may be' disabled at reset by clearing bit 0 of following the IDLPD in~truction. The bit in the pend-
the CCR (Chip Configuration Register). Since the de- ing registe~ will remain set, however.
fault value of the CCR bit 0 is 1, the Powerdown Mode
is normally enabled. All peripherals should be in an inactive state before
entering Powerdown. If the AID converter is in the
The Powerdown Mode can be exited by a chip reset or middle of a conversion, it is aborted. If the chip comes
a high level on the external interrupt pin. If the RESET out of Powerdown by an external interrupt, the serial
pin is used, it must be asserted long enough for the port will continue where it left off. Make sure that the
oscillator to stabilize. serial port is done transmitting or receiving before en-
tering Powerdown. The SFRs associated with the AID
Whim exiting Powerdown with an external interrupt, a and the serial port may also contain incorrect informa-
positive level on the pin mapped to INT7 (either tion when returning from Powerdown.
EXTINT or portO.7) will bring the chip out of Power-
down Mo<Je. The interrupt does not have to be un· When the chip is in Powerdown, it is impossible for the
masked to exit Powerdown. An internal timing circuit watchdog timer to time out because its clock has
ensures that the oscillator has time to stabilize before stopped. Systems which must use the Watchdog and
turning on the internal clocks. Figure 14-1 shows the Powerdown, should clear the Watchdog right before
power down and power up sequence using an external entering Powerdown. This will keep the Watchdog
interrupt. from timing out when the oscillator is stabilizing after
leaving Powerdown.
D~ring normal operation, before entering Powerdown
Mode, the Vpp pin will rise to Vee through an internal 14.3, ONCETM and Test Modes
.' pullup. The user must connect a capacitor between Vpp
aIld Vss. A positive level on the external interrupt pin Test Modes can be entered on the 80C196KB by hold-
starts to discharge this capacitor. The internal current ing ALE, INST or RD in their active state on the rising
source that discharges the capacitor can sink approxi- edge of RESET. The only Test Mode not reserved for
mately 100 uA. When the voltage goes below about 1 use by Intel is the ONCE, or ON-Circuit-Emulation
volt on the Vpp pin, the chip begins executing code. A Mode.
1uF capacitor would take about 4 ms to discharge to 1
volt.

4-73
 80C196KB USER'S GUIDE

ONCE is entered by driving ALE high, INST low and Address Latch" Enable (ALE) provides' a strobe to
RD low on the rising edge of RESET. All pins except transparent latches (74AC373s) to demultiplex the bus.
XTALl and XTAL2 are floated. Some of the pins are To avoid confusion, the latched address signals will be
not truly high im'pedance as they have weak pullups or, called MAO-MAI5 and the data signals will be named
pulldowns. The ONCE Mode is useful in electrically MDO-MDI5.
removing the 80C 196KB from the rest of the system. A
typical application of the ONCE Mode would be to The data returned from external memory must be on'
program discrete EPROMs onboard without removing the bus and stable for a specified setlip time before the
the 80CI96KB from its socket. rising edge of RD (read). The rising edge of RD signals
the end of the sampling window. Writing to ·external
ALE, INST, and RD are weakly pulled high or low memory is controlled with the WR (write) ~ Data is
during reset. It is important that a circuit does not in- valid on MDO-MD 15 on the'rising edge of WR. At this
advertantly drive these signals during reset, or a Test time data must be latched by the external system. The
Mode could be entered by accident. 80C 196KB has ample setup and hold' times for writes.

When BHE is asserted, the memory connected to the

15.0 EXTERNAL MEMOR't high byte of the data bus is selected. When MAO is a 0,
INTERFACING the memory connected to the low byte of the data bus is
selected. In this way accesses to a 16-bit wide memory
can be to the low (even) byte only (MAO = 0, BHE= I),
15.1 Bus Operation to the high (odd) byte only (MAO = I, BHE = 0), or the
, both bytes (MAO = 0, BHE = 0).
There are several different external operating modes on
the 80C196KB. The standard bus mode uses a 16 bit When a block of memory is decod~r reads only, the
multiplexed address/data bus. Other bus modes include system does not have to decode BHE and MAO. The
an 8 bit external bus mode and a mode in which the bus 80Cl96KB will discard the byte it, does not need. For
size can be dynamically switched between 8-bits and systems that write to external memory, a system must
16-bits. In addition, there are several options available generate separate write strobes to both the high and low
on the type of bus control signals which make an exter~ byte of memory. This is discussed in more detitillater.
nal bus simple to design.
All of the external bus signals are gated by the rising
In the standard mode, external memory is addressed and falling edges of CLKOUT. A zero waitstate bus
through lines ADO-ADI5 which form a 16 bit multi- cycle consists of two CLKOUT periods. Therefore,
plexed bus. The address/data bus shares pins with ports there are 4 clock edges that generate a complete bus
3 and 4. Figure 15-1 shows an idealized timing diagram cycle. The first falling edge of CLKOUT asserts ALE
for the external bus signals. and drives an address on the bus. The rising edge of

XTAL1

CLKOUT

ALE~~ ______________________

READY

BUS WIDTH

BUS -< ADDRESS OUT ) ( OUT )}),

R~D------------~~

WRITE - - - - -......----""'\~
270651-50

Figure 15-1. Idealized Bus Timings

4-74
 80C196KB USER'S GUIDE

CLKOUT drives ALE inactive. The next falling edge Mode. Before the CCB fetch, if the program memory is
of CLKOUT asserts RD (read) and floats the bus for a external, the CPU assumes that the bus is configured as
read cycle. During a WR (write) cycle, this edge asserts an 8-bit bus. In the 8-bit bus mode, during the CCB
WR and drives valid data on the bus. On the last rising fetch, address lines 8-15 use only the weak drivers.
edge of CLKOUT, data is latched into the 80CI96KB However, in a 16-bit bus system, the external memory
for a read cycle, or data is valid for a write cycle. device will be driving the high byte of the bus while
outputting the CCB. This could cause bus contention if
location 2019H contains FFH: A value 20H in location
READY Pin 2019H will help prevent the contention.
The READY pin can insert wait states into the bus
cycle for interfacing to slow memory or peripherals. A
wait state is 2 Tosc in length. Since the bus is synchro- CHIP CONFIGURATION REGISTER
nized to CLKOUT, it can only be held for an integral """rLT¥rLT¥r'
ENABLE POWERDOWN FEATURE
number ofwaitstates. Because the 80Cl96KB is a com-
pletely static part, the number of waitstates that can be BUS WIDTH SELECT
(16 - BIT BUS /';-8-"'B"'"IT"'B"'U"'S)
inserted into a bus cycle is unbounded. Refer to the
next section for information on internally controlling WRITE STROBE MODE SELECT
(WR AND BHE/WRL AND WRH)
the number of waitstates inserted into a bus cycle.
......--ADDRESS VALID STROBE SELECT
There are several setup and hold times associated with (ALE/ ADV)
the READY signal. If these timings are not met, the (lRCO) } INTERNAL READY
part may insert the incorrect number of waitstates. '------(IRC1) CONTROL MODE

(LOCO) }PROGRAM LOCK

INST Pin
' - - - - - - - - ( L O C 1 ) MODE
The INST pin is useful for decoding more than 64K of 270651-51
addressing space. The INST pin allows both 64K of
code space and 64K of data space. For instruction Figure 15-2. Chip Configuration Register
fetches from external memory, the INST pin is assert-
ed, or high for the entire bus cycle. For data reads and READY control
writes, the INST pin is low. The INST pin is low for
the Chip Configuration Byte fetch and for interrupt To simplify ready control, four modes of internal ready
vector fetches. control are available. The modes are chosen by bits 4
and 5 of the CCR and are shown in Figure 15-3.

15.2 Chip Configuration Register Description

IRC1 IRCO
The CCR (Chip Configuration Register) is the first 0 0 Limit to one wait state
byte fetched from memory following a chip reset. The 0 1 Limit to two wait states
CCR is fetched from the CCB (Chip Configuration
Byte) at location 2018H in ,either internal or external 1 0 Limit to three wait states
memory depending on the state of the EA pin. The 1 1 Wait states not limited internally
CCR is only written once during the reset sequence. Figure 15-3. Ready Control Modes
Once loaded, the CCR cannot be changed until the next
reset. The internal ready control logic limits the nuinber of
waitstates that slow devices can insert into the bus cy-
The CCR is shown in Figure 15-2. The two most signif- cle. When the READY pin is pulled low, waitstat"s are
icant bits control the level of ROM/EPROM protec- inserted into the bus cycle until the READY pin goes
tion. ROM/EPROM protection is covered in the last high, or the number of waits tate equal the number pro-
section. The next two bits control the internal READY grammed into the CCR. So the ready control is a sim-
mode. The next three bits determine the bus control ple logical OR between the READY pin and the inter-
signals. The last bit enables or disables the Powerdown nal ready control.

4-75
 80C1961{B USER'S GUIDE

This feature gives very simple and flexible ready con- hardware. The ALE, WR,; and BHE. pins serve dual
trol. For example, every slow memory chip select line functions. Bits 2 and 3 of the CCR specify the functiqn
could be ORed together and connected to the READY performed by these control lines.
pip with Internal Ready Control programmed to insert
the desired number of waitstates into the bus cycle.
Standard Bus Control
If the READY pin is pulled low during the CCR fetch, If CCR bits 2 and 3 are Is, the standard bus control
the bus controller will automatically insert 3 waitstates signals ALE, WR, and BHE are generated as show.n in
into the CCR bus cycle. This al10ws the CCR fetch to Figure 15-4. ALE rises as the address starts to be driv-
come from slow memory without having to assert the en, and falls to externally latch the address. WR is driv-
READY pin. en for every write. BHE and MAO can be combined to
form WRL and WRH for even and odd byte writes.
Bus Control
Using the CCR, the 80Cl96KB can generate several
types of control signals designed to reduce external

ALE ALE

u u
VALID ADO-7 ~ADDR LOwl DATA OUT ~

ADO -15 ~....._A_DD_R_"'-_DA_T_A_O_U_T_......~ AD8 -15 ---.-1. .__ ~.

A_D_D_RE_S;..S_H_I_GH_ _.....
270651-52 270651-53
16-Bil Bus Cycle 8-Bil Bus Cycle

Figure 15-4. Standard Bus Control

BHE ---..-<Jr"""""l
WRITE HIGH

WRITE LOW

MAO
270651-79

Figure 15-5. Decoding WRL and WRH

4·76
inter 80C196KB USER'S GUIDE
J,,4f,',r· ... :1
,,~,' .

Figure 15·5 is an example of external circuitry to de· Address Valid Strobe Mode
code WRL and WRH.
Address Valid strobe replaces ALE if CCR bit 3 is O.
When Address valid Strobe mode is selected, ADV will
Write Strobe Mode be asserted after an external address is setup. It will
The Write Strobe Mode eliminates the need to external· stay asserted until the end of the bus cycle as shown in
ly decode for odd and even byte writes. If CCR bit 2 is Figure 15·7. ADV can be used as a simple chip select
0, and the bus is a 16·bit cycle, WRL and WRH are for external memory. ADV looks exactly like ALE for
generated in place of WR and BHE. WRL is asserted back to back bus cycles. The only difference is ADV
for all byte writes to' an even address and all word will be inactive when the external bus is idle.
writes. WItH is asserted for all byte writes to odd ad·
dresses and all word writes. The Write Strobe mode is Address Valid with Write Strobe
shown in Figure 15·6.
If CCR bits 2 and 3 are 0, the Address Valid with Write
In the eight bit mode, WRL and WRH are asserted for Strobe mode is enabled. Figure 15·8 shows the signals.,
both even and odd addresses.

ALE ALE

VALID

WRH VALID ADD -7 -1ADDR LOW I DATA OUT

~
ADO -15
~ ADDR DATA OUT
~ AD8 -15
-1 ADDRESS HIGH '~
270651-55 270651-56
16·Bil Bus Cycle 8·BII Bus Cycle

Figure 15-6. Write Strobe Mode

'--__. .'r
.
WRITE
·u
BHE VALID ADO-7 ---1ADDR LOwl DATA OUT ~

ADO -15 ---1 ADDR 'DATA OUT ~ AD8-15 ---1 ADDRESS OUT HIGH' ~
270651-57 270651-58
16·BII Bus Cycle 8·BII Bus Cycle

Figure 15-1. Address Valid Strobe Mode

4·77
inter 80C196KB USER'S GUIDE

15.3 Bus Width During 16 bit bus cycles, Ports 3 and 4 .contain the
address multiplexed with data using ALE to latch the
The SOC196KB external bus width can be run-time address. In 8-bit bus cycles, Port 3 is multiplexed with
conFigured to operate as a 16 bit multiplexed address/ address/data but Port 4 only outputs the upper & ad-
data bus, or as an MCS-51 style multiplexed 16 bit ad- dress bits. The Addresses on Port 4 are valid through-
dress/8 bit data bus. out the entire bus cycle. Figure .15-9 shows the two bus
width options.

WRITE LOW VALID WRITE

WRITE HIGH VALID ADO-7 -1 ADDR LOW I DATA OUT J---

ADO-.15 ~ ADDR 1 DATA OUT J--- AD8 -15 -1..__ A_D_D_R_ES_S_H_I_GH
__.....IJ---
270651-59 270651-60
16-BII Bus Cycle 8-Blt Bus Cycle

FigIJre 15-8. Address Valid with Write Strobe Mode

BUS CONTROL BUS CONTROL

80C196KB 80C196KB

8-BIT
PORT 4 LATCHED
ADDRESS HIGH

PORT 4
PORT 3

PORT 3

270651-61 270651-62
(a) 16-Blt Bus (b) 8-Blt Bus

Figure .15-9. Bus Width Options

4-78
intJ 80C196KB USER'S GUIDE

The external bus width can be changed every bus cycle protocol consists of three signals, HOLD, HLDA, and
if a I was loaded into bit CCR.I at reset. The bus width BREQ. HOLD is an input asserted by a device which
is changed on ,the fly by using the BUSWIDTH pin. If requests the 80CI96KB bus. Figure 15-10 shows the
the BUSWIDTH pin is a I, the bus cycle is 16-bits. For timing for HOLD/HLDA. The 80C196KB responds
an 8-bit bus cycle, the BUSWIDTH pin is a zero. The by releasing the bus and asserting HLDA. When the
BUSWIDTH is sampled by the 8OCl96KB after the device is done accessing the 8OCl96KB memory, it re-
address is on the bus. The BUSWIDTH pin has about linquishes the bus by deactivating the HOLD pin. The
the same timing as the READY pin. 8OCl96KB will remove its HDLA and assume control
of the bus. The third signal, BREQ, is asserted by the
Applications for the BUSWIDTH pin are numerous. 80CI96KB during the hold sequence when it has a
For example, a system could have code fetched from 16 pending external bus cycle. The 80CI96KB deactivates
bit memory, while data would come from ,8 bit memo- BREQ at the same time it deactivates HDLA.
ry. This saves the C,ost of using two 8 bit static RAMS if
only tlle capacity of one is needed. This system could be The HOLD, HLDA, and BREQ pins are multiplexed
easily implemented by tying the chip select input of the with Pl.7, PI.6,and PI.5, respectively. To enable
8-bit memory to the BUSWIDTH pin. HOLD, HLDA and BREQ, the HLDEN bit (WSR.7)
must be 1. HLDEN is cleared during reset. Once this
If CCR bit I is a 0, the 8OC196KB is locked into the 8 bit is set, the port I pins cannot be returned to being
bit mode and the BUSWIDTH pin is ignored. quasi-bidirectional pins until the device is reset, but can
still be read. The HOLD/HLDA feature, however, can
When executing code from a 8-bit bus, some perform- be disabled by clearing the HLDEN bit.
ance degradation is to be expected. Theprefetch queue
cannot be kept full under all conditions from an 8-bit The HOLD is sampled on phase I, or when CLKOUT
bus. Also, word reads and writes to external memory is low.
will take an extra bus cycle for the extra byte.
When the 80CI96KB acknowledges the hold re~,
the output buffers for the addr/data bus, RD, WR,
15.4 HOLD/HLDA Protocol BHE and INST are floated. Although the strong pullup
and pulldown on ALEIADV are disabled, a weak pull-
The 80CI96KB supports a bus exchange protocol, al. down is turned on. This provides the option to wire OR
lowing other, devices, to gain control of the bus. The ALE with other bus masters. The request to hold laten-
cy is dependent on the state of the bus controller.

CLKOUT

HOLD
Hold Lot.no

HLDA

BREQ
\~--------~--~;-
ADDR/DATA _ _ _ _ _ _ _ _..JX~______.;..Floe.;.;;,;;,t.d;...._ _ _ _ _ _....X

ALE ____________________,,~______________
w._a_kl~Y_D_m_.n______________ _J1'
270651-63

Figure 15·10. HOLD/HLDA Timings

4-79
 80Ct96KB USER'S GUIDE

MAXIMUM HOLD LATENCY REGAINING BUS CONTRQL

The time between HOLD being asserted and HLDA There is no delay from the time the 80C196KB re-
being driven is known as Hold Latency. After recogniz- moves HLDA to the time·it takes control of the bus.
ing HOLD, the 80CI96KB waits for any current bus After HOLD is removed, the 80CI96KB drops HLDA
cy,cle to finish, and then asserts HLDA. There are 3 in the following state and resumes control of the bus.
types bus cycles; 8-bit external cycle, 16-bit external
cycle, .and an idle bus. Accessing. on-chip BREQ is asserted when the part is in hold and needs to
ROM/EPROM is an idle bus. perform an external memory cycle. An external memo-
ry cycle can be a ¢ita access or a request from the
HOLD is an asynchronous input. There are two differ- prefetch queue for a code request. A request comes
ent system configurations for asserting HOLD. The from the queue when it contains two bytes or less. Once
80C196KB will recognize HOLD internally on the next asserted, it remains asserted until HOLD is removed.
clock edge if the system meets Thvch (HOLD valid to At the earliest, BREQ can be asserted with HLDA.
CLKOUT high). If Thvch is not met (HOLD applied
asynchronously), HOLD may be recognized one clock Hold requests do not freeze the 80C196KB when exe-
later (see Figure 15-12). Consult the latest 80C196KB cuting out of internal memory. The part continues exe-
data sheet for the Thvch specification. cuting as long as the resources it needs are located in-
ternal to the 80C196KB. As soon as the part needs to
Figure 15-12 shows the 80C196KB entering HOLD access external memory, it asse.rts BREQ and waits for
when the bus is idle. This is the minimum hold latency the HOLD to be removed. At this time, the part cannot
for both the synchronous and asynchronous cases. If respond to any interrupt requests until HOLD is re-
Thvch is met, HLDA is asserted about on the next moved.
falling edge of CLKOUT. See the data sheet for Tclhal
(CLKOUT low to HLDA low) specification. For this When executing out of external memory during a
case, the minimum 40ld latency =. Thvcl + 0.5 states HOLD, the 80C196KB keeps running until the queue
+ TclhiLl. is empty or it needs to perform an external data cycle.
The 80CI96KB cannot service any interrupts until
If HOLD is asserted asynchronously, the mlmmum HOLD is reIl).oved.
hold latency increases by one state time and = Thvcl
+ 1.5 states + Tclhal. The 80C196KB will also respond to hold requests in
the Idle Mode. The latency for entering bus hold from
Figure 15-11 summarizes the additional hold latency the Idle Mode is the same as when executing out of
added to the minimum latency for the 3 types of bus internal memory.
cycles. When accessing external memory, add one state
for each waitstate inserted into the bus cycle. For an Special consideration must be given to the bus arbiter
8-bit bus, worst case hold latency is for word reads or design if the 80C196KB can be reset while in HOLD.
writes. For this case, the bus controller must access the For example, a CPU part would try and fetch the CCR
bus twice, which increases latency by two states. from external memory after RESET is brought high.
Now there would be two parts attempting to access
For exiting Hold, the minimum hold latency times ap- 80C196KB memory. Also, if another bus l;I1aster is di-
ply for when the 80C196KB will deassert HLDA in rectiy driving ALE, RD, and INST, the ONCE mode
response to HOLD being removed. or another test mode could be entered. The simplest
solution is to make the RESET pin ofthe80C196KB a
Idle Bus Min •system reset. This way the other bus master would also
16-bit External Access Min + 1 state be reset. Examples of system reset circuits are given in
Section 13.
8-bit External Access Min + 3 states
Min ~ Thvcl + 0.5 slales + Tclhallf Thvclls mel
~ Thvcl + 1.5 states + Tclhal for asynchronous HOLD
Figure 15-11. Maximum Hold Latency

4-S0
 80C196KB USER'S GUIDE

Case 1. Meeting Thvcl

I one state time

CLKOUT

Minimum Hold Exit Latency

Latency

270651-82

Case 2. Asserting HOLD Asynchronously

CLKOUT

I-- Tclhal -Tclha h

----- Minimum Hold

Latency - - - Exit Latency--

r-
270651-83

Figure 15-12. HOLD Applied Asynchronously

DISABLING HOLD REQUESTS The safest way is to add a -lBC instruction to check the
status of the HLDA pin after the code that clears the
Clearing the HLDEN bit (WSR.7), can disable HOLD HLDEN bit. Figure 15-13 is an example of code that
requests when consecutive memory cycles are required. prevents the part from executing a new instruction until
Clearing the HDLEN bit. however. does not cause the both current HOLD requests are serviced and the hold
80C196KB to take over the bus immediately. The feature is disabled.
80C196KB waits for the current HOLD request to fin-
ish. Then it disables the bus hold feature. causing any
new requests to be ignored until the HLDEN bit is set 15.5 AC Timing Explanations
again. Since there is a delay from the time the code for
clearing this bit is fetched to the time it is actually exe- Figure 15-14 shows the timing of the ADDR/DATA
cuted. the code that clears HLDEN needs to be a few bus and control signals. Refer to the latest data sheet
instructions ahead of the block that needs to be protect- for the AC timings to make sure your system meets
ed from HOLD requests. specifications. The major timing specifications are ex-
plained in Figure 15-15.

DI disable interrupts
ANDB WSR, #OEFH disable hold request
WAIT: JBC PORT1, 6, WAIT; Check the HLDA pin
• If set, execute
• protected instructions
•
ORB WSR,#80h enable HOLD requests
EI enable interrupts
NOTE:
Interrupts should be disabled to prevent code interruption

Figure 15-13. HOLD code

4-81
inter 80C1~6KB USER'S GUIDE

XTALl

CLKOUT

ALE

BUS

BUS - { ADDRESS, OUT »« ADDRESS

~ tRHBX...
I
I
tWHBX
BHE,INST VALID

~ tRHAX ...
tWHAX
AD8-15 ADDRESS OUT

270651-80

Figure 15·14. AC Timing Diagrams

4-82
inter 80C196KB USER'S GUIDE

XTAL1

CLKOUT

ALE

READY

_-+-_______"" j . - - - - tRLRH + 2Tosc ---4...---------

tRLDV + 2Tose ~
1 + - - - - - - - - - t AVDV --------1--1
+ 2 Tose
BUS
-{, . ADDRESS OUT ) -D_f--T_A~)~»~»~»-----
_(i-_I

_-+._____-.,.._----.~f.'--- t WLWH + ZTose )

~1;:·:::::-t-QVW-H-+-2-To-s-c-~
BUS I
--<:::::AD:D:RE:SS:O:U:T ::::>X( _ _ _ _ _ _ _ _ _ _ X
~I
DATA OUT
J~ ______
ADDRESS _

270651-81

XTAL1

~ ,~:J ~~:'. )
CLKOUT

ALE

BUSWIDTH ~----------------
--:'1-'- - -tAVGV
- -~1 I
BUS
--<~--------~~~----)~---------- 270651-84

Figure 15-14. AC Timing Diagrams (Continued)

4·83
 80C196KB USER'S GUIDE

TIMINGS THE MEMORY SYSTEM MUST MEET: TCLDV - CLKOUT Low to Input Data Valid:
Maximum time the memory system has
TAVYV - ADDRESS Valid to READY Setup: to output valid data'after. the CtKOUT
Maximum time the memory system has falls.
to decode READY after ADDRESS is - RD High to Input Data Float: Time af-
output by the 80C196KB to guarantee at ter RD is inactive until the memory sys-
least one-wait state will occur. tem must flbat the bus. If this timing is
TLLYV - ALE Low to READY Setup: Maximum not met, bus contention will occur.
time the memory system has to decode - Data Hold after RD Inactive: Time after
READY after ALE falls to guarantee at RD is inactive that the memory system
least one wait state will occur. qlUst hold Data on the bus. Always 0 ns
TYLYH - READY Low to READY HIGH: on the 80C196KB.
Maximum amount of nonREADY time
or the maximum number of wait states
that can be inserted into a bus cycle. TIMINGS THE 80C196KB WILL PROVIDE:
Since the 80C196KB is a completely FXTAL
- Frequency on XTALl: Frequency ofsig-
static part, T YLYH is unbounded. nal input into the 80C196KB. The
80C196KB runs internally at 1/2 FXTAL.
TCLYX - READY Hold after CLKOUT Low:
Minimum time the level on the READY Tosc -l/FxTAL: All A.C. Timings are refer-
pin must be valid after CLKOUT falls. enced to T osc.
The minimum hold time is always 0 ns. TXHCH - XTALl High to CLKOUT High or
If maximum value is exceeded, addition- Low: Needed in systems where the sig-
al wait states will occur. nal driving XTALl is also a clock for
TLLYX - READY Hold AFTER ALE Low: external devices.
Minimum time the level on the READY TCLCL - CLKOUT Cycle Time: Nominally 2
pin must be valid after ALE falls. If Tosc·
maximum value is exceeded, additional TCHCL - CLKOUT High Period: Needed in sys-
wait states will occur. tems which use CLKOUT as clock for
ITAVGV - ADDRESS Valid to BUSWIDTH Val- external devices,
id: Maximum' time the memory system
has to decode BUSWIDTH after AD- TCLLH - CLKOUT Falling Edge to ALE/ADV
Rising: A help in deriving other timings.
DRESS is output by the 80C196KB. If
exceeded, it is not guaranteed the - ALE/ADV Falling Edge to CLKOUT
80C196KB will respond with an 8- or Rising: A help in deriving other timings.
16-bit bus cycle. - ALE Cycle Time: Time between ALE
TLLGV - ALE Low to BUSWIDTH Valid: pulses.
Maximum time after ALE/ADV falls TiHLL - ALE/ ADV High Period:' Useful in de-
until BUSWIDTH must be valid. If ex- termining ALE/ADV rising edge to
ceeded, it is not guaranteed the ADDRESS valid. External latches must
80C196KB will respond with an 8- or also meet this spec.
16-bit bus cycle.
- ADDRESS Setup to ALE/ADV Falling
T CLGX - BUSWIDTH Hold after CLKOUT Edge: Length of time ADDRESS is val-
Low: Minimum time BUSWIDTH must id before ALE/ADV falls. External
be held valid after CLKOUT falls. Al- latches must meet this spec.
ways 0 ns of the 80C I 96KB. - ADDRESS Hold after ALE/ADV Fail-
TAVDV - ADDRESS Valid to Input Data Valid: ing Edge: Length of Time ADDRESS is
Maximum time the memory system has valid after ALE/ADV falls. External
to output valid data after the 80C196KB. latches must meet this spec.
outputs a valid address.
- ALE/ADV Low to RD Low: Len~ of
TRLDV - RD Low to Input Data Valid: Maximum time after ALE/ADV falls before RD is
time the memory system has to output asserted. Could be needed to insure
valid data after the 80C 196KB asserts proper memory decoding takes place be-
RD. fore a device is enabled.

Figure 15-15. AC Timing Explanations

4-84
 80C196KB USER'S GUIDE

TRLCL - RD Low to CLKOUT Falling Edge: TWLWH - WR Low to WR High: WR pulse width.
Length of time from RD asserted to Memory devices must meet this spec.
CLKOUT falling edge: Useful for sys- TWHQX - Data Hold after WR Rising Edge:
tems based on CLKOUT. Amount of time data is valid on the bus
TRLRH - RD Low to RDHigh: RD pulse width. after WR going inactive. Memory devic-
- RD.High to ALE/ADV Asserted: Time es must meet this spec.
between RD going inactive and next TWHLH - WR Rising Edge to ALE/ADV Rising
ALE/ADV, also used to calculate time Edge: Time between WR goirig inactive
between inactive and next ADDRESS and next ALE/ADV. Also used to cal-
valid. culate WR inactive and next ADDRESS
- RD Low to ADDRESS Float: Us~d to valid.
calculate when the 80C196KB stops TWHBX - BHE, INST, Hold after WR Rising
driving ADDRESS on the bus. Edge: Minimum time these signals wiil
- ALE/ADV Low Edge to WR Low: be valid after WR inactive.
Length of time ALE/ADV falls before TRHBX - BHE, INST HOLD after RD Rising
WR is asserted. Could be needed to en- Edge: Minimum time these signals will
sure proper memory decoding takes be valid after RD inactive.
place before a device is enabled. TWHAX - ADS-IS Hold after WR Rising Edge:
TCLWL - CLKOUTFalling Edge to WR Low: Minimum time the high byte of the ad-
Time between CLKOUT going low and dress in 8-bit mode will be valid after
WR being asserted. Useful in systems WR inactive.
based on CLKOUT. TRHAX - ADS-IS Hold after RD Rising Edge:
- Data Valid to WR Rising Edge: Time Minimum time the high byte of the ad-
between data being valid on the bus and dress in 8-bit mode will be valid after
WR going inactive. Memory devices RD inactive.
must meet this spec.
TCHWH - CLKOUT High to WR Rising Edge:
Time between CLKOUT going high and
WR going inactive. Useful in systems
based on CLKOUT.

Figure 15-15. AC Timing Explanations (Continued)

Ri5 i5E
AD8-15 HIGH ADDRESS

80C196KB
I -74AC
DATA
EPROM
ADO-7 373 LOW ADDRESS

ADV
-y-~ cs
\
OPTIONAL IF
LATCHED EPROM
IS USED
270651-66

Figure 15-16. 8-Bit System with EPROM

4-85
inter 80C196KB USER'S GUIDE

15.6 Memory System Examples ed in the lower half of memory,and the RAM in the
upper half.
External memory systems for the 80C196KB can be set
ull in many different ways. Figure 15-16 shows a simille Figure 15-18 shows a 16 bit system with 2 EPROMs.
8 bit system with a single EPROM. The ADV Mode Again, ADV is used to chip select the memory. Figure
can be selected to Ilrovide a chill select to the memory. 15-19 shows a system with dynamic bus width. Code is
By setting bit CCR.I to 0, the system is locked into the executed from the two EPROMs and data is stored in
eight bit mode. An eight bit system with EPROM and the single RAM .. Note the Chip Select of the RAM also
RAM is shown in Figure 15-17. The EPROM is decod- is input to the BUSWIDTH pin to select an eight bit
cycle.

AD15

AD8-1SI-_ _...._ _..

HIGH ADDRESS
. -_ _ _ _ DATA
DATA
80C196KB EPROM RAM
ADO-7t-. ..j LOW ADDRESS

ADV 1------1

~ ~--------4--------I
WR ~----------------------~
270651-67

Figure 15-17. 8-Bit System with EPROM and RAM

cs CS
HIGH ADDRESS HIGH ADDRESS
EPROM EPROM

~~~;;:t~ DATA DATA

LOW ADDRESS LOW ADDRESS

80C196KB
~ ~ ____________-+__________-J

270651-68

Figure 15-18. 16-Bit System with EPROM

4-86
 80C196KB USER'S GUIDE

EPROM RAM

ADV r~;;l::J DATA

LOW ADDRESS

DE
R5 ~ ____________ ~~ __________ ~ ____________-J

WR ~--------------------------------------------~
270651-69

Figure 15-19. 16-Bit System with Dynamic Buswidth

WRL----------q--,P-______________~

MDO-MD7 P3

WRH

74LS
8 8 74LS
MD8-MD15 04 P4
(x11Az) 273
CLR

RESET INPUT
ADDR = P3, P4
RD
ADO-AD7

AD8-AD15

270651-70

Figure 15-20. 1/0 Port Reconstruction

4-87
inter 80C196KB USER'S GUIDE

15.7 1/0 Port Reconstruction The Run-Time Programming Mode allows individu-
al EPROM'locations to be programmed at run-time
When a single-chip system is being designed using a under complete software control. (Run-Time Pro-
multiple chip system as a prototype, it may be neces- gramming is done with EA = 5V.)
sary to reconstruct I/O Ports 3 and 4 using a memory
mapped I/O technique. The circuit to reconstruct the In the Programming Mode some I/O pins have new
Ports is shown in Figure 15-20. It can be attached to a functions. These pins determine the programming func-
80C196KB system which has the required address de- tion, provide programming control signals and slave ID
coding and bus demultiplexing. numbers, and pass error information. Figure 16-1
shows how the pins are renamed. Figure 16-2 describes
The output circuitry is a latch that operates when each new pin function.
IFFEH or IFFFH are placed on the MA lines. The
inverters surrounding the latch create an open-collector PMODE sf;!lects the programming mode (see Figure
output to emulate~n-drain output found on the 16-3). The 87C196KB does not need to be in the Pro-
80C196KB. The RESET line sets the ports to all Is gramming Mode to do run-time programming; it can be
when the chip is reset. The voltage and current specifi- done at any time.
cations of the port will be different from the
80C196KB, but the functionality will be the same. When an 87C196KB EPROM device is not being
erased the window must be covered with an opaque
The input circuitry is a bus transceiver that is addressed label. This prevents ftmctional degradation and data
at IFFEH and IFFFH. If the ports are going to be loss from the array.
either inputs or outputs, but not both, some of the cir-
cuitry may be eliminated.
16.1 Power-Up and Power-Down
16.0 USING THE EPROM To avoid damaging devices during programming, fol-
low these rules:
the 87CI96KB contains 8 Kbytes of ultraviolet Eras- RULE # 1 Vpp must be within IV of Vee while Vee
able and electrically Programmable Read Only Memo- is below 4.5V.
ry (EPROM). When EA is a TTL high, the EPROM is
located at memory locations 2000H through 3FFFH. RULE #2 Vpp can not be higher than 5.0V until Vee
is above 4.5V.
Applying + 12.75V to EA when the chip is reset places RULE #3 Vpp must not have a low impedance path
the 87C196KB device in the EPROM Programming to ground when Vee is above 4.5V.
Mode. The Programming Mode supports EPROM pro- RULE #4 EA must be brought to 12.75V before Vpp
gramming and verification. The following is a brief de- is brought to 12.75V (not needed for run-
scription of each of the programming modes: time programming).
The Auto Configuration Byte Programming Mode RULE # 5 The PMODE and SID pins must be in
programs the Programming Chip Configuration Byte their desired state before RESET rises.
and the Chip Configuration Byte. RULE #,6 All voltages must be within tolerance and
the oscillator stable before RESET rises.
The Auto Programming Mode enables an RULE #7 The supplies to Vee, Vpp, EA and RE-
87C196KB to program itself without using an SET must be well regulated and free of
EPROM programmer. spikes and glitches.
The Slave Programming Mode provides a standard To adhere to these rules you can use the following pow-
interface for programming any number of er-up and power-down sequences:
87C196KB's by a master device such as an EPROM
programmer.

4-88
inter 80C196KB USER'S GUIDE

POWER-UP EA = 5V
PALE = PROG = SID = PMODE = PORT3,4 =
RESET = OV OV
Vee = vpp = EA = 5V Vee = Vpp = EA = OV
CLOCK on (if using an external clock instead of the CLOCK OFF
internal oscillator)
PALE = PROG = PORT3,4 = VIH(1) NOTES:
SID and PMODE valid ' 1. VIH = logical "I" (2.4V minimum)
EA = 12.75V(2) 2. The same power supply can be used for EA and
Vpp = 12.75V(3) Vpp. However, the EA pin must be powered up before
WAIT (wait for supplies and clock to settle) Vpp is powered up. Also, EA should be protected
RESET = 5V from noise to prevent damage to it.
WAIT Tshll (RESET high to first PALE low) 3. Exceeding the maximum limit on Vpp for any
BEGIN amount of time could damage the device permanently.
The Vpp source must be well regulated and free of
glitches.
POWER-DOWN

RESET = OV
Vpp"" 5V 16.2 Reserved Locations
All Intel Reserved locations except address 2019H,
when mapped internally or externally, must be loaded
with OFFH to ensure compatibility with future devices.
Address 2019H must be loaded with 20H.

PROGRAMMING VOLTAGE

ADDRESS

P 2 . 7 1 - - - - - - - + PACT ~VAL (P3.0)

P2.1 PALE

P2.2 PROG
HSI.O
~.".SI",.D-"\IHSI.1 P2.0 PVER
~--"rIHSI.2
HSI.3 P2.4 AINC
87C196KB
270651-71

Figure 16-1. Programming Mode Pin Functions

4-89
 80C196KB .USER'S GUIDE

Mode Name Function

General PMODE Programming Mode Select. Determines the EPROM programming
(PO-0.4, 0.5, algorithm that is performed. PMODE is sampled after a chip reset and
0.6,0.7) should be static while the part is operating.
Auto PCCB PVER Program Verification Output. A high signal indicates that the bytes
Programming Mode (P2.0) have programmed correctly.
f5iIIE Programming ALE Input. Indicates that Port3 contains the data to be
(P2.1) programmed into the CCB and the PCCB.
Auto Programming PACT Programming Active Output. Indicates when programming activity is
Mode (P2.7) complete.
P'i7A[ Program Valid Output. Indicates the success or failure of
(P3.0) programming. A zero indicates successful programming.
Ports Address/Command/Data Bus. Used in the Auto Programming Mode
3 and4 as a regular system bus to access external memory. Should have
pullups to Vee (15 k!1).
Slave Programming SID Slave 10 Number. Used to assign a pin of Port 3 or 4 to each slave to
Mode (HSI-O.O, use for passing programming verification acknowledgement. For
0.1, 0.2, 0.3) example, ·if gang programming in the Slave Programming Mode, the
slave with SID = 001 will use Port 3.1 to signal correct or .incorrect
program verification.
f5iIIE Programming ALE Input. Indicates that Ports 3 and 4 contain a
(P2.1) command/ address.
PROG Programming Input. Falling edge indicates valid data on PBUS and the
(P2.2) beginning of programming. Rising edge indicates end of programming.
PVER Program Verification Output. Low signal after rising edge of PROG
(P2.0) indicates programming was not successful.
AINC Auto Increment Input. Active low input signal indicates that the auto
(P2.4) increment mode is enabled. Auto Increment will allow reading or
writing of sequential EPROM locations without address transactions
across the PBUS for each read or write.
Ports Address/Command/Data Bus. Used to pass commands, addresses,
3 and 4 and data to and from 87C196KBs in the Slave Programming Mode.
One pin each can be assigned to up to 15 slaves to pass verification
information.
Figure 16-2.. Programming Mode Pin Definitions

PMODE Programming Mode 16.3 Programming Pulse Width

0-4 Reserved
Register (PPW)
5 Slave Programming In the Auto and Run-Time Programming Modes the
width of the programming pulse is determined by the 8
6 ROM Dump bit PPW (Programming Pulse Width) register. In the
7-0BH Reserved Auto Programming Mode, the PPW is loaded from lo-
cation 4014H in external memory. In Run-time Pro-
OCH Auto Programming gramming Mode, the PPW is iocated in window 14 at
ODH Program Configuration Byte 04H. In order for the EPROM to properly program,
the pulse width must'be set to approximately 100 uS.
OEH-OFH Reserved
The pulse width is dependent on the oscillator frequen-
Figure 16-3. Programming cy and is calculated with the following formula:
Function Pmode Values Pulse Width = PPW * (Tosc • 8)

PPW = 150 @ 12 Mhz

In the Slave Programming Mode the width of the pro-

gramming pulse is determined by the PROG signal.
 80C196KB USER'S GUIDE

16.4 Auto Configuration Byte or WRITE lock bits are enabled, some programming
Programming Mode modes will require security key verification before exe-
cuting and some modes will not execute. See Figure
The Programming Chip Configuration Byte (PCCB) is 16-10 and the sections on each programming mode for
a non-memory mapped EPROM location. It gets load- details of the effects of enabling the lock bits.
ed into the CCR during reset for auto and slave pro-
gramming. The Auto Configuration Byte Programming If the PCCB is not programmed, the CCR will be load-
Mode programs the PCCB. ed with OFFFH when the device is iii the Programming
Mode.
The Chip Configuration Byte (CCB) is at location
2018H and can be programmed like any other EPROM
location using Auto, Slave, or Run-Time Programming. 16.5 Auto Programming Mode
However, you can also use Auto Configuration Byte
Programming to program the CCB when no other loca- The Auto Programming Mode provides the ability to
tions need to be programmed. The CCB is programmed program the 87C196KB EPROM without using an
with the same value as the PCCB. EPROM programmer. For this mode follow the power-
up sequence described in Section 16,1 with PMODE =
The Auto Configuration Byte Programming Mode is OCH. External location 4014H must contain the PPW.
entered by following the power-up sequence described When RESET rises, the 87CI96KB automatically pro-
in 'Section 16.1 with PMODE = ODH, Port 4 = grams itself with the data found at external locations
OFFH, and Port J = the data to be programmed into 4000H through SFFFH.
the PCCB and CCB. When a 0 is placed on PALE the
CCB and PCCB are automatically programmed with The 87CI96KB begins progral)1ming by setting PACT
the data on Port 3. After programming, PVER is driv- low. Then it reads a word from external memory, The
en high if the bytes programmed correctly 'and low if Modified Quick-Pulse Programming Algorithm (de-
they did not. scribed later) programs the corresponding EPROM lo-
cation. Since the erased state of a byte is OFFH, the
Once the PCCB and CCB are programmed, all pro- Auto Programming Mode will skip locations with
gramming activities and bus operations use the selected OFFH for data. When all 8K have been programmed,
bus width, READY control, bus controls, and READ/ PACT goes high and the device outputs a 0 on PV AL
WRITE protection until you erase the device. You (P3.0) if it programmed correctly and a 1 ,if it failed.
must be careful whsm programming the READ and Figure 16-4 shows a minimum configuration using an
WRITE lock bits in the peCB and CCB. If the READ 8K X 8 EPROM to program an 87CI96KB in the
Auto Programming Mode.

+12,75 Vdc AUTO PROGRAMMING MODE AND THE

CCB/PCCB
EA Vpp
In the Auto Programming Mode the CCR is loaded
with the PCCB, The PCCB must correspond to the
memory system of the programming setup, including
the READY and bus control selections, You can pro-
gram the PCCB using the Auto Configuration Byte
Programming Mode (see Section 16.4).

The data in the PCCB takes effect upon reset. 'If you
enable the READ and WRITE lock bits during Auto
Programming but do not reset the device,' Auto Pro-
gramming will continue. If you enable either the
270651-73 READ or WRITE lock bits in the CCB using Auto
NOTES: Configuration Byte Programming and then reset the
Tie Port 3 to the value desired to be programmed into 87C196KB for Auto Programming, the device does a
CCS and PCCS. security key verification. The same security keys that
Make all necessary minimum connections for power, reside at internal addresses 2020H-202FH must reside
ground and clock, at external locations 4020H-402FH. If the keys match,
auto programming continues. If the keys do not match,
Figure 16·5. The PCCB Programming Mode the device enters an endless loop of internal execution.

4-91
 80Ct96KB USER'S GUIDE

0.1-1.0,uF
+5V

Rii
lOOK AD8-AD15

RESET
HSI.0-HSI.3 74LS AO-A7
373
RXD ADO-AD7
T2CLK ALE
2764
T2RST +5V
EXTINT READY
NMI BUSWIDTH
EA
+5V
+5V
+12.75V
Vpp PO.7
+12.75V PO.6
PO.S
POA
PACT
87C196KB
27065~ -72

NOTES:
~Inputs !pust be driven high or'low. _
"Allow RESET to rise after the voltages to Vee. EA. and Vpp are stable.

Figure 16-4. Auto Programming Mode

4-92
inter 80C196KB USER'S GUIDE

16.6 Slave Programming Mode The 87C196KB receives an input signal, PALE, to in·
dicate a valid command is present. PROG causes the
Any number of 87C196KBs can be programmed by a 87C196KB to read in or output a data word. PVER
master programmer through the Slave Programming indicates if the programming was successful. AINC au·
Mode. There is no 87C196KB dependent limit to the tomatically increments the address for the Data Pro-
number of devices that can be programmed. gram and Word Dump commands.

In this mode, the 87C196KB programs like a simple

Data Program Command
EPROM device and responds to three different com·
mands: data program, data verify, and word dump. The A Data Program Command is illustrated in Figure 16-
87C196KB uses Ports 3 and 4 and five other pins to 7. Asserting PALE latches the command and address
select commands, to transfer data and addresses, and to on Ports 3 and 4. PROG is asserted to latch the data
provide handshaking. The two most significant bits on present oli Ports 3 and 4. PROG also starts the actual
Ports 3 and 4 specify the command and the lower 14 programming sequence. The width of the PROG pulse
bits contain the address. The address ranges from determines the programming pulse width. Note that the
2000H·3FFFH and refers to internal memory space. PPW is not used in the Slave Programming Mode.
Figure 16·6 is a list of valid Programming Commands.
After the rising edge of PROG, the slaves automatically
P4.7 P4.6 Action verify the contents of the location just programmed.
PVER is asserted if the location programmed correctly.
0 0 Word Dump This gives verification information to programmers
0 1 Data Verify which can not use the Data Verify Command. The
1 0 Data Program AINC pin can increment to the next location or a new
1 1 Reserved Data Program Command can be issued.
Figure 16-6. Slave Programming
Mode Commands

PORTS
3/4 --< ADDR/COMMAND :>-----<:,___ --I:>-----<:
D_A_TA__ ADDR/COMMAND

!
\'--_-J!
\\.....---J! 270651-74

Figur.e 16-7. Data Program Command in Slave Mode

4-93
inter 80C196KB USER'S GUIDE

PVER is a I if the data program was successful. PVER mand and plac~s the value at the new address on Ports
is a 0 if the data program was unsuccessful. Figure 16-7 3 and 4. For example, when the slave receives the ~om­
shows the relationship of PALE, PROG, and PVER to mand OlOOH, it will place the' word at internal address
the Command/Data path on Ports 3 and 4 for the Data 2100H on Ports 3 and 4. PROG governs when the slave
Program Command. drives the bus. The Timings are the same as s'lOwnin
Figure 16-7.
Data Verify Command Note that the Word Dump Command only works when
When the Data Verify Command is sent, the slaves in- a single slave is attached to the bus. Also, there is no
dicate correct or incorrect verification of the previous restriction on commands that precede or follow a Word
Data Program Command by driving one bit of Ports 3 Dump Command.
and 4. A I indicates a correct verification, and a 0 indi-
cates incorrect verification. The SID (Slave I.D) of each Gang Programming With the Slave
slave determines which bit of Ports 3 and 4 will be Programming Mode
driven. For example, a SID of 0001 would drive Port
3.1. PROG governs when the slaves drive the bus. Fig- Gang Programming of 87CI96KBs can be done using
ure 16-8 shows the relationship of ports 3 and 4 to the Slave Programming Mode. There is no 87CI96KB
PALE and PROG. based limit on the number of devices that may be
hooked to the same Port 3 and 4 data path for gang
A Data Verify Command is always preceded by a Data programming.
Program Command in a programming system with as
many as 16 slaves. However, a Data Verify Command If more than 16 devices are being gang programmed,
does not have to follow every Data Program Com- the PVER outputs of each chip can be used for verifica-
mand. tion. The master programmer can issue a Data Pro-
gram Command, then either watch every device's error
signal, or AND all the signals together to form a sys-
Word Dump Command tem PVER.
When the Word Dump Command is issued, the
87C 196KB adds 2000H to the address field of the com-

ADDR ADDR+ 2
PORTS
ADDR/COMMAND VER BITS/WD DUMP VER BITS/WD DUMP
3/4

\~_---JI

\~_--.-JI

\~---------------------- 270651-75

Figure 16-8. Ports 3 and 4 to PALE and PROG

4-94
inter 80C196KB USER'S GUIDE

If 16 or fewer 87CI96KBs are to be gang programmed 16.7 Run-Time Programming

at once, a more flexible form of verification is available
by giving each device a unique SID. The master pro- The 87Cl96KB can program itself under software con-
grammer can issue a Data Verify Command after the trol. One byte or word can be programmed instead of
Data Program Command. When a verify command is the entire atray. The only additional requirement is
seen by the slaves, each will drive a bit of Ports 3 or 4 that you apply a programming voltage to Vpp and have
corresponding to its unique SID. A I indicates the ad- the ambient temperature at 25°C. Run-time program-
dress verified, while a 0 means it failed. ming is done with EA at a TTL high (internal memory
enabled).
SLAVE PROGRAMMING MODE AND THE
To Run-Time Program, the user writes to the location
CCB/PCCB to be programmed. The value of the PPW register de-
Devices in the Slave Programming Mode use Ports 3 termines the programming pulse. To ensure 87CI96KC
and 4 as the command/data path. The data bus is not compatibility, the Idle Mode should be used for Run-
used. Therefore, you do not need to program either the Time Programming. Figure 16-9 is the recommended
CCB or the PCCB before starting slave programming. code sequence for Run-Time Programming" The Modi-
fied Quick Pulse algorithm guarantees the programmed
You can program the CCB like any other location in EPROM cell for the life of the part.
slave mode. Data programmed into the CCB takes ef-
fect upon reset. If you enable eitller the READ or the RUN-TIME PROGRAMMING AND THE
WRITE lock bits in the CCB during slave program- CCB/PCCB .
ming and do not reset the device, slave programming
will continue. If you do reset the device, the device first For run-time programming, the CCR is loaded with the
does a security key verification. The same security keys CCB. Run-time programming is done with EA equal to
that reside at intern<ll addresses 2020H-202FH must a TTL-high (internal execution) so the internal CCB
reside at external addresses 4020H -402FH. If the keys must correspond to the memory system of the applica-
match, slave programming continues. If the keys do not tion setup. You can use Auto Configuration Byte Pro-
match, the device enters an endless loop of internal exe- gramming or a generic programmer to program the
cution. . CCB before using Run-Time Programming.

LD WSR,#14 ;Initialize programmable

LD PPW,#VALUE ;pulse width

PROGRAM: POP ADDRESS_TEMP ;Load program data

POP DATA_TEMP ;and address
PUSHF
LD COUNT, #25T
LOOP: ST DATA_TEMP, [ADDR_TEMP] ;begin programming
;enter idle mode
DJNZ COUNT, LOOP ;loop 25 times
POPF
RET
NOTE:
'Not Really Needed on Current 87C196KB Part

Figure 16-9. Future Run-Time Programming Algorithm

4-95
inter 80C196KB USER'S GUIDE

The CCB can lflso be prog~amm\!d during Run-Titne

CCB.1 CCB.O
Programming like any other EPROM location.
RD WR Protection
Data programmed into the'CCB takes effect immedi- Lock Lock
ately. If the WRITE lock bit of the CCB is enabled, the 1 1 Array is unprotected. ROM
array can.no longer be programmed. You should only Dump Mode and all
program the WRITE lock bit when no further pro-
gramming will be done to the array. If the READ lock programming modes are
bit is programmed the array can still be programmed allowed. __ ._M
using run-time programming but a data access will only 0 1 Array is READ protected. Run-
be performed when the program counter is between time programming is allowed.
2000H and 3PFFH. Auto, Slave, and ROM Dump
Mode are allowed after security
key verification.
16.8 ROM/EPROM Memory Protection
Options ' 1 0 Array is WRITE protected. Auto,
Slave, and ROM Dump Mode
Write protection is available for EPROM parts, and are allowed after security key
read protection is provided for both ROM and
EPROM parts. verification. Run-time
programming is not allowed.
Write protection is enabled by clearing the LOCO bit in 0 0 Array is READ and WRITE
the CCR. When write protection is enabled, the bus protected. Auto, Slave, and
controller will cycle through the write sequence but will
ROM Dump Mode are allowed
not actually dri~e data to the EPROM or enable Vpp to after security key verification.
the EPROM. This protects the entire EPROM (loca-
tions 2000H-3FFF,H) from inadvertent or unautho- Run-time programming is not
rized programming. allowed.
Figure 16·10
Read protection is enabled by clearing the LOCI bit of
the CCR. When read protection is selected, the bus
controller will only perform a data read from -the ad- ROM DUMP-MODE
dress range 2020H-202FH (Security Key) and 2040H-
3FFFH if the Slave Program Counter is in the range You can use the security key and ROM Dump Mode to
2000H-3FFFH. Since the Slave PC can be as many as 4 dump the internal ROM/EPROM for testing purposes.
bytes ahead of the CPU program counter, an instruc-
tion after address 3FFAH may not access protected The security key is a 16 byte number. The internal
memory. Also,note the interrupt vectors and CCB are ROM/EPROM must contain the security key at loca-
not read protected. tions 2020H-202FH. The user must place the same
security key at'external address 4020H-402FH. Before
EA is latched on reset so the device cannot be switched doing a ROM dump, the device checks that the keys
from inter~al to external memory by' toggling EA. match.

If the CCR has any protection enabled, the security key

is write protected to keep unauthorized users from ov-
'erwriting the key with a known security key.

NOTE:
'Substantial effort has been made to provide an excel-
lent program protection scheme. However, Intel can-
not and does not guarantee that these protection
methods will always prevent unauthorized access.

4-96
 80C196KB USER'S GUIDE

For the 87C196KB, the ROM dump mode is entered

Description Location Value
like the other programming modes described in Section
16.1 with PMODE equal to 6H. For the 83C196KB, Signature Word 2070H 897CH
the ROM Dump Mode is entered by placing EA at a Programming Vee 2072H 040H
TTL high, holding ALE low and holding INST and (5.0V)
RD high on the rising edge of RESET. The device first 2073H
Programming Vpp OA3H
verifies the security key. If the security keys do not
(12.75V)
match, the device puts itself into an endless loop of
internal execution. If the keys match, the device dumps Figure 16·10. Signature Word and Voltage Levels
internal locations 2000H-3FFFH to external locations
4OOOH- 5FFFH.
Erasing the 87C196KB

After each erasure, all bits of the 87C196KB are logical

16.9 Algorithms Is. Data is introduced by selectively programming Os.
The only way to change a 0 to a I is by exposure to
The Modified Quick-Pulse Algorithm ultraviolet light.
The Modified Quick-Pulse Algorithm must be used to Erasing begins upon exposure to light with wavelengths
guarantee programming over the life of the EPROM in shorter than approximately 4000 Angstroms. It should
Run-time and Slave Programming Modes. be noted that sunlight and certain types of fluorescent
lamps have wavelengths in the 3000-4000 Angstrom
The Modified Quick-Pulse Algorithm calls for .each range. Constant exposure to room level fluorescent
EPROM location to receive 25 separate 100 uS (± 5 lighting could erase an 87C 196KB in about 3 years. It
J.Ls) programming cycles. Verification is done after the would take about 1 week in direct sunlight to erase an
25th pulse. If the location verifies, the next location is 87C196KB.
programmed. If the location fails to verify, the location
fails the programming sequence. Opaque labels should always be placed over the win-
dow to prevent unintentional erasure. In the Power-
Once all locations are programmed and verified, the down Mocte, the part will draw more current than nor-
entire EPROM is again verified. mal if the EPROM window is exposed to light.

Programming of 87CI96KB EPROMs is done with The recommended erasure procedure for the
Vpp = 12.75V ±0.25V and Vee = 5.0V ±0.5V. 87C196KB is exposure to ultraviolet light which has a
wavelength of 2537 Angstroms. The integrated dose
(UV intensity * exposure time) should be a minimum of
Signature Word
IS Wsec/cm 2. The total time for erasure is about IS to
The 87CI96KB contains a signature word at location 20 minutes at this level of exposure. The 87CI96KB
2070H. The word can be accessed in the Slave Mode by should be placed within 1 inch of the lamp during expo-
executing a Word Dump Command. The programming sure. The maximum integrated dose an 87C196KB can
voltages are determined by reading the test ROM at be exposed to without damage is 7258 Wsec/cm 2 (1
locations 2072H and 2073H. The voltages are calculat- week @ 12000 uW /cm 2). Exposure to UV light greater
ed by using the following equation. than this can cause permanent damage. -

Voltage = 20/256 * (test ROM data)

The values for the signature word and voltage levels are
shown in Figure 16-10.

4·97
 ~(ffi[§[!"OIr1l000~(ffiW
87C196KB/83C196KB/80C196KB
16-BIT HIGH PERFORMANCE CHMOS
MICROCONTROLLER
87C196KB - 8 Kbytes of On-Chip EPROM
83C196KB - 8 Kbytes of Factory Mask-Programmed ROM
80C196KB - ROMless

• 8 Kbytes of On-Chip EPROM

• Full Duplex Serial Port

• 232 Byte Register File

• High'Speed I/O Subsystem

• Register-to-Register Architecture
• 16-Bit Timer

• 28 Interrupt Sources/16 Vectors

• 16-Bit Up/Down Counter with Capture

• 2.3 /-Ls 16 x 16 Multiply (12 MHz)

• Pulse-Width-Modulated Output

• 4.0 /-Ls 32/16 Divide (12 MHz)

• Four 16-Bit Software Timers

• Powerdown and Idle Modes

• HOLD/HLDA
10-Bit A/D Converter with Sample/Hold

• Five 8-Bit I/O Ports

• 12 MHz Version-
Bus Protocol

• 16-Bit Watchdog Timer

• 87C196KB12/83C196KB12/80C196KB12
• Dynamically Configurable 8-Bit or
16-Bit Buswidth 10 MHz Version-
87C196KB10/83C196KB10/80C196KB10
The 80C196KB 16-bit microcontroller is a high performance member of the MCS®-96 microcontroli~r family.
The 80C196KB is compatible with the 8096BH and uses a true superset of the 8096BH instructions, Intel's
CHMOS process provides a high performance processor along with low power consumption. To further reduce
power requirements, the processor can be placed into Idle or Powerdown Mode.
The 80C196KB has a 232-byte register file and an optional 8 Kbyte of on-chip ROM or EPROM. The
80C196KB will refer to all of the above products unless otherwise stated.
Bit, byte, word and some 32-bit operations are available on the 80C196KB. With a 12 MHz oscillator a 16-bit
addition takes 0.66 p.s, and the instruction times average 0.5 p.s to 1.5 P.s in typical applications.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start anA/D conversion. Events can be based on the timer or up/down counter.
Also provided on-chip are an AID converter, serial port, watchdog timer, and a pulse-width-modulated output
signal.

270918-1
Figure 1. 80C196KB Block Diagram
MCS"'-96 is a registered trademark of Intel Corporation.

October 1990
4-98 Order Number: 270918-001
inter 87C196KB/83C196KB/80C196KB

ARCHITECTURE
The 80C196KB is a member of the MCS(8)-96 family, and as such has the same architecture and uses the
same instruction set as ~he 8096BH. Many new features have been added on the 80C196KB including:

CPU FEATURES
Divide by 2 instead of divide by 3 clock for 1.5X performance

Faster instructions, especially indexed/indirect data operations

2.33 '""S 16 x 16 multiply with 12 MHz clock (was 6.25 ,""S on t~e 8096BH)
Faster interrupt response (almost twice as fast as 8096BH)

Powerdown and Idle Modes

5 new instructions including Compare Long and Block Move

8 new interrupt vectors/6 new interrupt sources

PERIPHERAL FEATURES
SFR Window switching allows read-only registers to be written and vice-versa

Timer2 can count up or down ,by external selection

Timer2 has an independent capture register

HSO line events are stored in a register

HSO has CAM Lock and CAM Clear commands

New Baud Rate values are n~eded for serial port, higher speeds possible in.all modes

Double buffered serial port transmit register

Serial Port Receive Overrun and Framing Error Detection

PWM has a Divide-by-2 Prescaler

HOLD/HLDA Bus Protocol.

PACKAGING
The S7C196KB is available in a 68-pin LCC (windowed) package and a 68-pin PLCC (One Time Programma-
ble) package.

The 80C196KB and S3C196KB are available in a 68~pin PLCC package and an SO-pin QFP package, In
addition, the 80C196KB is available in a 68-pin PGA package. Contact your local sales office to determine the
exact ordering code for the part desired.

LCC PLCC QFP PGA

87C196KB R87C196KB N87C196KB - -
83C196KB - N83C196KB . S83C196KB -
80C196KB - N80C196KB . S80C196J(B A80C196KB

4-99
 87C196KB/83C196KB/80C196KB'

PGA PLCC Description PGA PLCC Description PGA PLCC' Description

1 9 ACH7/PO.7 24 54 ADS/P3.S 47 31 . Pl.S/HLDA
2 8 ACHS/PO.S 25.. 53 AD7/P3.7 48 30 Pl.5/BREQ
3 7 ACH2/PO.2 26 52 AD8/P4.0 49 29 HSO.1
4 6 ACHO/PO.O 27 '. 51 AD9/P4.1 50 28 HSO.O
5 5 ACH1/PO.1 28 50 AD10/P4.2 51 27 HSO.5/HSI.3
6 4 ACH3/PO.3 29 49 AD11/P4.3 52 26 HSO.4/HSI.2
7 3 NMI 30 48 AD12/P4.4 53 25 HSI.1
8 2 EA 31 47 AD13/P4.5 54 24 HSI.O
9 1 Vee 32 46 AD14/P4.6 55 23 P1.4
10 68 Vss 33 45 AD15/P4.7 56 22 P1.3
11 67 XTAL1 34 44 T2CLK/P2.3 57 21 P1.2
12 66 XTAL2 35 43 READY 58 20. Pl.l
13 65 CLKOUT 36 42 T2RSTIP2.41 AINC 59 19 Pl.0
14 64 BUSWIDTH 37 41 SHE/WRH 60 18 TXD/P2.0
15 63 INST 38 40 WR/WRL 61 17 RXDIP2.1
16 62 ALE/ADV 39 39 PWM/P2.5 62 16 RESET
17 61 RD 40 38 P2. 7/T2CAPTURE/PACT 63 15 EXTINTIP2.2
18 60 ADO/P3.0 41 37 Vpp 64 14 VSS(1)
19 59 AD1/P3.1 42 36 Vss 65 13 VREF
20 58 AD2/P3.2 43 35 HSO.3/SID3 66 12 ANGND
21 57 AD3/P3.3 44 34 HSO.2/SID2 67 11 ACH4/PO.4
22 56 AD4/P3.4 45 33 P2.6/T2UP-DN 68 10 ACH5/PO.5
23 55 AD5/P3.5 46 32 P1.7 lFiOiJ)

NOTE:
1. This pin was formerly the Clock Detect Enable pin. This function is not guaranteed to work. This pin rnust be directly
connected to Vss.
Figure 2. Pin Definitions

1 2 3 4 5 6 7 8 9 ,1011 121314151617
68 18
67 19
66 20
65 21
64 MCS®-96 22
63 68 PIN 23
62 LEADLESS CHIP CARRIER 24
61 TYPE "8" 25
60 26
59 27
TOP VIEW
58 28
LOOKING DOWN ON
57 COMPONENT SIDE 29
56 OF PC 80ARD 30
55 31
54 32
53 33
H Y
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
270918-6

Figure 3. 6S·Pln Package (LCC-Top View)

4-100
inter 87C196KB/83C196KB/80C196KB

Pins Facing Down

171513 11 9 7 5 3 1 "
18 19 16 14 12 10 8 6 4 2 68
2021 67 66
MCS(ffi-96
2223 6564
68 PIN
2425 GRID ARRAY 6362
2627 61 60
TOP VIEW 5958
2829
LOOKING DOWN ON
3031 COMPONENT SIDE 5756
OF PC BOARD 5554
3233
34 36 38 40 42 44 46 48 50 53 52
3537394143'45474951
270918-2

Figure 4. 5S-Pin Package (Pin Grid Array-Top View) SOC196KB Only

.." . ..'" . . .
0
U>
0 0 0 0
0 "1
0
...........................................
" CD NO,.... to') .... ~
.... '"b
::>
0
I~
~ .........
...'" ...'" '"~ ...'" ...'" ...'"
CJ CJ CJ CJ CJ
~ I~ >tl ~:! j:!
> x x
~ ::>
CJ ., ~ ~I~
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 6261
ACH5/PO.5 ADO/PM
ACH4/PO.4 AD1/P3.1
ANGND AD2/P3.2
VREF AD3/P3.3
MCS®-96 AD4/P3.4
Vss
EXTINT/P2.2 68 PIN AD5/PM
RESET 16 PLCC AD6/P3.6
RXD/P2.1 AD7/P3.7
TXD/P2.0 AD8/P4.0
P1.0 19 AD9/P4.1
PLI TOP VIEW AD10/P4.2
PL2 ADll/P4.3
LOOKING DOWN ON
PL3 ADI2/P4.4
PL4
COMPONENT SIDE ADI3/P4.5
HSIO OF PC BOARD ADI4/P4.6
HSII ADI5/P4.7
HSI2/HS04 T2CLK/P2.3
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

270918-3

Figure 5. 5S-Pin Package (PLCC-Top View)

4-101
inter 87C196KB/83C196KB/80C196KB

80-Pln Quad Flat Pack (EIAJ)

Con~octs Contacts
Facing Up Facing Down
PIN NO. 1 MARK
65 80 80

64 64

41 24 24 41

40 25 25 40
270918-4

Top View

1111111111111111
64 T2CLK/P2.3
A01/P3.1
63 VSS
ADD/P3.0 62 READY
Rii 61 T2RST/P2.4
ALE/AOV
60 BHE/WRH
INST
59 WR/WRL
BUSWIOTH
58 PWM/P2.5
CLKOUT
57 P2.7/T2CAPTURE
XTAL2 .,--
56 Vpp
XTALI
55 VSS
VSS 10
54 VSS
Vss 11
53 HSO.3
Vee 12
52 Vee
Vee 13
51 Vss
EA 14
50 HSO.2
NMI 15
49 P2.6/T2UP/ON
ACH3/PO.3 16
48 PI.7
ACH1/PO.l 17
47 PI.6
ACHO/pO.O 18 Pl.5
46
ACH2/PO.2 19 45 HSO.l
ACH6/PO.6 20 44 HSO.O
ACH7/PO.7 21 43 HSO.5/HSI.3
N.C. 22 42 Vss
ACH5/PO.5 23
41 HSO.4/HSI.2
ACH4/PO.4

1111111111111111

270918-5

Figure 6. 80·Pin Quad Flat Pack (QFP)

4·102
 Thermal Characteristics
Package
Type Bja. BJc

LCC 28°C/W 3SC/W

PGA 28°C/W 3SC/W
PLCC 35°C/W 12°C/W
OFP 85°C/W -
PIN DESCRIPTIONS
Symbol Name and Function
Vee Main supply voltage (5V).
Vss Digital circuit ground (OV). There are two Vss pins, both of which must be connected.
VREF Reference voltage for the AID converter (5V). VREF is also the supply voltage to the analog
portion of the AID converter and the logic used to read Port O. Must be connected for AID
and Port 0 to function.
ANGND Reference ground for the AID converter. Must be held at nominally the same potential as
Vss·
Vpp . Timing pin for the return from powerdown circuit. Connect this pin with a 1 ).LF capacitor to·
VSS. If this function is not used, connect to Vee. This pin is the programming voltage on the
EPROM device.
XTAL1 Input of the oscillator inverter and of the internal clock generator.
XTAL2 Output of the oscillator inverter.
CLKOUT Output of the internal clock generator. The frequency of CLKOUT is 1kthe oscillator
frequency. It has a 50% duty cycle.
RESET Reset input to the chip. Input low for at least 4 state times to reset the chip. The subsequent
low-to-high transition re- synchronizes CLKOUT and commences a 1O-state-time sequence in
which the PSW is cleared, a byte read from 2018H loads CCR, and a jump to location 2080H
is executed. Input high for normal operation. RESET has an internal pullup.
BUSWIDTH Input for buswidth selection. If CGR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit
cycle occurs. If eCR bit 1 js a 0, the bus is always an a-bit bus.
NMI A positive transition causes a vector through 203EH.
INST Output high during an external memory read indicates the read is an instruction fetch. INST is
valid throughout the bus cycle. INST is activated only during external memory accesses and
output .Iow for a data fetch.
EA Input for memory select (External Access). EA equal to a TTL-high causes memory accesses
to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM. EA equal to a
TTL-low causes accesses to these locations to be directed to off-chip memory. EAmust be
lied low for the 80G196KB ROM less device.
ALE/ADV Address Latch Enable or Address Valid output, as selected by CGR. Both pin options provide
a latch to demultiplex the address from the address/data bus. When the pin is ADV, it goes
inactive high at the end of the bus cycle. ADV can be used as a chip select for external
memory. ALE/ ADV is activated only during external memory accesses.
RD Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL Write and Write Low output to external memory, as selected by the GGR. WR will go low for
. every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.

4-103
 87C196KB/83C196KB/80C196KB

PIN DESCRIPTIONS (Continued)

Symbol Name and Function
BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCR. BHE = 0
selects the bank of memory that is connected to the high byte of the data bus. AO = 0
selects the bank of memory that is connected ,to the low byte of the data bus. Thus accesses
to a 16-bit wide memory can be to the low byte only (AO = 0, BHE = 1), to the high byte only
(AO = 1, BHE = 0), or both bytes (AO = 0, BHE = 0). If the WRH function is selected, the
pin will go low if the bus cycle is writing to an odd memory location. BHE/WRH is valid only
during 16-bit external memory write cycles.
READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. If the pin is high, CPU operation continues in a'normal manner. If the pin is
low prior to the falling edge of CLKOUT, the memory controller goes into a wait mode until the
next positive transition in CLKOUT occurs with READY high. When the external memory is
not being used, READY has no effect. Internal control of the number of wait states inserted
into a bus cycle held not ready is available through configuration of CCA.
HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2, and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. The HSI pins are also used as
the SIDin Slave Programming Mode on the EPROM device.
HSO Outputs from High Speed Output Unit, Six HSO pins are available: HSO.O, HSO.1, HSO.2,
HSO.3, HSO.4, and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
PortO B-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter. These pins set the Programming Mode on the
EPROM device.
Port 1 B-bit quasi-bidirectional 110 port.
Port 2 B-bit multi-functional port. All of its pins are shared with other fUQctions in the BOC196KB.
Ports 3 and 4 B-bit bi-directionall/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups. Available as I/O only on the
ROM and EPROM devices.
HOLD Bus Hold input requesting control of the bus. Enabled by setting WSR. 7.
HLDA Bus Hold acknowledge output indicating release of the bus. Enabled by setting WSR.7.
BREQ Bus Request output activated when the bus controller has a pending external memory cyc;le.
Enabled bY setting WSA.7.
TxD The TxD pin is used for serial port transmission in M<;>des 1,2, and 3. The TxD function is
enabled by setting lOCi 5. In mode 0 the pin is used as the serial clock output.
RxD Serial Port Receive pin used for serial port reception. The RxD function is enabled by setting
SPCON.3. In mode 0 the pin functions as input or output data.
EXTINT A rising edge on the EXTINT pin will generate an external interrupt. EXrlNT is selected as the
external interrupt source by setting IOC1.1 high.
T2CLK The T2CLKpin is the Timer2 clock input or the serial port baud rate generator input.
T2RST A riSing edge on the T2RST pin will reset Timer2. The external reset function is enabled by
setting IOCO.03 T2RST is enabled as the reset source by clearing IOCO.5.
PWM Port 2.5 can be enabled as a PWM output by setting IOC1.0 The duty cycle of the PWM is
determined by th~ value loaded into the PWM-CONTROL register (17H).
T2UPDN The T2UPDN pin controls the direction of Timer2 as an up or down counter. The Timer2 up/
down function is enabled by setting IOC2.1.
T2CAP A rising edge on P2.7 will capture 'the value of Timer2 in the T2CAPTURE register (location
OCH in Window 15). ..

4-104
inter 87C 196KB/83C196KB/80C 196KB

NEW INSTRUCTIONS
The following five instructions have been added to the 8096BH instruction set for the 80C196KB.

PUSHA - PUSHes the PSW, IMASK, IMASK1, and WSR

(Used instead of PUSHF when new interrupts and registers are used.)
assembly language format: PUSHA
object code format: < 1111 01 00 >
bytes: 1
states: on-chip stack: 12 .
off-chip stack: 18
POPA - POPs the PSW, IMASK, IMASK1, and WSR .
(Used instead of POPF when new interrupts and registers are used.)
assembly language format: POPA
object code format: < 1111.0101 >
bytes: 1
states: on-chip stack: 12
off-chip stack: 18
IDLPD - Sets the part into Idle or Powerdown Mode
assembly language format: IDLPD # key (key = 1 for Idle, key = 2 for Powerdown.)
object code format: < 1111011 0> < key>
bytes: 2
states: legal key: 8 '
illegal key: 25

CMPL - Compare 2 long direct values

assembly language format: DST SRC
CMPL Lreg, Lreg
object code format: < 11000101 > < src Lreg> < dst Lreg>
bytes: 3
states: 7

BMOV - Block move using 2 auto-incrementing pointers and a counter

assembly language format: PTRS CNTREG
BMOV Lreg, wreg
object code format: <11000001> <wreg> < Lreg>
bytes: 3
states: internal/internal: 8 per transfer + 6
external/internal: 11 per transfer + 6
external/external: 14 per transfer + 6

4-105
 87C 196KB/83C196KB/80C 196KB

SFR OP1:RATION
All of the registers that were present on the 8096BH work the same way as they did, except that the baud rate
value is different. The new registers shown in the memory map control new functions. The most important new
register is the Window Select Register (WSR) which allows reading of the formerly write-only registers and
vice-versa. '

USING THE ALTERNATE REGISTER WINDOW (WSR= 15)

I/O register expansion on the new CHMOS members of the MCS-96 family has been provided by making two
register windows available. Switching between these windows is done using the Window Select Register
(WSR). The PUSHA and POPA instructions can be used to push and pop the WSR and second interrupt mask
when entering or leaving interrupts, so it is easy to change between windows. '

On the 80C196KB only Window 0 and Window 15 are active. Window 0 is a true superset of the standard
8096BH SFR space, while Window 15 allows the read-only registers to be written and write-only registers to be
read, The only major exception to this is the Timer2 register which is the Timer2 capture register in Window 15,
The writeable register for Timer2 is in Window O. There are also some minor changes and cautions. The
descriptions of the registers which have different functions in Window 15 than in Window 0 are listed below:
AD_COMMAND (02H) - Read the last written command
AD_RESULT (02H, 03H) - Write a value into the result register
HSLMODE (03H) - Read the value in HSLMODE
HSI_TIME (04H,05H) - Write to FIFO Holding register
HSO_TIME (04H,05H) - Read the last value placed in the holding register
HSLSTATUS (06H) - Write to status bits but not to HSI pin bits. (Pin bits are 1,3,5,7).
HSO_COMMAND (06H) - Read the last value placed in the holding register
SBUF(RX) (07H) - Write a value into the receive buffer
SBUF(TX) (07H) - Read the last value written to the transmit buffer
WATCHDOG(OAH) - Read the value in the upper byte of the WDT
TIMER1 (OAH,OBH) - Write a value to Timer1
TIMER2 (OCH,ODH) .- Read/Write the Timer2 capture register.
Note that Timer2 read/write is done with WSR = O.
IOC2(OBI-j) - Last written value is readable, except bit 7 (note 1)
BAUDRATE (OEH) - No function, cannot be read
PQRTO (OEH) - No function, no output drivers on the pins. Register reserved.
PORT1 - IOPORT1 cannot be read or written in Window 15. Register reserved.
SP_STAT (11H) - Set the status bits, TI and RI can be set, but it will not cause an interrupt
SP_CON (11 H) - Read the current control byte
10SO (15H) - Writing to this register controls the HSO pins. Bits 6 and 7 are inactive for writes.
lOCO (15H) - Last written value is readable, except bit 1 (note 1)
IOS1 (16H) - Writing to this register will set the status bits, but not cause interrupts. Bits 6 and
7 are not functional
IOC1 (16H) - Last written value is readable
IOS2 (17H) - Writing to this register will set the status bits, but not cause interrupts.
PWM_CONTROL (17H) - Read the duty cycle value written to PWM_CONTROL

NOTE:
1. IOC2.7 (CAM CLEAR) and IOCO.1 (T2RST) are not latched and will read as a 1 (precharged bus).

Being able to write to the read-only registers and vice-versa provides a lot of flexibility. One of the most useful
advantages is the ability to set the timers and HSO lines for initial conditions other than zero.

Reserved registers may be used for testing or for future features. Do not write to these registers. Reads from
reserved registers will return indeterminate values.
4-106
inter 87C196KB/83C196KB/80C196KB

MEMORY MAP 80C196KBINTERRUPTS

Vector
OFFFFH Number Source Priority
EXTERNAL MEMORY OR 1/0
Location
4000H INT15 NMI 203EH 15
INTERNAL ROMIEPROM OR
EXTERNAL MEMORY INT14 HSI FIFO Full 203CH 14
2080H
INT13 EXTINTPin 203AH 13
RESERVED
2040H INT12 TIMER2 Overflow 2038H 12
UPPER 8 INTERRUPT VECTORS
2030H INT11 TIMER2 Capture 2036H 11
ROM/EPROM SECURITY KEY INT10 4th Entry into HSI FI FO 2034H 10
2020H
RESERVED INT09 RI 2032H 9
2019H
INT08 TI 2030H 8
CHIP CONFIGURATION BYTE
2018H SPECIAL Unimplemented Opcode 2012H N/A
RESERVED
SPECIAL Trap 2010H N/A
2014H
LOWER 8 INTERRUPT VECTORS INT07 EXTINT 200EH 7
PLUS 2 SPECIAL INTERRUPTS
2000H INT06 Serial Port 200CH 6
PORT 3AND PORT 4 INT05 Software Timer 200AH 5
1FFEH
EXTERNAL MEMORY OR 1/0 INT04 HSI.O Pin 2008H 4
0100H
INT03 High Speed Outputs 2.006H 3
INTE'RNAL DATA MEMORY· REGISTER FILE
(STACK POINTER. RAM AND SFRS) .INT02 HSI Data Available 2004H 2
EXTERNAL PROGRAM CODE MEMORY
OOOOH
INT01 AID Conversion Complete 2002H 1
INTOO Timer Overflow 2000H 0

19H 19H
STACK POINTER STACK POINTER
18H 18H
17H 'IOS2 17H PWM CONTROL
16H IOS1 16H IOC1
15H 10SO 15H lOCO
14H 'WSR 14H 'WSR
13H 'INT_MASK1 13H 'INT_MASK1
12H 'INT PEND 1 12H 'INT PEND 1
11H 'SP STAT 11H 'SP CON
10H PORT2 10H PORT2 RESERVED (1)
OFH PORn OFH PORn OFH RESERVED (1)
OEH PORTO OEH BAUD RATE OEH RESERVED (1)
ODH TIMER2(HI) ODH TIMER2(HI) ODH 'T2 CAPTURE (HI)
OCH TIMER2 (LO) OCH TIMER2(LO) OCH 'T2 CAPTURE (LO)
OBH TIMER1 (HI) OBH 'IOC2
WSR ~ 15
OAH TIMER1 (LO) OAH WATCHDOG
09H INT_PENDING 09H INTJENDING OTHER SFRS IN WSR
08H INT_MASK 08H INT_MASK 15 BECOME READABLE
IF THEY WERE WRITABLE
07H SBUF(RX) 07H SBUF(TX) IN WSR ~ 0 AND WRITABLE
06H HSI_STATUS 06H HSO_COMMAND IF THEY WERE READABLE
INWSR ~ 0
05H HSLTIME(HI) 05H HSO_TIME (HI)
04H HSI TIME (LO) 04H HSO TIME (LO)
03H AD RESULT (HI) 03H HSI MODE
02H AD RESULT (LO) 02H AD COMMAND 'NEW OR CHANGED
01H ZERO REG (HI) 01H ZERO REG (HI) REGISTER FUNCTION FROM B096BH

OOH ZERO REG (LO) OOH ZERO REG (LO) NOTE:

1. Reserved registers should not be written.
WHEN READ WHENWRITIEN
WSR ~O

4-107
intJ 87C196KB/83C196KB/80C196KB

SFR BIT SUMMARY'

AD-Result (LO) (02H) AD_Command (02H)

A/D CHANNEL NUMBER

STATUS:

X
.
0;; A/D CURRENTLY IDLE
=
1 CONVERSION IN PROCESS
Il
I--
X
CHANNEL # SELECTS WHICH OF THE 8
ANALOG INPUT CHANNELS IS TO BE
<;:ONVERTED TO DIGITAL FORM.

3 fo- GO INDICATES'WHEN THE CONVERSION IS TO

=
BE INITIATED (GO 1 MEANS START NOW,
GO = 0 MEANS THE CONVERSION IS TO BE
~ INITIATED BY THE HSO UNIT AT A SPECIFIED TIME).
X
I--
A/D RESULT: X SET UPPER FOUR BITS TO ZERO
LEAST SIc;lNIFICANT 2 BITS f0-
X
~

270918-7 270918-8

I
Chip Configuration (2018H) WSR (14H)

117161514131211 10 ICHIP CONFIGURATION REGISTER

121 = SFR's FUNCllON UKE SUPERSET OF 8096BH
L.:~OWERDOWN MODE ENABLE 14(111I21B) = PPW REGISTER
15(1111B)=EXCHANGE READ/WRITE REGISTERS
BUS WIDTH SELECT
(16 - BIT BUS /8- BIT BUS)
=
OTHER UNDEFINED, DO NOT USE

'--WRITE STROBE MODE SELECT

(WR AND BHE/WRI AND WRH) 121
ADDRESS VALID STROBE SELECT 121
(ALE/ ADV)
121
(IRCO) lNTERNAL READY CONTROL ENABLES HOLD/HOLDA
(IRC1) MODE
270918-10
(LOCO) }
(LOC1) PROGRAM LOCK MODE

270918-9

HSI_Mode (03H) HSLStatus (06H)

17 6 15 14 13 2 11 1 0 1 r7 6 r 5 413 211 101

L, HSI.O MODE L, HSI.O STATUS

HSI.1 MODE HSI.1 STATUS
HSI.2 MODE HSI.2 STATUS
HSI.3 MODE HSI.3 STATUS
WHERE EACH 2 - BIT MODE CONTROL FtELD WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
DEFINES ONE OF 4 POSSIBLE MODES: BIT INDICATES WHETHER OR NOT AN EVENT HAS
OCCURED ON THIS PIN AND THE UPPER BIT INDICATES
00 II POSITIVE TRANSITIONS THE CURRENT STATUS OF THE PIN.
01 EACH POSITIVE TRANSITION 270918-12
10 EACH NEGATIVE TRANSITION
11 EVERY TRANSITION
(POSITIVE AND NEGATIVE)
270918-11

4-10.8
 87C196KB/83C196KB/80C196KB

INT_PEND/INT_MASK (09H/08H) INT_PEND1/INT~MASK1 (12H/13H)

TIMER OVERFLOW TRANSMIT INTERRUPT

AID CONVERSION COMPLETE RECEIVE INTERRUPT
HSI DATA AVAILABLE HSIFIFO 4
HIGH SPEED OUTPUTS TIMER 2 CAPTURE
HSI.O PIN TIMER 2 OVERFLOW
SOFTWARE TIMER EXTINT PIN
SERIAL PORT HSI 1'11'0 FULL
EXTERNAL INTERRUPT (EXTINT NMI (SET TO 0)
OR PO.7 PIN)
270918-14
270918-13

SP_CON(11H)
BIT. 1, BIT.O SPECIFY THE MODE
0.0 = MODE 0 1.0 = MODE 2 X
0.1 = MODE 1 1. 1 = MODE 3 X

PEN ENABLE THE PARITY FUNCTION RECEIVE OVERRUI'l ERROR

W
R REN ENABLES THE RECEIVE FUNCTION: TRANSMITIER EMPTY
I
T TB8PROGRAMS THE 9TH DATA BIT FRAMII'lG ERROR
E
TRAI'lSMIT INDICATOR
RECEIVE INDICATOR
RECEIVE PARITY ERROR

270918-15 270918-16

HSO Command (OSH)

CHANNEL: 0-5 HSO.O - HSO.5 II'lDIVIDUALLY
BIT: HSO.O AND HSO.l
7 HSO.2 AND HSO.3
8-B SOFTWARE TIMERS
C- 0 RESERVED FOR FUTURE USE
RESET TlMER2
START AID CONVERSIOI'l
INTERRUPT I NO INTERRUPT
SET I CLEAR
TIMER 2/TIMER 1
LOCK CAM
270918-17,

4-109
 87C 196KB/83C,196KS/80C196KB

10SO (15H) lOCO (15H)

HSO.O CURRENT STATE HSI.O INPUT ENABLE I DISABLE·

HSO.l CURRENT STATE TIMER 2 RESET EACH WRITE
HSO.2 CURRENT STATE HSI.1 INPUT ENABLE I DISABLE
HSO.3 CURRENT STATE TIMER 2 EXTERNAL RESET ENABLE I DISABLE
HSO.4 CURRENT STATE H$I.2 INPUT ENABLE I DISABLE
HSO.5 CURRENT STATE TIMER 2 RESET SOURCE HSI.O I T2RST
CAM QB HOLDING REGISTER IS FULL HSI.3 INPUT ENABLE I DISABLE
HSO HOLDING REGISTER IS FULL TIMER 2 CLOCK SOURCE HSI.l /. T2CLK
270918-18 270918-19

IOS1 (16H) 19C1 (16H)

SOFTWARE TIMER 0 EXPIRED o SELECT PWM I SELECT P2.5

SOFTWARE TIMER 1 EXPIRED EXTERNAL INTERRUPT ACH7 I EXTINT
SOFTWARE TIMER 2 EXPIRED TIMER 1 .oVERFLOW INTERRUPT ENABLE I DISABLE
SOFTWARE TIMER 3 EXPIRED TIMER 2 OVERFLOW INTERRUPT ENABLE I DISABLE
TIMER 2 HAS OVERFLOW HSO.4 OUTPUT ENABLE I DISABLE
TIMER 1 HAS OVERFLOW SELECT TXD I SELECT P2.0
HSI FIFO IS FULL HSO.5 OUTPUT ENABLE I DISABLE
HSI HOLDING REGISTER DATA AVAILABLE HSI INTERRUPT
FIFO FU LL I ;oH""OL"D'"IN"'G""RE"'G'"IS"'T""ER"'L"OAOiD'"E"'D
270918-20
270918-21

IOS2(17H) IOC2 (OBH)

INDICATES WHICH HSO EVENT OCCURED
ENABLE FAST INCREMENT OF T2
HSO.O ENABLE T2 AS UP IDOWN COUNTER
HSO.l
ENABLE +2 PRESCALER ON PWM
HSO.2 X (SET TO l'J)
HSO.3 AID CLOCK PRESCALER ·DISABLE
HSO.4 T2 ALTERNATE INTERRUPT @ BOOOH
HSO.5 ENABLE LOCKED CAM ENTRIES
T2RESET CLEAR ENTIRE CAM
START AID 270918-23
270918-22

4·110
 87C196KB/83C196KB/80C196KB

ELECTRICAL CHARACTERISTICS NOTICE: This data sheet contains preliminary infor-

mation on new products in prqduction. The specifica-
tions are subject to change without notice.
Absolute Maximum Ratings* • WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
Ambient Temperature
These are stress ratings only. Operation beyond the
Under Bias ...................... O°C to + 70°C
"Operating Conditions" is not recommended and ex-
Storage Temperature .......... - 65°C to + 150°C tended exposure beyond the "Operating Conditions"
Voltage On Any Pin to Vss ........ -0.5V to + 7.0V may affect device reliability.
Power Dissipation .......................... 1.5W

Operating Conditions
Symbol Description Min Max Units
TA Ambient Temperature Under Bias 0 +70 °C

Vce Oig.ital Supply Voltage 4.50 5.50 V

VREF Analog Supply Voltage 4.50 5.50 V

fose Oscillator Frequency 3.5 12 MHz

NOTE:
ANGND and Vss should be nominally at the same potential.

D.C. Characteristics (Over Specified Operating Conditions)

Symbol Description Min Max Units Test Conditions
VIL Input Low Voltage -0.5 0.8 V

VIH Input High Voltage (Note 1) 0.2 Vee + 0.9 Vee + 0.5 V

VIH1 Input High Voltage on XTAL 1 0.7 Vee Vee + 0.5 V

VIH2 Input High Voltage on RESET 2.6 Vcc + 0.5 V

VOL Output Low Voltage 0.3 V IOL = 200 p,A

0.45 V IOL = 3.2 rnA
1.5 V IOL = 7 rnA

VOH, Output High Voltage Vee - 0.3 V IOH = -200 p,A

(Standard Outputs) Vee - 0.7 V IOH = -3.2mA
Vee - 1.5 V IOH = -7 rnA

VOH1 Output High Voltage Vee - 0.3 V IOH= -10 p,A

(Quasi-bidirectional Outputs) Vee - 0.7 V IOH = -30 p,A
Vee - 1.5 V IOH = -60 p,A
III Input Leakage Current (Std. Inputs) ±10 p,A 0< VIN < Vee - 0.3V
ILl1 Inpu~ Leakage Current (Port 0) +3 p,A 0< VIN < VREF
ITL 1 to 0 Transition Current (QBO Pins) -650 p,A VIN = 2.0V
IlL Logical 0 Input Current (QBO Pins) -50 p,A VIN = 0.45V
11L1 Logical 0 InPllt Current in Reset (Note 2) -1.2 rnA VIN = 0.45 V
(ALE, RD, WR, BHE, INST, P2.0)
Hyst Hysteresis on RESET Pin 300 mV (Note 3)

NOTES:
1. All pins except RESET and XTAL 1.
2. Holding these pins below VIH in Reset may cause the part to enter test modes.
3. Not guaranteed for the 87C196KB.
4-111
inter 87C196KB/83C196KB/80C196KB

D.C. Characteristics (Continued)

Symbol Description Min Typ(7) Max Units Test Conditions

Icc Active Mode Current in Reset 40 55 rnA XTAL 1 = 12 MHz
AID Converter Reference Current 2 5 rnA Vcc = Vpp = VREF = 5.5V
IREF
IIDLE Idle Mode Current 10 22 rnA
.-.
ICCl Active Mode Current 15 22 rnA XTAL 1 = 3.5 MHz
Ipo Powerdown Mode Current 5 50 !LA Vcc = Vpp = VREF = 5.5V
RRST Reset Pullup Resistor 6K 50K n
Cs Pin Capacitance (Any Pin to Vss) 10 pF fTEST = 1.0 MHz

NOTES:
(Notes apply to all specifications)
1. QBD (Quasi-bidirectional) pinS Include Port 1, P2.6 and P2.7.
2. Standard Outputs include ADO-15, RD, WR, ALE, SHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
TXD/P2.0, and RXD (in serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
3. Standard Inputs include HSI pins, CDE, EA, READY, SUSWIDTH, NMI, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3, and
T2RST IP2.4. '
4. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below Vee - 0,7V: /
IOl on Output pins: 10 mA
IOH on quasi-bidirectional Pins: self limiting
IOH on Standard Output pins: lOrnA
5. Maximum current per bus pin (data and control) during normal operation is ± 3.2 rnA.
6. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6 IOl: 29 mA IOH is self limiting
HSO, P2.0, RXD, RESET IOl: 29 mA IOH: 26 rnA
P2.5, P2,7, WR, SHE IOl: 13 mA IOH: 11 mA
ADO-AD15 IOl: 52 mA IOH: 52 mA
RD, ALE, INST-CLKOUT IOl: 13 rnA IOH: 13 mA
7, Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and VREF = Vee = 5V,

60r-----,------,-----,

50

40 ---],1''---..,../ Icc TYPICAL (7)

ICC 30 I-----+-----;,~____:.....'---__t
rnA

10 --±..-"""'---+-----=o~ IIDLE TYPICAL

O'--____-L-____-L..____- J
4MHz 8MHz 12MHz
ICC Max = 3.88 x FREQ + 8.43 FREQ
IIDLE Max = 1.65 x FREQ + 2.2 270918-24

Figure 7. Icc and IIDLE vs Frequency

4-112
 87C196KB/83C196KB/SOC196KB

A.C. Characteristics
For use over specified operating conditions
Test Conditions: Capacitive load on ali pins = 100 pF, Rise and fali times = 10 ns, fosc = 12'MHz

The system must meet 'these specifications to work with the 80C196KB: (Note 1)

Symbol Description Min Max , Units Notes-

\
TAVYV Address Valid to Ready Setup
87C196KB10/83C196KB10 2Tose - 90 ns
87C196KB12/83C196KB12/80C196KB 2Tose ,- 85 ns

hLYV ALE Low to READY Setup

80C196KB Tose - 65 ns
87C196KB10/83C196KB10 Tose - 80 ns
87C196KB12/83C196KB12 Tose - 72 ns
TYLYH Non READY Time No upper limit ns
TeLYX READY Hold after CLKOUT Low 0 Tose - 30 ns (Note 2)
TLLYX READY Hold after ALE Low Tose - 15 2Tose - 40 ns (Note 2)
TAVGV Address Valid to Buswidth Setup 210se - 85 ns
TLLGV ALE Low to Buswidth Setup
80C196KB Tose - 60 ns
87C196KB/83C196KB Tosc - 70 ns
TCLGX Buswidth Hold after CLKOUT Low 0 ns
TAVDV Address Valid tq Input Data Valid
80C196KB 3Tosc - 60 ns
(Note 3)
87C196KB10/83C196KB10 3Tosc- 70 ns
87C196KB12/83C196KB12 3Tosc - 67 ns
TRLDV RD Active to Input Data Valid
87C196KB10/83C196KB10 Tose - 30 ns (Note 3)
87C196KB12/83C196KB12/80C196KB Tosc - 23 ns
TCLDV CLKOUT Low to Input Data Valid Tosc - 50 ns
TRHDZ End of RD to Input Data Float Tosc - 20 ,Os
TRXDX ' Data Hold after RD Inactive 0, ns

NOTES:
1. Customers whose applications require an 83C1'96KB to meet the 80C196KB specifications listed above should contlict an
Inte.l Field Sales Representative,
2. If max is exceeded, additional wait states will occur.
3. When using wait states, add 2TOSC x n, where n = number of wait states.

4-113
 87C196KB/83C196KB/80C196KB

A.C. Characteristics
For use over specified operating conditions
Test Conditions: Capacitive load on all pins = 100 pF, Rise and f~1I times ~ 10 ns, fosc = 12 MHz
The 80~196KB will meet these specifications: (Note 1)
Symbol Description Min Max Units Notes
FXTAL Frequency on XTAL1
87C196KB10/83C196KB10 3.5 10 MHz (Note 2)
87C196KB12/83C196KB12/80C196KB 3.5 12 MHz (Note 2)
Tosc II FXTAL
87C196KB10/83C196KB10 100 286 ns
87C196KB12/83C196KB12/80C196KB 83 286 ns
TXHCH XTAL 1 High to CLKOUT High or Low 40 110 ns (Note 3)
TCLCL CLKOUT Cycle Time 2Tosc ns
TCHCL CLKOUT High Period Tosc - 10 Tosc+ 10 ns
TCLLH CLKOUT Falling Edge to ALE Rising -5 15 ,ns
TLLCH ALE Falling Edge to CLKOUT Rising -15 15 ns
TLHLH' ALE Cycle Time 4Tosc ns (Note 5)
TLHLL. ALE High Period Tosc - 10 Tosc+ 10 ns
TAVLL Address Setup to ALE Falling Edge Tosc - 20
TLLAX Address Hold after ALE Falling Edge Tosc - 40 ns
TLLRL ALE Falling Edge to RD Falling Edge
80C196KB Tosc - 30 ns
87C196KS/83C196KS Tosc - 40, ns
TRLCL RD Low to CLKOUT Falling Edge 5 30 ns
TRLRH RD Low Period Tosc - 5 Tosc + 25 ns (Note 5)
TRHLH RD Rising Edge to ALE ,Rising Edge Tosc Tosc + 25 ns (Note 4)
TRLAZ RD Low to Address Float 10 ns
TLLWL ALE Falling Edge to WR Falling Edge Tosc - 10 ns
TCLWL CLKOUT Low to WR Falling Edge 0 25 ns
TQVWH Data Stable to WR Rising Edge
87C196KB10/83C196KB10 Tosc - 30 ns (Note 5)
87C196KB12/83C196KB12/80C196KB Tosc - 23 ns
TCHWH CLKOUT High to WR Rising Edge -10 10 ns
TWLWH WR Low Period Tosc - 30 Tosc +5 ns . (Note 5)

TWHQX Data Hold after WR Rising Edge Tosc - 10 ns

TWHLH WR Rising Edge to ALE Rising Edge Tosc - 10 Tosc + 15 ns (Note 4)
TWHBX BHE, INST Hold after WR Rising Edge Tosc -10 ns
TRHBX BHE, INST Hold after RD Rising Edge Tose - 10 ns
TWHAX AD8-15 Hold afterWR Rising Edge Tosc - 50 ns
TRHAX AD8-15 Hold after RD Rising Edge Tosc - 25 ns

NOTES:
Tosc = 83.3 ns at 12 MHz; Tosc = 100 ns at 10 MHz. " .
1. Customers whose applications require an 83C196KB to meet the 80C196KB specifications listed above should contact an
Intel Field Sales Representative.
2. Testing performed at 3.5 MHz. However. the part is static by design and will typically operate below 1 Hz.
3. Typical specification, not guaranteed.
4. Assumingback-to-back "bus cycles.
5. When using wait states, add 2Tosc x n, where n = number of wait states,
4.114
inter 87C 196KB/83C 196KB/80C196KB

System Bus Timings

XTAL1

CLKOUT

ALE

BUS

BUS --<. ADDRESS OUT •. DATA OUT }~~(_ _AD_D_RE_S_S_ _ __

I LtRHBX.
itWHBX

BHE.INST VALID

AD8-15 ADDRESS OUT

270918-25

4-115
 87C196KB/83C196KB/80C196KB

READY Timings (One Waitstate)

XTAL1

CLKOUT

ALE

READY

_+_______ 1 - - - - - tRLRH + 2Tose ---4--------

tRLDV + 2Tose
1 - - - - - - - - - tAvDV + 2Tose
==='
-------1--..1
~--AD-DR-ES-S-OU-T--~) (~-M-TA--»-»)~»~--------
I

_~~~~~~~~~~~~~~~~
r l~.---
~:.:~~-----tW-L-W-H
....
~
...+-2-T-os-e-4
tQVWH + 2Tose

~--A-D-DR-E-SS-·-OU-T--.u~~(~------D-AT-A-O-U-T-----~X~__A_DD_R_ES_S__
I
270918-26

Buswidth Timings

XTAL1

'~::: ~ .~~~ ] r- .~:.,,) ~ ~ ~

BUSWIDTH _ _ -----~'----------------
I--- t AVGV ---l I
BUS
-{ ~-----)~---------- 270918-27

4-116
inter 87C196KB/83C196KB/80C196KB

HOLD/HLDA TIMINGS
Symbol Descrlptl~n Min Max Units Notes
THVCH HOLD Setup 1
80C196KB 75 ns.
87C196KB/83C196KB 85
TCLHAL CLKOUT Low to HLDA Low . -15 15 ns
TCLBRL CLKOUT Low to BREQ Low -15 15 ns
THALAZ HLDA Low to Address Float
80C196KB 15 ns
87C196KB/83C196KB 20
THALBZ HLDA Low to BHE, INST, RD, WR Float ns
TCLHAH CLKOUT Low to HLDA High -15 15 ns
TCLBRH CLKOUT Low to BREQ High -15 15 ns
THAHAX HLDA High to Address No Longer Float -5 ns
THAHBV HLDA High to BHE, INST, RD, WR Valid -20 ns
TCLLH CLKOUT Low to ALE High -5 15 ns

NOTE:
1. To guarantee recognition at next clock.

BUS -<~ ____

BHE,INST ,,
Rii,WR

,ACE r---\.
.-' ~!-I----~.II
!-_ _ _tC_LL_H 1.~
~.~
. "'-_____
270918-28

4-117
inter 87C196KB/83C196KB/80C196KB

EXTERNAL CLOCK DRIVE

'Symbol Parameter Min Max Units
1/TxLXL ' Oscillator Frequency
80C196KB10 3.5 10.0 MHz
80C196KB12 3.5 12.0 MHz
TXLXL Oscillator Frequency
80C196KB10 100 286 ns
80C198KB12 83 286 ns
TXHXX High Time 32 ns
TXLXX Low Time 32 ns
TXLXH Rise Time 10 ns
TXHXL Fall Time 10 ns

EXTERNAL CLOCK DRIVE WAVEFORMS

270918-29

, An external oscillator may encounter as much as a 100 pF load at XTAL 1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external Signal meets the VIL and
VIH specifications the capacitance will not exceed 20 pF.

A.C. TESTING INPUT, OUTPUT WAVEFORM FLOAT WAVEFORM

0.45
2 . 4 = X 2.0"
0.8
;> TEST POINTS < 2.0
0.8
>C
270918-30
A.C. Testing inputs are driven at 2,4V for a Logic "I" and 0,45V , 270918-31
for a LogIc "0" Tlmlng'measurements are made at 2.0V for a For TImIng Purposes a Port Pin is no Longer Floating when a
Logic "I" and 0,8V for a Logic "0" 100 mV change from Load Voltage Occurs and Begins to Float
when a 100 mV change from the Loaded VOHIVOL Level occurs
IOLIiOH = ±15 mAo

EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions: Signals:
H '" High A - Address HA - Rti5A
L ~Low B -~ L - ALE/ADV
V - Valid BR - BREO Q - DATA OUT
x - No Longer Valid C ,- CLKOUT R - RD
Z - Floating D - DATA IN W - Wi=i/WRH/'fRL
G - Buswidth X - XTAL1
( H - HOiJj \ Y - READY

. 4-118
 87C196KB/83C196KB/80C196KB

EPROM SPECIFICATIONS

A.C. EPROM Programming Characteristics

Operating Conditions: Load Capacitance = 150 pF, TA = +25°C ±5°C, Vee, VREF = 5V, Vss, ANGND =
OV, Vpp = 12.75V ± 0.25V, EA = 12.75V ± 0.25

Symbol Description Min Max Units

TSHLL Reset High to First PALE Low 1100 Tosc

TLLLH PALE Pulse Width 40 Tosc

TAVLL Address Setup Time 0 Tosc

TLLAX Address Hold Time 50 Tosc

TLLVL PALE Low to PVER Low 60 Tosc

TpLDV PROG Low to Word Dump Valid 50 Tosc

. TpHDX Word Dump Data Hold 50 Tosc

TDVPL Data Setup Time 0 Tosc

TpLDX Data Hold Time 50 Tosc

TpLPH PROG Pulse Width 40 Tosc

TPHLL PROG High to Next PALE Low 120 Tosc

TLHPL PALE High to PROG Low 220 Tosc

TpHPL PROG High to Next PROG Low 120 Tosc

TpHIL PROG High to AINC Low 0 Tosc

TILIH AINC Pulse Width 40 Tosc

TILVH PVER Hold after AINC Low 50 Tosc

TILPL AINC Low to PROG Low 170 Tosc

TPHVL PROG High to PVER Low 90 TOsc

NOTE:
1. Run Time Programming is, <;lone with Fosc = 6.0 MHz to 12.0 MHz, VREF =: 5V ± 0.65V. TA = + 25'e to ±5'e and
Vpp = j'2.75V. For run-time programming over a full operating range, contact the factory. '

D.C. EPROM Programming Characteristics

Symbol Description
Ipp Vpp Supply Current (When Programming)

NOTE:
Vpp must be within 1V of Vee while Vee < 4.5V. Vpp must not have a low impedance path to ground or \ISS while
Vee> 4.5V.

4·119
 intJ· \ 81C196KB/83C196KB/80C196KB.

. EPROM PROGRAMMING WAVEFORMS

StAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE

PORTS
3/4 --t--~~~~~~

PVER

270918-32

\
SLAVE PROGRAM MODE IN WORD ,DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT·

, ~', .
''

270918-33

SLAVE PROGRAMMiNG MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT

pbRTS
3/4 ( ACOR/COMMAND >--< ADDR

DATA )>--------«
AODR+ 2

DATA >--

PVER

tPHIL

270918-34

4-120
inter 87C196KB/83C196KB/80C196KB

A:C. CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE

SERIAL PORT TIMING-SHIFT REGISTER MODE

Symbol . Parameter Min Max Units
TXLXL Serial Port Clock Period (BRR 2 8002H) 6 Tose ns.

TXLXH Serial Port Clock Falling Edge 4 Tose ±50 ns

to 8ising Edge (BRR 2 13002H) ,
TXLXL Serial Port Clock Period (BRR = 8001 H) 4 Tose ns
TXLXH Serial Port Clock Falling Edge 2 Tose ±50 ns
to Rising Edge (BRR = 8001 H)

TQVXH Output Data Setup to Clock Rising Edge 2 Tose -50 ns

TXHQX Output Data Hold after Clock Rising Edge 2 Tose ~50 ns
TXHQV Next Output Data Valid after Clock Rising Edge 2 Tosc +50 ns

TDVXH Input Data Setup to Clock RiSing Edge Tosc +50 ns

TXHDX Input Data Hold after Clock Rising Edge 0 ns

TXHQZ Last Clock Rising to Output Float 1 Tose ns

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE

SERIAL PORT WAVEFORM-SHIFT REGISTER MODE

270918-35

4-121
 87C196KB/83C196,KB/80C196KB

A TO D CHARACTERISTICS ,stability of ,V REF .. VREF must ,be ,close to Vee sinc~ it

supplies both the resistor ladder and the digital sec-
There are two modes of AID operation: with or with- tion of the converter.
out clock prescaler. The speed of the AID converter
. can be adjusted by. setting a clock prescaler on or '
off. At high frequencies more time is needed for the AID CONVERTER SPECIFICATIONS
comparator to settle. The maximum frequency with
the clock prescaler disabled is 8 MHz. The conver- The specifications given below assume adherence
sion times with the prescaler turned on or off is to the Operating Conditions section of this data
shown in the table below. sheet. Testing is performeci with VREF = 5.12V.,

The converter is ratiometric, so the absolute

accuracy is, directly dependent on the accuracy and

Clock Prescaler On Clock Prescaler Off ,

IOC2.4 = 0 10C2.4 = 1
158 States 91 States
26.33 fJos @ 12 MHz 22.75 fJos @ 8 MHz

Parameter Typle&I(1) Minimum Maximum Units· Notes

Resolution 512 1024 Levels
9 10 Bits
Absolute Error 0 ±4 LSBs
Full Scale Error 0.25 :to.50 LSBs
"

" Zero Offset Error -0.25 ±0.50 LSBs I

Non-Linearity Error 1.5 ±2.5 0 ±4 LsBs

Differential Non-Linearity Error >-1 +2 LsBs
Channel-to~Channel Matching ±0.1 0 ±1 LSBs
Repeatability ±0,25 LsBs
Temperature Coefficients:
. Offset 0.009 LsB/oC
Full Scale 0.009 ,LsBI"C
Differentilil Non-Linearity 0.009 LsBrC,
Off Isolation -60 dB 2,3
Feedthrough -60 dB 2
Vee Power Supply Rejecti~n -60 dB 2
Input Resistance 1K 5K n
D.C. Input Leakage 0 3.0 fJoA
Sample Time: Prescaler On 15 States ,4
Prescaler Off 8' States 4
Input Capacitance 3 pF

NOTES:
·An "LSB", as used here, has a value ot approxh:nately 5 mV. '
1. Typical values are expect~d tor most devices at 25°e but are not tested or guaranteed.
2. De to 100 KHz.
3. Multiplexer Break-Betore-Make Guaranteed.
4. One state = 167 ns at 12 MHz, 250 ns at 8 MHz.

, 4-122
inter 87C196KB/83C196KB/80C196KB

AID GLOSSARY OF TERMS IDEAL CHARACTERISTIC-A characteristic with

its first code transition at VIN = 0.5 LSB, its last
ABSOLUTE ERROR-The maximum difference be- code transition at VIN = (VR6F - 1.5 LS6) and all
tween corresponding actual and ideal code tran- code widths equal to one LSB.
sitions. Absolute Error accounts for all deviations of
an actual converter from an ideal converter. INPUT RESISTANCE-The effective series resist-
ance from the analog input pin to the sample capaci-
ACTUAL CHARACTERISTIC-The characteristic tor.
of an actual converter. The characteristic of a given
converter may vary over temperature, supply volt- LSB-Least Significant Bit: The voltage corre-
age, and frequency conditions. An actual character- sponding to the full scale voltage divided by 2n,
istic rarely has ideal first and last transition locations where n is the number of bits of resolution of the
or ideal code widths. It may even vary over multiple converter. For an 8-bit converter with a reference
conversions under the same conditions. voltage of 5.12V, one LSB is 20 mV. Note. that this is
different than digital LS6s, since an uncertainty of
BREAK-BEFORE-MAKE-The property of multi- two LSB, when referring to an AID converter, equals
plexer which guarantees that a previously selected 40 mY. (This has been confused with an uncertainty
channel will be deselected before a new channel is of two digital bits, which would mean four counts, or
selected (e.g., the converter will not short inputs 80 mV.)
together).
NON-LINEARITY-The maximum deviation of code
CHANNEL-TO-CHANNEL MATCHING-The, differ- transitions of the terminal based characteristic from
ence between corresponding code transitions of the corresponding code transitions of the ideal char-
actual characteristics taken from different channels acteristic.
under the same temperature, voltage and frequency
conditions. OFF-ISOLATION-Attenuation of a voltage applied
on a deselected channel of the AID converter. (Also
CHARACTERISTIC-A graph of input voltage referred to as Crosstalk.)
versus the resultant output code for an AID convert-
er. It describes the transfer function of the AID con- REPEATABILITY-The difference betweencorre-
verter. sponding code transitions from different actual char-
acteristics taken from the same converter on the
CODE-The digital value output by the converter. same channel at the same temperature, voltage and
frequency conditions.
CODE TRANSITION-The point at which the con-
verter changes from an output code of Q, to a code RESOLUTION-The number of input voltage levels
of Q + 1. The input voltage corresponding to a code that the converter can unambiguously distinguish
transition is defined to be that voltage which is between. Also defines the number of useful bits of
equally likely to produce either of two adjacent information which the converter can return.
codes.
SAMPLE TIME-Begins when the sample capaCitor
CODE WIDTH-The voltage correspondin,g to the is attached to a selected channel and ends when
difference between two adjacent code transitions. the sample capacitor is disconnected from the se-
lected, channel.
D.C. INPUT LEAKAGE-leakage current to ground
from an analog input pin. TEMPERATURE COEFFICIENTS-Change in the
stated variable per degree centigrade temperature
DIFFERENTIAL NON-LiNEARITY-The difference change. Temperature coefficients are added to the
between the ideal and actual code widths of the ter- typical values of a specification to see the effect of
minal based characteristic. temperature drift.

FEEDTHROUGH-Attenuation of a voltage applied TERMINAL BASED CHARACTERISTIC-An actual

on the selected channel of the AID Converter after characteristic which has been rotated and translated
the sample window closes. to remove zero offset and full scale error.

FULL SCALE ERROR-The difference between the Vee REJECTION-Attenuation of noise on the Vee
expected and actual input voltage corresponding to line to the AID converter.
the full scale code transition.
ZERO OFFSET-The difference between the ex-
pected and actual input voltage corresponding to
the first code transition. .
4-123
 87C 196KB/83C196KB/80C196KB

80C196KB FUNCTIONA,L DEVIATIONS DIFFERENCES BETWEEN THE'

80C196KA AND THE 80C196KB
The aOC196KB has the following problems.
1. The DJNZW instruction is not guaranteed to be The aXC196KB is Identical to aXC19'6KA except for
functional. The instruction, if encountered, will not the following differences.
. cause an unimplemented opcode interrupt. (The 1. ALE is high after reset on the aOC19GKB instead
opcode for DJNZW is OE1 Hex.) The DJNZ (byte) of low as on the aOC196KA.
instruction works correctly and should be used in-
2. The DJNZW instruction is not guaranteed to work
stead.
on the aOC196KB.
2. The CDE function is not guaranteed to work. The 3. The RQ[iJ/HLDA bus protocol is available on the
CDE pin must be directly connected to Vss. aOC196KB.
3. The HSI unit has two errata: one dealing with res-
olution and the other with first entries into the
FIFO. CONVERTING FROM OTHER 8096BH
The HSI resolution is 9 states instead of a states: FAMILY PRODUCTS TO THE
Events on the same line may be lost if they occur 80C196KB
faster than once every 9 state times.
There is a mismatch between the 9 s~atetime HSI The following list of suggestions for designing an
resolution and the a state time timer. This causes a09XBH system will yield a design that is easily con-
one time value to be unused every 9 timer counts. verted to the aOC196KB.
Events may receive a time-tag one count later 1. Do not base critical timing loops on instruction or
than expected because of this "skipped" time val- peripheral execution times.
ue. 2. ·Use equate statements to set all timing parame-
If the first two events into an empty FIFO (not ters, including the baud rate.
including the Holding Register) occur in the same 3. Do not base hardware timings on CLKOUT or
internal phase, both are recorded with one time- XTAL1. The timings of the aOC196KB are differ-
tag. Otherwise, if the second event occurs within ent than those of the 8X9XBH, but they will func-
9 states after the first, its time-tag is one count tion with standard ROM/EPROMlPeriphera:i type
later than the first's. If this is the "skipped" time memory systems.
value, the second event's time-tag is 2 counts lat-
er than the first's. 4. Make sure all inputs are tied hjgh or low and not
left floating.
If the FIFO and Holding Register are empty, the
first event will· transfer into the Holding Register 5. Indexed and indirect operations relative to the
after a state times, leaving the FIFO empty again. stack pOinter (SP) work differently on the
If the second event occurs after this time, it will aOC196KB than on the a096BH. On the a096BH,
act as a new first event into an empty FIF~. the address is calculated based on the un-updat-
ed version of the stack pointer. The aOC196KB
4. The serial port Framing Error flag fails to indicate uses the updated version. The offset for POP[SPj
.an error if the bit preceding the stop bit is a 1. This and POP nn[SPj instructions may need to be,
is the case in both the a-bit and 9-bit modes. changed .by a count of 2.
False framing errors are never generated.
6. The VPD pin On the a096BH has changed to a
Vss pin on the aOC196KB.

4-124
 87C196KB/83C196KB/80C196KB

DATA SHEET REVISION HISTORY

This data sheet is valid for the CPU and ROM devices which have a "B" suffix on th~ topside tracking number.
The 87C196 mayor may not have the suffix on the topside number.

This is a new data sheet that integrates the 87C196KB (order number 270590-003) and the 83C196KBI
80C196KB (order number 270634-003) data sheets.

The following differences exist between this data sheet (-001) and each of the above mentioned data sheets.
1. The status of the data ,sheet was upgraded from ADVANCE INFORMATION to PRELIMINARY.
2. The warning about the ABSOLUTE MAXIMUM RATINGS was reworded and a notice of disclaimer was
added to the electrical specific,<!tions section.
3. VIH2 was increased from2.2V to 2.6V.
4. IlL 1 was increased from - 950 p.A to -'-1.2 mA. This change was documented in the previous revision of the
data sheets but the D.C. Characteristics table did not reflect the change. ' ,
5. Maximum Ipo specification was added to the D.C. table and Ipo note was deleted.

4-125
 87C196KB16
16-BIT HIGH PERFORMANCE CHMOS
MICROCONTROLLER
• 8232KBytes of On-Chip EPRO,M
• Dynamically Configurable 8-Bit or
16-Bil Buswidth
• Register-to-Register
Byte Register File
• Full
• 28 Interrupt Sources/16 Arch.itecture Duplex Serial Port

• 2.3 J-I-s 16 x 16 Multiply (12Vectors

• 4.0 J-I-s 32116 Divide (12 MHz)MHz)
• Powerdown and Idle Modes
-.• High Speed 110 Subsystem
16-Bit Timer

• Pulse-Width-Modulated
16-Bit Up/Down Counter with Capture

• Five • Four 16-Bit Software Timers

Output

• 16-Bit8-Bit 110 Ports • 10-Bit A/D Converter with Sample/Hold

• Watchdog Timer • HOLD/HLDA Bus Protocol
•
The 87Ci96KBi6 is a i6-bit microcontroller with 8 Kbytes of on-chip EPROM and a high performance mem-
ber of the MCS®-96 microcontroller family. The 87Ci96KBi6 is compatible and uses a true superset of the
8096BH instructions. Intel's CHMOS process provides a high performance processor along with low power
consumption. To further reduce power requirements, the processor can be placed into Idle or Powerdown
Mode. 111 the rest of this document, the device will be referred to as 87C196KB.

Bit, byte, word and some 32-bit operations are available on the 87C196KB. With a 16 MHz oscillator a i6-bit
addition takes 0.50 ,...,S, and the instruction times average 0.37 ,...,S to 1.1 ,...,S in typical applications.

Four high-speed capture inputs are provided to record times when.events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an AID conversion. Events can be based on the timer or upldown counter.

AI:;;o provided on-chip are an AID converter, serial port, watchdog timer, and a pulse-width-modulated output
signal.

V Ef ANGND

CONTROL
SIGNALS

} ~~f:
BUS

PORT 4

~
HSO
270909-1 '
Figure 1. 87C196KB Block Diagram

November 1990
4-126 Order Number: 270909-001
inter 87C196KB16

ARCHITECTURE
The 87C196KB is a member of the MCS®·96 family, and as such has the same architecture and uses the
same instruction set as the 8096BH. Many new features 'have been added on the 87C196KB including:

CPU FEATURES

Divide by 2 instead of divide by 3 clock for 1.5X performance

Faster instructions, especially indexed/indirect data operations

1.75 ""S 16 x 16 multiply with 16 MHz clock (6.25 ""S on the 8096BH)
Faster interrupt response (almost twice as fast as 8096BH)

Powerdown and Idle Modes

5 new instructions including Compare Long and Block, Move

8 new interrupt vectors/6 new interrupt sources

PERIPHERAL FEATURES

SFR Window switching allows read·only registers to' be written and vice-versa

Timer2 can count up or down by external selection

Timer2 has an independent capture register

HSO line events are stored in a register

HSO has CAM Lock and CAM Clear commands

New Baud Rate values are needed for serial port, higher speeds possible in all modes

Double buffered serial port transmit register

Serial Port Receive Overrun and Framing Error Detection

PWM has a Divide-by-2 Prescaler

HOLD/HLDA Bus Protocol

4-127
 inter 87C196KB16
.---~-- -------_.---_...

PACKAGING
The 87C196KB is available in a 68-pin PLCC (One-Time Programmable) package, Contact your local sales
office to determine the exact ordering code for the part desired: .

PLCC Description PLCC Description PLCC Description

9 ACH7 IPO, 7/PMD3 54 AD6/P3.6 31 P1 ..6/HLDA
8 ACH6/PO.6/PMD2 53 AD7/P3.7 30 P1.5/BREQ
7 ACH2JPO,2 52 AD8/P4.0 29 HSO,1
6 ACHO/PO.O 51 AD9/P4.1 28 HSO.O
5 ACH1/PO.1 50 AD10/P4,2 27 HSO.5/HSI.3/SID3
4 ACH3/PO.3 49 AD11/P4,3 26 HSO,4/HSI.2/SID2
3 NMI 48 AD12/P4,4 25 HSI.1/SID1
2 EA 47 AD13/P4.5 24 HSI.O/SIDO
Vee .46 AD14/P4.6 23 P1,4
68 Vss 45 AD15/P4.7 22 P1.3
67 XTAL1 44 T2ClK/P2,3 21 P1.2
66 XTAL2 43 READY 20 P1.1
65 CLKOUT 42 T2RST IP2,41 AINC 19 P1.0
64 BUSWIDTH 41 BHE/WRH 18 TXD/P2,0/PVER
63 INST 40 WR/WRL 17 RXD/P2,1/PALE
62 ALE/ADV 39 PWM/P2.5, 16 RESET
61 RD 38 P2.7/T2CAPTURE/PACT 15 EXTINT IP2.2/PROG
60 ADO/P3,0 37 Vpp 14 Vss
\' ~'
59 AD1/P3,1 36 Vss 13 VREF
58 AD2/P3,2 i35 HSO..3 12 ANGND
57 AD3/P3,3 34 HSO.2 11 ACH4/POA/PMDO
,
56 ' AD4/P3,4 33 P2.6/T2UP-DN 10 ACH5/PO,5/PMD1
'---_._--
55 AD5/P3,5 32 P1.7/HOLD
-
Figure 2. Pin Definitions

4-128
 87C196KB16

8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
ACH5/PO.5 / ADO/P3.0
~--------~-------
ACH4/PO.4 AD1/P3.1
ANGND AD2/P3.2
V REF 13 AD3/P3.3
VSS 14
MCS®-96 AD4/P3.4
EXTINT/P2.2 15 68 PIN A05/P3.5
RESET 16 PLCC AD6/P3.6
RXD/P2.1 17 AD7/P3.7
TXO/P2.0 18 A08/P4.0
P1.0 51 AD9/P4.1
P1.1 TOP VIEW AD10/P4.2
P1.2 ADI1/P4.3
LOOKING DOWN ON
P1.3 ADI2/P4.4
P1.4
COMPONENT SIDE ADI3/P4.5
HSIO OF PC BOARD AOI4/P4.6
HSII ADI5/P4.7
HSI2/HS04 26 T2CLK/P2.3
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

5 '"0 >'"
......
o ..
~ I~I~,"-~ ~
." 0 f'; Col
0 0 0 '" .. 0:
> ~
,!2
III
x x
III
~~~~cL III
x x
III
"-
< 'Iii!
.:'i
~ ~ ~ 'In
IX
"- 0:

III 10ttl~ 1<1 0

~
9 <.5 .t::.. u
"- l!'i
x :J: ::I: U)
N '"
t::.. >-
"- "
N
0.
270909-2

Figure. 3. 68-Pin Package (PLCC-Top View)

Thermal Characteristics

4-129
intef " 87C196KB16

PIN DESCRIPTIONS
I
Symbol Name and,Function
Vee Main supply voltage (5V). ~

Vss Digital circuit ground (OV). There are three Vss pins, all of them must be connected.
VREF Reference voltage for the AID converter (5V). VREF is also the supply voltage to the analog
portion of the AID converter and the logic used to read Port O. Must be connected for AID
and Port 0 to function.
ANGND Reference ground for the AID converter. Must be held at nominally the same potential as
Vss·
Vpp Programming voltage. Also timing pin for the return from power down circuit. Connect this pin
with a 1 /LF capacitor to Vss. If this function is not used, connect to Vee.
XTAL1 Input of the oscillator inverter and of the internal clock generator.
XTAL2 Output of the oscillator inverter.
CLKOUT Output of the internal clock generator. The frequency of CLKOUT is% the oscillator
frequency. It has a 50% duty cycle.
RESET Reset input to the chip. Input low for at least 4 state times to reset the chip. The subsequent
low-to-high transition re- synchronizes CLKOUT and commences a 10-state-time sequence in
which the PSW is cleared, a byte read from 2018H loads CCR, and a jump to location 2080H
is executed. Input high for normal operation. RESET has an internal pullup.
BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is ai, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit
cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
NMI A positive transition causes a vector through 203EH.
INST Output high during an external memory read indicates the read is an instruction fetch and
output low indicates a data fetch. INST is valid throughout the bus cycle. INST is activated
only during external memory accesses.
EA Input for memory select (External Access). EA equal to a TIL-high causes memory accesses
to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM. EA equal to a
TTL-low causes accesses to these locations to be directed to off-chip memory.
ALE/ADV Address Latch Enable or Address Valid output, as selected by CCA. Both pin options provide
a latch to demultiplex the address from the address/data ,bus. When the pin is ADV, it goes
inactive high at the end of the bus cycle. ADV can be used as a chip select for external
memory. ALE/ ADV is activated only during external memory accesses.
RD Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL Write and Write Low output to external memory, as selected by the CCA. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.
BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCR. BHE = 0
selects the bank of memory that is connected to the high byte of th,e data bus. AO = 0
selects the bank of memory that is connected to the low byte of the data bus. Thus accesses
to a i6-bit wide memory can be to the low byte only (AO = 0, BHE = 1), to the high byte only
(AO = 1, BHE = 0), or both bytes (AO = 0, BHE = 0). If the WRH function is selected, the
pin will go low if the bus cycle is writing to an odd memory location. BHE/WRH is valid only
during 16-bit external memory write cycles.

4-130
infef 87C196KB16

PIN DESCRIPTIONS (Continued)

,
Symbol Name and Function
READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. If the pin is high, CPU operation continues in a normal manner. If the pin is
low prior to the faning edge of CLKOUT, the memory cory troller goes into a wait mode until the
hext positive transition in CLKOUT occurs with READY high. When the external memory is
not being used, READY has no effect. Internal control of the number of wait states inserted
into a bus cycle (held not ready) is available through configuration of CCR,.
HSI Inputs to High Speed Input Unit. Four HSI pins are availa9le: HSI.O, HSI.1, HSI.2, and HSI.3.
" Two of them (HSI.2 and HSI.3) ar~ shared with the HSO Unit. The HSI pins are also used as
the SID in Slave Programming Mode.
HSO Outputs from High Speed Output Unit. Six HSO pins are ,available: HSO.O, HSO.1, HSO.2,
HSO.3, HSO.4, and HSO.5. Two of them (HSO.4 and HSO,5) are shared with the HSI Unit.
PortO 8-bit high impedance input-only port. Three pins can be used as digital inputs and/or as
analog inputs to the on-Chip AID converter. These pins set the Programr:ning Mode.
Port 1 8-bit quasi-bidirectional I/O port. These pins are shared with HOLD, HLDA and BREQ.
Port 2 8-bit multi-functional'port. All of its pins are shared with other functions in the 87C196KB.
Ports3-and4 8-bit bi-directionalllO ports with open drain'outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pull ups.
HOLD Bus Hold input requesting control of the bus. Enabled by setting WSR. 7.
HLDA Bus Hold acknowledge output indicating release of the bus. Enabled by setting WSR.7.
BREQ Bus Request outPl,lt activated when the bus controller has a pe.nding external memory cycle.
Enabled by setting WSR. 7.
TxD The TxD pin is used for serial port transmission in Modes 1, 2, a,nd 3, The TxD function is
enabled by setting IOC1 ,5. In mode 0 the pin is used as the serial clock output.
RxD .Serial Port Receive pin used for serial port reception. The RxD function is enabled by setting
SPCON.3. In mode 0 the pin iunction~ as input or O!)tput data.
EXTINT A rising edge on the EXTINT pin will generate an external interrupt. EXTINT is selected as the
external interrupt source by setting IOC1. thigh. ,
T2CLK The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.
T2RST A rising edge on the T2RST pin will reset Timer2. The external reset function is enabled by
setting IOCO.3. T2RST is enabled as the reset source by clearing IOCO.5.

4-131
 inter, 87C1'96KB16 '

PIN DESCRIPTIONS (Continued)

Symbol Name and Function
PWM Port 2.5 can be enabied as a PWM output by setting IOC1.0. The duty cycle of 'the PWM is
determined by the vallte loaded into the PWM-CONTROL register (17H).
T2UPDN The T2UPDN pin controls the direction of Timer2 as an up or down counter. The Timer2
up/Qown function is enabled by setting IOC2.1. /

T2CAP A rising edge on P2.7 will capture the value of Timer2 in the T2CAPTURE register (location
OCH in Window 15). ' ,
PMODE Programming Mode Select. Determines the EPROM programming algorithm that is
performed. PMqDE is sampled after a chip reset and should be static while the part is
operating.
SID Slave 10 Number. Used to assign each slave a pin of Port 3 or 4 to use for passing
programming verification acknowledgement. For example, if gang programming in the Slave
Programming Mode, the slave with SID = 001 will use Port 3.1 to signal correct or incorrect
program verification.
pALE ' Programming ALE Input. Accepted by the 87C196KB when it is in SI~lVe Programming Mode.
Used to indicate that Ports 3 and 4 oontain a command/address. '
~ Programming. Falling edge indicates valid data on PBUS and the beginning of progfamming.
Rising edge indicates end of programming.
PACT Programming Active. Used in the Auto Programming Mode to indicate when programming
activity is complete.
1", "
PVAL Program Valid. This signal indicates the success or failure of programming in the Auto
I, Programming Mode. A zero indicates successful programming.
PVER Program Verification. Used in Slave Programming and Auto CLB Programming Modes. Signal
is low after rising edge of PROG if the programming was not successful.
AING Auto Increment. Active low signal indicates that the auto increment mode is enabled. Auto
Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
PORTS Address/CommandlData Bus. Used to pass commands, addresses, and data to and from
slave mode 87C196KBs. Used by chips in Auto Programming Mode to pass command,
addresses and data to slaves. Also used in the Auto Programming Mode as a regular system
bus to access external memory. Should have pull ups to Vee (15 kO).

4-132
inter 87C196KB16

NEW INSTRUCTIONS
The following five instructions have been added to the 8096BH instruction set for the 87C196KB.

PUSHA - PUSHes the PSW, IMASK, IMASK1, and WSR

(Used instead of PUSHF when new interrupts and registers are used.)
assembly language format: PUSHA
object code format: <11110100>
bytes: 1
states: on-chip stack: 12
off-chip stack: 18
POPA - POPs the PSW, IMASK, IMASK1, and WSR
(Used instead of POPF when new interrupts and registers are used.)
assembly language format: POPA
object code format: < 11110101 >
bytes: 1
states: on-chip stack: 12
off-chip stack: 18
IDLPD - Sets the part into Idle or Powerdown Mode
assembly language format: IDLPD # key (key= 1 for Idle, key = 2 for Powerdown.)
object code format: <11110110> <key>
bytes: 2
states: legal key: 8
illegal key: 25

CMPL - Compare 2 long direct values

assembly language format: DST SRC
CMPL Lreg, Lreg
object code format: < 11 000101 > < src Lreg> < dst Lreg>
bytes: 3 '
states: 7

BMOV - Block move using 2 auto-incrementing pointers and a counter

assembly language format: ,PTRS CNTREG
BMOV Lreg, wreg
object code format: < 11 000001 > < wreg > < Lreg >
bytes: 3
states: internal/internal: 8 per transfer + 6
external/internal: 11 per transfer + 6
external/external: 14 per transfer + 6

4-133
 inter 87C196KB16

USING THE ALTERNATE REGISTER WINDOW (WSR= 15)

I/O register,expansion on the new CHMOS members of the MCS-96 family has been provided by making three
register windows available. switching between these windows is done using the Window Select Register
(WSR). The PUSHA and POPA instructions can be used to push and pop the WSR and second interrupt mask
when entering or leaving interrupts, so it is easy to change between windows.

On the 87C196KB only Window 0, Window 14 and Window 15 are active. Window 0 is a true superset of the
standard 8096EiH SFR space, while Window 15 allows the read-only registers to be written and write-only
registers to be read. The only major exception to this is the Timer2 register which is the Timer2 capture register
in Window 15. The writeable register for Timer2 is in Window O. There are also some minor changes and
cautions. Window 14 contains the Programmable Pulse Width register (PPW) at location 14H. The descriptions
of the registers which have different functions in Window 15 than in Window 0 are listed below,:
AD_COMMAND (02H) - Read the last written command
AD_RESULT (02H, 03H) - Write a value into the result register
HSI_MODE (03H) - Read the value in HSLMODE
HSI_TIME (04H,05H) - Write'to FIFO Holding register
HSO_TIME (04H,05H) - Read the last value placed in the holding register
HSI_STATUS (06H) - Write to status bits but not to HSI pin bits. (Pin bits are 1,3,5,7).
HSO_COMMAND (06H) - Read the last value placed in the holding register
SBUF(RX) (07H) - Write a value into the receive buffer
SBUF(TX) (07H) - Read the last value written to the transmit buffer
WATCHDOG(OAH) - Read the value in the upper byte of the WDT
TIMER1 (OAH,OBH) - Write a value to Timer1
, TIMER2 (OCH,ODH) - Read/Write the Timer2 capture register.
Note that Timer2 read/write is done with WSR = o.
IOC2 (OBH) - Last written value is readable, except bit 7 (note 1)
BAUDRATE (OEH) - No function, cannot be read
PORTO (OEH) - No function, no output drivers on the pins. Registers reserved.
PORT1 (OFH) - IOPORT1 cannot be read or written in Window 15. Register reserved.
SP_STAT (11 H) - 8et the status bits, TI and RI can be set, but it will not cause an interrupt
SP_CON (11 H) - Read the current control byte
1080 (15H) - Writing to this register controls the HSO pins. Bits 6 and 7 are inactive for writes.
lOCO (15H) - Last written value is readable, except bit 1 (note 1)
IOS1 (16H) - Writing to this register will set the status bits, but not cause interrupts. Bits 6 and
7 are, not functional' .
IOC1 (16H) - Last written value is readable
1082 (17H) - Writing to this register will set the status bits, but not cause interrupts.
PWM_CONTROL (17H) - Read the duty cycle value written to PWM_CONTROL

NOTE:
1. IOC2.7 (CAM CLEAR) and IOCO.1 (T2RST) are not latched and will read as a 1 (precharged bus) .

Being able to write to the read-only registers and vice-versa provides a lot of flexibility. One of the most useful
advantages is the ability to set the timers and HSO lines for initial conditions other than ,zero.

Reserved registers may be used for testing or future features. Do not write to these registers. Reads from
reserved registers will return indeterminate values.

4-134
inter 87C196KB16

MEMORY MAP 87C196KBINTERRUPTS

Vector
OFFFFH Number Source Priority
Location
EXTERNAL MEMORY OR 1/0
4000H INT15 NMI 203FH 15
INTERNAL ROMIEPROM OR
EXTERNAL MEMORY INT14 HSI FIFO Full 203CH 14
20S0H
INT13 EXTINTPin 203AH 13
RESERVED
2040H INT12 TIMER2 Overflow 2038H 12
UPPER S INTERRUPT VECTORS
2030H INT11 TIMER2 Capture 2036H 11
ROMIEPROM SECURITY KEY INT10 4th Entry into HSI FIFO 2034H 10
2020H
RESERVED INT09 RI 2032H 9
2019H
INT08 TI 2030H 8
CHIP CONFIGURATION BYTE
201SH SPECIAL Unimplemented Opcode 2012H N/A
RESERVED
SPECIAL Trap 2010H N/A
2014H
LOWER SINTERRUPT VECTORS INT07 EXTINT 200EH 7
PLUS 2 SPECIAL INTERRUPTS
2000H INT06 Serial Port 200CH 6
PORT 3 AND PORT 4
INT05 Software Timer 200AH 5
lFFEH
EXTERNAL MEMORY OR 1/0 INT04 HSI.O Pin 2008H 4
0100H
INT03 High Speed Outputs 2006H 3
INTERNAL DATA MEMORY - REGISTER FILE
(STACK POINTER, RAM AND SFRS) INT02 HSI Data Available 2004H 2
EXTERNAL PROGRAM CODE MEMORY
OOOOH
INT01 AID Conversion Complete 2002H 1
INTOO Timer Overflow 2000H 0

19H
STACK POINTER 19H STACK POINTER
ISH ISH
17H 'IOS2 17H PWM_CONTROL
16H 10SI 16H lOCI
15H 10SO 15H lOCO
14H 'WSR 14H 'WSR
13H 'INT_MASKI 13H 'INT_MASKI
12H 'INT_PENDI 12H 'INT_PENDI
llH 'SP~STAT llH 'SP_CON
10H PORT2 10H PORT2 10H RESERVED(1)
OFH PORTI OFH PORT1 OFH RESERVED(1 )
OEH PORTO OEH BAUD RATE OEH RESERVED(1)
ODH TIMER2(HI) ODH TIMER2(HI) ODH 'T2 CAPTURE (HI)
OCH TIMER2 (LO) OCH TIMER2 (LO) OCH 'T2 CAPTURE (LO)
OBH TIMER 1 (HI) OBH 'IOC2 /
WSR ~ 15
OAH TIMER 1 (LO) OAH WATCHDOG
09H INT_PEND 09H INT PEND ,OTHER SFRS IN WSR 15 BECOME
INT_MASK OSH INT MASK READABLE.
OSH
IF THEY WERE WRITABLE
07H SBUF(RX) 07H SBUF(TX) IN WSR ~ OANDWRITABLE IFTHEY
06H HSI STATUS 06H HSO COMMAND WERE READABLE IN WSR ~ 0
05H HSI TIME (HI) 05H HSO_TIME (HI)
04H HSI TIME (LO) 04H HSO_TIME (LO) 4H I PPW I
03H AD_RESULT (HI) 03H HSLMODE WSR ~ 14
02H AD_RESULT (LO) 02H AD_COMMAND
01H ZERO REG (HI) 01H ZERO REG (HI) 'NEW OR CHANGED REGISTER
ZERO REG (LO) OOH ZERO REG (LO) FUNCTION FROM S096BH
OOH
NOTE:
WHEN READ WHENWRITIEN
WSR ~O 1. RESERVED REGISTERS SHOULD
Nor BE WRITIEN

4-135
inter 87C196KB16

SFR BIT SUMMARY

... AD_RESULT (LO) {02H}

~l-
CHANNEL # SELECTS WHICH OF THE 8
A/D CHANNEL NUMBER ANALOG INPUT CHANNELS IS TO BE
CONVERTED TO DIGITAL FORM.
STATUS:
0= A/D CURRENTLY ID.LE 3 - GO INDICATES WHEN THE CONVERSION IS TO
1 = CONVERSION IN PROCESS - BE INITIATED (GO = 1 MEANS START NOW,
x X GO = 0 MEANS THE CONVERSION IS TO BE
X INITIATED BY THE HSO UNIT AT A SPECIFIED TIME).
X
A/D RESULT:
- X SET UPPER FOUR BITS TO ZERO
\ LEAST SIGNIFICANT 2 BITS -
270909-4
- X

270909-5

CCR {2018H} WSR (14H)

IL7 lsJ 5141 3J 2111 0 ICHIP CONFIGURATION REGISTER

L.: POWERDOWN MODE ENABLE
1
0 = SFR's FUNCTION LIKE SUPERSET OF 809SBH
14 (111 OB) = PPW REGISTER
15 (1111 B) = EXCHANGE. READ/WRITE REGISTERS
BUS WIDTH SELECT
(lS - BIT BUS /8- BIT BUS)
OTHER = UNDEFINED, 00 NOT USE

-WRITE STROBE MODE SELECT

(WR AND BHE/WRL AND WRH) o
ADDRESS VALID STROBE SELECT o
(ALE/ ADV)
o
(IRCO) }'NTERNAL READY CONTROL ENABLES HOLD/HOLDA
(IRC1) MODE
270909-7
(LOCO) }
(LOC1) PROGRAM LOCK MODE

270909-6

HSI_STATUS {OSH}

I7 sI5 41 3 12 I 1 I 0 I

I L HSI.O STATUS
HSI.1 STATUS.
' - - - - - - - - H S I . 2 MODE HSI.2 STATUS
' - - - - - - - - - - H S I . 3 MODE HSI.3 STATUS
WHERE EACH 2 - BIT MODE CONTROL FIELD WHERE FOR EACH 2 - BIT STATUS .FIELD THE LOWER
DEFINES ONE OF 4 POSSIBLE MODES: BIT INDICATES WHETHER OR NOT AN EVENT HAS
. OCCURED ON THIS PIN AND THE UPPER BIT INDICATES
00 8 POSITIVE TRANSITIONS THE CURRENT STATUS OF THE PIN.
01 EACH POSITIVE TRANSITION 270909-9
10 EACH NEGATIVE TRANSITION
11 EVERY TRANSITION
(POSITIVE AND NEGATIVE)
270909-8.

4-136
 87C196KB16

SFR BIT SUMMARY

IOSO(15H) lOCO (15H)

HSO.O CURRENT STATE HSI.O INPUT ENABLE I DISABLE

HSO.l CURRENT STATE TIMER 2 RESET EACH WRITE
HSO.2 CURRENT STATE HSI.l INPUT ENABLE I DISABLE
HSO.3 CURRENT STATE TIMER 2 EXTERNAL RESET ENABLE I DISABLE
HSO.4 CURRENT STATE HSI.2 INPUT ENABLE I DISABLE
HSO.5 CURRENT STATE TIMER 2 RESET SOURCE HSI.O I T2RST
CAM ~ HOLDING REGISlER IS FULL HSI.3 INPUT ENABLE I DISABLE
HSO HOLDING REGISTER IS FULL TIMER 2 CLOCK SOURCE HSt.l I T2CLK
270909-10 270909-11

IOS1 (16H) IOC1 (16H)

SOFTWARE TIMER 0 EXPIRED SELECT PWM I SELECT P2.5

SOFTWARE TIMER 1 EXPIRED EXTERNAL INTERRUPT ACH7 I EXTINT
SOFTWARE TIMER 2 EXPIRED TIMER 1 OVERFLOW INTERRUPT ENABLE I DISABLE
SOFTWARE TIMER 3 EXPIRED TIMER 2 OVERFLOW INTERRUPT ENABL~ I DISABLE
TIMER 2 HAS OVERFLOW HSO.4 OUTPUJ ENABLE I DISABLE
TIMER 1 HAS OVERFLOW SELECT TXD I SELECT P2.0
HSI FIFO IS FULL HSO.5 OUTPUT ENABLE I DISABLE
HSI HOLDING REGISTER DATA AVAILABLE HSI INTERRUPT
FIFO FULL I ;'H"'OL"D'"IN"'G~RE"'G'"IS-'T""ER"'L"OA"D"E"'D
270909-12
270909-13

IOS2 (17H) IOC2(OBH)

INDICATES WHICH HSO EVENT OCCUR ED
ENABLE FAST INCREMENT OF T2
HSO.O ENABLE T2 AS UP jDOWN COUNTER
HSO.l ENABLE +2 PRESCALER ON PWM
HSO.2 X (SET TO 0)
HSO.3 AID CLOCK PRESCALER DISABLE
HSO.4 T2 ALTERN'ATE INTERRUPT @ 8000H
HSO.5 ENABLE LOCKED CAM ENTRIES
T2RESET CLEAR ENTIRE CAM
START AID 270909-15
270909-14

4-137
 87C196KB16

SFR BIT SUMMARY

INLPEND/INLMASK (09H/08H) INLPEND1/INLMASK1 (12H/13H)

TIMER OVERFLOW o TRANSMIT INTERRUPT

A/D CONVERSION COMPLETE RECEIVE INTERRUPT
HSI DATA AVAILABLE HSI FIFO 4
HIGH SPEED OUTPUTS TIMER 2 CAPTURE
HSI.O PIN TIMER 2 OVERFLOW
SOFTWARE TIMER EXTINT PIN
SERIAL PORT HSI FIFO FULL
EXTERNAL INTERRUPT (EXTINT NMI (SET TO 0)
OR PO.7 PIN)
270909-17
270909-16

SP_STAT(11H)
BIT.1, BIT.O SPECIFY THE MODE
o O.O=MODEO 1.0=MODE2
O. r = MODE 1 1.1 = MODE 3

2 PEN ENABLE THE PARITY FUNCTION RECEIVE OVERRUN ERROR

W
R REN ENABLES THE RECEIVE FUNCTION: TRANSMITTER EMPTY
I
T TB8 PROGRAMS THE 9TH DATA BIT FRAMING ERROR
E
TRANSMIT INDICATOR
RECEIVE INDICATOR
RECEIVE PARITY ERROR

270909-18 270909-19

HSO_COMMAND (06H)
CHANNEL: 0-5 HSO.O - HSO.5 INDIVIDUALLY

BIT: ]6 HSO.O AND HSO.1

7 HSO.2 AND HSO.3
8-B SOFTWARE TIMERS
C-D RESERVED FOR FUTURE USE
E RESET TIMER2
F START A/D CONVERSION
INTERRUPT / NO INTERRUPT
SET /CLEAR
TIMER 2/TIMER 1
LOCK CAM
270909-20

4-138
inter 87C196KB16

ELECTRICAL CHARACTERISTICS NOTICE: This data sheet contains information on

products in the sampling and initial production phases
of development. It is valid for the devices indicated in
Absolute Maximum Ratings* the revision history. The specifications are subject to
change without notice.
Ambient Temperature
• WARNING: Stressing the device beyond the "Absolute
Under Bias ...................... O°C to + 70°C
Maximum Ratings" may cause permanent damage.
Storage Temperature .......... - 65°C to + 150°C These are stress ratings only. Operation beyond the
Voltage On Any Pin to Vss ........ -0.5V to + 7.0V "Operating Conditions" is not recommended and ex,
tended exposure beyond the "Operating Conditions"
Power Dissipation .......................... 1.5W may affect device reliability.

Operating Conditions
Symbol Description Min Max Units
TA Ambient Temperature Under Bias 0 +70 °C
Vee Digital Supply Voltage 4.50 5.50 V

VREF Analog Supply Voltage 4.50 5.50 V

fose Oscillator Frequency 3.5 16 MHz

NOTE:
ANGND and Vss should be nominally at the same potential.

D.C. Characteristics: (Over Specified Operating Conditions)

Symbol Description Min Max Units Test Conditions
VIL Input Low Voltage -0.5 0.8 V

VIH Input High Voltage (Note 1) 0.2 Vee + 0.9 Vee + 0.5 V

VIH1 Input High Voltage on XT AL 1 0.7 Vee Vee + 0.5 V

VIH2 Input High Voltage on RESET 2.6 Vee + 0.5 V

VOL Output Low Voltage 0.3 V IOL = 200 fLA

0.45 V IOL = 3.2 mA
1.5 V IOL = 7mA
VOH Output High Voltage Vee - 0.3 V IOH = - 200 fLA
(Standard Outputs) Vee - 0.7 V IOH = -3.2 mA
Vce- 1.5 V IOH = -7mA
VOH1 Output High Voltage Vee - 0.3 V IOH = -10 fLA
(Quasi-bidirectional Outputs) Vee - 0.7 V IOH = -30 fLA
Vee - 1.5 V IOH = -60 fLA
III Input Leakage Current (Std. Inputs) ~

±10 fLA o < VIN < Vee - 0.3V

ILl1 Input Leakage Current (Port 0) +3 . fLA 0< VIN < VREF
ITL 1 to 0 Transition Current (QBD Pins) -650 fLA VIN = 2.0V
IlL Logical 0 Input Current (QBD Pins) -50 fLA VIN = 0.45V
IIL1 Logical 0 Input Current in Reset -6 mA VIN = 0.45V
ALE, RD, INST (Note 2)
Hyst. Hysteresis on RESET Pin 300 mV

NOTES:
1. All pins except RESET and XTAL 1.
2. Holding these pins below VIH in Reset may cause the P!lrt to enter test modes.
4-139
 87C196KB16

DC,, Characteristics (Continued)

"
,Symbol Description Min Typ(7) Max Units Test Conditions
Icc Active Mode Current in Reset 50 60 rnA XTAL1 = 16 MHz
Vcc = Vpp = VREF = 5.5V
IREF AID Converter Reference Current 2 5 rnA

IIDLE Idle Mode Current 10' 25 rnA

'ICCl Active Mode Current 15 25 rnA XTAL 1 = 3.5 MHz

Ipo Powerdown Mode Current 5 30 /-I- A Vcc = Vpp = VREF = 5.5V

RRST Reset Pullup Resistor 6K 50K n

Cs Pin Capacitance (Any Pin to VSS) r 10 pF fTEST = 1.0 MHz

NOTES:
(Notes apply to all specifications)
1. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.
2. Standard Outputs include ADO-15, RD, WR, ALE, SHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
TXD/P2.0, and RXD (in serial mode 0). The VQjj specification is' not valid for RESET. Ports 3 and 4 are open-drain outputs.
3. Standard Inputs include HSI pins, CDE, EA, READY, BUSWIDTH, NMI, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3, and
T2RST IP2.4.
4. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
, below Vee - 0.7V: '
IOl on Output pins: 10 mA
IOH on quasi-bidirectional pins: self limiting
IOH on Standard Output pins: 10 mA
5. Maximum current per bus pin (data and control) during normal operation is ± 3.2 mA.
6. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6 IOl: 29 mA IOH is self limiting
HSO, P2.0, RXO, RESET IOl: 29 mA IOH: 26 mA
P2.5, P2.7, WR, BHE IOl: 13 mA IOH: 11 mA
ADO-AD15 IOl: 52 mA IOH: 52 mA
RD, ALE, INST -CLKOUT IOl: 13 mA IOH: 13 mA
7. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and VREF = Vee = 5V.

60r-----~------_r------,-----~

50~----_+------4_------~~--~

40~----_+------~~--~~~--~

ICC
rnA 30~----_+~~--~~----+-----~

20~----_+~~---r----~~~--~

FREQUENCY
270909-21
ICC Max = 3.88 x FREQ + 8.43
IIDlE Max = .1.65 x FREQ + 2.2

Figure 4. ICC and IIDLE vs. Frequency

4-140
 87C196KB16

A.C.Characteristlcs (Over specified operating conditions)

Test Conditions: Capacitiveioad on all pins = 100 pF, Rise and fall times == 10 ns, fose = 16 MHz

The system must meet these specifications to work with the 87C196KB:

Symbol Description Min Max Units Notes

TAVYV Address Valid to READY Setup 2Tose - 75 ns
TLLYV . ALE Low to READY Setup Tose - 60 ns
TYLYH NonREADY Time No upper limit ns
TeLYX READY Hold after CLKOUT Low 0 Tose - 30 ns (Note 1)
TLLYX READY Hold after ALE Low Tose - 15 2Tose - 40 ns (Note 1)
TAVGV Address Valid to Buswidth Setup 2Tose - 75 ns
hLGV ALE Low to Buswidth Setup Tose - 60 ns
TeLGX Buswidth Hold after CLKOUT Low 0 ns
TAVDV Address Valid to Input Data Valid 3Tose - 55 ns (Note 2)
TRLDV RD Active to Input Data Valid Tose - 23 ns (Note 2)
TeLDv CLKOUT Low to Input Data Valid Tose - 50 ns
TRHDZ End of RD to Input Data Float Tose - 20 ns
TRXDX Data Hold after RD Inactive 0 ns

NOTES:.
1. If max is exceeded, additional wait states will occur.
2. When using wait states, add 2Tasc x n where n = number of wait states.

4-141
 87C196KB16

. A.C. Characteristics (Over specified operating conditions) (Continued)

Test Conditions: Capacitive loat! on all pins = 100 pF, Rise and fall times"" 10 ns, fosc "" 16MHz

The 87C196KB will meet these specifications:

,
Symbol Description Min Max Units Notes
FXTAL Frequency on XTAL 1 3.5 16.0 MHz (Note 3)
Tosc 1/ FxTAL 62.5 ' 286 ns
TXHCH XT AL 1 High to CU<OUT High or Low 40 110 ns (Note 1)
TCLCL CLKOUT Cycle Time 2Tosc ns
TCHCL CLKOUT High Period Tosc - 10 Tosc+ 10 ns
TCLLH CLKOUT Falling Edge to ALE Rising -10 10 ns
TLLCH ALE Falling Edge to CLKOUT Rising -15 15 ns
TLHLH ALE Cycle Time 4TOSC ns (Note 4)
TLHLL ALE High Period Tosc - 10 Tosc+10 ns
TAVLL Address Setup to ALE Falling Edge Tosc - 20 ns
TLLAX Address Hold after 'ALE Falling Edge Tosc - 40 ns
TLLRL ALE Falling Edge to RD Falling Edge Tosc - 35 ns
TRLCL RD Lowto CLKOUT Falling Edge 5 25 ns
TRLRH RD Low Period Tosc- 5 Tosc + 25 ns (Note 4)
TRHLH RD Rising Edge to ALE Rising Edge TosC Tosc+ 25 ns (Note 2)
TRLAZ RD Low to Address Float 5 ns
TLLWL ALE Falling Edge to WR Falling Edge Tosc - 10 ns
TCLWL CLKOUT Low to WR Falling Edge 0 25 ns
TQVWH Data Stable to WR Rising Edge Tosc 23 ns (Note 4)
TCHWH CLKOUT High to WR Rising Edge -10 10 ns
TWLWH WR Low Period Tosc - 20 Tosc + 5 ns (Note 4)
TWHQX Data Hold after WR Rising Edge Tosc - 10 ns'
TWHLH WR Rising Edge to ALE Rising Edge Tosc - 10 Tosc + 15 ns (Note 2)
TWHBX SHE, INST HOLD after WR Rising Edge Tosc - 10 ns
TRHBX SHE, INST HOLD after RD Rising Edge Tosc - 10 ns
TWHAX AD8-15 hold after WR Rising Edge Tosc - 30 ns
TRHAX AD8-15 hold after RD Rising Edge Tosc - 25 ns

NOTES:
, Tose = 83.3 ns at 12 MHz; Tosc = 100 ns at 10 MHz.
1. Typical specification, not guaranteed.
2. Assuming back-to-back bus cycles.
3. Testing performed at 3.5 MHz, however, the device is static by design and will typically operate below 1 Hz.
4. When using wait states, all 2Tose + n where n = number of wait states.

4-:142
 87C196KB16

System Bus Timings

~--------------~-------------------------------------------------------,

XTAL1

CLKOUT

. tCLLH

ALE

BUS

BUS - - (
~I
AbDRESS OUT
__ ~ _ _U DATA OUT )~\I(__A_D_DR_E_SS_ _ _ __
L tRHBX ...
itWHBX

BHE,INST VALID

AD8-15 ADDRESS OUT

270909-22

4-143
 87C196KB16

READY Timings (One Wait State)

XTAL1

CLKOUT

tCLLH

ALE

READY

- - - tRLRH + 2TOSC ---~_ _ _ _ _ _ __

tRLDV + 2TOSC ---=I

1-------- t AVDV + 2 Tose -------+1--+1
~--AD-DR-ES-S-OU-T--~) (~DA-TA~»>~»m»~--------
I

\t=-- t WLWH + 2Tosc 4

I---A-D-DR-E-SS-OU-T---»«
'-r: t AVWH + ZTose
DATA OUT
::=::j
X,--_AD_D_RE_S_S_ _
I
270909-23

Buswidth Bus Timings

XTAL1

~': ~ ,~c: J~ ~,:".)

BUSWIDTH ~-----------------
I
-":'"I.-------t~AU-G-V------1-

BUS
-{~:---------~~-----)~---------- 270909-24

4-144
 87C196KB16

HOLD/HLDA Timings
------
Symbol Description tJ!in Max Units Notes
THVCH' HOLD Setup 85 55 ris (Note 1)

TCLHAL CLKOUT Low to HLDA Low -10 20 ns

-
TCLBRL CLKOUT Low to BREQ Low -10 20 ns

THALAZ HLD-A Low to Address Float 10 ns

THALBZ HLDA Low to BHE, INST, RD, WR Float 10 ns

TCLHAH CLKOU T Low to HLDA High -15 15 ns

TCLBRH CLKOUT Low to BREQ High -15 15 ns

- ..
, ._.
THAHAX HLDA High to Address No Longer Float -10 ns

THAHBV HLDA High to BHE, INST, RD; WR Valid -10 ns

TCLLH CLKOUT Low to ALE High -5 15 ns

,--
NOTE:
1. To guarantee recognition at next clock,

Maximum Hold Latency

Max Hold Latency
------- .-
Internal Access 1.5 States
---_.
16-Bit External Execution 2.5 States
- -------.
8-Bit External 4.5 States
--_ ..

CLKOUT

BUS - { ' - _ " " ' ; "_ __

BHE,INST \ I, ,\ ,,
RD.WR ----~----~'--~!~/----~

ALE ~I-I 1--. '-______

----""'lll-I_ _ _tC_L_LH_n.J

270909-25
L-.._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .. _ _ _ _ _ _ _ _ _ _ .. _. _ _ _ _ _ _ _ _ _ _ _ _ _ _--'

4-145
inter 87C196KB16

EXTERNAL CLOCK DRIVE

Symbol Parameter Min Max Units
1/TxLXL Oscillator Frequency 3.5 16 MHz
TXLXL Oscillator Frequency 62.5 286 ns
TXHXX High Time 32 ns
TXLXX Low Time 32 ns
TXLXH Rise Time 10 ns
TXHXL Fall Time 10 ns

EXTERNAL CLOCK DRIVE WAVEFORMS

270909-26

An external oscillator may encounter as much as a 100 pF load at XTAL 1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and
VIH specifications, the capacitance will not exceed 20 pF.

A.C. TESTING INPUT, OUTPUT WAVEFORM FLOAT WAVEFORM

2.4~ 2.0> TEST POINTS

0 . 4 5 - 1 \ O.B
< 2.0
O.B.
>C
270909-27
A.C. Testing inputs are driven at 2.4V for a Logic "I" and 0.45V 270909-28
for a Logic "0" Timing measurements are made at 2.0V for a For Timing Purposes a Port Pin is no Longer Floating when a
Logic "I" and 0.8V for a Logic "0". 200 mV change from Load Voltage Occurs and Begins to Float
when a 100 mV change from the Loaded VOHIVOl Level occurs
IOl/lOH = :!; 15 mAo

EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by "T" for. time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions: Signals:
H High A - Address HA - HLDA·
L Low B - BHE L - ALE/ADV
V Valid BR - BREQ Q - DATA OUT
x No Longer Valid C - CLKOUT R - RD
z - Floating o - DATA IN W - WR/WRH/WRL
G - Buswidth x .- XTAL1
H - HOLD Y -READY

4-146
inter 87C196KB16

EPROM SPECIFICATIONS

A.C. EPROM Programming Characteristics

Operating Conditions: Load Capacitance = 150 pF. TA = + 25°C ± 5°C. Vee. VREF:' = 5V. Vss. ANGND =
OV. Vpp = 12.75V ± 0.25V. EA = 12.75V ± 0.25
Symbol Description Min Max Units
TSHLL Reset High to First PALE Low 1100 Tosc
TLLLH PALE Pulse Width 40 Tosc
TAVLL Address Setup Time 0 Tosc
TLLAX Address Hold Time 50 Tosc
hLVL PALE Low to PVER Low 60 Tosc
TpLDV PROG Low to Word Dump Valid 50 Tosc
TpHDX Word Dump Data Hold 50 Tosc
TDVPL Data Setup Time 0 Tosc
TpLDX Data Hold Time 50 Tosc
TpLPH PROG Pulse Width 40 Tosc
TpHLL PROG High to Next PALE Low 120 Tosp
TLHPL PALE High to PROG Low 220 Tosc
I
TpHPL PROG High to Next PROG Low 120 Tosc
TpHIL PROG High to AINC Low 0 Tosc
TILIH AINC Pulse Width 40 Tosc
TILVH PVER Hold after AINC Low 50 Tosc
TILPL AINC Low to PROG Low 170 Tosc
TPHVL PROG High to PVER Low 90 Tosc

NOTES:
1. Run Time Programming is done with Fosc = 6.0 MHz to 16.0 MHz. VREF = 5V ± 0.65V. TA = -i- 25°C to ± 5°e and
Vpp = 12.75V. For run-time programming over a full operating range, contact the factory.

D.C. EPROM Programming Characteristics

Symbol Description
Ipp Vpp Supply Current (When Programming)

NOTE:
Vpp must be within 1V of Vee while Vee < 4.5V. Vpp must not have a low impedance path to ground or VSS while
Vee> 4.5V.

4-147
 87C196KB16

EPROM PROGRAMMING WAVEFORMS

SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE

PORTS
3/4 --t-~~:::!~~~~

PVER

270909-29

SLAVE PROGRAM MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT

--J
I ADDR
.1 I ADDR+ 2
.1
PORTS
ADDR/COt.4t.4AND VEA: BITS/WO DUMP VER BITS/WO DUMP
3/4

-tSHLl~ tPLDV -
f-- - tPHDX ~ -+tPLDV - tPHDX· ~
/

\ f \ V
tlLPL~ -tPHPL-

i'- 270909-30

SLAVE PROGRAMMING MODE TIMING IN.DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT

PO:;! _ _ _--( .. ODR/COMMAND >---< ADDR

DATA> <
ADDR+ 2
DATA ) -

270909-31

4-148
inter 87C196KB16

A.C. CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE

SERIAL PORT TIMING-SHIFT REGISTER MODE

Symbol Parameter. Min Max Units
TXLXL Serial Port Clock Period (BRR ;;:: 8002H) 6 Tose ns
TXLXH Serial Port Cloc.k Falling Edge to Rising Edge (BRR ;;:: 8002H) 4Tose ±50 ns
TXLXL Serial Port Clock Period (BRR = 8001 H) 4 Tose ns
TXLXH Serial Port Clock Falling Edge to Rising Edge (BRR = 8001 H) 2 TosC ±50 ns
TQVXH Output Data Setup to Clock Rising Edge 2 Tose -50 ns
TXHQX Output Data Hold after Clock Rising Edge 2 Tose -50 ns
TXHQV Next Output Data Valid after Clock Rising Edge 2 Tosc +50 ns
TDVXH Input Data Setup to Clock Rising Edge Tose +50 ns
TXHDX Input Data Hold after Clock Rising Edge 0 ns
TXHQZ Last Clock Rising to Output Float 1 Tose ns

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE

•
SERIAL· PORT WAVEFORM-SHIFT REGISTER MODE

RXO-""""'-'
(IN) __J~._CC:~"L
270909-32

4·149
 87C196KB16

10-81T AID CHARACTERISTICS stability of VREF. VREF must be., close toVee since it
supplies both the resistor ladder and the digital sec-
The speed of the AID converter in the 10-bit mode tion of the converter.
can be adjusted by setting a clock prescaler on or
off. At high frequencies more time is needed for the
comparator to settle. The maximum frequency with AID CONVERTER SPECIFICATIONS
the clock prescaler disabled is 6 MHz. The conver-
sion times with the prescaler turned on or off is The specifications given below assume adherence
shown in the table below. The AD_TIME register to the Operating Conditions section of this data
has not been characterized for· the 10-bit mode. sheet. Testing is performed with VREF = 5.12V.

The converter is ratiometric, so the absolute

accuracy is directly dependent on the accuracy and

Clock Prescaler On Clock Prescaler Off

IOC2.4 = 0 IOC2.4 ='1
156.5 States 89.5 States
19.5 fJ-s @ 16 MHz 29.8 fJ-s @ 6 MHz

Parameter Typical(1) Minimum Maximum Units' Notes

Resolution 1024 1024 Levels
10 10 Bits
Absolute Error 0 ±3 LSBs
Full Scale Error 0.25 ±0.50 LSBs
Zero Offset Error -0.25 ±0.50 LSBs
Non-Linearity Error 1.5 ±2.5 0 ±3 LSBs
Differential Non-Linearity Error > -1 +2 LSBs
Channel-to-Channel Matching ±0.1 0 ±1 LSBs
Repeatability ±0.25 LSBs
Temperature Coefficients:
Offset 0.009 LSBrC.
Full Scale 0.009 LSBrC
Differential Non-Linearity 0.009 l,.SBrc
Off Isolation -60 dB 2,3
Feedthrough -60 dB 2
Vee Power Supply Rejection -60 dB 2
Input Resistance 750 1.2K n
D.C. Input Leakage 0 3.0 fJ-A
Sample Time: Prescaler On 15 States
Prescaler Off 8 States
Sample Capacitive 3 pF ,
NOTES:
'An "L$S", as used here, has a value of approximately 5 mY.
1. Typical values are expected for most devices at 25'e.
2. DC to 100 KHz.
3. Multiplexer Sreak-Sefore-Make Guaranteed.

4-150
 87C196KS16

AID GLOSSARY QF TERMS INPUT RESISTANCE-The effective serie,s resist-

ance from the analog input pin, to tf:le sample capaci-
ABSOLUTE ERROR-The 'maximum difference be- tor.
tween corresponding actual and ideal code tran-
sitions. Absolute Error accounts for all deviations of LSB-:-Least Significant Bit: The voltag~ corre-
an actual converter from an ideal converter. sponding to the full scale voltage divided by 2""
where n is the number of bits of resolution of the
ACTUAL CHARACTERISTIC-The characteristic converter. For an 8-bit converter with a reference
of an a9tual converter. The characteristic of a given voltage of 5.12V, one LSB is 20 mV. Note that this is
converter may vary over temperature, supply volt- different than digital LSBs, since an uncertainty of
age, and frequency conditions. An actual character- two LSB, when referring to an AID converter, equals
istic rarely has ideal first and I~st transition loca~ions 40 mV. (This has been confused with an uncertainty
or ideal code widths. It may'even vary over multiple of two digital bit!!, which would mean four counts, or
conversions under the same con'ditions. 80mV.)

BREAK BEFORE MAKE-The property of a multi- NON·LINEARITY-The maximum deviation of ~ode

plexer which .guarantees that a previously selected transitions of the terminal based characteristic from
channel is selected (i.e., the converter will not short the corresponding code transitions of the ideal char-
inputs together). acteristic.

CHANNEL-TO-CHANNEL MATCHING-The differ- OFF-ISOLATION-Attenuation of a voltage applied

ence between corresponding code transitions of ac- on a deselected'channel of the AID converter. (Also
tual characteristics taken from different channels un- referred to as Crosstalk.)
der the same temperature, voltage and frequency
conditions. REPEATABILITY-The difference between corre-
sponding code transitions from different actual char-
CHARACTERISTIC-A graph of input voltage ver- acteristics taken from the same converter on the
sus the resultant output code for an AID converter. same channel at the same temperature, voltage and
It describes the transfer function of the AID convert- frequency conditions.
er.
RESOLUTION-The number of input voltage levels
CODE-The digital value output by the converter.
that the converter can unambiguously distinguish
between. Also defines the number of useful bits of
CODE TRANSITION-The point at which the con-
verter changes from an output code of Q, to a code information which the converter can return.
of Q + 1. The input voltage corresponding to a code
SAMPLE TIME-The time that the sample window
transition is defined to be that voltage which is
equally' likely to produce either of two adjacent is open.
codes.
SAMPLE WINDOW-Begins when the sample ca-
CODE WIDTH-The voltage corresponding to the pacitor is attached to a selected channel and ends
difference between two adjacent code transitions. when the sample capacitor is disconnected from the
selected channel.
D.C. INPUT LEAKAGE-Leakage current to ground
from an analog input pin. TEMPERATURE COEFFICIENTS-Change in the
stated variable per degree centigrade temperature
DIFFERENTIAL NON-LINEARITY-The difference change. Temperature coefficients are added to the
between the ideal and actual code widths of the ter- typical values of a specification to see the effect of
minal based characteristic. temperature drift.

FEEDTHROUGH",,:,Attenuation of a voltage applied TERMINAL BASED CHARACTERISTIC-An actu,al

on the selected channel of the AID Converter after characteristic which has been rotated and translated
the sample window closes. to remove zero offset and full scale error.

FULL SCALE ERROR-The difference between the Vee REJECTION-Attenuation of noise on the Vee
expected and actual input voltage corresponding to line to the AlP converter.
the full 'scale code transition;
ZERO OFFSET-The difference between the ex-
IDEAL CHARACTERISTIC-A characteristic with pected and actual input voltage corresponding to
its first code transition at VIN = 0.5 LSB, its last the first code,transition.
code transition at VIN = (VREF - 1.5 LSB) and all
code widths equal to one LSB.

4-151
 87C196KB16

CONVERTING FROM OTHER 8096BH 5. Indexed and indirect operations relative- to the
stack pointer' (SP) work .differently . on the
FAMILY PRODUCTS TO THE
80C196KB than on the 8096BH. On the 8096BH,
8XC196KB the address is calculatfild baSed on the· un-updat-
The following list of suggestions for designing 'an ed version ·of the. stack pointer. The 87C196KB
879XBH system will yield· a design that is easily con- uses the updated version. The offset for POP[SPj
verted to the 87C196KB. and POP nn[SPj instructions may need to be
changed by a count of 2.
1. Do not base critical timing loops on 'instruction or
peripheral execution ti~es. ' 6. PACT has changed from the HSO.O on the
8796BH to P2. '? on the 87C196KB.
2.. Use equate statements to set all timing parame-
ters, Including the baud rate. 7. The VPD on the 8096BH has changed to a Vss
pin on the 87C196KB. .
3. Do not base hardware -timings on CLK0UT or
XTAL1. The timings of the 87C196KB are differ-
ent than those of the 8X9XBH, l;lUt they will func-
. tion with standard ROM/EPROM/Peripheral type
DATA SHEET REVISION HISTORY
. memory systems. This data sheet (version -001) is valid for devices
4. Verify that all inputs are driven high or low and net with a "C" suffix on the topside tracking number.
left floating.
This is the first version of the 87C196KB16 data
sheet.

: ,

4-152
 ~OO[gIl..O[M]OOO&OOW

83C198/80C198,83C194/80C194
16-BIT CHMOS MICROCONTROLLER
. 83C198 - 8 Kbytes of Factory Mask-Programmed ROM
80C198 -.ROMless

• 232 Byte Register File

• Full Duplex Serial Port

• Register-to-Register Architecture
• High Speed 1/0 Subsystem

• 28 Interrupt Sources/16 Vectors

• 16-Bit Timer

• 2.3 ,."s 16 x 16 Multiply (12 MHz)

• 16-Blt Counter

• 4.0 ,."s 32/16 Divide (12 MHz)

• Pulse-Width-Modulated Output

• Powerdown and Idle Modes

• Four 16-Blt Software Timers

• 16-Bit Watchdog Timer

• 10-Bit AID Converter with SamplelHold

• 8-Bit External Bus

• The 8XC194 is an 8XC198 without an
On-Chip AID Converter
The 80C198 is the low cost member of the CHMOS MCS®-96 microcontroller family. Intel's CHMOS process
provides a high performance processor along with low power consumption. To further reduce power require-
ments, the processor can be placed into Idle or Powerdown Mode.

The 83C198 is an 80C198 with 8 Kbytes on-chip ROM. In this document, the 80C198 will refer to both
products unless otherwise stated. .

Bit, byte, word and some 32-bit operations are available on the 80C198. With a 12 MHz oscillator a 16-bit
addition takes 0.66 J.A-s,and the instruction times average 0.5 J.A-s to 1.5 J.A-s in typical applications.

Four high-speed 'capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an AID conversion. Events can be based on the timer or counter.

Also provided on-chip are an AID converter, serial port, watchdog timer, and a pulse-width-modulated output
signal.

V EF ANGND

CONTROL
SIGNALS

PORT 3

ADDR /
} DATA
BUS

PORT 4

HSI
HSO
270815-1
Figure 1. 83C198/80C198 Block Diagram
MCS®-96 is a registered trademark of Intel Corporation.

October 1990
4-153 Order Number: 270815-002
 83C198/80C198,83C194/80C194

PACKAGING With AID Without AID

The BOC19B and B3C19B are available in a 52-pin ROMless NBOC19B-PLCC NBOC194-PLCC
PLCC package and an BO-pin OFP package. Contact SBOC19B-OFP SBOC194-0FP
your local sales office to determine the exact order-.
ing code for the part desired. . ROM NB3C19B-PLCC NB3C194-PLCC
SB3C19B-OFP SB3C194-,QFP
The BXC194 is an BXC19B without the AID convert-
er.

"ci c.i'" 0
..; ..;
11. 11.
I~
"" '"
:I: :I:
~ ~~ ;5
:::; N
..J
.... 8 ;:; '
.11.

"
11.

« ~ I~ > > x x >~ ~ ~ I~ « «

(.)

ACHS/PO.S AD2/P3.2
. ACH4/PO.4 . AD3/P3.3
ANGND AD4/P3.4
VREF AD5/P3.5
vss
EXTINTjP2.2
RESET
inter AD6/P3.6
AD7/P3;7
A8/P4.0
RXD/P2.1 N80C198 A9/P4.1
TXD/P2.0 TOP VIEW Al0/P4.2
HSI.O All/P4.3
HSI.l A12/P4.4
HSO.4/HSI.2 A13/P4.5
HSO.5/HSI.3 A14/P4.6

0
ci ci
N
'" .
"'''' ljl a: "! ...
I~ N ~ '"N .....
...
ci >
Vl Vl Vl
:I:
0
Vl > > ,
~
,....
11. « 11.
W 11.
:I: :I: :I:
:::;
~
11.
Vl
0::
0::
"""
..J
(.)
U")

:t
....
'" ....
'" 270815-2

Figure 2. 52-Pin PLCC Package

4-154
inter 83C198/80C198,83C194/80C194

SO-Pin Quad Flat Pack (EIAJ)

Contacts Contacts
Facing Up Facing Down

64

41

40 25 25 40
270815-3

111111111111!1!!
64 T2CLK/P2.3
AD1/P3.1 - 1 63 Vss
ADO/P3.0 2 62 READY
Rli 3 61 T2RST/P2.4
ALE/ADV - 4 60 ---"-- N.C.
INST
59 WR
Vss 58 PWt.l/P2.5
N.C. - 7 57 N.C.
XTAL2 - 8 56 Vpp
XTAL1 - 9 55 vss
Vss 10 54 vss
Vss 11
53 HSO.3
Vee 12
52 Vee
Vee 13
51 ¥ss
EA 14
50 HSO.2
Vss 15
49 N.C.
N.C. 16 48 N.C.
N.C. 17
.47 N.C.
N.C. 18
46 N.C.
N.C. 19
45 HSO.1
ACH6/PO.6 20
44 HSO.O
ACH7/PO.7 21 43 HSO.5/HSI.3
N.C. 22 42 ¥ss
ACH5/PO.5 23
~ ~ ::. ~ ~ :il ;;; ~ ::l ~ :ll ~ ::; :ll Sl
HSO.4/HSI.2
ACH4/PO.4 24 ;f 41

!llllll!!!l!!l!!

270815-4

Figure 3. SO-Pin Quad Flat Pack (QFP)

4·155
inter 83C198/80C198,83C194/80C194

PIN DESCRIPTIONS
Symbol Name and Function
Vee Main supply voltage (5V).
Vss The PLCC package has 5 VSS pins and the QFP package has 12 VSS pins. All must be
connected to circuit ground.
VREF Reference voltage for the AID converter (5V). VREF is also the supply voltage to the
analog portior;J of the AID converter and the logic used to read Port O. Must be
connected for AID and Port 0 to function.
ANGND Reference ground for the AID converter. Must be held at nominally the same potential
as Vss.
Vpp Timing pin for the return from powerdOwn circuit. Connect this pin with a 1 p.F capacitor
to Vss. If this function is not used. connect to Vee. This pin is the programming voltage
on the EPROM device.
XTAL1 Input of the oscillator inverter and of the internal clock generator.
XTAL2 Output of the oscillator inverter.
RESET Reset inpl,lt to the chip. Input low for at least 4 state times to reset the chip. The
subsequent low-to-high transition commences the Reset Sequence in which the PSW is
cleared. a byte read from 2018H loads CCR. and a jump to location 2080H is executed.
Input high for normal operation. RESET has an internal pull up.
INST Output high during an external memo!), read indicates the read is an instruction fetch.
INST is valid throughout the bus cycle. INST is activated only during external memory
accesses and output low for a data fetch.
EA Input for memory select (External Access). EA equal to a TTL-high causes memory
accesses to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM.
EA equal to a TTL-low causes accesses to these locations to be directed to off-chip
memory.
ALE/ADV Address Latch Enable or Address Valid output. as selected by CCR. Both pin options
provide a latch to demultiplex the address from the addressl data bus. When the pin is
ADV. it goes inactive high at the end of the bus cycle. ADV can be used as a chip select
for external memory. ALEI ADV is activated only during external memory accesses.
RD Read signal output to external memory. RD is activated-only during external memory
reads.
WR Write output to external memory. WR will go low for every external write.

4-156
inter . 83C198/80C198, 83C194/80C194

PIN DESCRIPTIONS (Continued)

Symbol Name and Function
READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic
memory, or for bus sharing. If the pin is high, CPU operation continues in a normal
manner. When the external memory is not being used, READY has no effect. Internal
control of the number of wait states inserted into a bus cycle held not ready is available
through configuration of CCR.
HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2, and
HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1,
HSO.2, HSO.3, HSO.4, and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the
HSI Unit.

Port ° 4-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter. These pins set the Programming Mode on
the EPROM device.
Port 2 Multi-functional port. All of its pins are shared with other functions in the 80C198.
Ports 3 and 4 8-bit bi-directionall/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pull ups. Available as I/O only
on the ROM and EPROM devices.
TxD
°
The TxD pin is used for serial port transmission in Modes 1, 2, and 3. The TxD function is
enabled by setting IOC1 5. In mode the pin is used as the serial clock output.
RxD
°
Serial Port Receive pin used for serial port reception. The RxD function is enabled by
setting SPCON.3. In mode the pin functions as input or output data.
EXTINT A positive transition on the EXTINT pin will generate an external interrupt. EXTINT is
selected as the external interrupt source by setting IOC1.1 high.
T2CLK The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.
T2RST A rising edge on the T2RST pin will reset Timer2. The external reset function is enabled
by setting IOCO.03 T2RST is enabled as the reset source by clearing IOCO.5.
PWM Port 2.5 can be enabled as a PWM output by setting IOC1.0 The duty cycle of the PWM
is determined by the value loaded into the PWM-CONTROL register (17H).

4-157
 83C198/80C198,83C194/80C194

MEMORY MAP

OFFFFH
EXTERNAL MEMORY OR 1/0
4000H
INTERNAL ROMIEPROM OR
EXTERNAL MEMORY
2080H
RESERVED
2040H
UPPER 8 INTERRUPT VECTORS
2030H
ROMIEPROM SECURITY KEY
2020H
RESERVED
2019H
CHIP CONFIGURATION BYTE
2018H
RESERVED
1--- 2014H,
LOWER 8 INTERRUPT VECTORS
PLUS 2 SPECIAL INTERRUPTS
2000H
PORT 3 AND PORT 4
1FFEH
EXTERNAL MEMORY OR 1/0
0100H
INTERNAL DATA MEMORY· REGISTER FILE
(STACK POINTER, RAM AND SFRS)
EXTERNAL PROGRAM CODE MEMORY
OOOOH

1'9H 19H
STACK POINTER STACK POINTER
18H 18H
17H IOS2 17H PWM CONTROL
16H IOS1 16H IOC1
15H 1050 15H lOCO
14H WSR 14H WSR
13H INT_MASK1 13H INT_MASK1
12H INT_PEND1 12H INT_PEND1
11H SP_STAT 11H SP_CON
10H PORT2 10H PORT2 10H RESERVED (1)
OFH RESERVED (1) OFH RESERVED (1) OFH RESERVED (1)
OEH PORTO OEH BAUD RATE OEH RESERVED (1)
ODH TIMER2 (HI) ODH TIMER2(HI) ODH RESERVED (1)
OCH TIMER2 (LO) OCH TIMER2 (LO) OCH RESERVED (1)
OBH TIMER1 (HI) OBH IOC2
WSR ~ 15
OAH TIMER1 (LO) OAH WATCHDOG
OSH INT PENDING 09H INT PENDING OTHER SFRS IN WSR
08H INT MASK 08H INT MASK 15 BECOME READABLE
IF THEY WERE WRITABLE
07H SBUF.(RX) 07H SBUF(TX) INWSR ~ OANDWRITABLE
06H HSI_STATUS 06H HSO_COMMAND IF THEY WERE READABLE
INWSR ~ 0
05H 'HSI_TIME (HI) 05H HSO_TIME (HI)
04H HSI_TIME (LO) 04H HSO_TIME (LO)
03H AD RESULT (HI) 03H HSI MODE
02H AD RESULT (LO) 02H AD COMMAND
01H ZERO REG (HI) 01H ZERO REG (HI)
OOH ZERO REG (LO) OOH ZERO REG (LO) 'NOTE,
1. Reserved registers should not be written.
WHEN READ WHEN WRITTEN
WSR =0

4-158
intJ 83C198/80C198,83C194/80C194

SFR BIT SUMMARY

AD-Result (LO) (02H) AD_Command (02H)

AID CHANNEL NUMBER

STATUS:

X
o = AID CURRENTLY IDLE
1 = CONVERSION IN PROCESS
II CHANNEL # SELECTS WHICH OF THE 4
ANALOG INPUT CHANNELS IS TO BE
CONVERTED TO DIGITAL FORM.

3 '"- GO INDICATES WHEN THE CONVERSION IS TO

-
X
=
BE INITIATED (GO 1 MEANS START NOW,
GO = 0 MEANS THE CONVERSION IS TO BE
X
~ INITIATED BY THE HSO UNIT AT A SPECIFIED TIME).
f0-
AID RESULT: X SET UPPER FOUR BITS TO ZERO
LEAST SIGNIFICANT 2 BITS f0-

270815-5
....X
270815-6

Chip Configuration (2018H) WSR (14H)

117161514131211 10 ICHIP CONFIGURATION REGISTER

o=SFR's FUNCTION UKE SUPERSET OF 80968H
L::OWERDOWN MO~E ENABLE 14( 1 1 10B) = PPW REGISTER .

..
15(111 lB)=EXCHANGE READ/WRIlt REGISTERS

~0
;1 OTHER = UNDEFINED, DO NOT USE

4 o
ADDRESS VALID STROBE SELECT o
(ALE I ADV)
o
(lRCO) l~TERNAL READY CONTROL o
(lRCt) MODE
270815-8
(LOCO) }
(LOC1) PROGRAM LOCK MODE

270815-7

HS'-Mode (03H) HSI_Status (06H)

'-----HSl.l MODE
L - - - - - - - H S I . 2 MODE L - - - - - - - H S I . 2 STATUS
' - - - - - - - - - - H S I . 3 MODE L - - - - - - - - - H S I . 3 STATUS
WHERE EACH 2 - BIT MODE CONTROL FIELD WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
DEFINES ONE OF 4 POSSiBLE MODES: BIT INDICATES WHETHER OR NOT AN EVENT HAS
OCCURED ON THIS PIN AND THE UPPER BIT INDICATES
00 8 POSITIVE TRANSITIONS THE CURRENT STATUS OF THE PIN.
01 EACH POSITIVE TRANSITION 270815-10
10 EACH NEGATIVE TRANSITION
11 EVERY TRANSITION
(POSITIVE AND NEGATIVE)
270815-9

4-159
 83C198/80C198,83C194/80C194

,..-----------'----- ------- ,..-----------'------_._--'-------

INT_PENDIINT_MASK (09H/OSH)

TIMER OVERFLOW TRANSMIT'INTERRUPT

AID CONVERSION COMPLETE RECEIVE INTERRUPT

HSI DATA AVAILABLE HSI FIFO 4

HIGH SPEED OUTPUTS (SET TO 0)

HSI.O PIN , TIMER 2 OVERFLOW

SOFTWARE TIMER EXTINT 1

SERIAL PORT HSI FIFO FULL

EXTERNAL INTERRUPT (SET TO 0)

270815-11 270815-12
'--------_._------------'
,..-----------------
SP_CON (11H)
BIT. 1, BIT.O SPECIFY THE MODE
o O.O=MOOEO 1.0=MODE2
0.1 = MODE 1 1.1 = MODE 3
,
PEN ENABLE THE PARITY FUNCTION RECEIVE OVERRUN ERROR
W
R REN ENABLES TH~ RECEIVE FUNCTION: TRANSMITIER EMPTY
I
T 4 TB8 PROGRAMS THE 9TH DATA BIT FRAMING ERROR
E
5 SET UPPER THREE TRANSMIT INDICATOR
BITS TO ZERO
6 RECEIVE INDICATOR

7 RECEIVE PARITY ERROR

270815-13 270815-14

...--------------------------------------------------~

HSO Command (06H)

CHANNEL: 0-5 HSO.O - HSO.5 INOIVIOUALL Y

BIT: 0]6 HSO.O AND HSO.l

7 HSO.2 AND HSO.3
8-B SOFTWARE TIMERS
C-D RESERVED FOR FUTURE USE
E RESET TIMER2 '
F START AID CONVERSION .
INTERRUPT 1 NO INTERRUPT
SET ICCEAR

TIMER 21 TIMER 1
LOCK CAM
270815-15

4-160
 83C198/80C198,83C194/80C194

,-------~~---. -~---.- .. -~- ~--------,

10$0 (15H) lOCO (15H)

HSO.O CURRENT STATE HSI.O INPUT ENABLE / DISABLE
HSO.l CURRENT STATE TIMER 2 RESET EACH WRITE

HSO.2 CURRENT STATE HSl.l INPUT ENABl.E / DISABLE

HSO.3 CURRENT STATE TIMER 2 EXTERNAL RE"SET ENABLE / DISABLE

HSO.4 CURRENT STATE HSI.2 INPUT ENABLE/DISABLE

HSO.5 CURRENT STATE TIMER 2 RESET SOURCE HSI.O / T2RST
CAM Q.!l HOLDING REGISTER IS FULL HSI.3 INPUT ENABLE / i5iSABLE
HSO HOLDING REGISTER IS FULL TIMER 2 CLOCK SOURCE HSI.l / T2C~K
\
270815-16 270815-17

,---------------------~

1051 (16H) IOC1 (16H)

SOFTWARE TIMER 0 EXPIRED SELECT PWM / SELECT P2.5
SOFTWARE TIMER 1 EXPIRED EXTERNAL INTERRUPT ACH7/ EXTINT
SOFTWARE TIMER 2 EXPIRED TIMER 1 OVERFLOW INTERRUPT ENABLE / DISABLE
SOFTWARE TIMER 3 EXPIRED TIMER 2 OVERFLOW INTERRUPT ENABLE / DISABLE
TIMER 2 HAS OVERFLOW HSO.4 OUTPUT ENABLE / DISABLE
TIMER 1 HAS OVERFLOW SELECT TXD / SELECT P2.0
HSI FIFO IS FULL HSO.5 OUTPUT ENABLE / DiSABLE
HSI HOLDING REGISTER DATA AVAILABLE HSI INTERRUPT
FIFO FULL / HOLDING REGISTER LOADED
270815-18
270815-19

1052 (17H) IOC2(OBH)

INDICATES WHICH HSO EVENT OCCURED
o ENABLE FAST INCREMENT OF T2
0 HSO.O

HSO.l "
ENABLE +2 PRESCALER ON PWM
HSO.2 X (SET TO 0)
HSO.3 A/D CLOCK PRESCALER DISABLE
HSO.4 T2 ALTERNATE INTERRUPT @ 8000H
HSO.5 ENABLE lOCKED CAM ENTRIES
T2RESET CLEAR ENTIRE CAM
START A/D 270815-21
_ _ _ _ _ _ _ _ _ _ _ _ _ • _ _ _ _ _ _.....J

270815-20
L......_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~ ~.

4-161
 inter, 83C198/80C198,83C194/80C194

ELECTRICAL CHARACTERISTICS NOTICE: This data sheet contains preliminary infor-

mation on new products in production. It is valid for
the devices indicated in the revision history. The
Absolute Maximum Ratings* specifications are subject to change without notice.

Ambient Temperature
* WARNING: Stressing the device beyond the "Absolute
MaximUm Ratings". may cause permanent damage.
Under Bias ...................... O°C to + 70°C
These' are stress ratings only. Operation beyond the
. Storage Temperature .......... -65°C to + 150°C "Operating Conditions" is not recommended and ex-
Voltage On Any Pin to VSS ........ -0.5V to + 7.0V tended exposure beyond the "Operating Conditions"
may affect device reliability.
Power Dissipation .......................... 1.5W

Operating Conditions
Symbol Description Min Max Units
TA Ambient Temperature Under Bias 0 +70 °C
Vee Digital Supply Voltage 4.50 5.50 V

VREF Analog Supply Voltage 4.50 5.50 V

fose Oscillator Frequency 3.5 12 MHz

NOTE:
ANGND and Vss should be nominally at the same potential.

D.C. Characteristics (Over specified operating conditions)

Symbol Description Min Max Units Test Conditions
Vil Input Low Voltage -0.5 0.8 V
-
VIH Input High Voltage (Note 1) 0.2 Vee + 1.0 Vee + 0.5 V

VIHI Input High Voltage on XTAL 1 0.7 Vee Vee + 0.5 V

VIH2 Input High Voltage on RESET 2.6 Vee + 0.5 V

Val Output Low Voltage 0.3 V IOl = 200 p.A

0.45 V IOl = 32mA
1.5 V IOl = 7 mA
,---------
VOH Output High Voltage Vee - 0.3 V IOH = - 200 p.A
(Standard Outputs) Vee - 0.7 V IOH = -3.2 mA
Vee - 1.5 V IOH = -7 mA
lu Input Leakage Current (Std. Inputs) ±10 p.A o< VIN < Vee - 0.3V
--
IU1 Input Leakage Current (Port 0) +3 p.A 0< VIN < VREF
IlL 1 Logical 0 Input Current in Reset (Note 2) -1.2 mA YiN = 0.45 V
(ALE, RD, WR, INST, P2.0)
Hyst Hysteresis on.RE'SET Pin 300 mV

NOTE:
1. All pms except RESET and XTAl1.
2. Holding these pins below VIH In Reset may cause the part to enter test modes.

4-162
 83C198/80C198,83C194/80C194

D.C. Characteristics (Over specified operating conditions) (Continued)

Symbol Description Min Typ(6) Max Units Test Conditions

Icc Active Mode Current in Reset 40 55 rnA XTALl = 12MHz

AID Converter Reference Current 2 5 rnA Vce = Vpp = VREF = 5.5V
IREF
IIDLE Idle Mode Current 10 22 rnA

ICCl Active Mode Current 15 22 rnA XTAL 1 = 3.5 MHz

IpD Powerdown Mode Current 5 50 /J- A Vee = Vpp = VREF = 5.5V

RRST Reset Pullup Resistor '6K 65K n

Cs Pin Capacitance (Any Pin to VSS) 10 pF fTEST = 1.0 MHz

NOTES:
(Notes apply to all specifications) ,
1. Standard Outputs include ADO-15, RD, WR, ALE, INST, HSO pins, PWM/P2.5, RESET, Ports 3 and 4, TXO/P2.0, and
RXD (In serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
2. Standard Inputs include HSI pins, EA, READY, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3, and T2RST/P2.4.
3. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below Vee - 0.7V:
IOL on Output pins: 10 mA
IOH on Standard Output pins: 10 mA
4. Maximum current per bus pin (data and control) during normal operation is ± 3.2 rnA.
5. During normal (non-transient) conditions the following total current limits apply:
HSO, P2.0, RXD, RESET IOL: 29 rnA IOH: 26 rnA
P2.5, WR IOL: 13 rnA IOH: 11 rnA
ADO-AD15 IOL: 52 rnA IOH: 52 rnA
RD, ALE,INST IOL: 13 rnA IOH: 13 rnA
6. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room. temperature
and VREF = Vee = 5V.

60r-----~-----r----~

ICC MAX
50~----+-----~---~~

40 f------t-----¥- ICC TYPICAL (7)

10 ::J.ooo'''''---j-----==--.-1 IIDLE TYPICAL

4MHz 8MHz 12MHz

ICC Max = 3.88 x FREQ + 8.43 FREQ
IIDLE Max = 1,65 x FREQ + 2.2 270815-22

Figure 4. Icc and IIDLE vs Frequency

4-163
 83C198/80C198,83C194/80C194

A.C. Characteristics
For uSe over specilie,d operatiRQ conditions,
Test Conditions: Capacitive load on all phlS = 100 pF, Rise and fall times = 10 ns, lose = 12 MHz

The system must meet these specifications to work with the 83C198/80C198:
Symbol Description Min Max Vnlts Notes

TAVYV Address Valid to Ready Setup 2Tose - 85 ns

hLYV ALE Low to READY Setup Tose - 70 ns

TYLYH Non READY Time ' No upper limit ns
TLLYX READY Hold alter ALE Low Tose - 15 2Tose -.40 ns (Note 1)

TAVDV Address Valid to Input Data Valid 3Tose - 60 ns (Note 2)

TRLDV RD Active to Input Data Valid Tose - 23 ns (Note 2)

TRHDZ End 01 RD to Input Data Float Tose - 20 ns

TRXDX Data Hold after RD Inactive 0 ns

NOTES:
1. If max is exceeded, additional wait states will occur.
2. When using wait states, add 2Tasc x n, where n = number of wait states.

4-164
inter 83C198/80C198,83C194/80C194

A.C. Characteristics
For use over specified operating conditions
Test Conditions: Capacitive load on all pins = 100 pF, Rise and fall times = 10 ns, fose = 12 MHz

The 83C198/80C198 will meet these specifications:

Symbol Description Min Max Units Notes
FXTAL Frequency on XTAL1 3.5 12 MHz (Note 1)
Tosc II FXTAL 83 286 ns

TLHLH ALE Cycle Time 4Tosc ns (Note 4)

TLHLL . ALE High Period Tose - 10 Tosc+ 10 ns

TAVLL Address Setup to ALE Falling Edge Tose - 20

TLLAX Address Hold after ALE Falling Edge Tose - 40 ns

TLLRL . ALE Falling Edge to RD Falling Edge Tosc - 30 ns

TRLRH RD Low Period Tose - 5 Tosc + 25 ns (Note 4)

TRHLH· RD Rising Edge to ALE Rising Edge Tose Tose + 25 ns (Note 3)

TRLAZ RD Low to Address Float 10 ns

hLWL ALE Falling Edge to WR Falling Edge Tosc - 10 ns

TQVWH Data Stable to WR Rising Edge Tosc - 23 ns (Note 4)

TWLWH WR Low Period Tose - 30 Tosc + 5 ns (Note 4)

TWHQX Data Hold after WR Rising Edge Tosc - 2.5 ns

TWHLH WR Rising Edge to ALE Rising Edge rose - 10 Tosc + 15 ns (Note 3)

TWHBX INST HQld after WR Rising Edge Tose - 10 ns

TRHBX INST Hold after RD Rising Edge Tosc - 10 ns

TWHAX AD8-15 Hold after WR RiSing Edge Tosc - 50 ns

TRHAX AD8-15 Hold after RD Rising Edge Tose - 25 ns

NOTES:
1. Testing performed at 3.5 MHz. However, the part is static by design and will typically operate below 1 Hz.
2. Typical specification, not guaranteed.
3. Assuming back-to-back bus cycles.
4. When using wait states, add 2TOSC x n, where n = number of wait states.

4-165
 83C198/80C198,83C194/8QC194

System Bus Timings

XTALI

ALE
--1.
, tLHLH

J \
I+- tLHLL.-- I-- tLLRL --I-- tRLRH --- - tRHLH ....

~
J
tRLDV
rt.t.vLL- ,-.tLLAX ~.
BUS
-<r-- ADDRESS OUT >--< DATA »}}~
tAVDV I .1
I-- t LLWL ~ tWLWH ~ ~tWHLH""
tWHox.1
I--tOVWH 1 .

BUS - ( . ___ ADDRESS OUT)X(

•• DATA OUT }~y~__
AD_DR_E_SS_ _ __
I . I
LtRHBX ..
ItWHBX
BHE,INST VALID

AS-IS ADDRESS OUT

,
270815-23
 83C198/80C198,83C194/80C194

READY Timings (One Waitstate)

XTALI

ALE

READY

_+_______ 1 - - - - - tRLRH + 2Tose -----1--------

tRLDV + 2Tose ~
1 - - - - - - - - - t AVDV + 2Tose --------1--
~--AD-DR-ES-S-OU-T--~) (C·!DA~~:]»~»~)-»r--------
I

~. tWLWH+2Tos e J
j.1·--- tOVWH ~ 2 Tose =:::J
r---A-D-DR-E-SS-OU-T--~~~<~_ _ _ _._D_AT_A_O_UT_ _ _ _ _~X~
I
___A_DD_R_ES_S__~ II
270815-24

.4-167
 83C198/80C198,83C194/80C194

EXTERNAL CLOCK DRIVE

Symbol Parameter Min Max Units
1/TxLXL Oscillatqr Frequency 3.5 12.0 MHz
TXLXL Oscilll;ltor Period 83 286 ns
TXHXX High Time 32 ns
TXLXX· Low Time 32 ns
TXLXH Rise Time 10 ns
TXHXL Fall Time 10 ns

EXTERNAL CLOCK DRIVE WAVEFORMS

270615-25

An external oscillator· may encounter as much as a 100 pF load at XTAL 1 when it starts-up. This is due to
interaction between the amplifier and .its feedback capacitance. Once the external signal meets the VIL and
VIH specifications the capacitance will not exceed 20 pF. .

A.C. TESTING INPUT, OUTPUT WAVEFORM FLOAT WAVEFORM

2.4 -V- 2.0> TEST POINTS < 2.0 V-- VLOAO+ O. 15V - - - - - - - - -
vLOAO ____ TIMING REF'ERENCE.____
....--- POINTS
VLOAO-O.15 V ' -_ _ _ _ _ _ __
----..
0.45---1\ O.B O.B-A-
270815-26
A.C. Testing Inputs are driven at 2 4V for a Logic "1" and 0.45V 270815-27
for a LogiC "0" Timing measurements are made at 2.0V for a For Timing Purposes a Port Pin IS no Longer Floating when a
Logic "I" and 0.8V for a Logic "0". 100 mV change from Load Voltage Occurs and BeginS to Float
when a 100 mV change from the Loaded VOHIVOl Level occurs
IOl/lOH = ± 15 rnA

EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions: Signals:
H - High A Address
L Low D DATA IN
V - Valid L - ALE/ADV
X - No Longer Valid Q DATA OUT
Z Floating R RD
W WR
X XTAL1
Y READY

4-168
 83C198/80C198,83C194/80C194 ,

A.C. CHARACTERISTICS--SERIAL PORT-SHIFT REGISTER MODE

SERIAL PORT TIMING-SHIFT REGISTER MODE

Symbol Parameter Min Max Units
TXLXL Serial Port Clock Period (BRR :2 8002H) 6 Tose ns
-
TXLXH Serial Port Clock Falling Edge 4 Tose ±50 ns
to Rising Edge (BRR :2 8002H)
TXLXL Serial Port Clock Period (BRR = 8001 H) 4 Tose ns
TXLXH Serial Port Clock Falling Edge 2 Tose ±50 ns
to Rising Edge (BRR = 8001 H)

TOVXH Output Data Setup to Clock Rising Edge 2 Tose -50 ns

TXHOX Output Data Hold after Clock Rising Edge 2 Tose -50 ns

TXHOV Next Output Data Valid after Clock Rising Edge 2 Tose +50 ns
TDVXH Input Data Setup to Clock Rising Edge Tose +50 ns
TXHDX Input Data Hold after Clock Rising Edge 0 ns
TXHOZ Last Clock Rising to Output Float 1 Tose ns

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE

SERIAL PORT WAVEFORM-SHIFT REGISTER MODE

r- --j TXLXL
TXD---U ---U ---U ---U ---U- ---U ---U ---U
TovxW'1 r- TXLXH-I r- TXHOV i-1 -I r-TXHOX TXHQZ-l I
(O~;)--<!)(----"X 2 X 3 X"'-4-""\X 5 X 6 X 7 >-
TDVXH -+j f..- -l r- TXHDX
RXD
(IN)
270815-28

4-169
I"m:.-r
•• ~"' 83C198/80C198,83C194/80C194

A TO D CHARACTERJSTICS stability of VREF. VREF must be close to Vee since it

supplies both the resistor ladder and the digital sec-
There are two modes of AID operation: with or with- tion of the converter. '
out clock prescaler. The speed of the AID converter
can be adjusted by setting a clock prescaler on or
off. At high frequencies more time is needed for the AID CONVERTER SPECIFICATIONS
comparator to settle. The maximum frequency with
the clock prescaler" disabled is 8 MHz. The conver- The specifications given below assume adherence
sion times with the prescaler turned on or off is to the Operating Conditions section of this data
shown in the table below. sheet. Testing is performed with VREF = 5.12V.

The converter is ratiometric, so the absolute The 8XC194 does not have an AID converter.
accuracy is directly dependent on the accuracy and

Clock Prescaler On Clock Prescaler Off

IOC2.4 = 0 IOC2.4 = 1
158 States 91 States
26.33 p.s @ 12 MHz 22.75 p.s @ 8 MHz

Parameter Typical(1) Minimum Maximum Units' Notes

Resolution 512 1024 Levels
9 10 Bits
Absolute Error 0 ±4 LSBs
Full Scale Error 0.25 ±0.50 LSBs
Zero Offset Error -0.25 ±0.50 LSBs
Non-Linearity Error 1.5 ±2.5 0 ±4 LSBs
Differential Non-Linearity Error > -1 +2 LSBs
Channel-to-Channel Matching ±0.1 0 ±1 LSBs
Repeatability ±0.25 LSBs
Temperature Coefficients:
Offset 0.009 LSBrC
Full Scale 0.009 LSBrC
Differential Non-Linearity 0.009 LSBrC
Off Isolation -60 dB 2,3
Feedthrough -60 dB 2
Vee Power Supply Rejection -60 dB 2
Input Resistance 1K 5K n
D.C. Input Leakage 0 3.0 p.A
Sample Time: Prescaler On 15 States 4
Prescaler Off 8 States 4
Input Capacitance 3 pF

NOTES:
'An uLSB", as used here, has a value 01 approximately 5 mY.
1. Typical values are expected for most devices at 25°e but are not tested or guaranteed.
2. De to 100 KHz.
3. Multiplexer Break-Belore-Make Guaranteed.
4. One state = 167 ns at 12 MHz, 250 ns at 8 MHz.

4-170
 83C198/80C198,83C194/80C194

80C198 FUNCTIONAL DEVIATIONS 2. Location 201 AH is reserved for use by Intel and
must contain OFFH.
The 80C198 has the following problems. 3. HSO commands OCH and ODH are reserved and
1. The DJNZW instruction is not guaranteed to be must not be used.
functional. The instruction, if encountered, will not 4. All unused Windows are reserved and must never
cause an unimplemented opcode interrupt. (The be accessed.
opcode for DJNZW is OE1 Hex.) The DJNZ (byte)
in.!ltruction works correctly and should be used in- 5. Do not toggle the EA pin when the device is exe-
stead. cuting.
2. Factory test' modes. On future devices, factory 6. The device will make use of many of the unimple-
test modes will be entered by holding the ALE, mented opcodes and these opcodes will no long-
RD, WR and PWM pins in their active states on er cause an umimplemented opcode interrupt.
the rising edge of RESET. ALE, RD and WR are 7. On future devices, An AID conversion may take·
active low, and PWM is active high. During RE- 1.5 less states to complete. Do not base critical
SET, these pins will be held inactive by semi- timing .Ioops on an AID conversion time.
strong devices. These semi-strong devices will 8. The ONCE (ON Circuit Emulator) mode will be en-
sink or source about 2 mA and still stay above VIH tered differently. ONCE is currently entered by
or below VIL. Factory test modes are reserved by holding ALE high, and INST, RD, and EA low on
Intel. However, a system must be designed so the rising edge of RESET. For future versions, the
that it does not inadvertantly enter one of these ONCE mode will be entered by holding the TxD
modes. (P2.0) pin low on the riSing edge of RESET.
The PWM pin is the qualifier. If the PWM pin is
above VIL and any of the other pins are below ONCE mode entry is primarily a concern for emula-
VIH, the device may enter a factory test mode. A tors. However, a system needs to be designed so it
system must not override any of these semi- will not enter ONCE. Currently, the TXD pin is weakly
strong devices. driven high during RESET. For future versions, the
TXD pin will be semi-strongly driven high during
RESET so an external load will not pull the TXD pin
80C198 DESIGN CONSIDERATIONS below VIH and put the device into ONCE. The TXD
pin on future devices will source about 2.0 mA and
In order to remain compatible with future versions of still remain above VIH. A system must not pull more
the 80C198, the following design considerations than 2.0 mA from the TXD pin during RESET or the
need to be taken into account when implementing device will enter the ONCE mode.
an 80C198 design: 9. RESET. The RESET pin currently must be held
1. Reserved Bits in SFR spaGe. Reserved bits must low for a minimum of 4 states for a valid device
always be written as zeroes when writing to an Reset. The two internal Reset sources, WDT
SFR that has reserved bits. Never rely on the overflow and RST instruction, also drive the
state of a reserved bit. when reading an SFR as RESET pin low for 4 states.
these bits are indeterminate. Reserved bits in-
clude: On future versions, the RESET pin must be held low
Program Status Word bit two (PSW.2) for a minimum of 16 states for a valid device Reset.
To remain compatible, always assert the RESET pin
Window Select Register bits four through six for at least 16 states. The internal' Reset sources will
(WSR.4-.6) . also drive the pin low for 16 states.
110 Control Register Two bit three (IOC2.3)
AID Command Register bits four through sev- Also, future versions will take 5 to 8 more state times
en (AD_COMMAND.4-.7) from the rising edge of RESET to begin executing
from location 2080H.
Serial Port Control Register bits five through
seven (SP_CON.5-.7)
AID Result LO Register bits four and five
(AD_RESULT_L0.4-.5)
Serial Port Status Register bits zero and one
(SP_STAT.0-.1)
Interrupt Mask Register one bit seven
(IMASK1.7)

4-171
 83C198/80C198,83C194/80C194

REVISION HISTORY 1. PORT t, PORT1 is a qUlisi-bidirectional port.

A. HOLD/HLDA. This Jeature is multiplexed on
This data sheet (270815-002) is valid for devices PORT1.5-.7 and Is not available.
with a "B" at the end of the topside tracking number.
2. The AID converter loses four of its input chan-
nels, ACHO-3.
The following differences exist between this and the
001 version of the 80C198 data sheet. 3. T2CAPTURE (P2.7) Timer2 Capture feature is not
available. . .
1. Vss pin description was altered to reflect the cor-
rect number of pins. 4. T2UP/DN (P2.6) The Timer2 UP/DOWN feature
is not available.
2. VIH2 min was changed from changed 2.2V to
2.6V. 5. CLKOUT
3. Max IpD was added and the IpD note was delet- 6. NMI
ed. 7. BUSWIDTH

For more detailed information on the 80C198, re- 8. BHE

fer to the 80C196KB User's Manual, Order #
270651. The 80Ct96KB User's Guide applies to
the 80C198 except for the design considerations
listed above. Because the 80C198 is a reduced
pin count version, some 80C196KB features are
not available and are listed here:

4-172
 87C 198/87C 194
16-BIT CHMOS MICROCONTROLLER
8 Kbytes of OTPROM

• 8 Kbytes of On-Chip OTPROM

• Full Duplex Serial ~ort

• 232 Byte Register File

• High Speed I/O Subsystem

• Reglster-to-Register Architecture
• 16-Bit Timer

• 28 Interrupt Sources/16 Vectors

• 16-Bit Counter

• 2.3 ,""S 16 x 16 Multiply (12 MHz)

• Pulse-Width-Modulated Output

• 4.0 ,""S 32/16 Divide (12 MHz)

• Four 16-Blt Software Timers

• Powerdown and Idle Modes

•• 10-Blt A/D Converter with Sample/Hold

• 16-Bit Watchdog Timer

• The 87C194 is an 87C198 without an
On-Chip A/D Converter
• 8-Bit External Bus
The 87C198 is the one time user programmable version of the low-cost 83C198/80C198. The 8XC198 family
offers low-cost entry into Intel's powerful MCS-96® 16-bit microcontroller architectur~. Intel's CHMOS process
provides a high performance processor along with low power consumption. To further reduce power require-
ments, the processor can be placed into Idle or Powerdown Mode.

The 87C198 has 8 Kbytes of on-~hip One Time Programmable Read Only Memory (OTPROM).

Bit, byte, word and some 32-bit operations are available on the 87C198. With a 12 MHz oscillator a 16-bit
addition takes 0.66 f.Ls, and the instruction times average 0.5 f.Ls to 1.5 f.Ls in typic~1 applications.

Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an AID conversion. Events can be based on the timer or counter.

Also provided on-chip are an AID converter, serial port, watchdog timer, and a pulse-width-modulated output
signal.

V EF" ANGNO

CONTROL
SIGNALS

PORT 3

ADOR
} DATA
BUS

PORT 4

HSI

270899-1
Figure 1. 87C198 Block Diagram

MCS®-96 is a registered trademark of Intel Corporation.

October 1990
4-173 Order Number: 270899-001
inter 87C198/87C194

PACKAGING With AID Without AID

The 87C198 and 87C194 are available in a 52-pin 87C19X N87C198-PLCC N87C194-PLCC
PLCC package and an 80-pin QFP package. Contact S87C198-QFP S87C194-QFP
your local sales office to determine the exact order-
ing code for the part desired.

The 87C194 is an 87C198 without the AID convert-

er.

<D
"...0 ...0 If'; COl

;::-~ '~
'" >-~
...'" .;...
:I: :I:
u
00(
..J ..J

~ I~ >tl >~t!
x x
~ Jl ~ ~ 1li1 "c
0
00(
c
00(

ACH5/PO.5 AD2/P3.2
ACH4/PO.4 AD3/P3.3
ANGND AD4/P3.4
vREr AD5/P3.5
vss AD6/P3.6
EXTINT/P2.2
RESET
RXD/P2.1
inter
TOP VIEW
AD7/P3.7
A8/P4.0
A9/P4.1
TXD/P2.0 A10/P4.2
HSI.O A11/P4.3
HSI.1 A12/P4.4
HSO.4/HSI.2 A13/P4.5
HSO.5/HSI.3 A14/P4.6

0
0 >"''''
0VI 0Vl VI
N
III •
~ i ,...~ I~ ..... >-c~ '"... "...
:I: :I:
0
Vl
:I: :I:
:::E
~
'" '"
;::.Vl '" "'"
..J
Q.
of)
:;c
Q.
'"'">- U'">-
270899-2

Figure 2. 52-Pin PLCC Package

4-174
 87C 198/87C 194

SO-Pin Quad Flat Pack (EIAJ)

Contacts ' Contacts
Facing Up Foclng Down
PIN NO 1 MARK
65 ", 80 65

64 ",

41 41

40 25 25 40
270A99- 3

Top View

!l!!!!!!!!!!!!!!
~ ~ ~ ~ ~ ~ ~ ~ ~ ; R~ ~ ~ ~ ~
T2CLK/P2.3
AD1/P3.1 64
Vss
ADO/P3.0 63
62 READY
Rii 61 ....-..-..:. T2RST/P2.4
ALEji\DV 4
60 N.C.
INST 5 59 ViR
VSS 58 PWM/P2.5
N.C.
57 N.C.
XTAL2
56 Vpp
XTAL1
55 VSS
VSS 10
54 Vss
VSS 11
53 HSO.3
Vee 12
52 Vee
Vee
EA
13
14
51
50
- VSS
HSO.2
VSS 15
49 N.C.
N.C. 16
48 N.C.
N.C. 17
47 N.C.
N.C. 18
46 N.C.
N.C. 19 45 HSO.1
ACH6/PO.6 20
44 HSO.O
ACH7/PO.7 21
43 HSO.5/HSI.3
N.C. 22
42 VSS
ACH5/PO.5 23
HSO.4/HSI.2
ACH4/PO.4

!!!!!!!!!!!!!!!l
270899-4

Figure 3. SO-Pin Quad Flat Pack (QFP)

4·175
 87C1.98/87C194

PIN DESCRIPTIONS
Symbol Name and Function
Vee Main supply voltage (5V).
V~s The PLCC package has 5 Vss pins and the QFP package has 12 Vss pins. All must be
connected to circuit ground.

VREF Reference voitage for the AID converter (5V). VRI::F is ~Iso the supply voltage to the
analog portion of the AID converter and the logic used to read Port O. Must be
connected for AID and Port 0 to function .
._----
ANGND Reference ground for the AID converter. Must be held at nominally the same potential
as Vss.
-
Vpp Programming Voltage. Also, timing pin for the return from powerdown circuit. Connect
this pin with a 1 IJ.F capacitor to Vss. If this function is not used, connect to Vee.
XTAL1 Input of the oscillator inverter and of the internal clock generator.
XTAL2 Output of the oscillator inverter.
RESET Reset input to the chip. Input low for at least 4 state times to reset the chip. The
subsequent low-to-high transition commences the Reset Sequence in which the PSW is
cleared, a byte read from 2018H loads CCR, and a jump to location 2080H is executed.
Input high tor ~ormal operation. RESET has an internal pullup.
INST Output high during an external memory read indicates the read is an instruction fetch.
INST is valid throughout the bus cycle. INST is activated only during external memory
accesses and output low for a data fetch.
EA Input for memory select (External Access). EA equal to a TTL-high causes memory
accesses to locations 2000H through 3FFFH to be directed td on-chip ROM/EPROM.
EA equal to a TTL-low causes accesses to these locations to be directed to Off-chip
memory
ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options
provide a latch to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ADV can be used as a chip select
for external memory. ALE/ ADV is activated only during external memory accesses.
RD Read signal output to external memory. RD is activated only during external memory
reads .
._ - -
WR Write output to external memory. WR will go low for every external write.
-

4-176
inter 87C198/87C194

PIN DESCRIPTIONS (Continued)

Symbol Name and Function
READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic
memory, or for bus sharing. If the pin is high, CPU operation continues in a normal
manner. When the extf!r:1al memory is not being used, READY has no effect. Internal
control of the number of wait states inserted into a bus cycle held not ready is available
through configuration of CCA.
HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2; and
HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1,
HSO.2, HSO.3, HSO.4, and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the
HSI Unit.
Port 0 4-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter. These pins set the Programming Mode on
the EPROM device.
Port 2 Multi-functional port. All of its pins are shared with other functions in the 80C198.
Ports 3 and 4 8-bit bi-directionall/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pull ups. Available as I/O only
on the ROM and EPROM devices.
TxD The TxD pin is used for serial port transmission in Modes 1, 2, and 3. The TxD function is
enabled by setting IOC1 5. In mode 0 the pin is used as the serial clock output.
RxD Serial Port Receive pin used for serial port reception. The RxD function is enabled by
setting SPCON.3. In mode 0 the pin functions as input or output data.
EXTINT A positive transition on the EXTINT pin will generate an external interrupt. EXTINT is
selected as the external interrupt source by setting IOC1.1 high.
T2CLK The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.
T2RST A rising edge on the T2RST pin will reset Timer2. The external reset function is enabled
by setting IOCO.03 T2RST is enabled as the reset source by clearing IOCO.5.
PWM Port 2.5 can be enabled as a PWM output by setting IOC1.0 The duty cycle of the PWM
is determined by the value loaded into the PWM-CONTROL register (17H).

4-177
inter 87C198/87C194

MEMORY MAP

OFFFFH
EXTERNAL MEMORY OR I/O
4000H
INTERNAL ROM/EPROM OR
EXTERNAL MEMORY
20S0H
RESERVED
2040H
UPPER 8 INTERRUPT VECTORS
2030H
ROM/EPROM SECURITY KEY
2020H
RESERVED
2019H
CHIP CONFIGURATION BYTE
201SH
RESERVED
2014H
LOWER S INTERRUPT VECTORS
PLUS 2 SPECIAL INTERRUPTS
2000H
PORT 3 AND PORT 4
lFFEH
EXTERNAL MEMORY OR I/O
0100H
INTERNAL DATA MEMORY - REGISTER FILE
(STACK POINTER, RAM AND SFRS)
EXTERNAL PROGRAM CODE MEMORY
OOOOH

19H 19H
STACK POINTER STACK POINTER
lSH lSH
17H IOS2 17H PWM CONTROL
16H 10Sl 16H 10Cl
15H 10SO 15H lOCO
14H WSR 14H WSR
13H INT_MASKl 13H INT~ASKl
12H INT_PENDl 12H INT_PENDl
llH SP_STAT llH SP_CON
10H PORT2 10H PORT2 10H RESERVED (1)
OFH RESERVED (1) OFH RESERVED (1) OFH RESERVED (1)
OEH PORTO OEH BAUD RATE OEH RESERVED (1)
ODH TlMER2(HI) ODH TIMER2 (HI) ODH RESERVED (1)
OCH .TIMER2 (LO) OCH TIMER2(LO) OCH RESERVED (1)
OBH TIMERl (HI) OBH IOC2
WSR ~ 15
OAH TIMERl (LO) OAH WATCHDOG
QSH INT PENDING OSH INT PENDING OTHER SFRS IN WSR
OSH INT MASK OSH INT MASK 15 BECOME READABLE
IF THEY WERE WRITABLE
07H SBUF(RX) 07H SBUF(TX) INWSR ~ o AND WRITABLE
06H HSI STATUS 06H HSO_COMMAND IF THEY WERE READABLE
INWSR ~ 0
05H HSI_TIME (HI) OSH HSO_TIME (HI)
04H HSI_TIME (LO) 04H HSO_TIME (LO)
03H AD_RESULT (HI) 03H HSI MODE
02H ·AD RESULT (LO) 02H AD COMMAND
01H ZERO REG (HI) 01H ZERO REG (HI)
OOH ZERO REG (LO) OOH ZERO REG (LO) NOTE:
1. Reserved registers should not be wntten.
WHEN READ WHEN WRITTEN
WSR ~O

4-178
inter 87C198/87C194

.SFR BIT SUMMARY

AD-Result (LO) (02H) AD_Command (02H) ,

AID CHANNEL NUMBER

STATUS:

X
0= AID CURRENTLY IDLE
1 = CONVERSION IN PROCESS
Il3 -
I--
X
CHANNEL # SELECTS WHICH OF THE 4
ANALOG INPUT CHANNELS IS TO BE
CONVERTED TO DIGITAL FORM.

GO INDICATES WHEN THE CONVERSiON is TO

BE INITIATED (GO = 1 MEANS START NOW,
GO = 0 MEANS THE CONVERSION IS TO BE
X
7 INITIATED BY THE HSO UNIT AT A S'PECIFIED TIME).
I--
AID RESULT: X SET UPPER FOUR BITS TO ZERO .
• LEAST SIGNIFICANT 2 BITS t--

270899-5
.....
X
270899-6

Chip Configuration (2018H) WSR (14H)

71s1514131211 10 ICHIP CONFIGURATION REGISTER
0= SFR'. FUNCTION UKE SUPERSET OF B09SBH
L,:POWERDOWN MODE ENABLE 14( 1110B} = PPW REGISTER
o . 15(1111B)=EXCHANGE READ/WRITE REGISTERS
OTHER = UNDEFINED, DO NOT USE,

-0
o
ADDRESS VALID STROBE SELECT o
(ALEI ADV)
o
(IRCO) } INTERNAL READY CONTROL o
(IRC1) MODE .
270899-8
(LOCO) }
(LOC1) PROGRAM LOCK MODE

270899-7

HSI_Mode (03H) HSI_Status (OSH)

17 S 15 41 3 2 11 10 1
HSI.O MODE L HSI.O STATUS
L----HSI.1 MODE HSI.1 STATUS
' - - - - - - - H S I . 2 MODE HSI.2 STATUS
......- - - - - - - - H S I . 3 MODE HSI.3 STATUS
WHERE EACH 2 - BIT MODE CONTROL FIELD WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
DEFINES ONE OF 4 POSSIBLE MODES: BIT INDICATES WHETHER OR NOT AN EVENT HAS
OCCURED ON THIS PIN AND THE UPPER BIT INDICATES
00 B POSITIVE TRANSITIONS THE CURRENT STATUS OF THE PIN.
01 EACH POSITIVE TRANSITION 270899-10
10 EACH NEGATIVE TRANSITION
11 EVERY TRANSITION
(POSITiVE AND NEGATiVE)
270899-9

4-179
 87C198/87C194

tNT_PEND/tNT_MASK (09H/OSH)

TiMER OVERFLOW TRANSMIT INTERRUPT

AID CONVERSION COMPLETE RECEIVE INTERRUPT
HSI DATA AVAILAIiiLE HSI FIFO 4
HIGH SPEED OUTPUTS (SET TO 0)
HSI.O PIN TIMER 2 OVERFLOW
SOFTWARE TIMER EXTINT 1
SERIAL PORT HSI FIFO FULL
EXTERNAL INTERRUPT (SET TO 0)
270899-11 270899-12

SP_CON (11H)
BIT.1, BI.1.O SPECIFY THE MODE
0 X
O.O=MODEO 1.0 = MODE 2
0.1 =MODE 1 1.1 =MODE3 X

2 PEN ENABLE THE PARITY FUNCTION 2 RECEIVE OVERRUN ERROR

W
R 3 REN ENABLES THE RECEIVE FUNCTION: 3 TRANSMITIER EMPTY
I
T 4 TB8 PROGRAMS THE 9TH DATA BIT 4 FRAMING ERROR
E
5 SET UPPER THREE TRANSMIT INDICATOR
BITS TO ZERO
6 RECEIVE INDICATOR

7 RECEIVE PARITY ERROR

270899-13 270899-14

HSO Command (06H)

CHANNEL: 0-5 HSO.O - HSO.5 INDIVIDUALLY

BIT: 0]6 HSO.O AND HSO.l

7 HSO.2 AND HSO.3
8-B SOFTWARE TIMERS
2 C-D RESERVED FOR FUTURE USE
E RESET TIMER2
3 F START A I D CONVERSION ,
INTERRUPT I NO INTERRUPT
SET ICLE;AR
TIMER 2/TIMER 1
LOCK CAM
270899-15

,4·180
 87C198/87C194

IOSO(15H) lOCO (15H)

'HSO.O CURRENT STATE HSI.O INPUT ENABLE I DiSABI'E

HSO.l CURRENT STATE TIMER 2 RESET EACH WRITE
HSO.2 CURRENT STATE HSI.l INPUT ENABLE I DiSABI'E
HSO.3 CURRENT STATE TIMER 2 EXTERNAL RESET ENABLE I DISABLE
HSO.4 CURRENT STATE HSI.2 INPUT ENABLE I DISABLE
HSO.5 CURRENT STATE TIMER 2 RESET SOURCE HSI.O I T2RST
'----
CAM Q!! HOLDING REGISTER IS FULL HSI.3 INPUT ENABLE I DISABLE
HSO HOLDING REGISTER IS FULL TIMER 2 CLOCK SOURCE HSI.l I T2CLK
270899-16 270899-17

IOS1 (16H) IOC1 (16H)

o SOFlWARE TIMER 0 EXPIRED SELECT PWM I SELECT P2.5

SOFlWARE TIMER 1 EXPIRED EXTERNAL INTERRUPT ACH7 I EXTINT
SOFlWARE TIMER 2 EXPIRED TIMER 1 OVERFLOW INTERRUPT ENABLE I DISABLE
SOFlWARE TIMER 3 EXPIRED TIMER 2 OVERFLOW INTERRUPT ENABLE I DISABLE
TIMER 2 HAS OVERFLOW HSO.4 OUTPUT ENABLE I DISABLE
TIMER 1 HAS OVERFLOW SELECT TXD I SELECT P2.0
HSI FIFO IS FULL HSO.5 OUTPUT ENABLE I DISABLE
HSI HOLDING REGISTER DATA AVAILABLE HSI INTERRUPT
FIFO FULL I H'""O"'L-=D"'"INC::G-:R"'E""GI""ST=E"'R"'7L-=O""'AD"'E"'D
270899-18
270899-19

IOS2 (17H) IOC2(OBH)

INDICATES WHICH HSO EVENT OCCURED
ENABLE FAST INCREMENT OF T2
HSO.O o
HSO.l ENABLE +2 PRESCALER ON PWM
HSO.2 X (SET TO 0)
HSO.3 AID CLOCK PRES CALER DISABLE
HSO.4 T2 ALTERNATE INTERRUPT @ BOOOH
HSO.5 ENABLE LOCKED CAM ENTRIES
T2RESET CLEAR ENTIRE CAM
START AID 270899-21,
270899-20

4-181
 87C198/87C194

ELECTRICAL CHARACTERISTICS NOTICE: This document contains information on

products in the design phase of development. Do not
finalize a design with this information. Revised infor-
Absolute Maximum Ratings* mation will be published when the product is avail-
able. '
Ambient Temperature
• WARNING: Stressing the device beyond the "Absolute
Under Bias ...... : ............... O°C to + 7.0°C
Maximum Ratings" may cause permanent damage.
Storage Temperature .......... - 65°C to + 150°C These are stress ratings only. Operation beyond the
Voltage On Any Pin to Vss ........ -0.5V to+ 7.0V "Operating Conditions" is not recommended and ex-
tended exposure beyond .the "Operating Conditions"
Power Dissipation ..... : .................... 1.5W . may affect device reliability.

Operating Conditions
Symbol Description Min Max Units
TA Ambient Temperature Under Bias 0 +70 °C
Vee Digital Supply Voltage 4.50 5.50 V

VREF Analog Supply Voltage 4.50 5.50 V

fose Oscillator Frequency 3.5 12 MHz

NOTE:
ANGND and Vss should be nominally at the same potential.

D.C. Characteristics (Over specified operating conditions)

Symbol Description Min . Max Units Test Conditions
Vil Input Low Voltage -0.5 0.8 V
VIH Input High Voltage (Note 1) 0.2 Vee + 1.0 Vee + 0.5 V

VIH1 Input High Voltage on XTAL 1 0.7 Vee Vee + 0.5 V

VIH2 Input High Voltage on RESET 2.6 Vee + 0.5 V

Val Output Low Voltage 0.3 V IOL = 200/LA
0.45 V IOl = 32 mA
1.5 V IOl = 7 mA
VOH Output High Voltage Vee - 0.3 V IOH = - 200 /LA
(Standard Outputs) Vee - 0.7 V IOH = -3.2 mA
Vee - 1.5 V IOH = -7mA
III Input Leakage Current (Std. Inputs) ±10 /LA o < VIN < Vee - 0.3V
ILl1 Input Leakage Current (Port 0) +3 /LA 0< VIN < VREF
11L1 Logical 0 Input Current in Reset(Note 2) -6 mA VIN = 0.45 V
(ALE, RD, INST)

NOTE:
1. All pins except RESET and XTAL 1.
2. Holding these pins below VIH in Reset may cause the part to enter test modes.

4-182
inter 87C198/87C194

D.C. Characteristics (Over specified operating conditions) (Continued)

Symbol Description Min Typ(6) Max Units Test Conditions

Icc Active Mode Current in Reset 40 55 rnA XTAL1 = 12 MHz

AID Converter Reference Current 2 ~ rnA Vee = Vpp = VREF = !).5V
IREF' 5

IIDLE Idle Mode Current 10 22 rnA

ICC1 Active Mode Current - 15 22 rnA XTAL1 = 3.5 MHz

IpD Powerdown Mode Current 5 50 /-LA Vee = Vpp ;,. VREF = 5.5V

RRST Reset Pullup Resistor 61< 65K n

Cs Pin Capacitance (Any Pin to VSS) 10 pF foreST = 1.0 MHz

NOTES: ,
(Notes apply to all specifications)
1. Standard Olltputs include ADO-15, RD, WR, ALE, INST, HSO pins, PWM/P2.5, RESET, Ports 3 and 4, TXD/P2.0, and
RXD (in serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
2. Standard Inputs include HSI pins, EA, READY, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3, and T2RST/P2.4.
3. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below Vee - 0.7V:
IOL on Output pins: 10 mA
IOH on Standard Output pins: 10 mA
4. Maximum current per bus pin (data and control) during normal operation is ±3.2 mAo
5. During normal (non-transient) conditions the following total' current limits apply:
HSO, P2.0, RXD, RESET IOL: 29 rnA IOH: 26 rnA
P2.5, WR IOL: 13 rnA IOH: 11 rnA
ADO-AD15 IOL: 52 rnA IOH: 52 rnA
RD, ALE, INST IOL: 13 rnA IOH: 13 rnA
6. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and VREF = Vee = 5V.

, 60 r----,---,..--.,
Icct.lAX
50~----+------r--~~

40 1------+---~-__::..I1cc TYPICAL (7)

ICC 30 ~----+-~"'---j;,~---l
mA

10 I-------:!'OO~--_I_--_=-' IIDLE TYPICAL

o~-~~--~--~
4t.lHz 8t.lHz 12t.lHz
ICC Max = 3.88 x FREQ + 8.43 F'REQ
IIDLE Max = 1.65 X FREQ + 2.2 270899-22

Figure 4. Icc and IIDLE VB Frequency

4~183
 87C198/87C194

A.C. Characteristics
For use ~)VE!r specified operating conditions
Test Conditions: Capacitive load on all pins = 100 pF, Rise and 'fall times = 10 ns, fose = 12 MHz
The system must meet these specifications to work with the 87C198:
Symbol Description Min Max Units Notes
TAVYV Address Valid to Ready Setup ~

2Tose - 85 ns
TLLYV ALE Low to READY Setup . Tos~ - 70 , ns
TYLYH Non READY Time No upper limit ns
TLLYX READY Hold after ALE Low Tose - 15 2Tose - 40 ns (Note 1)

TAVDV Address Valid to Input Data Valid 3Tose - 60 ns (Note 2)

TRLDV RD Active to Input Data Valid Tose - 23 ns (Note 2)

TRHDZ End of RD to Input Data Float Tose - 20 ns

TRXDX Data Hold after RD Inactive 0 ns

NOTES:
1. If max is exceeded, additional wait states will occur.
2. When using wait states, add 2T OSC x n, where n = number of wait states.

",' I,:'

4·184
 87C198/87C194

A.C. Characteristics
For use over specified operating conditions
Test Conditions: Capapitive load on all pins = 100 pF, Rise and fall times = 10 ns, fose = 12 MHz

The 87C198 will meet these specifications:

Symbol Description Min Max Units Notes
FXTAL Frequency on XTAL1 3.5 12 MHz (Note 1)
Tose II FXTAL 83 286 ns
TLHLH ALE Cycle Time 4Tose ns (Note 4)
TLHLL ALE High Period Tose - 10 Tose+ 10 ns
TAVLL Address Setup to ALE Falling Edge, Tose - 20
TLLAX Address Hold after ALE Falling Edge Tose - 40 ns
TLLRL ALE Falling Edge to RD Falling Edge Tose - 30 ns
TRLRH RD Low Period Tose - 5 Tose + 25 ns (Note 4)
TRHLH RD Rising Edge to ALE Rising Edge Tose Tose + 25 ns (Note 3)
TRLAZ RD Low to Address Float 10 ns

hLWL ALE Falling Edge to WR Falling Edge Tose - 10 ns

TQVWH Data Stable to WR Rising Edge Tose - 23 ns (Note 4)
TWLWH WR Low Period Tose - 30 Tose + 5 ns (Note 4)
TWHQX Data Hold after WR Rising Edge Tose - 2.5 ns
"

TWHLH WR Rising Edge to ALE Rising Edge Tose - 10 Tose + 15 ns (Note 3)

TWHBX INST Hold after WR Rising Edge Tose - 10 ns
TRHBX INST Hold after RD Rising Edge Tose - 10 ns
TWHAX AD8-15 Hold after WR Rising Edge Tose - 50 ns
TRHAX AD8-15 Hold after RD RiSing Edge Tose - 25 ns

NOTES:
1. Testing performed at 3.5 MHz. However, the part is static by design and will typically operate below 1 Hz.
2. Typical specification, not guaranteed.
3. Assuming back-to-back bus cycles.
4. When using wait states, add 2Tase x n, where n = number of wait states.

4-185
 87C198/87C194

System Bus Timings

XTAL1

ALE
--1
, tLHLH

J
I-- tLHLL- I-- tLLRL- f.-- tRLRH ---I-- tRHLH .....

\ I
r-- t AVLL -
f.- tLLAX
tRLDV
~

BUS --(
I--
ADDRESS OUT

tAVDV I
>---<.1 DATA »»)~,

~ tWLWH - :
I--tWHLH .....
I-- t LLWL

I--tOVWH
tWHo~1
BUS -< . ADDRESS OUT ,}'I..( DATA OUT. }X( ADDRESS

I I
I-tRHBX..,
tWHBX

BHE,INST VALID

I-tRHAX..,
tWHAX

A8-1S ADDRESS OUT

270899-23

4,186
inter 87C198/87C194

READY Timings (One Waitstate)

XTAL1

ALE

READY

_+______""""\ 1 + - - - - tRLRH + 2Tose ----1----------

:==I
tRLDV + 2 Tose
1+-------- t AVDV + 2Tose -----1--1
~--AD-DR-ES-S-OU-T--~) {~-DA-~~»~»)m»~--------
I

_~~~~~~~~~~~~~~~~_~:.:~~-----tw-L-W-H-+-2-T-os-e--4
--j,._ _ _ _ _ _ __
,. 1-01·>---- t QVWH + 2 Tose ~
~--A-D-DR-E-SS-OU-T--.u)~~(~-----D-AT-A-O-U-T------JX~__A_DD_R_ES_S__
I
270899-24

4·187
 87C198/87C194

EXTERNAL CLOCK DRIVE

Symbol Parameter Min , Max Units
1/TXLXL Oscillator Frequency 3.5 12.0 MHz
TXLXL Oscillator Period 83 286 ns
TXHXX High Time 32 ns
TXLXX Low Time 32 ns
TXLXH Rise Time 10 ns
TXHXL Fall Time 10 ns

EXTERNAL CLOCK DRIVE WAVEFORMS

270899-25

An external oscillator may encounter as much as a 100 pF load at XTAL 1 when it starts-up. This is due to
interaction between the amplifier. and its feedback capacitance. Once the external signal meets the VIL and
VIH specifications the capacitance will not exceed 20 pF.

A.C. TESTING INPUT, OUTPUT WAVEFORM FLOAT WAVEFORM

2.4
0: 45
-V
.--A
2.0> TEST POINTS
0.8
< 2.0
0.8 .
>C VLOA O+O.20V
vLOAO
----
r-------_
"",-----TIMING REFERENCE...___
POINTS
VLOAO-O.20V - - - - - - - - -
-...........

270899-26
A.C. Testing inputs are driven at 2.4V for a LogiC "1" and 0.45V 270899-27
for a LogiC "0" Timing measurements are made at 2.0V for a For Timing Purposes a Port Pin is no Longer Floating when a
LogiC "1" and 0.8V for a LogiC "0". 200 mV change from Load Voltage Occurs and Begins to Float
when a 200 mV change from the Loaded VOHIVOl Level occurs
IOl/loH ~ ± 15 mAo

EXPLANATION OF AC SYMBOLS

Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions: Signals:
H High A - Address
L - Low D - DATA IN
V Valid L - ALE/ADV
X No Longer Valid Q - DATA OUT
Z Floating R RD
W WR
X - XTAL1
Y READY
inter 87C198/87C194

EPROM SPECIFICATIONS

A.C. ~PROM Programming Characteristics

Operating Conditions: Load Capacitance = 150 pF, TA = +25°C ±5°C, Vee, VREF = SV, Vss, ANGND =
OV, VPP = 12.7SV ±0.2SV, EA = 12.7SV ±0.2S
Symbol Description Min Max Units
TSHLL Reset High to First PALE Low 1100 Tosc
TLLLH PALE Pulse Width 40 Tosc
TAVLL Address Setup Time 0 Tosc
TLLAX Address Hold Time 50 Tosc
TLLVL PALE Low to PVER Low 60 Tosc
TpLDV PROG Low to Word Dump Valid SO Tosc
TpHDX ' Word Dump Data Hold SO Tosc
TDVPL Data Setup Time 0 Tosc
TpLDX Data Hold Time SO Tosc
TpLPH . PROG Pulse Width 40 Tosc
TpHLL PROG High to Next PALE Low 120 Tosc
TLHPL PALE High to PROGLow 220 Tosc
TpHPL PROG High to Next PROG Low 120 Tosc
TpHIL PROG High to AINC Low 0 Tosc
TILIH AINC Pulse Width 40 Tosc
TILVH PVER Hold after AINC Low SO Tosc
TILPL AINC Low to PROG Low 170 Tosc
TPHVL PROG High to PVER Low 90 Tosc

NOTES:
1. Run Time Programming is done with Fosc = 6.0 MHz to 12.0 MHz, VREF = 5V ± 0.65V. TA = + 25°e to ± 5°C and
Vpp = 12.75V. For run-time programming over a full operating range, contact the factory.

D.C. EPROM Programming Characteristics

Symbol .Descrlption Min
Ipp VPP Supply Current (when Programming)

NOTE:
Vpp must be within 1V of Vee while Vee < 4.5V. Vpp must not have a low impedance path to ground or Vss while
Vee> 4.5V.

4·189
 inter 87C 198/8,7C 194

EPROM PROGRAMMING WAVEFORMS

SLAVE PROGRAMMING MODE DATA PROGRAM MODE W.ITH SINGLE PROGRAM PULSE

3/<
PORTS --t--~~$~~~

PVER

270899-28

SLAVE PROGRAM MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT

.. I.

270899-29

SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT

PO:;: _ _ _-« Aoo./eO".ANO

ADOR
>---<:::!DA~TA~»>---:-- __----« ADDR+ 2
DATA >--

PVER

tPHIL

270899-30

4-190
 87C198/87C194

A.C. CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE

SERIAL PORT TIMING-SHIFT REGISTER MODE

Symbol Parameter Min Max Units
TXLXL Serial Port Clock Period (BRR 2 8002H) 6 Tose ns

TXLXH Serial Port Clock Falling Edge 4 Tose ±50 ns

to Rising Edge (BRR 2 8002H)
TXLXL Serial Port Clock Period (BRR = 8001 H) 4 Tose ns
TXLXH Serial Port Clock Falling Edge 2 Tose ±50 ns
to Rising Edge (BRR = 8001 H)

TOVXH Output Data Setup to Clock Rising Edge 2 Tose -50 ns

TXHOX Output Data Hold after Clock Rising J;:dge 2 Tose -50 ns
TXHOV Next Output Data Valid after Clock Rising Edge 2 Tose +50 ns

TOVXH Input Data Setup to Clock Rising Edge Tose +50 ns

TXHOX Input Data Hold after Clock Rising Edge 0 ns

TXHOZ Last Clock Rising to Output Float 1 Tose ns

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE

SERIAL PORT WAVEFORM-'sHIFT REGISTER MODE

270899-31

4-191
inter 87C198/87C194

A TO D CHARACTERISTICS stability OfVREF. VREF must be close to Vee since it

supplies both the resistor ladder and the digital sec-
There are two modes of AID operation: with or with- tion of the converter.
out clock prescaler. The speed of the AID converter
can' be adjusted by setting a clock prescaler on or
off. At high frequencies more time is needed for the AID CONVERTER SP,ECIFICATIONS
comparator to settle. The maximum frequency with
the clock prescaler disabled is 8 MHz. The conver- The specifications given below assume adherence
sion times with the prescaler turned on or off is to the Operating Conditions section of this data
shown in the table below. sheet. Testing is performed with VREF = 5.12V.

The converter is ratio metric, so the absolute The 87C194 does not have an AID converter.
accuracy is directly dependent on the accuracy and

Clock Prescaler On Clock Prescaler Off

IOC2.4 = 0 IOC2.4 = 1
158 States 91 States
26.33 p.s @ 12 MHz 22.75 p.s @ 8 MHz

Parameter Typical(1) Minimum Maximum Units' Notes

Resolution 512 1024 Levels
9 10 Bits
Absolute Error 0 ±4 LSBs
Full Scale Error 0.25 ±0.50 LSBs
Zero Offset Error -0.25 ±0.50 LSBs
Non-Linearity Error 1.5 ±2.5 0 ±4 LSBs
Differential Non-Linearity Error > -1 +2 LSBs
Channel-to-Channel Matching' ±0.1 0 ±1 LSBs
Repeatability ±0.25 LSBs
Temperature Coefficients:
Offset 0.009 LSBrC
Full Scale 0.009 LSBrC
Differential Non-Linearity 0.009 LSBrC
Off Isolation -60 dB 2,3
Feedthrough -60 dB 2
Vee Power Supply Rejection -60 dB 2
Input Resistance 1K 5K n
D.C. Input Leakage 0 3.0 p.A
Sample Time: Prescaler On 15 States 4
Prescaler Off 8 States 4
Input Capacitance 3 pF

NOTES:
'An "LSB", as used here, has a value 01 approximately 5 mY.
1. Typical values are expected lor most devices at 25°e but are not tested or guaranteed.
2. De to 100 KHz.
3. Multiplexer Break-Belore·Make Guaranteed.
4. One state = 167 ns at 12 MHz, 250 ns at 8 MHz.

4-192
inter 87C198/87C194

87C198 FUNCTIONAL DEVIATIONS REVISION HISTORY

The 87C198 has the following problems. This is the first version of the 87C198/87C194 Data
Sheet. .
1. Factory test modes. On future devices, factory
test modes will be entered by holding the ALE,
RD, WR and PWM pins in their active states on For more detailed information on the 87C198, re-
the rising edge of RESET. ALE, RD and WR are fer to the 80C196KB User's Manual, Order
active low, and PWM is active high. During RE- #270651. The 80C196KB User's GuIde applies to
SET, these pins will be held inactive by semi- the 87C198. Because the 87C198 is a reduced pin
strong devices. These semi-strong devices will count version, some 80C196KB features are not
sink or source about 2 mA and still stay above VIH available and are listed here:
or below VIL. Factory test modes are reserved by 1. PORT 1. PORT1 is a quasi-bidirectional port.
Intel. However, a system must be designed so A. HOLD/HLDA. This feature is multiplexed on
that it does not inadvertently enter one of these PORT1.5-.7 and is not available.
modes.
2. The AID converter loses four of its input chan-
The PWM pin is the qualifier. If the PWM pin is nels, ACHO-3.
above VIL and any of the other pins are below
VIH, the device may enter a factory test mode. A 3. T2CAPTURE (P2.7) Timer2 Capture feature is not
system must not override any of these semi- available.
strong devices. 4. T2UP/DN (P2.6) The Timer2 UP/DOWN feature
is not available.
5. CLKOUT
6. NMI
7. BUSWIDTH
8. SHE

4-193
 MCS®-96
87C196KB/83C196KB/80C196KB
Express

• Extended Temperature Range • Burn-In

( - 40°C to + 85°C)

The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®:96 family of
microcQntroliers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.

The EXPRESS program includes an extended temperature range with orwithout burn-in, depending on the package
type.

With the commercial standard temperature range operational characteristics are guaranteed over the temper-
ature range of O°C to +' 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40°C to +' 85°C.

The optional burn-in is dynamic, for a minimum time of 160 hours at 125°C with Vcc = 5.5V ± 0.5V, following
guidelines in MIL-STD-883, Method 1015. .

Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.

This data sheet specifies the parameters for the extended temperature range option. The commercial temperature
range data sheets including functional deviations are applicable otherwise.

VREF ANGND

CONTROL
SIGNALS

PORT 3

} ~f~:
BUS

PORT 4

~
270590-1

Figure 1. 8XC196KB Block Diagram

Intel Corporation assumes no responsibilityforthe use of any circuitry other than circuitry embodied in an Intel product. No other circuit
patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
August 1989
© l[ltel Corporation, 1987 Order Number: 270780-002

4-194
 8XC196KB,EXPRESS

Table 1. Express Prefix Identification

Product Prefix Package, Temperalure Burn,-In

80C 196KB12/80C196TB12 LA PGA " Extended ' Yes
TN PLCC Extended No
83C 196KB12/83C196TB12 TN filLCC Extended No
87C196KB10 LR LCC Extended Yes

Table 2. Thermal'Cllaracteristlcs

Package Type ala ajc .

" ,
PGA .28°CIW " 3.5°CIW

PLCC 35°CIW 12°CIW

LCC 28°CIW 3.5°CIW

4·195
 ~[Q)W~[NJ©~ n[NJlF(Q)lRlfl~un©[f.!]·
8XC196KBEXPRESS , ,~

EXPRESS PACKAGING
The 80C196KBITB and 83C196KBITB are available in a 68~pin PLCC package. In addition, the80C196KBITB is
available in a 68-pin PGA package. The 87C196KB is only available in a 68-pin LCC package.

PGAI PGAI PGAI

LCC PLCC Description LCC PLCC Description LCC PLCC Description

1 9 ACH7/PO.7 24 54 AD6/P3.6 47 31
--
P1.6/HLDA
2 8 ACH6/PO.6 25 . 53 AD7/P3.7 48 30 P1.5/BREQ
3 7 ACH2/PO.2 26 52 AD8/p4.0 49 29 HSO.1
4 6 ACHO/PO.O 27 51 . AD9/P4.1 50 28 HSO.O
5 5 ACH1/pO.1 28 50 AD10.P4.2 51 27 HSO.5/HSL3
6 4 ACH3/PO.3 29 49 AD11/P4.3 52 26 HSO.4/HSL2
7 3 NMI 30 48 AD121P4.4 53 25 HSL1
8 2 EA 31 47 AD13/P4.5 54 24 HSLO
9 1 Vee 32 46 AD14/P4.6 55 23 P1.4
10 68 Vss 33 45 AD15/P4.7 56 22 P1.3
11 67 XTAL1 34 44 T2CLKlP2.3 57 21 P1.2
12 66 XTAL2 35 43 READY 58 20 P1.1
13 65 CLKOUT 36 42 T2RST/P2.4/AINC 59 19 P1.0
14 64 BUSWIDTH 37 41 BHElWRH 60 18 TXD/P2.0
15 63 INST 38 40 WRIWRL 61 17 RXD/P2.1
16 62
-
ALE/ADV 39 39 PWM/P2.5 62 16 RESET
17 61 RD' 40 38 P2.71T2CAPTURE/PACT
-- 63 15 EXTINT/P2.2
18 60 ADO/P3.0 41 37 Vpp 64 14 Vss
(1)

19 59 AD1/P3.1 42 36 Vss 65 13 V REF

20 58 AD2/P3.2 43 35 HSO.3/SID3 66 12 ANGND
21 57 AD3/P3.3 44 34 HSO.2/SID2 67 11 ACH4/PO.4
22 56 AD4/P3.4 45 33 P2.61T2UP-DN 68 10 ACH5/PO.5
23 55 AD5/P3.5 46 32 P1.7/HOLD

NOTE: Figure 2. Pin Definitions

1. This pin was formerly the Clock Detect Enable Pin. The CDE function is not guaranteed t9 work, therefore this
pin must be directly connected to Vss'

Pins FaCing Down

17 15 13 11 9 7 5 3 1'-
18191614 1210 8 6 4 2 68
2021 6766
~CSiP)-96
2223 6564
68 PIN
2425 GRID ARRAY 6362
2627 61 60
2829 TOP VIEW 5958
LOOKING DOWN ON
3031 CO~PONENT SIDE 5756
OF PC BOARD 5554
3233
3436 38 40 4244 46 48 50 5352
35 37 39 41 43 45 47 49 51
270634-23
Figure 3. 68-Pin Package (Pin Grid Array - Top View) 80C196KB Only
·4-196
 8XC196KB EXPRESS

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
ACH5/PO,5 10 AOO/P3,0
ACH4/PO,4 A01/P3,1
ANGND AD2/P3,2
V REf AD3/P3,l
'VSS
MCS®-9.6 AD4/P3.4
EXTINT/P2,2 68 PIN AD5/P3,5
RESET PLCC AD6/P3,6
RXO/P2,1 AD7/P3,7
TXO/P2,0 AD&/R4,0
P1.0 AD9/P4,1
P1.1 TOP VIEW AD10/P4.2
P1.2 ADll/PO
LOOKING DOWN ON
P1.3 ADI2/P4,4
P1.4
COMPONENT SIDE ADI3/P4,5 '
HSIO OF PC BOARD AD14/P46
HSll AD15/P4.7
H512/H504 , 44 T2CLK/P2,3
272,8 29 30 31 323334 35 36 37 38 3& 40 41 42 43

270634-2

Figure 4. 58-Pin Package (PLCC-Top View) 83C196KB/80C196KB

.... co NO ....
c:i c:i c:i c::i c:i c:i
~~.e::..e::.~~
.... co N O .... I")
...,

N
..
::>
:t
Q I~
.." .." ." "..
:>: :>: :>: :>: :>: :>:
~ ~
Vl~
'i I~ ~ '"
z > > x . ~ d.
-' 0
~ Iii
::>
l!:
"~ 1~
;'1 2 3 4 5 6 7 1011 12 13 14 15 16 17 L
ACH5/PO,5 68 18 ADO/P3,0
ACH4/PO.4 67
68 PIN AD1/P3,1
19
ANGND 66 LEADLESS CHIP CARRIER 20 AD2/P3,2
VREF 65 TYPE "S" 21 AD3(P3,3
v88 64 22 AD4/P3.4
EXTINT/P2,2 63 23 ADS/P3,5
RE5ET 62 ' 24 AD6/P3,6

0
RXO/P2,1 61 25 A07/P3,7
TXD/P2,0 60 26 A08/P4,0
PLO 59 27 AD9/P4,1
Pt.1 58 28 A010/P4,2
P1.2 57 29 A011/PO
P1.3 56 30 AD12/PU
P.l.4 55 31 A013/P4,5
H51.0 54 (EPROM ONLY) 32 A014/P4,6
H51,1 53 TOP VIEW 33 , A015/P4,7
H51.2/H50.4 52 34 T2CLK/P2,3
., 51 50 49 48 47 46 45 44 43 4241 40 39 38 37 36 35 r"

8 ~ ~ ~ ~:; ~ ~'~ ;>8:~

~ z x ~ ~ ~ ~ x z
en
:>:
270680-2
(Top view looking down on component side of PC boards)

Figure 5. 58-Pin Package (LCC-Top View) 87C196KB Only

4-197
in1:el 8XC196KBEXPRESS

ELECTRICAL CHARACTERISTICS • Notice: Stresses above those listed under '~bso­

lute Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
Absolute Maximum Ratings* functional operation of the device at these or any
other conditions above those indicated in the opera-
Ambient Temperature tional sections of this specification is not implied. Ex-
Under Bias ................................... -40°C to +85°C posure to absolute maximum rating conditions for
Storage Temperature ..................... -65°C to +150°C extended periods may affect device reliability.
Voltage On Any Pin to V ss ................ -0.5V to +7.0V
NOTICE Specifications contained within the
Power Dissipation ............................................. 1.5W fol/owing tables are subject to change.

Operating Conditions
Symbol Description Min Max Units
TA Ambient Temperature Under Bias -40 +85 ·C

• Vee Digital Supply Voltage

Analog Supply Voltage
4.50
4.50
5.50
5.50
V
V
VREF
fose Oscillator Frequency 3.5 12 MHz

NOTE:
ANGND and Vss should be nominally at the same potential.

This Is an Advance Data Sheet. It is expected that parameters may change before Intel releases this
product for sale. Contact your local sales office before finalizing the Timing ,and D.C. Characteristics
section of a design to verify you have the latest information.

D.C. Characteristics (Over specified operating conditions)

Symbol Description Min Max Units Test Conditions
VIL • Input Low Voltage -0.5 0.8 V
VIH Input High Voltage (Note 1) 0.2 Vee + 0.9 Vee + 0.5 V
VIH1 Input High Voltage on XTAL 1 0.7 Vee Vee + 0.5 V
VIH2 Input High Voltage on RESET 2.4 Vee + 0.5 V
VOL Output Low Voltage 0.3 V IOL = 200/LA
0.45 V IOL = 3.2mA
1.5 V IOL = 7,mA
VOH Output High Voltage Vee - 0.3 V IOH = -200/LA
(Standard Outputs) Vee - 0.7 V IOH = -3.2 mA
Vee- 1.5 V IOH = -7mA
VOH1 Output High Voltage Vee - 0.3 V IOH = -71lA
(Quasi-bidirectional Outputs) Vee - 0.7 V IOH = -30/LA
Vee - 1.5 V IOH = -60/LA
III Input Leakage Current (Std. Inputs) ±10 /LA o< VIN < Vee - 0.3V
ILl1 Input Leakage Current (Port 0) ±3 /LA 0< VIN < VREF
ITL 1 to 0 Transition Current (QBD Pins) ..,..650 /LA VIN = 2.0V
IlL Logical 0 Input Current (QBD Pins) ~50 /LA VIN = 0.45V
IILl Logical 0 Input Current in Reset (Note 2)
-1.2 mA VIN = 0.45 V
(ALE, RD, WR, BHE, INST,P2.0)

NOTE:
1. All pins except RESET and XTAL 1. ,
2. Holding these pins below VIH in Reset may cause the part to enter test modes.

4-198
inl:el 8XC196KB EXPRESS

D.C. Characteristics (Over specified operating conditions) (Contirludd)

Symbol Description Min Typ(7) Max Units Test Conditions

Icc Active Mode Current in Reset 40 55 rnA XTAL 1 = 12 MHz
AID Converter Reference Current 2 5 rnA Vcc = Vpp = VREF = 5.5V
IREF
IIDLE Idle Mode Current 10 2.5 rnA

ICCl Active Mode Current in Reset 15 22 rnA XTAL1 =; 3.5 MHz

IpD(6) Powerdown Mode Current 5 tJ-A VCC = Vpp = VREF = 5.5V

RRST. Reset Pull up Resistor 6K 100K n

Cs Pin Capacitance (Any Pin to VSS) 10 pF fTEST = 1.0 MHz

NOTES:
(Notes apply to all specifications)
1. QSD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7. "
2. Standard Outputs include ADO-15, RD, WR, ALE, SHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
'TXD/P2.0, and RXD (in serial mode 0). The V.Qt! specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
3. Standard Inputs include HSI pins, CDE, EA, READY, SUSWIDTH, NMI, RXD/P2,1, EXTINT/P2.2, T2CLK/P2.3, and
T2RST IP2.4.
4. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below Vee - 0.7V:
IOL on Output pins: 10 mA
IOH on quasi-bidirectional pins: self limiting
IOH on Standard Output pins: 10 mA
5. Maximum current per bus pin (data and control) during normal operation is ±3.2 mAo
6. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6 IOL: 29 mA IOH is self limiting
HSO, P2.0, RXD, RESET IOL: 29 mA IOH: 26 mA
P2.5, P2.7, WR, SHE IOL: 13 mA IOH: 11 mA
ADO-AD15 IOL: 52 mA IOH: 52 mA
RD, ALE, INST -CLKOUT IOL: 13 mA IOH: 13 mA .
7. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and VREF = Vee = 5V.
6. Ipo is not guaranteed on the standard 60C196KS part and may exceed 100 IJ.A on some parts. Customers whos.e applica-
tions use the powerdown mode and require a guaranteed maximum value of Ipo should contact an Intel Field Sales Repre-
sentative.

60r------r-----,r-----~

40 f---+----:J~-__:;..! ICC lYPICAL (7)

ICC 30 f-------+-~fL-__j"""'----_j
rnA
20 f--___..::t-,"""''----c:J.....=---_jI,OLE MAX

10 f-----'9------If--:=:..-lIIDLE lYPICAL

O~----~----~~----~
ICC Max = 3.88 X FREO + 8.43 4MHz 8MHz 12MHz

IIDLE Max = 1.65 X FREO + 5.2 FREQ

270634-15

Figure 6. Icc and IIDLE vs Frequency

4-199
inter 8XC196KB 'EXPRESS

A.C. CHARACTERISTICS
For use over specified operating conditions
Test Conditions: Capacitive. load on. all pins'; 100 pF, Rise and fall times = 10 ns, fosc = 12 Mhz

The system must meet these specifications:

Symbol Description Min Max Notes

TAvyV Address valid to READY setup
80C196KB12/83C196KB12 2Toscr-85
87C196KB10 2TosC:-105

T LLyV ALE low to READY setup

80C196KB12/83C196KB12 Tosc-65
87C196KB10 Tosc-95
TYLYH Non READY time No Upper Limit

TCLYX READY hold after CLKOUT low 0 Tosc-30 Note 1

TLLyX READY hold after ALE low Tosc-15 2Tosc-40 Note 1

TAVGV Address valid to BUSWIDTH setup

80C196KB12/83C196KB12 2Tosc-85
87C196KB10 2Tosc-95

TLLGV ALE low to BUSWIDTH setup

80C196KB12/83C196KB12 Tosc--60
87C196KB10 Tosc-85
TCLGX BUSWIDTH hold after CLKOUT low 0
TAVDV Address valid to input data valid
80C196KB12/83C196KB12 3Tosc--60 Note 2
87C196KB10 3Tosc-80

TRLDV RD low to input data valid

80C 196KB 12/83C 196KB 12 Tosc-25 Note 2
87C196KB10 Tosc-30

TCLDV CLKOUT low to input data valid

80C196KB12/83C196KB12 Tosc-50
87C196KB10 Tosc--60
T RHDZ RD high to input data float Tosc-20

T RXDX Data hold after RD inactive 0

NOTE:
1. If max is exceeded, additional wait states will occur.
2. When using wait states, add 2Tosc x n where n = number of wait states.

4·200
 8XC196KB EXPRESS

A.C. CHARACTERISTICS
For use over specified operating conditions ,
TestConditions: Capacitive load on all pins = 100 pF, Rise and fall.times = 10 ns, fosc =,12 Mhz

The 8XC196KB will meet these specifications:

Symbol Description Min Max Notes

FXTAL Frequen~y on XTAL 1

80C196KB12/83C196KB12 3.5 12 Note 1
87C196KB10 3.5 10 Note 1

Tosc 1/FXTAL
80C 196KB12/83C 196KB 12 83 286
87C196KB10 100 286
T XHCH XTAL 1 high to CLKOUT high or low Note 2
80C196KB12/83C196KB12 35 110
87C196KB10 40 130
T CLCL CLKOUT cycle time 2Tosc
T CHCL CLKOUT high time Tosc-10 Tosc+10

TCLLH CLKOUT falling edge to ALE rising -5 15

T LLCH ALE falling edge to CLKOUT rising -15 15

TLHLH ALE cycle time 4Tosc Note 4

TLHLL ALE high period Tosc-12 Tosc+12

T AVLL Address setup to ALE falling Tosc - 20
T LLAX Address hold after ALE falling
80C196KB12/83C196KB12 Tosc-40
87C196KB10 . Tosc - 45

TLLRL ALE falling edge to RD falling

80C196KB12/83C196KB12 Tosc-40
87C196KB10 Tosc-45
• T RLCL RD low to CLKOUT falling 5 30

TRLRH RD low period Tosc- 5 Tosc+25 Note 4

TRHLH RD rising edge.to ALE rising Note 3

80C196KB12/83C196KB12 Tosc Tosc+25
87C196KB10 Tosc Tosc+30

TRLAZ RD low to address float 10

T LLWL ALE falling edge to WR falling Tosc-10
TCLWL CLKOUTlow to WR falling
80C196KB12/83C196KB12 0 25.
87C196KB10 0 30

TOVWH Data stable to WR rising

80C196KB12/83C196KB12 Tosc-23 Note 4
87C196KB10 Tosc - 30
T CHWH CLKOUT high to WR rising -10 +10
T WLWH WR low period Tosc-30 Tosc+5 Note 4

4-201
 8XC196KB EXI:>RESS

A.C. CHARACTERISTICS (continued from page 8)

Symbol Description Min Max Notes

TWHQX Data hold after WR rising Tosc-10

TWHLH WR rising edge to ALE rising Tosc-10 Tosc+15 Note 3

TWHBX BHE, INST hold after WR rising Tosc-10
TWHAX AD8-15 hold after WR rising Tosc-50
TRHBX BHE, INST hold after RD rising Tosc-10
TRHAX AD8-15 hold after RD rising Tosc-50

NOTES:
1. Testing performed at 3.5 MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Typical specification, not guaranteed.
3. Assuming.l;>ack-to-back bus cycles.
4. When using wait states, add 2 Tosc x n where n =number of wait states.

4-202
intel 8~C196KB EXPRESS

System Bus Timings

XTALl

CLKOUT

ALE

BUS ADDRESS OUT ADDRESS

BHE,INST VALID

AD8-15 ADDRESS OUT

270634-24

4-203
 aXC196KB EXPRESS

READY Timings (One Waitstate)

_TAVYV_

TRLRH + 2Tose

READ

T RLDV,+ 2Tose
TAVDV+ 2Tose

BUS ADDRESS OUT

~.
~
TWLWH+ 2Tose
WRITE

TOVWH+ 2Tose

BUS ADDRESS OUT DATA OUT ADDRESS

4·204
 8XC196KB EXPRESS

Buswidth Timings

XTAL1

CLKOUT

ALE

BUSWIDTH

~TAVGV
BUS -{ ADDRESS OUT )~~(~_ _D_AT_A-J)~-------

4-205
inler aXC196KB EXPRESS

HOLD/HLDA Timings

Symbol Description Min Max Units Notes

, ~"

-- ,
THVCH HOLD Setup 90 ns 1
--
CLKOUT Low to HLDA Low -15 15 ns
TCLHAL

TCLBRL CLKOUT Low to BREQ Low -15 15 ns

THALAZ HLDA Low to Address Float -25 ns

THALBZ HLDA Low to SHE, INST, RD, WR Float -30 ns

TCLHAH CLKOUT Low to HLDA High -15 15 ns

TCLBRH CLKOUT Low to SREQ High -15 15 ns

THAHAX HLDA High to Address No Longer Float -5 ns

IHAHBV HLDAHigh to SHE, INST, RD, WR Valid -25 ns

TCLLH CLKOUT Low to ALE High -5 15 ns

NOTES':
1, To guarantee recognition at next clock,

CLKOUT

HOLD
LATENCY
HOLD

HLDA
TCLHAL_
-- TCLHAH_
--
BREQ
TCLBRH-
--
BUS
THAHAX---
--
BHE, THAHBV
\ I
INST
' I

n
\
Ro,WR

TCLLH

ALE.f\
{
II
, II
{ ,
4-206
 8XC196KB EXPRESS

EXTERNAL CLOCK DRIVE

Symbol Parameter Min Max Units

, 1fTXLXL Oscillator Frequency
80C196KB12/83C196KB12 3.5 12.0 MHz
87C196KB10 3.5 10.0 MHz
TXLXL Oscillator Frequency
80C 196KB12/83C196KB12 83 286 ns
87C196KB10 100 286 ns
TXLXX High Time 32 ns

TXLXX Low Time 32 ns

TXLXH Rise Time 10 ns

TXHXL Fall Time 10 ns

EXTERNAL CLOCK DRIVE WAVEFORMS

270634-18

An external oscillator may encounter as much as a 100 pf load at XTAL 1 when it starts-up. This is due to interaction
between the amplifier and its feedback capacitance. Once the external signal meets the V' I and V' h specifications,
the capacitance will not exceed 20pf. ' I I

A.C. TESTING INPUT, OUTPUT WAVEFORM FLOAT WAVEFORM

2,4=X
0.45
, ' 2 . 0 > TEST POINTS
. 0.8
<' 2.0
0.8 .
>C
270634-19
A.C, Testing inputs are driven at 24V for a Logic "1" and 0.45V 270634-20
for a Logic "0" Timing measurements are made at 2,OV for a For Timing Purposes a Port Pin is no Longer Floating when a
Logic "1" and 0,8V for a Logic "0", 100 mV change from Load Voltage Occurs and Begins to Float
when a 100 mV change from the Loaded VOHIVOL Level occurs
IOL/IOH = ± 15 mA.

EXPLANATION OF AC SYMBOLS

Eachsymbol is two pairs of letters prefixed by"T" fortime. The characters in a pair indicate a signal and its condition,
respectively. Symbols represent the time between the two signal/condition points.

Conditions: Signals:
H - High A - Address G - Buswidth R - RD
L - Low B - BHE H - HOLD W - WRIWRHIWRL
V - Valid BR - BREQ HA - HLDA X - XTAL1
X - No Longer Valid C - CLKOUT L - ALElADV Y - READY
Z - Floating D - DATA IN Q - DATA OUT

4-207
 8XC196KB EXPRESS

A.C. CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE

SERIAL PORT TIMING-SHIFT REGISTER MODE

Symbol Parameter Min Max Units
TXLXL Serial Port Clock Period (BRR ;?; 8002H) {Hose ns
TXLXH Serial Port Clock Falling Edge 4 Tose ±50 ns
to Rising Edge (BRR ;?; 8002H)
TXLXL Serial Port Clock Period (BRR = 8001 H) 4 Tose ns
TXLXH Serial Port Clock Falling Edge 2 Tose ±50 ns
to Rising Edge (BRR = 8001 H)
TOVXH Output Data Setup to Clock Rising Edge 2 Tose -50 ns
TXHOX Output Data Hold after Clock Rising Edge 2 Tose -50 ns
TXHOV Next Output Data Valid after Clock Rising Edge 2 Tose +50 ns
TDVXH Input Data Setup to Clock Rising Edge Tose +50 ns
TXHDX Input Data Hold after Cloqk Rising Edge 0 ns
TXHOZ Last Clock Rising to Output Float 1 Tose ns

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE

SERIAL PORT WAVEFORM-SHIFT REG,ISTER MODE

270634-21

4-208
ifltel 8XC196KB EXPRESS

A TO D CHARACTERISTICS stability of VREF. VREF must be close to Vee since it

supplies both the resistor ladder and the digital sec-
There are two modes of AID operation: with or with- tion of the converter.,
out clock prescaler. The speed of the AID converter
can be adjusted by setting a clock prescaler on or
off. At high frequencies more time is ne.:;ded for the AID CONVERTER SPECIFICATIONS
comparator to settle. The maximum frequency with
the clock prescaler disabled is 6 MHz. The conver- The specifications given below assume adherence
sion times with the prescaler turned on or off is to the Operating Conditions section of this data
shown in the table below. sheet. Testing is performed with VREF = 5.12V.

The converter is ratiometric, so the absolute

accuracy is directly dependent on the accuracy and

Clock Prescaler On Clock Prescaler Off

IOC2.4 = 0 IOC2.4 = 1
158 States 91 States
26.33 J.Ls @ 12 MHz 30.3 J.Ls @ 6 MHz

Parameter Typical(1) Minimum Maximum Units' Notes

Resolution 512 1024 Levels
9 10 Bits
Absolute Error 0 ±6 LSBs
Full Scale Error 0.25±0.50 LSBs
Zero Offset Error -0.25±0.50 LSBs
Non-Linearity Error 1.5±2.5 0 ±4 LSBs
Differential Non-Linearity >-1 +2 LSBs
Channel-to-Channel Matching ±0.1 0 ±1 LSBs
Repeatability ±0.25 LSBs
Temperature Coefficients:
Offset 0.009 LSBI'C
Full Scale 0.009 LSBI'C
Differential Non-Linearity 0.009 LSBI'C
Off Isolation -60 dB 2,3
Feedthrough -60 dB 2
Vee Power Supply Rejection -60 dB 2
Input Resistance 1K 5K n
D.C. Input Leakage 0 3.0 /LA
Sample Time: Prescaler On 15 States 4
Prescaler Off 8 States 4
Input Capacitance 3 pF

NOTES:
'An "LSB", as used here, has a value 01 approximately 5 mY.
1. Typical values are expected lor most devices at 25°C but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer Break-Belore-Make Guaranteed.
4. One state = 167 ns at 12 MHz, 333 ns at 6 MHz.

4-209
inter 8XC196KB EXPRESS

DATA SHEET REVISION HISTORY

The following differences exist between this and the -001 version of the 8XC196KB Express data sheet.

1. The 83C 196KB ROM device was added.

2. The,CDE (Clock Detect Enable) pin wa~ changed to a Vss pin.
3. Thermal Characteristics for all packages were added.
4. The figures for System Bus Timings were redrawn to include missing timings and to more accurately describe'
a wait state condition.
----
5. HOLD/HLDA timings were added.

4-210
 I ":nti Wd ci :1 4'1+' 'Ii i (1)@':il)iriP)

EV80C196KB FEATURES
• Zero Walt-State 12 MHz Execution Speed
• 24K Bytes of ROMsim
• Flexible Wait-State, Buswidth, Chip-Select Controller
• Totally CMOS, Low Power Board
• Concurrent Interrogation of Memory and Registers
• Sixteen Software Breakpoints
• Two Single Step Modes
-. High-Level Language Support
• Symbolic Debug
• RS-232-C Communication Link
LOW COST CODE EVALUATION TOOL
Intel's EV80C196KB evaluation board provides a hardware environment for code
execution and software debugging at a relatively low cost. The board features the
80C196KB advanced, CHMOS*, 16-bit microcontroller, the newest member of the
industry standard MCS®-96 family. The board allows the user to take full advantage of
the power of the MCS-96. The EV80C196KB provides zero wait-state, 12 MHz execution
of a user's code. Plus, its memory (ROMsim) can be reconfigured to match the user's
planned memory system, allowing for exact analysis of code execution speeds in a
particular application.
"CHMOS IS a patented Intel process
UIBM PC, XT, AT <lod DOS are regl(:.tered trddemarks of International Busme!>s Mathmes Corporalion

intel~-~-_·----·---- .---~--~..---.. -.--.-.-.-.--.-.

Intel CorporatlOP assume~ no responslblhty for the use of any CircUitry other than CircUItry embodte~ ll1 an lntE:! product No other CIrcUIt patent
hcenses CIre llilphed Infornldtwn con tamed herem super~ede" preVIOusly pUbh"hed :.p(,-'::lhcntlon'> on th(>$'" dl'vKes from Intel
FEBRUARY 1989
IS'- Intel Corp(watlon 1989 Orde~ number 270729~OOl

4-211
P~pular features such as a symbolic single, line assembler / disassembler, si~gle-step'
p~ogram exec(ltion, ,and sixteen software breakpoints are standard on the EV80C196KB.
Intel provides a c,omplete code development environment using assembler (ASM-96) as
Well as high-level languages such as Intel's iC-96 or PL/M-96 to accelerate development
schedules. "

The ,evaluation board is hosted on an IBM PC** or BIOS-compatible clone, already a

standard development solution in most of today's engineering environments. The source
code for the on~board monitor (written in ASM-96) is public domain. The program-is
about 1K,and can be easily modified to be included in the user's target hardware. In this
way, the provided PC host software can be used throughout the development phase.

FULL SPEED EXECUTION

The EV80C196KB executes the user's code from on-board ROMsim' at 12 MHz with zero
wait-states. By changing crystals on the 80C196KB any slower execution speed can be
evaluated. The boards host interface timing is not affected by this crystal change.

24KBYTES OF ROMSIM
the board comes with 24K bytes of SRAM to be used as ROMsim for the user s code and
as data memory if needed. 16K bytes of this memory are configured as sixteen bits wide,
and 8K bytes are configured as eight bits wide. The user can therefore evaluate the speed
of the part executing from either buswidth. '

FLEXIBLE MEMORY DECODING

By changing the Programable Logic Device (PLD) on the board, thememory on the board
can be made to look like the memory system planned for the user's hardware application.
The PLD controls the buswidth of the 80C196KB and the chip-select inputs on the board.
It also controls the number of wait states (zero to three) generated by the 80C196KB
during a memory cycle. These features can all be selected with 256 byte boundaries
of resolution.

TOTALLY CMOS BOARD

The EV80C196KB board is built totally with CMOS components. Its power consumption
is therefore very low, requiring 5 volts at only 300 rnA. If the on board LED's are
disabled, the current drops to only 165 rnA. The board also reqUires + / - 12 volts at
15mA.

CONCURRENT INTERROGATION OF MEMORY AND REGISTERS

The monitor for the EV80C196KB allows the user to read and modify internal registers
and external memory while the users code is ruiming in the board.

SIXTEEN SOFTWARE BREAKPOINTS

There are sixteen breakpoints available which automatically substitute a TRAP
instruction for a user's instruction at the breakpoint location. The substitution occurs
when execution is started. If the code is halted or a breakpoint is reached, the user's code
is restored in the ROMsim.

4-212
TWO STEP MODES
There are two single-step modes available. The first stepping mode locks out all
interrupts which might occur during the step. The second mode enables interrupts, and
treats subroutine calls and interrupt routines as one indivisible instruction.

HIGH LEVEL LANGUAGE SUPPORT

The host software for the EV80C196KB board is able to load absolute object code
generated by ASM-96, iC-96, PL/M-96 or RL-96 all of which are available from Intel.

SYMBOLIC DEBUG
The host has a Single Line Assembler, and a Disassmbler, which recognize symbolics
generated by Intel software tools.

RS-232-C COMMUNICATION LINK

The EV80C196KB communicates with the host using an Intel 82510 UART provided on
board. This frees the on-chip UART of the 80C196KB for the user's application.

PERSONAL COMPUTER REQUIREMENTS

The EV80Cl96KB Evaluation Board is hosted on an IBM PC, XT, AT" or BIOS
compatible done. The PC must meet the following minimum requirements:

• 512K Bytes of Memory

• One 360K Byte floppy Disk Drive
• PC DOS" 3.1 or Later
• A Serial Port (COM1 or COM2) at 9600 Baud
• ASM-96, iC-96 or PL/M-96
• A text editor such as AEDIT

PI

RS·232
ClFSELECT
BUFFERS
BUSWDIli
8OCI96KB READY
CPU
LOGIC

P2
T.d

R.d ADDRESS
l I ~ ...
82510
ANALOG INPUT 8to32K 8to32K 8to32K UART

,-
PortO DATA
ANALOG x16 .16 .8
DIGITAL RAMEPROM RAMEPROM RAMEPROM
DIGITAL 110 110 CONTROL
Port 1,2 '----

*
HSO,HSI

Block Diagram of the 80C196KB Board

4-213
"'.'
80C196KC, User's Guide 5
and Data Sheets
 October 1990

80C196KC
User's Guide

Order Number: 270704·003

5·1
· 80C196KC USER'S GUIDE CONTENTS PAGE
1.0 CPU OPERATION .................... 5-4
1.1 Memory Controller ................ 5-5
1.2 CPU Control ...................... 5-5
1.3 Internal Timing .. '.................. 5-5

2.0 MEMORY SPACE .................... 5-7

2.1 Register File ...................... 5-7
2.2 Special Function Registers ........ 5-7
2.3 Internal ROM and EPROM ....... 5-11
2.4 System Bus ...................... 5-11
3.0 SOFTWARE OVERViEW ............ 5-11
3.1 Operand Types .................. 5-11
3.2 Operand Addressing ............. 5-12
3.3 Register Windowing .............. 5-15
3.4 Program Status Word ............ 5-17
3.5 Instruction Set ................... 5-18
3.6 BOC196KC Instruction Set
Additions ...................... 5-27
3.7 Software Standards and
ConveJltions ................... 5-28
, ' 3.B Software Protection Hints ........ 5-29
4.,0 PERIPHERAL OVERVIEW .......... 5-29
4.1 POise Width Modulation Output
(D/A) .......................... 5-29
4.2 Timer1 and Timer2 ............... 5-29,
4.3 High Speed Inputs (HSI) ......... 5-29
4.4 High Speed Outputs (HSO) ....... 5-30
4.5 Serial Port ....................... 5-30
4.6 AID Converter ................... 5-31
4.7110 Ports ........................ 5-31
4.B Watchdog Timer ................. 5-31
5.0 INTERRUPTS ....................... 5-32
5.1 Interrupt Control ................. 5-33
5.2 Interrupt Priorities ................ 5-34
5.3 Critical Regions .................. 5-35
5.4 Interrupt Timing .................. 5-36
5.5 Interrupt Summary ............... 5-36
6.0 Peripheral Transaction Server ..... 5-38
6.1 PTS Control ..................... 5-39
6.2 PTS Modes ...................... 5-41

5-2
 CONTENTS PAGE CONTENTS PAGE

7.0 Pulse Width Modulation Output 14.0 MINIMUM HARDWARE

(D/A) ............................. 5-45 CONSIDERATIONS ............. 5-75
7.1 Analog Output ................... 5-46 14.1 Power Supply ................. 5-75
14.2 Noise Protection Tips .......... 5-75
8.0 TIMERS ............................. 5-47
14.3 Oscillator and Internal
8.1 Timer1 ........................... 5-47 . Timings ..................... 5-76
8.2 Timer2 ........................... 5-47 14.4 Reset and Reset Status ....... 5-77
8.3 Sampling on External Timer 14.5 Minimum Hardware
Pins ............................ 5-49 Connections .... : ........... 5-79
8.4 Timer Interrupts .................. 5-49
15.0 SPECIAL MODES OF
9.0 High Speed Inputs ................. 5-49 OPERATION .................... 5-81
9.1 HSI Modes ...................... 5-50 15.1 Idle Mode ~ .................... 5-81
9.2 HSI Status ........ : ............... 5-51 . 15.2 Powerdown Mode ............. 5-81
9.3 HSI Interrupts .................... 5-51 15.3 ONCE and Test Modes ........ 5-82
9.4 HSI Input Sampling .............. 5-52
16.0 EXTERNAL MEMORY
9.5 Initializing the HSI ................ !;i-52 INTERFACING .................. 5-82
16.1 Bus CYperation ............... ,. 5-82
10.0 HIGH SPEED OUTPUTS ........... 5-52
16.2 Chip Configuration Registers .. 5-83
10.1 HSO Interrupts and Software
Timers ...................... 5-53 16.3 Bus Width ..................... 5-86
10.2 HSO CAM ..................... 5-53 16.4 HOLD/HLDA Protocol ......... 5-87
10.3 HSO Status ................... 5-54 16.5 AC Timing Explanations ....... 5-89
10.4 Clearing the HSO and Locked 16.6 Memory System Examples .... 5-93
Entries ...................... 5-55 16.7 I/O Port Reconstruction ....... 5-95
10.5 HSO Precautions .............. 5-56
10.6 HSO Output Timing ............ 5-56. 17.0 USING ROM AND EPROM
PARTS .......................... 5-95
11.0 SERIAL PORT .................... . 5-56 17.1 Programming the 87C196KC .. 5-95
11.1 Serial Port Status and 17.2 Auto Programming Mode ...... 5-96
Control ..................... 5-56 17.3 Slave Programming Mode ..... 5-98
11.2 Serial Port Interrupts .......... 5-58 17.4 Run-Time Programming ....... 5-99
11.3 Serial Port Modes ............. 5-58 17.5 ROM/EPROM Memory
11.4 Multiproc€lc;sor Protection Options ......... 5-100
Communications ............ 5-60 17.6 UPROMs .................... 5-101
12.0 AID CONVERTER ............... ,. 5-61 18.0 80C196KB to 80C196KC ......... 5-102
12.1 AID Conversion Process ....... 5-64 18.1 New Features of the
12.2 AID Interface S~ggestions .... 5-65 BOC196KC ................. 5-102
12.3 The AID Transfer Function .... 5-66 1B.2 Converting 80C196KB Designs
to 80C196KC Designs ...... 5-102
12.4 AID Glossary of Terms ........ 5-70

. 13.0 I/O PORTS ........................ 5-71

13.1 Input Ports .................... 5-71
13.2 Quasi-Bidirectional Ports ...... 5-72
13.3 Output Ports .................. 5-73
13.4 Ports 3 and 4/ADO-15 ........ 5-74
5-3
 80C196KC USER'S GUIDE

The 80C196KC family is a CHMOS branqh of the There are many members of the 80C196KC family; to
MCS®-96 family of high performance, 16-bit microcon- provide easier reading this manual will refer to the fam-
trollers. Other members of the MCS-96 family include ily ge~erically as the 80Ct96KC. Where information
the 8096BH, 8098 and 80C196KB. All of the MCS-96 applies only to specific components it will be clearly
components share a common instruction set and archi- indicated.
tecture. However the CHMOS components have en-
hancements to provide higher performance and lower This document was written to be a standalone users'
power consumptions. The .80C196KC has twice the guide for anyone wishing to implement a design with
memory of any previous MCS-96 family member with the 80C196KC. Those customers who are already fa-
488 bytes of RAM and 16K of ROM/EPROM, and at miliar with the 80C196KB architecture can proceed to
16 MHz, is 33% faster thanari 80C196KB at 12 MHz section 18 for a description of the additional features of
and at least twice as fast as an 8096BH at 12 MHz. the 80C 196KC. Section 18 also contains the informa-
Because some instructions operate in fewer clock cycles tion needed to convert an 80C196KB design to a
than an NMOS device, the 80C196KC can be as much 80C196KC.
as 2.5-3X the performance of an NMOS device.

The MCS-96 family is a register-to-register architec- . 1.0 CPU OPERATION

ture, so no accumulator is needed, and most operations
can be quickly performed from or to any of the 256 The major components of the CPU on the 80C196KC
registers. Using the Vertical Windowing scheme, the are the Register File and the Register/Arithmetic Log-
additional 256 bytes of RAM can also be addressed as ic Unit (RALU). Communication with the outside
registers. In addition, the register operations control world is done through either the Special Function Reg-
the many peripherals which are available on the chips. isters (SFRs) or the Memory Controller. The RALU
These peripherals include a serial port; A/D converter, does not use an accumulator. Instead, it operates di-
three PWM outputs, up to48 I/O lines and a High- rectly on the 256-byte register space made; up of the
Speed I/O subsystem which has two 16-bit timer/coun- Register File and the SFRs. Efficient I/O operations
ters, an 8-level input capture FIFO and an 8-entry pro- are possible by directly controlling the I/O through the
grammable output generator. SFRs. The main benefits of this structure are the ability
to quickly change context, absence of accumulator bot-
Typical applications for MCS-96 products are closed- tleneck, and fast throughput and I/O times.
loop control and mid-range digital signal processing.
MCS-96 products are being used in modems, motor
controls, printers, engine controls, photocopiers, anti-
lock brakes, AC motor control, disk drives, and medi-
cal instrumentation.

V r ANGND

CONTROL
SIGNALS

PORT 3

} ~~~:
BUS

PORT 4
1+--+-
~~]::=+:::
L PWM1
PWM2

HSO
270704-1

Figure 1·1. 80C196KC Block Diagram

5-4
inter 80C196KC USER'S GUIDE

The CPU on the 80CI96KC is 16 bits wide and con- REGISTER! ALU (RALU)
nects to the interrupt controller and the memory con-
troller by a 16-bit bus. In addition, there is an 8-bit bus Most calculations performed by the 80Cl96KC take
which transfers instruction bytes from the memory con- place in the RALU. The RALU, shown in Figure 1-2,
troller to the CPU. An extension of the 16-bit bus con- contains a l7-bit ALU, the Program Status Word
nects the CPU to the peripheral devices. (PSW), the Program Counter (PC), a loop counter, and
three. temporary registers. All of the registers are 16-
bits or 17 -bits (16 + sign extension) wide. Some of the
1.1 Memory Controller registers have the ability to perform simple operations
to off-load the ALU.
The RALU accesses the memory, except for the loca-
tions in the register file and SFR space, through the A separate incrementor is used for the Program Coun-
memory controller. Within the memory controller is a ter (PC) as it accesses operands. However, PC changes
bus controller, a four byte prefetch queue and a Slave due to jumps, calls, returns and interrupts must be han-
Program Counter (Slave PC). Both the internal ROM/ dled through the ALU. Two of the temporary registers
EPROM bus and the external memory bus are driven have their own shift logic. These registers are used for
by the bus controller. Memory access requests to the the operations which require logical shifts, including
bus controller can come from either the RALU or the Normalize, Multiply, and Divide. The "Lower Word"
queue, with queue accesses having priority. Requests and "Upper Word" are used together for the 32-bit
from the queue are always for data at the address in tl;ie instructions and as temporary registers for many in-
slave PC. structions. Repetitive shifts are counted by the 6-bit
"Loop Counter".
By having program fetches from memory referenced to
the slave PC, the processor saves time as addresses sel- A third temporary register stores the second operand of
dom have to be sent to the memory controller. If the two operand instructions. This includes the multiplier
address sequence changes because of a jump, interrupt, during multiplications and the divisor during divisions.
call, or return, the slave PC is loaded with a new value, To perform subtractions, the output of this register can
the queue is flushed, and processing continues. be complemented before being placed into the "B" in-
put of the ALU.
Execution speed is increased by using a queue since it
usually keeps the next instruction byte available. The Several constants, such as 0, I and 2 are stored in the
instruction execution times shown in Section 3 show RALU to speed up certain calculations. (e.g. making a
the normal execution times with no wait states added 2's complement number or performing an increment or
and the 16-bit bus selected, Reloading the slave PC and decrement instruction.) In addition, single bit masks for
fetching the first byte of the new instruction stream bit test instructions are generated lin the constant regis-
takes 4 state times. This is reflected in the jump taken/ ter based on the 3-bit Bit Select register.
not-taken times shown in the table.

When debugging code using a logic analyzer, one must 1.3 Internal Timing
be aware of the queue. It is not possible to determine
when an instruction will begin executing by simply The 80Cl96KC requires an input clock on XTALl to
watching when it is fetched, since the queue is filled in function. Since XTALl and XTAL2 are the input and
advance of instruction execution. output of an inverter a crystal can be used to generate
the clock. Details of the circuit and suggestions for its
use can be found in Section 14. ,
1.2 CPU Control
Internal operation of the 80C196KC is based on the
A microcode engine controls the CPU, allowing it to crystal or external oscillator frequency divided by 2.
perform operations with any byte, ,word or double word Every 2 oscillator periods is referred to as one "state
in the 256 byte register space. By using the VWindow- time", the basic time measurement for all 80C196KC
ing scheme discussed in Section 3-3, the additional 256 operations. With a 16 MHz oscillator, a state time is
bytes of RAM can also be used as registers. Instruc- 125 nanoseconds. Since the 80CI96KC will be run at
tions to the CPU are taken from the queue and stored many frequencies, the times given throughout this
temporarily in the instruction register. The microcode chapter will be in state times 01: "states", unless other-
engine decodes the instructions and generates the cor- wise specified. A clock out (CLKOUT) signal, shown
rect sequence of events to have the RALU perform the in Figure 1-3, is provided as an indication of the inter-
desired function. Figure 1-2 shows the memory control- nal machine state. Details on timing relationships can
ler, RALU, instruction register and the control unit. be found in Section 14.

5-5
 (
Master
Pro9ram Counter
w/Incrementer Memory
::!! Bus
co
c
.... Upper word
ID
.... register
w/shifter
~ RAM
lJ
»
I""
Lower word
register
011
C
C w/shlfter (')
I»
j "*
CO
Q. CD
,Processor
s:
ID
3
Register
FlIe~ Status
Word
"c::
(')

m '<0... en
01
and
m
0 Special II
0
......
j Function
Registers
enC)
2- --r-- _ CPU s:c
...
is Control
and Status m
til
0' Signals
(') RAM &: SFR
71:' Control
!2
!II
Registers
CQ ~

3iill
16
CPU BUSES
1

8
270704-2

,/
 80C196KC USER'S GUIDE

2.1 Register File

PH:ASE1~
, Locations OOH through IFFH contain the Register
File, Special Function Registers (SFRs), and 256 bytes
PHASE2~ of additional RAM. If an attempt to execute instruc-
tions from locations ODOH through IFFH is made, the
, instructions will be fetched from external memory. This
CLKOUT~ section of exterual memory is reserved for use by Intel
development tools. This memory region, as well as the
270704-3
status of the majority of the chip, is kept intact while
Figure 1-3. Internal Clock Waveforms the chip is in the Powerdown Mode. Details\ on the
Powerdown Mode are discussed in Section IS.

The interual RAM from location Ol8H (24 decimal) to

2.0 MEMORY SPACE OFFH is the Register File. It contains 232 bytes of
The addressable memory space on the 8OCl96KC con- RAM which can be accessed as bytes (8 bits), words
sists of 64K bytes, most of which is available to the user (16 bits), or double-words (32 bits). Since each of these
for program or data memory. Locations which have locations can be used by the RALU, there are essential-
special purposes are OOOOH through OIFFH and ly 232 "accumulators". Also, the extra 256 bytes of
IFFEH through 2080H. All other locations can be RAM from lOOH-IFFH can be accessed as registers
used for either program or data storage or for memory by the RALU with Vertical Register Windowing. For
mapped peripherals. A memory map is shown in Figure more on Register Windowing, see Section 3.3.
2-1. Those locations marked "Reserved" must be filled
with OFFHs for future compatibility, except for loca- Locations 18H and 19H contain the stack pointer:
tion 2019H which must contain 20H to avoid bus con- These are not SFRs and may be used as standard RAM
tention during the CCB fetch. if stack operations are not being performed. Since the
stack pointer is in this area, the RALU can easily oper-
ate on it. The stack pointer must be initialized by the
OFFFFH user program and can point anywhere in the 64K mem-
EXTERNAL MEMORY OR I/O
6000H ory space. Stack operations cause it to build down, so
INTERNAL ROM/EPROM OR the stack pointer should be initialized to 2 bytes above
EXTERNAL MEMORY the highest stack location. The stack must be word
20BOH aligned.
RESERVED
205EH
PTSVECTORS

2040H
2.2 Spec;ial Function Registers
UPPER INTERRUPT VECTORS
Locations OOH through 17H are the I/O control regis-
2030H
ters or SFRs. All of the peripheral .devices on the
ROM/EPROM SECURITY KEY
2020H
80CI96KC (except Ports 3 and 4) are controlled
RESERVED
through the SFRs. As shown in Figure 2-2, three hori-
20l9H zontal windows (HWindows) are provided on the
CHIP CONFIGURATION BYTE 80CI96KC to increase SFR space while remaining up-
201BH ward compatible. with earlier MCS-96 products.
RESERVED' Switching between Horizontal Windows is discussed in
20l4H Section 3.3.
LOWER INTERRUPT VECTORS
2000H
HWindow 0 is a superset of the SFR space on the
PORT 3 AND PORT 4
8096BH and identical to the 80C196KB. As depicted in
lFFEH
Figure 2-2, it has 24 registers, some of which have dif-
EXTERNAL MEMORY
200H
ferent functions when read than when written.
, ADDITIONAL RAM
100H HWindow I contains the additional SFRs needed to
REGISTER FILE AND support the added functionality of the 80C196KC.
EXTERNAL PROGRAM MEMORY These SFRs support the Peripheral Transaction Server
o (PTS), the two new PWMs, Timer2, and the new func-
tions of the A/D converter. These registers are not
Figure 2-1. 80C196KC Memory Map needed to remain compatible with the 80C196KB. All
SFRs are read/writable in this window.

5-7
inter 80C 196KC, USER'S GUIDE

In register HWindow 15, the operation of the SFRs is labeled should be treated as reserved registers and bits.
changed, so that those which were read-only in HWin- Note that the default state of internal registers is 0,
dow, 0 space are write-only and vice versa. The only while that for external memory is 1. This is because
major exception is Timer2 is read/write in HWindow 0, SFR functions are typically disa,bled with a zero, while
and T2 Capture is read/write in HWindow 15. Timer2 external memory is typically erased to allis.
was read-only on the 8096BH.
Caution must be taken when using the SFRs as sources
Figure 2-3 contains brief descriptions of the SFR regis- of operations or as base or index registers for indirect or
ters. Detailed descriptions are contained in the seCtion indexed operations. It is possible to get undesired re-
which discusses the peripheral controlled by the regis- sults, since external events can change SFRs and some
ter. Figure 2-4 contains a description of the alternate SFRs clear when read. The potential for an SFR to
function in HWindow 15. change value must be taken into account when operat-
ing on these registers. This is particularly important
Within the SFR space are several registers and bit loca- when high level languages are used as they may not
tions labeled "RESERVED". A reserved bit location make allowances for SFR-type registers. SFRs can be
must always be written with 0 to maintain compatibil- operated on as bytes or words unless otherwise speci-
ity with future parts. Registers and bits which are not fied.

19H SP'(HI) 19H SP(HI) 19H SP(HI) 19H SP(HI)

18H SP(LO) 18H SP(LO) 18H SP(lO) 18H SP(LO)
17H IOS2 17H PWMO CONTROL 17H PWM1_CONTROL 17H
16H IOS1 16H IOC1 16H PWtvJ2_CONTROL 16H
15H 10SO 15H lOCO 15H RESERVED 15H
14H WSR 14H WSR 14H WSR 14H WSR
13H INT_MASK1 13H INT_MASK1 13H INT_MASK1 13H INT_MASK1
12H INT_PEND1 12H INT_PEND1 12H INT_PEND1 12H INT_PENDl
11H SP_STAT 11H SP_CON 11H RESERVED 11H
10H PORT2 10H PORT2 10H RESERVED· 10H RESERVED
OFH PORT1 OFH PORT1 OFH RESERVED OFH RESERVED
OEH PORTO OEH BAUD RATE OEH RESERVED oEi-! RESERVED
ODH TIMER2(HI) ODH TIMER2 (HI) ODH RESERVED ODH T2CAPTURE (HI)
OCH TlMER2 (LO) OCH TIMER2(LO) OCH IOC3' OCH T2CAPTURE (LO)
OSH TIMER1 (HI) OSH IOC2 OBH RESERVED OSH
OAH TIMER1 (LO) OAH WATCHDOG OAH RESERVED OAH
09H INT_PEND 09H INT_PEND 09H INT_PEND 09H INT_PEND
08H INT_MASK 08H INT_MASK 08H INT_MASK 08H INT_MASK
07H SSUF(RX) 07H SBUF(TX) 07H PTSSRV(HI) 07H
06H HSI_STATUS 06H HSO_COMMAND P6H PTSSRV (LO) 06H
05H HSI_TIME (HI) 05H HSO_TIME, (HI) 05H PTSSEL(HI) 05H
04H HSI_TIME (LO) 04H HSO_TIME (LO) 04H PTSSEL(LO) 04H
03H AD_RESULT (HI) 03H HSI_MODE 03H AD_TIME 03H
02H AD_RESULT (LO) 02H AD_COMMAND 02H RESERVED 02H
01H ZERO_REG (HI) 01H ZERO_REG (HI) 01H ZERO_REG (HI) 01H ZERO_REG (HI)
OOH ZERO~REG (LO) OOH ZERO_REG (LO) OOH ZERO_REG (LO) OOH ZERO_REG (LO)
HWINDOWO HWINDOWO HWINDOW1
when Read when Written Read/Write HWINDOW15

NOTE:
'This was previously called T2CONTROL or T2CNTC.

Figure 2-2. 'Multiple Register Windows

5-8
 80C196KC USER'S GUIDE

Register Description
RO Zero Register· Always reads as a zero, useful ,for a base when indexing and as a
constant for calculations and compares.
AD_RESULT AID Result Hillow • low and high order results of the A/D converter
AD_COMMAND A/D Command Register· Controls the A/D
HSI_MODE HSI Mode Register· Sets the mode of the High Speed Input unit.
HSI_TIME HSI Time Hillo • Contains the time at which the High Speed Input unit was triggered.
HSO_TIME HSO Time Hillo· Sets the time or count for the High Speed Output to execute the
command in the Command Register.
HSO_COMMAND HSO Command Register· Determines what will happen at the time loaded into the
HSO Time registers.
HSI_STATUS HSI Status Registers· Indicates which HSI pins were detected at the time in the HSI
Time registers and the 'current state of the pins.
SBUF(TX) Transmit buffer for the serial port, holds contents to be outputted.
SBUF(RX) Receive buffer for the serial port, holds the byte just received by the serial port.
INT_MASK Interrupt Mask Register· Enables or disables the individual interrupts.
INT_PEND Interrupt Pending Register· Indicates that an interrupt signal has occurred on one of
the sources and has not been serviced. (also INT_PENDING)
WATCHDOG Watchdog Timer Register· W'ritten periodically to hold off automatic reset every 64K
state times.
TIMER1 Timer 1 Hilla· Timer1 high and low bytes.
TIMER2 Timer 2 Hilla· Timer2 high and low bytes.
10PORTO
BAUD_RATE
IOPORT1
Port 0 Register· levels on pins of Port O.
Register which determines the baud rate, this register is loaded sequentially.
Port 1 Register· Used to read or write to Port 1,
II
IOPORT2 Port 2 Register. Used to read or write to Port 2.
SP_STAT Serlal Port Status· Indicates the status of the serial port.
SP_CON Serial Port Control· Used to set the mode of the serial port.
10SO I/O Status Register 0 . Contains information on the HSO status.
IOS1 I/O Status Register 1 • Contains information on the status of the timers and of the
HSI.
lOCO I/O Control Register O· Controls alternate functions of HSI pins, Timer 2 reset
sources and Timer 2 clock sources.
IOC1 I/O Control Register 1 • Controls alternate functions of Port 2 pins, timer interrupts
and HSI interrupts.
PWM_CONTROl Pulse Width Modulation Control Register· Sets the duration of the PWM pulse.
Figure 2·3. Special Function Register Description

5·9
inter 80C196KC USER'S GUIDE

Register Description
INT_PEND1 .Interrupt Pending register for the 8 new interrupt vectors (also INT_PENDING1)
INT_MASK1 Interrupt Mask register for the 8 new interrupt vectors
IOC2 1/0 Control Register 2
IOS2 1/0 Status Register 2 - Contains information on HSO events
WSR Window Select Register - Selects register window
AD_TIME Determin~s AID Conversion Time
IOC3 New 80C196KC features (T2 internal clocking, PWMs) (PreviOusly T2CONTROL or
T2CNTC)
PTSSEL Individually enables PTS channels
PTSSRV End-of-PTS Interrupt Pending Flags
Figure 2-3. Special Function Register Description (Continued)

AD_COMMAND (02H) - Read the last written command

AD_RESULT (02H, 03H) - Write a value into the result register
HSI_MODE (03H) - Read the value in HSI_MODE
HSI_TIME (04H, 05H) - Write to FIFO Holding register
HSO_TIME (04H, 05H) - Read the last value placed in the holding register
HSI_STATUS (06H) - Write to status bits but not to HSI inputs bits. (Inputs bits are I, 3, 5, 7)
HSO_COMMAND (06H) - Read the last value placed in the holding register
SBUF(RX) (07H) - Write a value into the receive buffer
SBUF(TX) (07H) - Read the last value written to the transmit buffer
WATCHDOG (OAH) - Read the value in the upper byte of the WDT
TIMER! (OAH, OBH) - Write a value to Timer!
TIMER2 (OCH, ODH) - Read/Write the Timer2 capture register.
(Timer2 read/write is done with WSR = 0)
IOC2 (OBH) - Last written value is read~ble, except bit 7 (Note I)
BAUD_RATE (OEH) - No function, cannot be read
PORTO (OEH) - No function, no output drivers on the pins
SP_STAT (llH) - Set the status bits, TI and RI can be set, but it will not cause an interrupt
SP_CON(IIH) - Read the, current control byte
IOSO(!5H) . - Writing to this register controls the HSO pins. Bits 6 and 7 are inactive for
writes.
lOCO (I5H) - Last written value is niadable, except bit I (Note 1)
lOS! (16H) - Writing to this register will set the status bits, but not cause interrupts. Bits
6 and 7 are not functional.
lOCI (16H) - Last written value is readable
IOS2 (I7H) - Writing to this register will set the status bits, but not cause interrupts.
PWM_CONTROL (17H) - Read the duty cycle value written to PWM_CONTROL
NOTE:
1. IOC2.7 (CAM CLEAR) and IOCO.1 (T2RST) are not latched and will read as a 1 (precharged bus).

Being able to write to the read-only registers and vice-versa provides a lot of flexibility. One of the most useful
advantages is the ability to set the timers and HSO lines for initial conditions other than zero.

Figure 2-4. Alternate SFR Function in HWindow 15

5-10
inter 80C196KC USER'S GUIDE

2.3 Internal ROM and EPROM MCS®-96 UTILITIES USER'S GUIDE

Order Number 122049 (Intel Systems)
For a ROM and EPRQM part, the internal memory Order Number 122356 (DOS Systems)
~
locations 20S0H through 5FFFH are user specified, as
are the interrupt vectors, and PTS (Peripheral Transac- PL/M-96 USER'S GUIDE
tion Server) vectors, Chip Configuration Register and Order Number 122134 (Intel Systems)
Security Key in locations 2000H through 207FH. 'Order Number 122361 (DOS Systems)

Instruction and data fetches from the internal ROM or C-96 USER'S GUIDE
EPROM occur only if EA is tied high, and the address Order Number 167632 (DOS Systems)
is' between 2000H and 5FFFH. At all other times data
is accessed from either the internal RAM space or ex- Throughout this chapter short sections of code are used
ternal memory and instructions are fetched from exter- to illustrate the operation of the device. For these sec-
nal memory. The EA pin is latched on RESET rising. tions it is assumed that the following set of temporary
Information on programming EPROMs can be found registers has been declared:
in Section 17 of this manual. AX, BX, CX, and DX are 16-bit registers.
AL is the low byte of AX, AH is the high byte.
A security feature can lock the chip against reading
and/or writing the internal memory. In order to main- BL is the low byte of BX
tain security, code can not be executed out of the last CL is the low byte of CX
four locations of internal ROM/EPROM if the lock is
DL is the low byte of DX
enabled. Details on this feature are in Section 17.
These are the same as the mimes for the general data
registers used in the 8086. In the 80CI96KC these are
2.4 System Bus not dedicated registers but merely the symbolic names
There are several modes cif system bus operation on the assigned by the programmer to an eight byte region
SOC 196KC. The standard bus mode uses a l6-bit multi- within the on-board register file.
plexed address/data bus. Other bus modes include an
S:bit mode and a mode in which the bus size can dy-
namically be switched between 8-bits and l6-bits. '3.1 Operand Types
The MCS-96 architecture supports a variety of data
Hold/Hold Acknowledge (HOLD/HLDA) and Ready
types ,likely to be useful in a control application. To
signals are available to create a variety of memory sys-
avoid confusion, the name of an operand type is capital-
tems. The READY line extends the width of the RD
ized. A "BYTE" is an unsigned eight bit variable; a
(read) and WR (write) pulses to allow a~ess of slow
"byte" is an eight bit unit of data of any type.
memories. Multiple processor systems. with shared
memory can be designed using HOLD/HLDA. Details
on the System Bus are in Sections 15 and 16. BYTES

BYTES are unsigned 8-bit variables which can take on

3.0 SOFTWARE OVERVIEW the values between 0 and 255. Arithmetic arid relational
operators can be applied to BYTE operands but the
This section provides information on writing programs result must be interpreted in modulo 256 arithmetic.
to execute in the SOCI96KC. Additional information Logical operations on BYTES are applied bitwise. Bits
can be found in the following documents: within BYTES are labeled from 0 to 7, with 0 being the
least significant bit.
MCS®-96 MACRO ASSEMBLER USER'S GUIDE
Order Number 122048 (Intel Systems)
Order Number 122351 (DOS Systems)

5-11
 80C~96KC ,USER'S,GUIDE

WORDS, 4,294,967,295. The MCS-96 architecture "provides di-

rect support for' this operand type oiuy for shifts, as the
WORDS are unsigned 16-bit variables which can take dividend in a 32 by 16 divide, the product ofa 16 by 16
on the values between 0 and 65535. Arithmetic and multiply, and for double-word compares. ,For these op,
relational operators can be,applie<i' to WORD operands erations a DOUBLE-WORD variable must ,reside in
but the result mllst be interpreted modulo 65536: Logi- the on-board register file of the 8OCl96KC and be
cal operations on WORDS are applied bitwise. Bits aligned at an address which is evenly divisible by 4. A
within words are labeled from 0 to, 15 with 0 being the DOUBLE-WORD operand is addressed by the address
least significant bit. WORDS must be aligned at even of its least significant byte. DOUBLE-WORD opera-
byte boundaries in the MCS-96 address space. The least tions which are not directly ,supported ()8n be easily
significant byte' of the WORD is in the even byte ad- implemented with two WORD operations. The CMPL
dress and the most significant byte,is in the next higher instruction views the zero register as a 32·bit value of
(odd) ,address. The address of a wor,d is the address of zero. This allows it to be used for comparison to zero.
its least significant byte. Word operations to odd ad- For consistency with Intel provided software the user
dresses are not guaranteed to ,operate in a consistent should adopt the conventions for a,ddressing DOU-
manner. BLE-WORD operands which are discussed in Section
3.6.
SHORT-INTEGERS
LONG-INTEGERS
SHORT-INTEGERS are 8-bit signed variables which
can take on the values between -128 and + 127. LONG-INTEGERS are 32-bit signed variables which
Arithmetic operations which generate results outside of can take on the values between -2,147,483,648 and
the range ofa SHORT-INTEGER will set the overflow +2,147,483,647.
indicators in the program status word. The actual nu-
meric result returned will be the same as the equivalent LONG-INTEGERS can also be normalized. For these
operation on BYTE variab1Cl1. operations a LONG-INTEGER variable must reside in
the onboard register file' of the 80CI96KC and be
aligned at an address which is evenly divisible by 4. A
INTEGERS LONG-INTEGER is addressed by the address of its
least significant byte. '
INTEGERS are 16-bit signed, variables which can take
on the values between - 32,768 and + 32,767. Arith-
metic operations which generate results outside of the LONG-INTEGER operations which are not directly
range of an INTEGER will set the overflow indicators supported can be easily implemented with two INTE-
GER operations. '
in the program status word. The actual rtumeric result
returned will be the same as the equivalent operation on
WORD variables. INTEGERS conform to the same
alignment and addressing rules as do WORDS. 3.2 Operand Addressing
Operands are accessed within the address space of the
BITS 80C196KC with one of six basic addressing modes.
Some of the details of how these addressing modes
BITS are single-bit operands which can take on the work are hidden by the assembly language,' If the pro-
Boolean values of true and false. In addition to the nor- grammer is to take full advantage of the architecture, it
mal'support for bits as' components of BYTE and is important that these details be Understood. This Sec-
WORD operarids, the 8OCl96KC provides for the di- tion will describe the addressing modes as they are han-
rect testing of any bit iri the register file. The MCS-96 dled by the hardware. At the end of this section the
architecture requires that bits be addressed as compo- ,addressing modes will be ,described as they are seen
nents of BYTES or WORDS, it does not support the through the assembly language. The six basic address
direct addressing of bits that can occur in the MCS-51 modes which will be described' are termed register-di-
architecture. , rect, indirect, indirect with auto-increment, immediate,
short-indexed, and long-indexed. Several other useful
addressing operations can be achieved by combining
DOUBLE-WORDS these basic addressing modes with specific registers
DOUBLE-WORDS are unsigned 32-bit variables such as the ZERO register or the stack pointer.
which can take on the values between 0 and

5-12
 80C196KC USER'S GUIDE

REGISTER·DIRECT REFERENCES
The register-direct mode is used to directly access a tion and the register address must conform to the oper-
register from' the 256 byte on-board register file. The and type's alignment rules. Depending on the instruc-
register is selected by an 8-bit field within the instruc- tion, up to three registers can take part in the calcula-
tion.

Examples
ADD AX,BX,CX AX:=BX+CX
MUL AX,BX AX:=AX*BX
INCB CL CL:=CL+l

INDIRECT REFERENCES
Th~ indirect mode is used to access an operand by plac- dress space of the 8OC196KC, including the register
ing its address in a WORD variable in the register file. file. The register which contains the indirect address is
The ,calculated address must conform to the alignment selected by an eight bit field within the instruction. An
rules for the operand type. Note that the indirect ad- instruction can contain only one indirect reference and
dress can refer to an operand anywhere within the ad- the remaining operands of the instruction (if any) must
be register-direct references.

Examples ,
LD ,AX, [AX] AX:=MEM_WORD(AX)
ADDB AL,BL, [CX] ,AL:=BL+MEM_BYTE(CX)
POP [AX]. MEM_WORD(AX)
:=MEM_WORD(SP)
SP:=SP+2

It:lDIRECT WITH AUTO·INCREMENT REFERENCES

This addressing mode is the same as the indirect mode SHORT-INTEGERS the indirect address variable will
except that the WORD variable which contains ~he in- be incremented by one, if the instruction operates' on
direct address is incremented after it is used to address WORDS or INTEGERS the indirect address variable
the operand. If the instruction operates on BYTES or will be incremented by two.

Examples
LD AX, [BX]+ AX:=MEM_WORD(BX) ; BX:=BX+2
ADDB AL,BL,[CX]+ AL:=BL+MEM_BYTE(CXI ; CX:=CX+l
PUSH [AX] + SP:=SP-2;
MEM_WORD(SP) :=MEM_WORD(AX)
AX::AX+2

IMMEDIATE REFERENCES
This addressing mode allows an operand to be taken GER operands the field is 16 bits wide. An instruction
directly from a field in the instruction. For operations can contain only one immediate reference and the re-
on-BYTE or SHORT-INTEGER operands this field is maining operand(s) must be register-direct references.
eight bits wide, for operations on WORD or INTE-

,Examples
ADD AX,#340 AX::AX+340
PUSH #1234H SP:=SP-2; MEM_WORD(SP) :=1234H
DIVB AX,#lO AL:=AX/10; AH::AX Mob 10

5-13
 80C196KC USER'S GUID.E

SHORT-INDEXED REFERENCES

In this addressing mode an eight bit field in the instruc- Since the eight bit field is sign-extended, the effective
tion selects a WORD variable in the register file which address can be up to 128 bytes before the addres~ in the
contains an address. A second eight bit field in the in- WORD variable and up to 127 bytes after it. An in-
struction stream is sign-extended and summed with the struction can contain only one short-in!1exed reference
WORD variable to form the address of the operand and the remaining operand(s) must be register-direct
which will take part in the calculation. references.

ExamplE1s
LD AX,12[BX] AX:=MEM_WORD(BX+12)
MULB AX,BL,3[CX] AX:=BL*MEM_BYTE(CX+3)

LONG-INDEXED REFERENCES

This addressing mode is like the short-indexed mode struction can contain only one long-indexed reference
except that a J6-bit field is taken from the instruction and the remaining operand(s) must be register-direct
and added to the WORD variable to form the address references;
of the operand. No sign extension is necessary. An in-

Examples
AND AX,BX,TABLE[CX] AX:=BX AND MEM_WORD(TABLE+CX)
ST AX, TABLE [BX] MEM_WORD(TABLE+BX) :=AX
ADDB AL,BL,LOOKUP[CX] AL:=BL+MEM_BYTE(LOOKUP+CX)

ZERO REGISTER ADDRESSING

The first two bytes in the register file are fixed at zero variable in a long-indexed reference. This combination
by the 80C196KC hardware. In addition to providing a of register selection and address mode allows any loca-
fixed source of the constant zero for calculations and tioll in memory to be addressed directly.
comparisons, this register can be used as the WORD

Examples
ADD AX,1234[0] AX:=AX+MEM_WORD(1234)
POP 5678[0] MEM_WORD(5678) :=MEM_WORD(SP)
SP:=SP+2

STACK POINTER REGISTER ADDRESSING

The system stack pointer in the 80Cl96KC is accessed accessed by using the stack pointer as the WORD vari-
as register 18H of the internal register file. In addition able in an indirect reference. In a similar fashion, the
to providing for convenient manipulation of the stack stack pointer can be used in the short-indexed mode to
pointer, this also facilitates the accessing of operands in access data within the stack.
the stack. The top of the stack, for example, can be

Examples
PUSH ESP] DUPLICATE TOP_OF_STACK
LD AX,2[SP] AX:=NEXT_TO_TOP

5-14
inter 80C196KC OSER'S GUIDE

ASSEMBLY LANGUAGE ADDRESSING MODES HORIZONTAL WINDOWS

The MCS-96 assembly language simplifies the choice of Horizontal Windows (HWindows) contain the extra
addressing modes to be used ~n several respects: S~s for the 80C196KC. Three HWindows are sup-
ported on the 8OC196KC, 0, 1, and 15. Figures 2-3 and
Direct Addressing. The assembly language will choose 2-4 in Section 2 show the HWindows and their con-
between register-direct addressing' and long-indexed tents. HWindow 15 is compatible with HWindow 15 on
,with the ZERO register depending on, where the oper- the 8OC196KB and HWindow lcontains extra SFRs to
and is in memory. The user can simply refer to an oper- support the additional functionality of the 8OC196KC.
and by its symbolic name; if the operand is in the regis- Switching Horizontal Windows maps the 24 bytes of
ter file, a register-direct reference will be used, if the the HWindow into the lowest 24 bytes of the Register
operand is elsewhere in 'memory, a long-indexed refer- File. There is no other way to access a Horizontal Win-
ence will be generatlld. dow. To switch between HWindows; simply write the
number of the HWindow into the four LSBs of the
Indexed Addressing. The assembly language will WSR. Bits 4-,6 of the WSR must be written as Os when
choose between short and long indexing depending on accessing Horizontal Windows.
the value of the index expression. If the value can be
expressed in eight bits then short indexing will be used,
if it cannot be expressed in eight bits then long indexing VERTICAL WINDOWS
r
will be used. Vertical Windows (VWindows) can be used to map sec-
tions of the 512 bytes of RAM from OOH-IFFH into
These features of the assembly language simplify ,the the upper section of the Register File. An important
programming task and should be used wherever possi- difference between Horizontal and Vertical Windows is
ble. VWindows reside directly in the 8OC196KC addressing
space. Therefore, lOOH-IFFH can be addressed direct-
ly with 16-bit addressing using an indexed or indirect
3.3 Register Windowing addressing mode, or as registers using Vertical Win-
One of the biggest advantages of the MSC-96 architec- dows.
ture is its ability to perform operations dir!lctly on the
Register File without using accumulators. The Register Vertical Windowing allows, 32-, 64-, or 128-byte "win-
Direct Addressing Mode makes for efficient code that dows" from 00-IFFH to be mapped onto the top 32-;
is easy to write. The RALU accesses the Register file 64-, or J28-byte block of the Register File. figure 3-2
using eight bit addressing, making 256 bytes available shows all the available VWindows on the 80C196KC.
to the RALU at one time. Register Windowing was Switching betweqn VWindows is done by setting bit 6,
implemented so the RALU could have access to more 5, or 4 in the WSR and writing the number of the
than 256 bytes of Registers by simply switching win- VWindow into the 4 LSBs. Figure 3-3 shows how to
dows. There are two types of Windows: Horizontal use the WSR to switch between VWindows.
Windows and Vertical Windows. Switching between
Windows is controlled by the WSR (Window Select For an example, let's map the 32-byte block from
Register) shown in Figure 3-1. The 7 LSBs ofthe WSR 120H-13FH into the upper part of the Register File
control the Windowing and the MSB (HLDEN) en- from bEOH-OFFH. Figure 3-4 shows the VWindow
ables the HOLD/HLDA function. being switched as well as the correct value to load into
the WSR. Now any access to locations OEOH-OFFH
7 0
using a register direct reference will actually access the
memory at 120H-13FH. However the two locations
wSRIHLDENI W6 W5 W4 W3 W2 Wl WO' I can still be accessed directly with 16-bit addressing.
14H The section of code in Figure 3-4 should clarify this.
Figure 3-1. Window Sel~ct Register I

5-15
inter 80C196KC USER'S GUIDE

32 BYTE 64 BYTE 128 BYTE

WINDOWS WINDOWS WINDOWS

01 EO 1:1
07
01COH 01COH
03
01AOH
06
0180H 0180H 0180H
0160H
05
0140H 0140H
02
0120H
04
0100H 0100H 0100H
WINDOWS
OOEOH
03
OOCOH DOCOH
01
OOAOH
02
0080H 0080H 0080H
0060H
0040H 0040H
0020H
OOOOH OOOOH OOOOH

OOFFH OOFFH OOFFH

OOEOH
OOCOH
REGISTER 0080H
FILE

OOOOH OOOOH OOOOH

270704-75

Figure 3·2. Vertical Windows

Forms A 9 Bit Address

7 o
WSR!HLDEN! W6 ! WS ! W4 ! W3 ! W2 ! WI

WWW WWWW = 000 XXXX: Select Horizontal Window (3 Possible)

= 100 XXXX: Select 32-Byte Window (16 Possible)
= 010 OXXX: Select 64-Byte Window (8 Possible)
= 001 OOXX: Select 12S-Byte Window (4 Possible)

32-Byte Window Addresses: W3 W2 WI WO A4 A3 A2 Al AO

64-Byte Window Addresses: W2 WI WO A5 A4 A3 A2 Al AO
12S-Byte Window Addresses: WI WO A6 A5 A4 A3 A2 Al AO

Figure 3·3. Accessing a VWindow

5-16
 80C196KC USER'S GUIDE

1FFH
,----..,

13FH
.......,....,.,....,.,....,....

Maps 32 Byte Window 09H .

into Register File
LOB WSR, #49H

OOOH
270704-76

ldb WSR_lMAGE, WSR

ldb WSR, #49H ;switch windows
add 40H, OFOH ;adds the value at l30H to the
;value at 40H
add 40H, OFOH[O] ;adds the value at OFOH to the
;value at 40H
add 40H, l30H [0] ;adds the value at l30H to the
;value at 40H
ldb WSR, WSR_lMAGE ;switch back to previous window
Figure 3·4. VWindow Example

VWindowing provides for fast context switching of reg- CONDITION FLAGS

ister sets. For example, an Interrupt Service Routine
could have its own set of local registers in a VWindow, The PSW bits on the 80C196KC are set as follows:
and pass results to a main routine through global regis-
ters in the Register File.

3.4 Program Status Word Figure 3·5. PSW Register

The program status word (PSW) is a collection of Boo- Z: The Z (Zero) flag is set to indicate that the opera-
lean flags which retain information concerning the state tion generated a result equal to zero. For the add-
of the user's program. There are two bytes in the PSW; with-carry (AOOC) and subtract-with-borrow
the actual status word and the low byte of the interrupt (SUBC) operations the Z flag is cleared if the
mask. Figure 3-5 shows the status bits of the PSW. The result is non-zero but is never set. These two in-
PSW can be saved in the system stack with a single structions are normally used in conjunction with
operation (PUSHF) and restored in a like manner the ADO and SUB instructions to perform mul-
(POPF). Only the interrupt section of the PSW can be tiple precision arithmetic. The operation of the Z
accessed directly. There is no SFR for the PSW status flag for these instructions leaves it indicating the
bits. proPer result for the entire multiple precision cal-
culation.

5-17
 80C196KC USER'S GUIDE

N: The Negative flag is set to indicate that the oper- flag can be used along with the C flag to control
ation generated a negative result. Note that the N rounding after a right shift. Consider multiplying
flag will be in the algebraically correct state even two eight bit quantities and then scaling the re-
if an overflow occurs. For shift operations, in- sult down to 12 bits:
cluding the normalize operation and all three
forms (SHL, SHR, SHRA) of byte, word and MULUB AX,CL,DL ;AX:=CL*DL
double word shifts, the N flag will be set to the SHR AX,#4 ;Shift right 4
same value as the most significant bit of the re- places
sult. This will be true even if the shift count is O.
V: The oVerflow flag is set to indicate that the oper- If the C flag is set after the shift, it indicates that the
ation generated a result which is outside the bits shifted off the end of the operand were greater-than
range for the destination' data type. For the SHL, or equal-to one half the least significant bit (LSB) of the
SHLB and SHLL instructions, the V flag will be result. If the C flag is c1el\r after the shift, it indicates
set if the most significant bit of the operand that the bits shifted off the end of tjIe operand were less
changes at any time during the shift. For divide than half the LSB of the result. Without the ST flag,
operations, the following conditions are used to the rounding decision must be made on the basis of the
determine if the V flag is set: C flag alone. (Normally the result would be rounded up
if the C flag is set.) The ST flag allows a finer resolution
For the in the rounding decision:
operation: V is set if Quotient is:
UNSIGNED
C ST Value of the Bits Shifted Off
BYTE DIVIDE> 255 (OFFH)
0 0 Value = 0
UNSIGNED
WORD DIVIDE> 65535 (OFFFFH) 0 1 o < Value < % LSB
1 0 Value = % LSB
SIGNED < -127(SlH)
BYTE or 1 1 Value> Y2 LSB
DIVIDE > 127 (7FH) Figure 3-6. Rounding Alternatives

SIGNED < -32767(SOOlH) 'Imprecise rounding can be a major source of error in a

WORD or' numerical cl'llculation; use of the ST flag improves the
DIVIDE > 32767 (7FFFH) options available to the programmer.
VT: The oVerflow Trap flag is set when the V flag is
set, but it is only cleared by the CLRVT, JVT
INTERRUPT FLAGS
and JNVT instructions. The operation of the VT
flag allows for the testing for a possible overflow The lower eight bits of the PSW individually mask the
condition at the end of a sequence of related lowest 8 sources of interrupt to the 80C196KC. These
arithmetic operations. This is normally more effi- mask bits can be accessed as an eight bit byte (INT_
cient than testing the V flag after each instruc" MASK-address 8) in the register file. A separate reg-
tion. ister (INT_MASKI-address I3H) contains the con-
C: ' The Carry flag is set to indicate the state of the trolbits for the higher 8 interrupts. A logical '1' in
arithmetic carry from the most significant bit of these bit positions enables the servicing of the corre-
the ALU for an arithmetic operation, or the state sponding interrupt. Bit 9 in the PSW is the global inter-
of the last bit shifted out of an operand for a rupt disable. If this bit is cleared then interrupts will be
shift. Arithmetic Borrow after a subtract opera- locked out. Further information on the interrupt struc-
tion ·is the complement of the C flag (i.e. if the ture of the 80C196KC can be found in Section 5.
operation generated a borrow then C~O.)
PSE: The Peripheral Transaction Server Enable bit.
Globally enables the PTS when set. Manipulated 3.5 Instruction Set
by the EPTS and DPTS instructions.
The MCS-96 instruction set contains a full set of arith-
I: The global Interrupt disable bit disables all inter- metic and logical operations for the 8-bit data types
rupts except NMI, TRAP, and unimplemented BYTE and SHORT INTEGER and for the 16-bit data
opcode when cleared. types WORD and INTEGER. The DOUBLE-WORD
ST: The ST (STicky bit) flag is set to indicate that and LONG data types (32 bits) are supported for shifts,
during a right shift a I has been shifted first into products of 16 by 16 multiplies, dividends of 32-by-16
the C flag and then been shifted out. The ST flag divides, and for 32-bit compares. The remaining oper-
is undefined after a multiply operation. The ST

5-1S
inter 80C196KC USER'S GUIDE

ations on 32-bit variables can be implemented by com- unsigned operands were involved or a JGT Gump if
binations of 16-bit operations. As an example the se- greater-than) if signed operands were involved.
quence:
Tables 3-7 and 3-8 summarize the operation of each of
ADD AX,CX the instructions.
ADDC BX,DX
The execution times for the instruction set is given in
performs a 32-bit addition, and the sequence Figure 3-8. These times ar.e given for a 16-bit bus with
no waitstates. On-chip EPROM/ROM space is a 16-
SUB AX,CX bit, zero waits tate bus. When executing from an 8-bit
SUBC BX,DX external memory system or adding waitstates, the CPU
becomes bus limited and must sometimes wait for the
performs a 32-bit subtraction. Operations on REAL prefetch queue. The performance penalty for an 8-bit
(i.e. floating point) variables are not supported directly external bus is difficult to measure, but has shown to be
by the hardware but are supported by the floating point between 10 and 30 percent based on the instruction
library for the 80C196KC (FPAL-96) which imple- mix. The best way to measure code performance is to
ments a single precision subset of Draft 10 of the IEEE actually benchmark the code and time it using an emu-
Staildard for Floating Point Arithmetic. The perform- lator or with TIMER!.'
ance of this software is significantly improved by the
80C196KC NORML instruction which normalizes a The indirect and indexed instruction timings are given
32-bit variable and by the existence of the ST flag in the for two memory spaces; SFR/Internal RAM space (0-
PSW. IFFH), and a memory controller reference (200H-
OFFFFH). Any instruction that uses an operand that is
In addition to the operations on the various data types, referenced thru the memory controller (ex. Add
the 80C196KC supports conversions between these rl,5000H[0l) takes 2-3 states longer than if the oper-
types. LDBZE (load byte zero extended) converts a and was in the SFR/Internal RAM space. Any data
BYTE to a WORD and LDBSE (load byte sign extend- access to on-chip ROM/EPROM is considered to be a
ed) converts a SHORT-INTEGER into an INTEGER. memory controller reference.
WORDS can be converted to DOUBLE-WORDS by
simply clearing the upper WORD of the DOUBLE- Flag Settings. The modification to the flag setting is
WORD (CLR) and INTEGERS can be converted to shown for each instruction. A checkmark (,....) means
LONGS with the EXT (sign extend) instruction. that the flag is set or cleared as appropriate. A hyphen
means that the flag is not modified. A one or zero (1) or
The MCS-96 instructions for addition, subtraction, and (0) indicates that the flag will be in that state after the
comparison do not distinguish between unsigned words instruction. An up arrow (t) indicates that the in-
and signed integers. Conditional jumps are provided to struction may set the flag if it is appropriate but will
allow the user to treat the results of these operations as not clear the flag. A down arrow ( J.- ) indicates that the
either signed or unsigned quantities. As an example, the flag can be cleared but not set by the instruction. A
CMPB (compare byte) instruction is used to compare question mark (1) indicates that the flag will be left in
both signed and unsigned eight bit quantities. A JH an indeterminant state after the operation.
Gump if higher) could be used following the compare if

5-19
 80C196KC USER'S GUIDE

Table 3-7A.lnstruction Summary

,
Flags
Mnemonic Operands Operation (Note 1) Notes
Z N C V VT ST
ADD/ADDB 2 . D~D+A /;' /;' /;' /;'
t -
ADD/ADDB 3 D~B+A /;' /;' /;' /;'
t -
ADDC/ADDCB 2 D~D+A+C J.- /;' /;' /;'
t -
SUB/SUBB 2 D~D-A /;' /;' /;' /;' t -
SUB/SUBB 3 D~B-A /;' /;' /;' /;'
t -
SUBC/SUBCB 2 D~D-A+C-1 J.- /;' /;' /;'
t -
CMP/CMPB 2 D-A /;' /;' /;' /;'
t -
MUL/MULU 2 D,D + 2 ~ Dx A - - - - !
- - 2
MUL/MULU 3 D,D + 2 ~ B x A - - - - - - 2
MULB/MULUB 2 D,D + 1 ~ D x A - - - - - - 3
MULB/MULUB 3 D,D + 1 ~ B x A - - - - - - 3
DIVU 2 D ~ (D,D + 2) / A,D + 2 ~ remainder - - - /;' t - 2
DIVUB 2 D ~ (D,D + 1) / A,D + 1 ~ remainder - - - /;'
t - 3
DIV 2 D ~ (D,D + 2) / A,D + 2 ~ remainder - - - /;'
t -
DIVB 2 D ~ (D,D + 1) / A,D + 1 ~ remainder - - - /;'
t -
AND/ANDB 2 D~DANDA /;' /;' 0 0 - -
AND/ANDB 3 D~BANDA /;' /;' 0 0 - -

OR/ORB 2 D~ DORA /;' /;' 0 0 - -

XOR/XORB. 2 D ~ D (eexl. or) A /;' /;' 0 O. - -
LD/LDB 2 D~A - - - - - -
ST/STB 2 A~D - - - - - -

XCH/XCHB 2 D~A,A~D - - - - - -
LDBSE 2 D ~ A; D + 1 ~ SIGN(A) - - - - - - 3,4
LDBZE 2 D~A;D + 1 ~O - - - - - - 3,4'
PUSH 1 SP ~ SP - 2; (SP) ~ A - - - - - -
POP 1 A ~ (SP); SP + 2 - - - - - -
PUSHF 0 SP ~ SP - 2; (SP) ~ PSW; 0 0 0 0 0 0
PSW ~ OOOOH; I ~ 0
POPF 0 PSW ~ (SP); SP ~ SP + 2; I ~ /;' /;' /;' /;' /;' /;' /;'

SJMP 1 PC ~ PC + 11-bit offset - - - - - - 5

LJMP 1 PC ~ PC + 16-bit offset - - - - - - 5
BR[indireet] 1 PC~ (A) - - - - - -
TIJMP 3 PC ~ [A] +2' ([B] AND C) - - - - - -
SCALL 1 SP~SP - 2; - - - - ,- - 5
(SP) ~ PC; PC ~ PC + 11-bit offset
LCALL 1 SP ~ SP - 2; (SP) ~ PC; - - - - - - 5
PC ~ PC + 16-bit offset

5-20
 80C196KC USER'S GUIDE

Table 3-7B. Instruction Summary

Flags
Mnemonic Operands Operation (Note 1) Notes
Z N C V VT ST
RET 0 PC +- (SP); SP +- SP + 2 - - - - - -
J (conditional) 1 PC +- PC + 8·bit offset (if taken) - - - - - - 5
JC 1 Jump if C = 1 - - -L - - - 5
JNC 1 jump ifC = 0 - - - - - - 5
JE 1 jump if Z = 1 - - - - - - 5
JNE 1 Jump if Z = 0 - - - - - - , 5
JGE 1 Jump if N = 0 - - - - - - 5
JLT 1 Jump if N = 1 - - - - - - 5
JGT 1 Jump if N = 0 and Z = 0 - - - - - - 5
JLE 1 Jump if N = 1 or Z = 1 - - - - - - 5
JH 1 Jump if C = 1 and Z = 0 - - - - - - 5
JNH 1 Jump if C = 0 or Z = 1 - - - - - - 5
JV 1 Jump if V = 0 - - - - - - 5
JNV 1 , Jump if V = 1 - - - - - - 5
JVT 1 Jump if VT = 1; Clear VT - - - - 0 - 5
JNVT 1 Jump if VT = 0; Clear VT - - - - 0 - 5
JST 1 JumpifST = 1 ..:. - - - - - 5
JNST 1 Jump ifST = 0 - - - - - - 5
JBS 3 Jump if Specified Bit = 1 - - - - - - 5,6
JBC 3 Jump if Specified Bit = 0 - - - - - - 5,6
OJNZI 1 o +- 0 - 1; - - - - - - 5
OJNZW If 0 "* 0 then PC +- PC + 8·bit offset
OEC/OECB 1 0+-0-1 ", ", ", ",
t -
NEG/NEGB 1 0+-0-0 ", ", ", ", t -

INCIINCB 1 0+-0+1 ", ", II' ", t -

EXT 1 o +- 0; 0 +2 +- Sign (0) ", ", 0 0 - - 2
EXTB 1 o +- 0; 0 + 1 +- Sign (0) ", ", 0 0 - - 3
NOT/NOTB 1 o +- Logical Not (0) ", ", 0 0 - -
CLR/CLRB 1 0+-0 1 0 0 0 - -
SHL/SHLB/SHLL 2 C +- msb····· Isb +- 0 ", ", ", ", t - 7
SHRISHRB/SHRL 2 o~ msb·····lsb ~ C ", ", ", 0 - ", 7
SHRA/SHRAB/SHRAL 2 msb ~ msb····· Isb ~ C ", ", ", 0 - ", 7
SETC 0 C+-1 - - 1 - - -
CLRC 0 C+-O - - 0 - - -

5·21
inter 8OC196KC USER'S GUIDE

Table 3·7C. Instruction Summary

Flags
Mnemonic Operands Operation (Note 1) Notes
Z N C V VT ST
CLRVT 0 VT - 0 - - - - 0 -
RST 0 PC - 2080H 0 0 0 0 0 0 8
DI 0 Disable All Interupts (I - 0)
- - - - - -
EI 0 Enable All Interupts (I - ' 1) - - - - - -
DPTS 0 Disable all PTS Cycles (PSE = 0) - - - - - -
EPTS 0 Enable all PTS Cycles (PSE = 1) - - - - - -
NOP 0 PC-PC+1 - - - - - -

SKIP 0 PC-PC+2 - - - - - -

NORML 2 Left shift till msb = 1; D - shift count ". ". O. - - - 7

TRAP 0 SP ~ SP - 2; - - - - - - 9
(SP) - PC; PC - (2010H)
PU~HA 1 SP - SP-2; (SP) - PSW; 0 0 0 0 0 0
PSW - OOOOH; SP - SP-2;
(SP) - IMASK1/WSR; IMASK1 - OOH
POPA 1 IMASK1/WSR - (SP); SP - SP+2 ".. ". ". ". ". ".
PSW - (SP); SP - SP+2
IDLPD 1 IDLE MODE IF KEY= 1; - - - - - -
POWERDOWN MODE IF KEY = 2;
CHIP RESET OTHERWISE
CMPL 2 D-A ". ". ". ". t -

BMOV, 2 [PTA_HI] + - [PTA_LOW] + ; - - - - - -

BMOVi UNTILCOUNT=O

NOTES:
1. If the mnemonic ends in "B" a byte operation is performed, otherwise a word operation is done. Operands D, B, and A
must conform to the alignment rules for the required operand type. D and B are locations in the Register File; A can ,be
located anywhere in memory.
2. D,D + 2 are consecutive WORDS in memory; D is DOUBLE-WORD aligned.
3. D,D + 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to word.
5. Offset is a 2's complement number.
6. Specified bit is one of the 2048 bits in the register file.
7. The "L" (Long) suffix indicates double-word operation.
8. Initiates a Reset by pulling RESET low. Software should re-initialize all the necesi;lary registers with code starting at
2080H.
9. The ~ssembler will not accept this mnemonic.

5-22
inter 80C196KC USER'S GUIDE

Table 3-7D.lnstructlon Length/Opcode

INDIRECT INDEXED
MNEMONIC DIRECT IMMED
NORMAL*(1) A-INC*(1) SHORT*(1) LONG*(1)
ADD (3-op) 4/44 5/45 4/46 4/46 5/47 6/47
SUB (3-op) 4/48 5/49 4/4A 4/4A 5/4B 6/4B
ADD (2-op) 3/64 4/S5 3/66 3/66 4/67 5/67
SUB (2-op) 3/68 4/69 3/6A 3/SA 4/6B· 5/6B
ADDC 3/A4 4/A5 3/A6 3/AS 4/A7 5/A7
SUBC 3/A8 4/A9 3/AA 3/AA 4/AB 5/AB
CMP 3/88 4/89 S/AB 3/AB 4/8B 5/8B
ADDB (3-op) 4/54 4/55 4/56 4/5S 5/57 6/57
SUBB (3-op) 4/58 4/59 4/5A 4/5A 5/5B 6/5B
ADDB (2-op) 3/74 3175 3176 3176 4/77 5/77
SUBB (2-op) 3178 3179 317A 317A 417B 5/7B
ADDCB 3/B4 3/B5 3/BS 3/BS 4/B7 5/B7
SUBCB 3/B8 3/B9 3/BA 3/BA 4/BB 5/BB
CMPB 3/98 3/99 3/9A 3/9A 4/9B 5/9B
MUL (3-op) 5/(2) 6/(2) 5/(2) 5/(2) 6/(2) 7/(2)
MULU (3-op) 4/4C 5/4D 4/4E 4/4E 5/4F 6/4F
MUL(2-op) 4/(2) 5/(2) 4/(2) 4/(2) 5/(2) 6/(2)
MULU (2-op) 3/6C 4/6D 3/6E 3/6E 4/6F 5/6F
DIV 4/(2) 5/(2) 4/(2) 4/(2) 5/(2) 6/(2)
DIVU 3/8C 4/8D 3/8E 3/8E 4/8F 5/8F
MULB (3-op) 5/(2) 5/(2) 5/(2) 5/(2) 6/(2) 7/(2)
MULUB (3-op) 4/5C 4/5D 4/5E 4/5E 5/5F 6/5F
MULB (2-op) 4/(2) 4/(2) 4/(2) 4/(2) 5/(2) 6/(2)'
MULUB (2-op) 3/7C 317D 317E 317E 417F 517F
DIVB 4/(2) 4/(2) 4/(2) 4/(2) 5/(2) 6/(2)
DIVUB 3/9C 3/9D 3/9E 3/9E 4/9F 5/9F
AND (3-op) 4/40 5/41 4/42 4/42 5/43 6/43
AND (2-op) 3/60 4/S1 3/62 3/62 4/63 5/63
OR (2-op) 3/80 4/81 3/82 3/82 4/83 5/83
XOR 3/84 4/85 3/86 3/86 4/87 5/87
ANDB (3-op) 4/50 4/51 4/52 4/52 5/53 5/53
ANDB (2-op) 3/70 3171 3/72 3172 4173 4/73
ORB (2-op) 3/90 3/91 3/92 3/92 4/93 5/93
XORB 3/94 3/95 3/96 3/96 4/97 5/97
PUSH 2/C8 3/C9 2/CA 2/CA 3/CB 4/CB
POP 2/CC - 2/CE 2/CE 3/CF 4/GF

NOTES:
1. Indirect and indirect + share the same opcodes, as do short and long indexed opcodes. If the second byte is even, use
indirect or short indexed. If odd, use indirect or long indexed.
2. The opcodes for signed multiply and divide are the unsigned opcode with an "FE" prefix.

5-23
 80C196KC USER'S GUIDE

Table 3-7E. Instruction Length (in bytes)/Opcode

INDIRECT .INDEXED
MNEMONIC DIRECT IMMED
NORMAL A-INC SHORT LONG
LO 3/AO 4/A1 3/A2 3/A2 4/A3 5/A3
LOB 3/BO 3/B1 3/B2 3/B2 4/B3 5/B3
ST ! 3/CO - 3/C2 3/C2 4/C3 5/C3
STB 3/C4 - 3/C6 3/C6 4/C7 5/C?

I
XCI;i 3/04 - - - 4/0B 5/0B
XCHB 3/14 - - - 4/1B 5/1B
LOBSE 3/BC 3/BO 3/BE 3/BE 4/BF 5/BF
LBSZE 3/AC 3/AO 3/AE 3/AE 4/AF 5/AF

Mnemonic Length/Opcode Mnemonic Length/Opcode

PUSHF 1/F2 OJNZ 3/EO
POPF 1/F3 OJNZW 3/E1
PUSHA 1/F4 NORML 3/0F
POPA 1/F5 SHRL 3/0C
SHLL 3/00
TRAP 1/F7 SHRAL 3/0E
LCALL 3/EF SHR 3/08
SCALL 2/28-2F(3) SHRB 3/18
RET 1/FO SHL 3/09
L.)MP 3/E7 SHLB 3/19
SJMP 2/20-27(3) SHRA 3/0A
BR[) 2/E3 SHRAB 3/1A
TIJMP 4/E2
CLRC 1/F8
JNST 1/00 SETC 1/F9
JST 1/08 01 1/FA
JNH 1/01 EI 1/FB
JH 1/09 OPTS 1/EC
JGT 1/02 EPTS 1/EO
JLE 1/0A CLRVT 1/FC
JNC 1/B3 NOP 1/FO
JC 1/08 RST 1/FF
JNVT 1/04 SKIP 2/00
JVT 1/0C 10LPO 1/F6
JNV 1/05 BMOV 3/C1
JV 1/00 BMOVi 3/CO
JGE 1/06
JLT 1/0E
JNE 1/07
JE 1/0F
JBC 3/30-37
JBS 3/38-3F
NOTES:
3. The 3 least si.gnificant bits of. the opcode are concatenated with the 8 bits to form an 11-bit, 2's complement offset.

5-24
 80C1'96KC USER'S GUIDE

Table 3-SA. Instruction Execution State Times (1)

INDIRECT INDEXED
MNEMONIC DIRECT IMMED
NORMAL' A-INC' SHORT' LONG"
ADD (3-op) 5 6 7/10 8/11 7/10 8/11
SUB (3-op) 5 6 7/10 8/11 7/10 8/11
ADD (2-op) 4 5 6/8 7/9 6/8 7/9
SUB, (2-op) 4 5 6/8 7/9 6/8 7/9
ADDC 4 5 6/8 7/9 6/8 7/9
SUBC 4 5 6/8 7/9 6/8 7/9
CMP 4 5 6/8 7/9 6/8 7/9
ADDB (3-op) 5 5 7/10 8/11 7/10 8/11
SUBB (3-op) 5 5 7/10 8/11 7/10 8/11
AD DB (2-op) 4 4 6/8 7/9 6/8 7/9
SUBB (2-op) 4 4 6/8 7/9 6/8 7/9
ADDCB 4 4 6/8 7/9 6/8 7/9
SUBCB 4 4 6/8 7/9 6/8 7/9
CMPB 4 4 6/8 7/9 6/8 7/9
MUL (3-op) 16 17 18/21 19/22 19/22 20/23
MULU (3-op) 14 15 16/19 17/19 17/20 18/21
MUL (2-op) 16 17 18/21 19/22 19/22 20/23
MULU (2-op) 14 15 16/19 17119 17/20 18/21
DIV 26 27 28/31 29/32 29/32 30/33
DIVU 24 25 26/29 27/30 27/30 28/31
MULB (3-op) 12 12 14/17 13/15 15/18 16/19
MULUB (3-op) 10 10 12/15 12/16 12/16 14/17
MULB (2-op) 12 12 14/17 15/18 15/18 16/19
MULUB (2-op) 10 10 12/15 13/15 12/16 14/17
DIVB 18 18 20/23 21/24 21/24 22/25
DIVUB 16 16 18/21 19/22 19/22 20/23
AND (3-op) 5 6 7/10 8/11 7/10 8/11
AND (2-op) 4 5 6/8 7/9 6/8 7/9
OR (2-op) 4 5 6/8 7/9 6/8 7/9
XOR 4 5 6/8 7/9 6/8 7/9
ANDB (3-op) 5 5 7/10 8/11 7/10 8/11
ANDB (2-op) 4 4 6/8 7/9 6/8 7/9
ORB (2-op) 4 4 6/8 7/9 6/8 7/9
XORB 4 4 6/8 7/9 6/8 7/9
LD, LOB 4,4 5,4 5/8 6/8 6/9 7/10
STJ STB 4,4 - 5/8 6/9 6/9 7/10
XCH,XCHB 5,5 - - - 8/13 9/14
LDBSE 4 4 5/8 6/8 6/9 7/10
I
LDBZE 4 4 5/8 6/8 6/9 7/10
BMOV 6 + 8 per word + 3 for each memory controller reference
BMOVi 7+8 per word
+ 14 for each interrupt + 3 for each memory controller reference
PUSH (int stack) 6 7 9/12 10/13 10/13 11/14
POP (int stack) 8 - 10/,12 11/13 11/13 12/14
PUSH (ext stack) 8 9 11/14 12/15 12/15 13/16
POP (ext stack) 11 - 13/15 14/16 14/16 " 15/17
"Times for operands addressed as SFRs and internal RAM (0-1 FFH)/memory controller references (200-0FFFFH)).

NOTE:
1. Execution times for memory controller references may be one to two states higher depending on the number of bytes in
the prefetch queue.
2. INT stack is 0-1FFH and EXT stack is 200-0FFFFH.

5-25
inter 80C 196KC USER'S GUIDE

Table 3·8B. Instruction Execution State Times, c

MNEMONIC ~ , MNEMONIC
PUSHF (int stack) 6 PUSHF (ext stack) 8
POPF (int stack) 7 POPF (ext stack) 10
PUSHA tint stack) 12 PUSHA (ext stack) 18
POPA (int stack) 12 POPA (ext stack) 18
TRAP (int stack) 16 TRAP (ext stack) 18.
LCALL (int stack) 11 LCALL (ext stack) 13
SCALL (int stack) 11 SCALL (ext stack) 13
RET (int stack) 11 RET (ext stack) 14
CMPL 7 DEC/DECB 3
CLR/CLRB 3 EXT/EXTB 4
NOTINOTB 3 INC/INCS 3
NEG/NEGB 3
LJMP 7
SJMP 7
BR [indirect] 7
TIJMP 15 + 3 ·for each memory controller reference
JNST,JST 4/8 jump not taken/jump taken
JNH, JH 4/8 jump not taken/jump taken
JGT, JLE 4/8 jump not taken/jump tak~n
JNC, JC 4/8 jump not taken/jump taken
JNVT, JVT 4/8 jump not taken/jump taken
JNV,JV 4/8 jump not taken/jump taken
JGE, JLT 4/8 jump not taken/jump taken
JNE, JE 4/8 jump not taken/jump taken
JBC, JBS 5/9 jump not taken/jump taken
OJNZ 5/9 jump not taken/jump taken
OJNZW 6/10 jump not taken/jump taken
NORML 8 + 1 per shift (9 for 0 shift)
SHRL 7 + 1 per shift (8 for 0 shift)
SHLL 7 + 1 per shift (8 for 0 shift)
SHRAL 7 + 1 per shift (8 for 0 shift)
SHR/SHRB 6 + 1 per shift (7 for 0 shift)
SHL/SHLB 6 + 1 per shift (7 for 0 shift)
SHRAISHRAB 6 + 1 per shift (7 for 0 shift) ,
CLRC 2
, SETC 2
01 2
EI 2
OPTS 2
EPTS 2
CLRVT 2
NOP 2
RST 20 (includes fetch of configuration byte)
SKIP 3
10LPO 8/25 (proper key/improper key)

5-26
 80C196KC USER'S GUIDE

Table 3-8C. Instruction Execution State Times

PTSCYCLES
Single Transfer 18 (+ 3 for each memory controller reference)
Block Transfer 13 (+ 7 for each transfer, 1 minimum
+ 3 for each memory controller reference)
AID Mode (SFRs/internal RAM) 21
(MEMORY CONT) , 25
HSI MODE (SFRs/internal RAM) 12 (+ 10 for each transfer, 1 minimum)
(MEMORY CONT) 16 (+ 10 for each transfer, 1 minimum)
HSO MODE (SFRs/internal RAM) 11 (+ 10 for each transfer, 1 minimum)
(MEMORY CONT) 15 (+ ,11 for each transfer, 1 minimum)

3.6 80C196KC Instruction Set BMOVI Block move using 2 auto-incrementing

Additions pointers and a counter which can be in-
terrupted. BMOV with interrupt.
For users already familiar with the 80C196KB, there BMOVI updates the counter when inter-
are six instructions added to the standard MCS-96 in- rupted
struction set to form the 80C196KC instruction set. All XCH/XCHB Exchanges the contents of two registers
of the former instructions perform the same function. or a register and a memory location
The new instructions and their descriptions are listed TIJMP Jumps to an address selected out of a
below: table of addresses. The table may have a
OPTS Disables the Peripheral Transaction Server by maxim,um 128 entries
clearing the PSE flag in the PSW
EPTS Enables the Peripheral Transaction Server by See Figure 3-9 for TIJMP address calculation.
setting the PSE flag in the PSW

TIJMP TBASE, [INDEX], #INDEX_MASK

TBASE = WORD REGISTER CONTAINING 16-BIT ADDRESS
OF BEGINNING OF JUMP TABLE
INDEX = WORD REGISTER CONTAINING 16-BIT ADDRESS
OF 8-BIT INDEX INTO JUMP TABLE
INDEX_MASK = 8-BIT IMMEDIATE DATA TO MASK (AND)
WITH INDEX
ADDRESS CALCULATION Jump Table
DESTO N
[INDEX] AND INDEX_MASK = OFFSET . TBASE -
(2 • OFFSET) + TBASE DEST X DEST1 N+2
DEST2 N+4
-
-
-
DESTX N + 2' X

Figure 3-9. TIJMP Address Calculation

5-27
 80C,196KC USER'S GUIDE

3.7 Software Standards and , SUBROUTINE LINKAGE

Conventions Parameters are passed to subrouti~eS in the stack. Pa-
For a software project' of any size it is a good idea to rameters are pushed into' the stack in the order that
modularize the program and to establish standards they are encountered in the scanning of the source text.
which control the communication between these ,mod- Eight-bit parameters (BYTES or SHORT-INTE-
ules. The nature of these standards will vary with the GERS) are pushed into the stack with the high order
needs of the final application. A common component of byte undefined. Thirty-two bit par:;Uneters (LONG-IN-
all of these standards, however, must be the mechanism TEGERS, DOUBLE-WORDS, and REALS) are
for passing parameters to procedures and returning re- pushed onto the stack as two l6-bit values; the most'
, suits from procedures. In the absence of some overrid- significant half of the parameter is pus,hed into the
ing consideration which prevents their use, it is suggest- stack first.
ed that the user conform to the conventions adopted by
the PLM-96 programming language for procedure link- As an example, consider the following PLM-96 proce-
age. It is a very usable standard for both the assembly dure:
language and PLM-96 environment and it offers com-
patibility between these environments. Another advan- example_procedure: PROCEDURE
tage is that it allows the user access to the same floating (param l,param2,param3);
point arithmetics library that PLM-96 uses to operate DECLARE paraml BYTE,
on REAL variables. param2 DWORD,
param3 WORD;

REGISTER UTILIZATION, When this procedure is entered at run time the stack
will contain the parameters in the following order:
The MCS-96 architecture provides a 256 byte register
file. Some of these registers are used to control register-
mapped I/Q devices and for other special functions , 7171?? : param 1
such as the ZERO register and the stack pointer. The high word of' param2
remaining bytes in the register file, some 230 of them,
plus the extra 256 bytes of RAM, are available for allo- low word of param2
cation by the programmer. If these registers are to be
used effectively, some overall strategy for their alloca- param3
tion must be adopted. PLM-96 adopts the simple and return address - StacLpointer
effective strategy of allocating the eight bytes between
addresses I CH and 23H as temporary storage. The Flgl,lre 3-9. Stack Image
starting address of this region is called PLMREG. The
remaining area in the register file is treated as a seg- If a procedure returns a value to the calling code (as
ment of memory which is allocated as required. opposed to modify~ng more global variables) then the
result is returned in the variable PLMREG. PLMREG
is viewed as either an 8-, 16- or 32-bit variable depend-
ADDRESSING 32-BIT OPERANDS ing on the type of the procedure.
These operands are f!lrmed from two adjacent 16-bit The standard calling convention adopted by PLM-96
words in memory. The least significant word of the has several key features:
double word is always in lower address, even when the
data, is in the'stack (which means that the most signifi- a) Procedures can always assume, that the eight bytes of
cant w\lrd must be pushed into the stllck first). A dou- register file memory starting at PLMREG can be
used as temporaries within the body of the proce-
ble word is addressed by the address of its least signifi-
cant byte. Note that the hardware supports some opera- dure.
tions on double words. ' b) Code which calls a procedure must assume that the
eight bytes of register file memory starting at
PLMREG are modified by the procedure.
c) The Program Status,Word (PSW-see Section 3.4) is
not saved and restored by procedures so the calling
code must assume that the condition flags (Z, N, V,
VT, C, apd ST) are modified by the pr9cedure.
d) Function results from procedures ate always re-
turned in the variable PLMREG.

5-28
inter 80C196KC USER'S GUIDE

PLM-96 allows the definition of INTERRUPT proce- 4.1 Pulse Width Modulation Output
dures which are executed when a predefined interrupt (D/A)
occurs. These procedures do not c.onform to the rules of
a normal procedure. Parameters cannot be passed to Digital to analog conversion can be done with the Pulse
these procedures and they cannot return results. Since Width Modulation output. The SOCl96KC has 3 PWM
they can execute essentially at any time (hence the term outputs, like the 1 PWM on the SOC196KB.
interrupt), these procedures must save the PSW and
PLMREG when they are entered and restore these val- The output waveform is a variable duty cycle pulse
ues before they exit. which is selectable to repeat every 256 state times or
512 state times. Changes in the duty cycle are made by
writing to the PWM registers. Several types of motors
3.8 Software Protection Hints require a PWM waveform for most efficient operation.
Additionally, if this waveform is filtered it will produce
Several features to assist in recovery from hardware
a DC level which can be changed in 256 steps by vary-
and software errors are available on the SOCI96KC.
ing the duty cycle. Details on the PWM are in Section
Protection is also provided against executing unimple-
mented opcodes by the unimplemented opcode inter- 7.0.
rupt. In addition, the hardware reset instruction (RST)
can cause a reset if the program counter goes out of 4.2 Timer1 and Timer2
bounds. This instruction has an opcode of OFFH, so if
the processor reads in bus lines which have been pulled Two 16-bit timers are available for use on the
high it will reset itself. SOC 196KC. The first is designated "Timerl", the sec-
ond "Timer2". The timers are the time bases for the
The Watchdog Timer (WOT) further helps protect HSI and HSQ units and can be considered an integral
against software and hardware errors. When using the part of the HSI/Q. Details on the Timers are in Section
WOT to protect software it is desirable to reset it from S4 .
only one place in code, lessening the chance of an unde-
sired WOT reset. The section of code that resets the
WOT should monitor the other code sections for prop- Timer1
er operation. This can be done by checking variables to Timer1 is a free-running timer which is incremented
make sure they are within reasonable values. Simply every eight state times. It can be read and written, but
using a software timer to reset the WOT every 10 milli- care must bb taken when writing to it if the HSIQ Sub-
seconds will provide protection only for catastrophic system is being used. The precautions necessary when
failures. writing to Timerl are described in Section S. Timerl
can cause an interrupt when it overflows.
4.0 PERIPHERAL OVERVIEW
Timer2
There ~re five major peripherals on the SOCI96KC: the
Pulse-Width-Modulated outputs (PWM), Timerl and Timer2 counts transitions, both positive and negative,
Timer2, High Speed I/O. Unit, Serial Port, and AID on its input which can be either the T2CLK pin or the
Converter. A minor peripheral is the watchdog timer. HSI.1 pin. Also, the SOC196KC has added the capabili-
With the exception of the high speed I/O unit (HSIQ), ty to clock Timer2 internally every 1 or S state times.
each of the peripherals is a single unit that can be dis- Timer2 can be read and written and can be reset by
cussed without further separation. hardware, software or the HSQ unit. It can be config-
ured to count up or down based on Port 2.6 and it's
Four individual sections make up the HSIQ and work value can be captured into the T2CAPTURE register
together to form a very flexible timer/counter based on a rising edge on Port 2.7.
I/O system. Included. in the HSIQ are a 16-bit timer
(Timerl), a l6-bit up/down counter (Timer2), a pro- When clocking Timer2 externally, the maximum input
grammable high speed input unit (HSI), and a pro- transition speed is Once every S state times or once per
grammable high speed output unit (HSQ). With very state time in the Fast Increment mode. CLKQUT can-
little CPU overhead ,.the HSIO can measure pulse not be used to clock Timer2 directly. It must first be
widths, generate waveforms, and create periodic inter- divided by 2 since Timer2 counts both positive and neg-
rupts. Oepending on the application, the HSI/O can ative transitions.
perform the work of up to IS timer/counters and cap-
ture/compare' registers.
4.3 High Speed Inputs (HSI)
A brief description of the peripheral functions and in-
terractions is included in this section. All of the details The High Speed ·Input (HSI) unit can capture the value
on control bits and precautions are in the individual of Timer1 when an event takes place on one of four
sections for each peripheral starting with Section 7. input pins (HSI.0-HSI.3). Four types of events can
5-29
 , \
80C196KC USER'S.GUIDE

trigger a capture: nsing edges only, falling edges onty, ~he HSO unit by first writing to HSO_COMMAND
rising or falling edges, or every eighth rising ,edge. Each 'with the event to occur, and then to HSO_TIME with
HSI pin can be independently programmed to look for the, timer match'value.
any of these conditions. A block diagram of this unit is
shown in Figure 4-1. ' Fourteen different types of events can be triggered by
the HSO: 8 external and 7 internal. There are two inter-
When events occur, the Timer! value gets stored in the rupt vectors associated with the HSO, one for external
FIFO along with 4 status bits whioh indicate the input events, and one for internal events. External events con-
line(s) that caused the event. The neltt event ready to Pe sist of switching one or more of the 6 HSO lines
unloadec;l from the FIFO is placed in the HSI Holding (HSO.0-HSO.5). HSO.4 and HSO.5 share pins with
Register, so a total of 8 pieces of data can be stored in HSI.2 and HSI.3 and it is possible to have these pin~
the FIFO. Data is taken off the FIFO by reading the enabled for both functions. Internal events include set-
HSIJTA11US register, followed by reading, the ting up 4 Software Timers, resetting Timer2, and start-
HSI_TIME register. When\ the time register is read ing an AID conversion. The software timers are flags
the next FIFO location is loaded into the holding regis- that can be set by the HSO and optionally cause inter-
ter. rupts. '

Independent of the HSI operation, the state of the HSI

pins is indicated by 4 bits of the HSI_STATUS regis- 4.5 Serial Port
ter so the pins can also be inputs. Also independent of
the HSI operation is the HSI.O pin interrupt, which can The serial port on the 80C!96KC is functionally com-
be used as an extra external interrupt. Details on the patible with the serial port on the MCS-51 and MCS-96
HSI are in Section 9.0 families of microcontrollers. One synchronous and
three asynchronous modes are available. The asynchro-
nous modes are full duplex. Double buffering is provid-
4.4 High Speed Outputs (HSO) ed for the receiver so a second byte can be received
before the first byte has been read. The transmitter is
The High Speed Output (HSO) unit can generate events also double buffered, allowing bytes to be written 2 at a
at specified values of Timet! or Timer2 with minimal time.
CPU overhead. A block diagram of the HSO unit is
shown in Figure 4-2. Up to 8 pending events can be The Serial Port STATus (SPJ TAT) register contains
stored in the CAM (Content Addressable Memory) of bits to indicate receive overrun, parity, and framing er-
the HSO unit at one time. Commands are placed into rors, and transmit and receive interrupts.

HSI Trigger Options

XTAL1/16
~ HITOLO HSI.O
-r- LOTOHI HSl.l
HSI.2
CHANGE
DETECTOR
TRIGGERED
INPUT(S)

--1""'HiOR "lO'"l..- HSI.3

I I
.JlJ1JlJU1J1JUl
EVERY EIGHTH POSITIVE
8
TRANSITION

270704-6

270704-7

Figure 4~1 •.HSI Block Diagram

5-30
(
inter 80C196KC USER'S GUIDE

16-BIT 16-BIT
, T2CLK
T21NT

16

Him.! SPEED OUTPUT CONTROLS

6 PINS
4 SOFTWARE TIMERS
2 INTERRUPTS
INITIATE AID CONVERSION
RESET TIMER2 270704-8

Figure 4-2. HSO Block Diagram

BAUD RATES tional and some have multiple functions. In addition to

these ports, the HSI/O lines can be used as standard
Baud rates are generated in an independent IS-bit I/O lines.
counter based on either the T2CLK pin or XTALl pin.
Common baud rates can be easily generated with stan- Port 0 is an input port which is also the analog input
dard crystal frequencies. A maximum baud rate of I for the A/D converter. Port I is a quasi-bidirectional
Mbaud is available in the asynchronous modes with port. The three MSBs of Port I are multiplexed with
16 MHz on XTAL1. The synchronous mode has a the HOLD/HLDA functions. Also, the 2 extra PWM
maximum rate of 4.0 Mbaud with a 16 MHz clock. outputs are multiplexed on Port 1.4 and 1.3. Port 2
contains three types of pins: quasi-bidirectional, input
and output. Its input and output lines are shared with
4.6 AID Converter other functions. Ports 3 and 4 are open-drain bidirec-
tional ports which share their pins with the address/
The A/D Converter consists of a sample-and-hold, an data bus.
8-channel multiplexer, and a 8- or IO-bit successive ap-
proximation analog-to-digital converter. Quasi-bidirectional pins can be used as input and out-
put pins without the need for a data direction register.
Analog signals can be sampled by any of the 8 analog They output a strong low value and a weak high value.
input pins (ACHO through ACH7) which are shared The weak high value can be externally pulled low pro-
with Port O. An A/D conversion is performed on one viding an input function. A detailed explanation of
input at a time using successive approximation with a these ports can be found in Section 13.
result equal to the ratio of the input voltage divided by
the analog supply voltage. If the ratio is 1.00, then the
result will be all ones. A conversion can be started by 4.8 Watchdog Timer
writing to the AD_COMMAND register or by an
HSO command. For details on the A/D Converter, see The Watchdog Timer (WDT) provides a means to re-
Section 12. cover gracefully from a software upset. When the
watchdog is enabled it will initiate a hardware reset
unless the software clears it every 64K state times.
4.7 1/0 Ports Hardware resets on the 80CI96KC pull the RESET pin
low, providing a system reset to other components on
There are five 8-bit I/O ports on the 80C196KC. Some the board.
are input only, some are output only, some are bidirec-

5-31
inter 80C196KC USER'S GUIDE

5.0 INTERRUPTS NMI

Twenty-eight (28) sources of interrupts are available on NMI, the external Non-Maskable Interrupt, is the
the 80C196KC. These sources are gathered into 15 vec- highest priority interrupt. It vectors indirectly through
tors plus special vectors for NMI, the TRAP instruc- location 203EH. For design symmetry, a mask bit ex-
tion, and Unimplemented Opcodes. Figure 5-1 shows ists in INT_MASK1 for the NMI. However, the bit
the routing of the interrupt sources into their vectors as does not function and will not stop an NMI from oc-
well as the control bits which enable some of the sourc- curring. For future compatibility, the NMI mask bit
es. The operation of the Peripheral Transaction Server must be set to zero.
(PTS) is intimately a part of interrupt operation and is
discussed in Section 6. NMI on the 8096BH vectored directly to location
OOOOH, so for the 80C196KC to be compatible with
8096BH software, which uses the NMI, location
Special Interrupts 203EH must be loaded with OOOOH. The NMI interrupt
vector and interrupt vector location is used by some
Three special interrupts are available on the Intel development tools. The NMI interrupt is rising
80C196KC: NMI, TRAP and Unimplemented opcode. edge triggered.
Although available for customer use, these interrupts
may be used in Intel development tools or evaluation
boards.

SOURCES VECTORS

NON - MASKABLE INTERRUPT - - - - - - - - - NMI

TIMER 2 CAPTURE - - - - - - - - - TIMER 2 CAPTURE

4TH FIFO ENTRY - - - - - - - - - HSI FIFO 4

UNIMPLEMENTED OPCODE - - - - - - - -___, UNIMPLEMENTED OPCODE

TRAP INSTRUCTION SOFTWARE TRAP

,EXTINT (PORT 2.2) - - - - " ".....- - - - EXTINT 1

PORTO.7 ---_e~IOC1.l
- ' EXTINT

TI FLAG -~-...<:::;O\~----- TI FLAG

" " ' _ - - - - - - SERIAL PORT
RI FLAG _ _ _..c::;.;..._ _ _ _ RI FLAG

SWTO - 3 SOF'TWA'RE TIMER

RESET TIMER 2 --------1
START AID - - - - -.....

HSI.O PIN - - - - - - - - - HSI.O PIN

HSO LINES 0 - 5 - - - - - - - - - HIGH SPEED OUTPUT

HSI FIFO FULL HSI FIFO FULL

~IOC1.7
HSI HOLDING REGISTER LOADED ---_e - HSI DATA AVAILABLE

AID CONVERSION COMPLETE - - - - - - . - . - - AID CONVERSION COMPLETE

TIMER 2 OVERFLOW - - - _ - -....-.,,- TIMER 2 OVERFLOW
L..:.-j-IOC 1.3
TIMER 1 OVERFLOW --.:a-r---
IOC1.2
. . . --- TIMER OVERFLOW

270704-9

Figure 5-1. 80C196KC Interrupt Sources

5-32
 80C196KC USER'S GUIDE

TRAP 5.1 Interrupt Control

Opcode OF7H, the TRAP instruction, causes an indi-
rect vector through location 201OH. The TRAP in- Interrupt Pending Register
struction provides a single instruction interrupt useful
in designing software debuggers. The TRAP instruc- When hardware detects one of the sixteen interrupts, it
tion prevents the acknowledgement of interrupts until sets the corresponding bit in one of two pending inter-
after execution of the next instruction. rupt registers (INT_PEND @ 09H and INT_
PENDI @ 12H). When the interrupt 'vector is taken,
the pending bit is cleared. The~ registers, the formats
Unimplemented Opcode. of which are shown in Figure 5-3, can be 'read or modi-
fied as byte registers. They can be read to determine
Opcodes which are not implemented on the 80C196KC which of the interrupts are pending at any given time or
will cause an indirect vector through location 2012H if modified to either clear pending interrupts or generate
executed; interrupts under software control. Any software which
modifies the INT_PEND registers should ensure that
The programmer must initialize the interrupt vector ta- the entire operation is inseparable: The easiest way to
ble with the starting addresses of the appropriate inter- do this is to use the logical instructions in the two or
rupt service routines. It is suggested that any unused three operand format, for example:
interrupts be vectored to an error handling routine.
ANDB INT_PEND,#llllllOlB
; Clears the AID Interrupt
INTERRUPT SOURCES ORB INT_PEND.#OOOOOOIOB
; Sets the AID Interrupt
Caution must be used when writing to the pending reg-
ister to clear interrupts. If the interrupt has already
been acknowledged when the bit is cleared, a 5 state
time "partial" interrupt cycle will occur. This is be-
cause the' 80CI96KC will have to fetch the next in-
struction of the normal instruction flow, instead of pro-
ceeding with the interrupt processing. The effect on the
program will be essentially that of an extra ,two NOPs.
This can be prevented by clearing the bits using a 2
operand immediate logical,as the 80C196KC holds off
80C196KC acknowledging interrupts during these "read/modify/
28 Sources write" instructions.
. 18 Vectors

Interrupt Mask Register

Individual interrupts can be enabled or disabled by set-

VECTOR STATUS ting or' clearing bits in the interrupt mask registers
270704-10 (INT_MASK @ 08H and INT~ASKI @ 13H).
The format of these registers is the same as the Inter-
Figure 5-2. 80C196KC Interrupt Structure rupt Pending Register shown in Figure 5-3. ,
Block Diagram
The INT_MASK and INT_MASKI registers can be
Five registers control the operation of the interrupt sys- read or written as byte registers. A one in anY bit posi-
tem: INT....;PEND, INT_PENDl, INT_MASK and tion will enable the corresponding interrupt source and
INT_MASKI and the PSW which contains a global a zero will disable the source. The hardware will save
disable bit. A block diagram of the system is shown in any interrupts that occur by setting bits in the pending
Figure 5-2. The transition detector looks for 0 to I tran- register, even if the interrupt mask bit is cleared.' The
sitions on any of the sources. External sources have a INT_MASK register is the lower eight bits of the
maximum transition speed of one edge every state time. PSW so the PUSHF and POPF instructions save and
restore the INT_MASK register as well as the PSW.
Both the INT_MASK and INT_MASKI registers
can be saved and restored with the PUSHA and POPA
Instructions.

5-33
 80C196KC USER'S GUIDE

7 6 5 4 3 2 1 0
,12H IPEND1:, FIFO EXT T2 T2
NMI HSI4 RI TI
13H IMASK1: FULL INT1 0VF CAP
,
7 6 5 4 3 2 1 0
09H IPEND: EXT SER SOFT HSI.O HSO HSI AID TIMER
OSH IMASK: INT PORT TIMER PIN PIN DATA DONE OVF
Figure 5·3. Interrupt Mask
, and Pending Registers
Global Disable Vector
Number Source Priority
The processing of all interrupts except the NMI, TRAP Location
and unimplemented opcode interrupts can be disabled INT15 NMI 203EH 15
by clearing the I bit in the PSW. Setting the I bit will
enable interrupts that have mask register bits set. The I INT14 HSI FIFO Full 203CH 14
bit is controlled by the EI (Enable Interrupts) and DI INT13 EXTINT1 203AH ' 13
(Disable Interrupts) instructions. Note that the I bit
only controls the actuat servicing of interrupts. Inter- INT12 TIMEA2 Overflow 2038H 12
rupts that occur when l'is cleared will be held in the INT11 TIMEA2 Capture 2036H 11
pending register and serviced on a prioritized basis
when I is set. INT10 4th Entry into' HSI FIFO 2034H 10

INT09 AI 2032H 9

5.2 Interrupt Priorities INT08, ' TI 2030H 8

The priority encoder looks at all of the interrupts which SPECIAL Unimplemented Opcode 2012H N/A
are both ,pending and enabled, and selects the one with SPECIAL Trap 2010H N/A
the highest priority. The priorities are shown in Figure
5-4 (15 is highest, 0 is lowest). The interrupt generator INT07 EXTINT 200EH 7
then forces a call to the location in the indicated vector INT06 Serial Port 200CH 6
'location. This location would be the starting location of
the Interrupt ServiCe Routine (ISR). INT05 Software Timer 200AH 5

INT04 HSI.OPin 2008H 4

This priority selection controls the order in which
pending interrupts are passed to the software via in~er­ INT03 High Speed Outputs 2006H 3
rupt calls. The software can then implement its own
INT02 HSI Data Available 2004H 2
priority structure by, controlling the mask registers
(INT_MASK and INT~ASKI). To see how this is INT01 AID Conversion Complete 2002H 1
done, consider the case of a serial I/O service routine
which must run at a priority level which is lower than INTOO Timer Overflow 2000H 0
the HSI data available interrupt ~ut higher than any Figure 5·4. 80C196KC Interrupt Priorities
other source. The "preamble" and exit code for this
interrupt service routine would 1000k life this: Note that location 200CH in the interrupt vector table
would have to be loaded with the lab!ll seriaLJo~sr
serial_io_isr: , and the interrupt be enabled for this routine to execute.
PUSHA ;: Save 'the PSW, INT_MASK
; INT_MASK1, and WSR There is an interesting chailil of instruction side~effects
LDB INT_MASK,#OOOOOlOOB ' which makes this (or any other) 80CI96KC interrupt,
EI , ; Enable interrupts again service routine execute properly:

I
a) After the Irtterrupt controller decides to process ari
interrupt, it executes a "CALL", using the location
Service the interrupt 'froJ;Il the corresponding interrupt vector table entry
as the destination. The return address is pushed onto
the stack. Another interrupt cannot be serviced \lntil
i after the first instruction following the interrupt call
POPA Restore' is executed.
RET
5-34
 80C196KC USER'S GU!DE

b) The PUSHA instruction, which is guaranteed to exe- sider clearing a bit in the interrupt pending register as
cute, saves the PSW, INT-MASK, INT-MASKl, part of a non-interrupt routine:
and the WSR on the stack as two words, and clears
them. An interrupt cannot be serviced immediately LDB A~,INT_PEND
following a PUSHA instruction. (If INT-MASK 1 ANDB AL,#b1t_mask
and the WSR register are not used, or 8096BH code STB AL,INT_PEND
is being executed, PUSHF, which saves only the
PSW and INT~ASK, can be used in place of This code works if no other routines are operating con-
PUSHA). currently, but can cause occasional and serious prob-
c) LO INT_MASK, which is guaranteed to execute, lems if used in a concurrent environment. (All pro-
enables those interrupts that are allowed to interrupt grams which make use of interrupts must be considered
this ISR. This allows the software to establish its a concurrent environment.) For example, assume that
own priorities independent of the hardware. the INT_PEND register contains OOOOllllB and bit 3
(HSO event interrupt pending) is to be reset. The ~ode
d) The EI instruction reenables the processing of inter- does work for this data pattern but what happens if an
rupts with the new priorities. HSI interrupt occurs somewhere between the LDB and
e) At the end of the ISR, the POPA instruction restores , the STB instructiQns? Before the LOB instruction
the PSW, INT_MASK, INT_MASKl, and WSR INT_PEND contains OOOOllllB and after the LOB
to their original state when the interrupt occurred. instruction so does AL. If the HSI interrupt service
Interrupts cannot occur immediately following a routine executes at this point then INTJENO will
POPA instruction so the RET instruction is guaran- change to 0000101 lB. The ANOB changes AL to
teed to execute. This prevents the stack from over- OOOOOlllB and the STB changes INT_PEND to
flowing if interrupts are occurring at high frequency. 000001 1lB. It should be 0000001 lB. This code se-
(IfINT_MASKl and the WSR are not being used, quence has managed to generate a false HSI interrupt.
or 8096BH code is being executed, POPF, which re- These problems can be avoided by assuring mutual ex-
stores only the PSW and INT_MASK, can be used clusion which means that if more than one routine can
in place of POPA. change a variable, then the programmer must ensure
exclusive access to the variable during the entire opera-
Notice that the "preamble" and exit code for the inter- tion on the variable.
rupt service routine does not include any code for sav-
ing or restoring registers. This is because it has been In many cases the instruction set ofthe 80C196KC al-
assumed that the interrupt service routine has been al- lows the variable to be modified with a single instruc-
located its own private set of registers from the on- tion. The code in the above example can be implement-
board register file. The availability of some 230 bytes of ed with a single instruction.
register storage makes tl}is quite practical. By using the
VWindowing Scheme, an additional 256 bytes become ANDB
available (See Section 3.4).
Instructions an;: indivisible so mutual exclusion is en-
sured in this case. Changes to the INT_PENO or
5.3 Critical Regions INT_PENDI register must be made ,as a single in-
struction, since bits can be changed in this register even
Interrupt service routines sometimes must share data if interrupts are disabled. Depending on system config-
with other routines. Whenever the programmer is cod- urations, several other SFRs might also need to be
ing those sections of a program which access these changed in .a single instruction for the same reason.
shared pieces of data, great care must be taken to en-
sure that the integrity of the data is maintained. Con- When variables must be modified without interruption,
and a single instruction can not be used, the program-
mer must create what is termed a critical region. One
way to do this is to simply disable interrupts with a 01
instruction, perform the modification, and then re-en-

5-35
 80C'196KC USER'S GUIDE

able interrupts with an EI instruction. The problem When an interrupt is acknowledged the interrupt pend-
with this 'approach is that it leaves the interrupts en- ing bit is cleared, and a call is forced to the location
abled even if they were not enabled at the start. A bet- indicated by the specified interrupt vector. This call oc-
ter solution is to enter the critical region with a PUSHF curs after the completion of the instruction in process,
-instruction which saves the PSW and also cleani the except as noted above. The procedure of getting the
interrupt enable flag. The region can then be terminat- vector and forcing the call requires 16 state times. If the
ed with a POPF instruction which returns the ,interrupt stack is in external RAM an additional 2 state times are
enable to the state it was in before the code sequence. It required. This assumes a 0 wait-state bus.
should, be ,noted that some system cOnfigurations might
require more protection to form a critical region. An The maximum number of state times required from the
example is a system in which more than one processor time an interrupt is generated (not acknowledged) until
has access to a common resource such as memory or the 80C196KC begins executing code at the desired lo-
external 110 devices. cation is the time of the longest instruction, NORML
(Normalize - 39 state times), plus the 4 state times
prior to the end of the previous instruction, plus the
5.4 Interrupt Timing response time (16(internal stack) or 18(external stack)
state times). Therefore, the maximum response time is
The 80C196KC can be interrupted from four different 61 (39 + 4 + 18) state times. This does not include the
external sources; NMI, P2.2, HSI.O and PO.7. All exter- 6 state times required for PUSHF if jt is used as the
nal interrupts are sampled during PHI or CLKOUT first instruction in the interrupt routine or additional
low and are latched internally. Holding levels on exter- latency caused by having the' interrupt masked or dis-
, nal interrupts for at least one state time wiII ensure abled. Refer to Figure 5-5, Interrupt Response Time, to
, recognition of the interrupts. visualize an example of worst case scenario.

The externaI.interrupts on the 8OC196KC, although Interrupt latency time can be reduced by careful selec-
sampled during PHI, are edge triggered interrupts as tion of instructions in areas of code where interrupts
opposed to level triggered. are expected. Using: 'EI' followed immediately by a
long instruction (e.g. MUL, NORML, etc.) will in-
Interrupts are not always acknowledged immediately. crease the maximum latency by 4 state times, as an
If the interrupt signal does not occur prior to 4 state- jnterrupt cannot occur between EI and the instruction
times before the end of an instruction, the interrupt following EI. The DI, PUSHF, POPF, PUSHA, POPA
may not be acknowledged until after the next instruc- and TRAP instructions wiII also cause the same situa-
tion has been executed. This is because an instruction is tion. Typically these instructions would only effect la-
fetched and prepared for execution a few state times tency when one interrupt routine is already in process,
before it is actually executed. as these instructions are seldom used at other times.
There are 6 instructions which always inhibit interrupts
from being acknowledged until after the next instruc- 5.5 Interrupt Summary
tion has been executed. These instructions'are:
EI, DI - Enable and disable all interrupts by tog- Many of the interrupt veotors on the 8096BH were
gling the global disable bit (PSW.9). shared by multiple interrupts. The interrupts which
were s~ared on the 8096BH are: Transmit Interrupt,
PUSHF - PUSH Flags ,pushes the PSW/INT_ Receive Interrupt, HSI FIFO Full, Timer2 Overflow
MASK pair then clears it, leaving both and P2.2.0n the 8OC196KC, each of these interrupts
INt_MASK and PSW.9 clear. have their own interrupt vectors. The source of the in-
POPF - POP Flags pops the PSWlINT.-MASK terrupt vectors 'are typically programmed through con-
pair off the stack - trol registers. These registers can be read in HWindow
PUSHA - PUSH All does a PUSHF, then pushes 15 to determine the source of any interrupt. Interrupt
, the INT_MASK I/WSR pair and clears sources with two possible interrupt vectors, serial re-
INT.-MASKI ceive interrupt sharing serial port and receive interrupt
vectors for example, should be configured for only one
POPA - POP All pops the INT.-MASKI/wSR interrupt vector.
pair and then does a POPF

Interrupts can also not occur immediately after execu-

tion of:
Unimple'mented Opcodes
TRAP - The software trap instruction
SIGND - The signed prefix for multiply and divide
instructions' \

5-36
inter 80C196KC USER'S GUIDE

STATE TIMES

EXECUTION

·EXTI~T~ INTERRUPT ROUTINE

PENDING I SET
BIT - I

RESPONSE TIME ""1.--------

270704-11

Figure 5-5. Interrupt Response Time

Interrupts with separate vectors include: NMI, TRAP, to one generates an interrupt when the FIFO, indepen-
Unimplemented Opcode" Timer2 Capture, 4th Entry dent of the holding register, has six entries in it.
into HSr FIFO, Software timer, HSI.O Pin, High Speed
Outputs, and AID' conversion Complete, The NMI, On the 80C196KC, separate interrupt vectors are avail-
TRAP ,and Unimplemented Opcode interrupts were able for the HSI FIFO FULL(203CH) and HSI DATA
covered in Section 5,1. . AVAILABLE(2004H) interrupts. The interrupts
should be programmed for separate vector locations.
Refer to Section 9 for more information on the High
EXTINT and PO.7 Speed Inputs.
The 8OCl96KC has two external interrupt vectors;
EXTINT (200EH) and EXTINTl (203AH), The
EXTINT vector has two alternate sources selectable by
IOCLl, the external interrupt pin (Port 2.2) and Port The HSI FIFO can generate an interrupt when the HSI
0.7. The external interrupt pin is the only source for the has four or more entries in the FIFO. The HSI
EXTINTl interrupt vector. The external interrupt pin FIFO_4 interrupt vectors through location ·2034H.
should not be programmed to interrupt thro\1gh both Refer to Section 9 for more information on the High
vectors. Both external interrupt sources are rising edge Speed Inputs.
triggered.
HSI.O External Interrupt
Serial Port Interrupts
A rising edge on HSI.O pin can be used as an external
The serial port generates one of three possible inter- interrupt. Sampling is guaranteed if the pin is held for
rupts: Transmit interrupt TI(2030H), Receive Interrupt at least one state time. The interrupt vectors through
RI(2032H) and SERIAL(200cH). Refer to section 10 location 2008H. The pin does not have to be enabled to
for information on· the serial port interrupts. The the FIFO to cause an interrupt.
8096BH shared the TI and RI interrupts on the
SERIAL interrupt vector. On the 80Cl96KC, these in-
terrupts share both the serial interrupt vector and have Tlmer2 and Tlmer1 OverflOW
their own interrupt vectors. Ideally, the transmit and Timer2 and Timer! can interrupt on overflow. These
receive interrupts should \:Ie programmed as sllParate interrupts shared the same interrupt vector TIMER
interrupt vectors while disabling the SERIAL inter- OVERFLOW(2000H) on the 8096BH. The interrupts
rupt. For 8096BH compatibility, the interrupts can still are individually enabled by setting bits 2 and 3 in lOCI.
use the SERIAL interrupt vector. Which timer actually caused the interrupt' can be deter-
mined by bits 4 and 5 of 10SL On the 80Cl96KC
HSI FIFO FULL and HSI DATA AVAILABLE Timer2 ovc;rflow (OH or 8000H) has a separate inter-
rupt vector through location 2038H.
HSI FIFO FULL and HSI DATA AVAILABLE in-
·terrupts shared the HSI DATA' AVAILABLE inter-
rupt I vector on the 8096BH. The source of the HSI Timer2 Capture
DATA AVAILABLE interrupt is controlled by the The 8OCl96KC can interrupt in response to a Timer2
setting of I/O Control Register 1,(IOCL7). Setting capture triggered by a rising edge on P2.7. Timer2 Cap-
IOCL7 to zero will generate an interrupt when a time ture vectors through location 2036H.
value is loaded into the holding register. Setting the bit

5-37
 80C196KC USER'S GUIDE

High Speed Output sion. The interrupt vectors indirectly through location
2002H. Refer to Section 12 for more information on the
The High Speed Output interrupt can be generated in AID Converter.
response to a programmed HSO command which caus-
es,an external event. HSO commands which set or clear
the High Speed Output pins are considered external 6.0 PERIPHERAL TRANSACTION
events. Status Register IOS2 indicates which HSO SERVER
events have occured and can be used to arbitrate which
HSO command caused the interrupt. The Hig~ Speed The Peripheral Transaction Server (PTS) is a new fea-
Output interrupt vectors indirectly through location ture of the 80C196KC. ,The PTS provides DMA-like
2006H. For more information on High Speed Outputs, response to an interrupt with much less CPU overhead.
refer to Section 10. Single and block transfer modes are supported, as well
as special modes to service the AID Converter and the
HSI/O. Any of the 15 interrupt vectors can be alterna-
Software Timers tively mapped to its PTS channel.
HSO commands which create internal events can inter-
rupt through the Software Timer interrupt vector. In- Figure 6-1 shows the difference between a normal In-
ternal events include triggering an AID conversion, re- terrupt Service Routine and the same interrupt mapped
setting Timer2 and software timers. Status registers to its PTS channel. Instead of an Interrupt Service
IOS2 and 10SI can be used to determine which internal Routine, the PTS channel generates a PTS cycle. The
HSO event has occured. Location 200AH is the inter- software overhead of forcing the interrupt call,
rupt vector for the Software Timer interrupt. Refer to PUSHA, POPA, and executing the RET instruction is
Section 10 for more information on software timers and eliminated. Instead, the PTS cycle is interleaved with
the HSO. the normal instruction flow much like a DMA cycle.

AID Conversion Complete

The AID Conversion Complete interrupt can generate
an interrupt in response to a completed AID conver-

Normal Interrupt Response

NORMAL EXECUTION INTERRUPT SERVICE ROUTINE

PUSHA
LD VAR, TEMP3 / - ; RESPONSE TO
MUL SPEED, DISTANCE - ; INTERRUPT
- ; GOES HERE
INTERRUPT OCCURS
_ _ POPA

OR HERE, THERE
RrT

270704-77

PTS Response
NORMAL EXECUTION PTS CYCLE

LD VAR, TEMP3 / - ; ONE OF 5 PTS MODES

--
MUL SPEED, DISTANCE / " : ; EXECUTED IN MICROCODE
; PROGRAM COUNTER NEVER
INTERRUPT OCCURS ; CHANGES

OR HERE, THERE

270704-78

Figure 6-1. PTS vs Interrupt Response

5·38
inter 80C196KC USER'S GUIDE

6.1 PTS Control PTSVector Location

The PTS' vector table is composed of 15 words at loca· HSI FIFO Full 205CH
tions 2040H-205CH as shown in Figure 6-2. The PTS
vector table has the same format as the Interrupt vector EXTINT1 205AH
table and the same priority scheme (14 highest, 0 low· TIMER2 Overflow 2058H
est). All PTS channels have higher priority over any
interrupts except NMI. Each PTS vector points t~ a TIMER2 Capture 2056H
PTS Control Block (PTSCB) which must reside in the 4th HSI FIFO Entry 2054H
internal RAM space (lAH-IFFH) at an address even·
ly divisible by 8. Figure 6-3 gives the format of the RI 2052H
PTSCB for the 5 PTS modes. Unused bytes in the T1 2050H
PTSCBs can be used as normal RAM locations. The
PTSCB must be initialized by the user before the PTS EXTINT 204EH
channel is enabled. The function of each register is dis· Serial Port 204CH
cussed in the next few sections.
Software Timer 204AH
The PTS is globally enabled by the PSE bit (Peripheral
transaction Server Enable) in the PSW. PSE is set by HSI.O Pin 2048H
the EPTS (Enable PTS) instruction and cleared by the High Speed Outputs 2046H
DPTS (Disable PTS) instruction. When executing a
PUSHA instruction the PSE bit is pushed onto the HSI Data Available 2044H
stack with the PSW and then cleared. The PTSSEL AID Conversion. Complete 2042H
(PIS SELect) word register in HWindow 1 at O4H in·
dividually enables each PTS channel over the normal Timer OVerflow 2040H
interrupt response. PTSSEL has the same format as the Figure 6-2. PTS Vector Table
INT_PEND and INT~ASK registers and is shown
in Figure 6-4. When a bit in PTSSEl- is set, the associ· As in the normal interrupt response, the current in·
ated interrupt request becomes a frrs request. Each struction is completed before the PTS cycle actually
PTS request will set. the corresponding bit in the Inter· starts. The internal priority resolver handles the PTS
rupt Pending Register. Ifthe corresponding bit in the requests based on their priority. Next,'the PTS Vector
Interrupt Mask Register is also set, and the PTS is is read from the PTS Vector table to get the address of
globally enabled by the PSE bit, a PTS cycle will be
initiated. See Figure 6-5.

UNUSED UNUSED UNUSED UNUSED UNI-'SED

UNUSED PTSBLOCK UNUSED PTSBLOCK PTSBLOCK

PTSDST(HI) PTSDST(HI) REG (HI) UNUSED PTSDEST (HI)

PTSDST(LO) PTSDST(LO) REG (LO) UN,USED PTSDEST (LO)

PTSSRC(HI) PTSSRC(HI) 'S/D(HI) PTSSRC(HI) UNUSED

PTSSRC(LO) PTSSRC(LO) SID (LO) PT!:!SRC(LO) UNUSED

PTSeoN PTSCON PTSCON PTSCON PTSCON

PTSCOUNT PTSeoUNT PTSeoUNT PTSCOUNT PTSeoUNT

PTSVEC-+
Single Block AID Mode HSOMode HSI Mode
Transfer Transfer

Figure 6-3. PTS Control Blocks

5-39
)
 80C196KC USER'S GUIDE

PTSSRV @ 06H, in HWINDOW 1

Figure 6-4. The PTSSRV and PTSSEL Registers

the PTS Control Block (PTSCB). The microcode then bit in PTSSRV (PTS Serve) is set to actually request the
executes the proper PTS cycle, based on the contents of end-of-PTS interrupt. PTSSRV is located in HWindow
the PTSCB.' 1 at 06H (see Figure 6-4). The PTSSRV register acts
just like the Interrupt Pending registers in requesting
The PTSCOUN1; in the "PTSCB defines the number of interrupts. The PTSSRV register is used instead of the
PTS cycles to be run consecutively without software Pending Registers for the end-of-PTS interrupt so one
intervention. Since PTSCOUNT is an 8-bit value, the actual PTS request from the interrupt source can be
maximum number is 256. Loading PTSCOUNT with buffered in the Pending Register.
zero causes 256 transfers to occur. At the end of each
'PTS cycle, PTSCOUNT is decremented. When The end-of-PTS interrupt vectors through, the associat-
PTSCOUNT expires (i.e., equals 0), an actual interrupt ed location in the interrupt vector table. For example, if
called the end-of-PTS interrupt is requested which the TI interrupt is mapped to its PTS channel with its
should inyoke any processing needed and reinitialize PTS vector at 2050H, its end-of-'PTS interrupt is at
the PTS chan!1el. 2030H. The end-of-PTS interrupt has the same priority
as the normal interrupt vector. When the end-of-PTS
When PTSCOUNT expires; a unique series of events interrupt is called, the bit in PTSSRV is automatically
happens. F~rst, the associated bit in PTSSEL is cleared cleared .. however the PTSSEL bit must be set manually
to inhibit any additional PTS cycles until after, the end- t? reenable the PTS channel. See Figure 6-5.
of-PTS inter..rupt has executed. Secondly, the associated

5-40
 80C196KC USER'S GUIDE

Interrupt Source,

270704-90

Figure 6-5

6.2 PTS Modes 7 o

I M2 I M1 MO IB/W I SU OU SI 01 I
PTS SINGLE TRANSFER MODE
PTSCON
In the Single Transfer Mode, the PTSCB (Figure 6-3) M2, MI, MO (000) PTS Block Transfer Mode
contains control (PTSCON), source (PTSSRC), desti-
(100) PTS Single Transfer Mode
nation (PTSDST), and count (PTSCOUNT) registers.
A single transfer may be a byte or word and the B/W Byte (1)/Word (0) Transfer
PTSSRC and PTSDST may be optionally incremented SU Update PTSSRC at End ofPTS Cycle
at the end of the PTS cycle (see PTSCON in Figure
DU Update PTSDST at End ofPTS Cycle
6-6). The registers increment by I for a byte transfer or
by 2 for a word transfer. In the single transfer mode, SI PTSSRC Auto-Increment
both the auto-increment (SI, DI) and update bits (SU, DI PTSDST Auto-Increment
DU) must be set if either PTSSRC or PTSDST are to
be incremented. 7 o
I M2 I M1 I MO I 0 IUPOTI 0 o I
PTSCON
M2, MI, MO (110) PTS AID Mode
(011) PTS HSI Mode
(001) PTS HSQ Mode
UPDT Optional Update of Incremented
Value to:
AlD- SID REGISTER
HSI- PTSDST
HSO-PTSSRC
Figure 6-6. PTS Control Register Format

5-41
 80C196KC USER'S GUIDE

During a single transfer cycle, a byte or word is trans- to set up the ISR, 84 states to transfer each byte, and 59
ferred from the memory location pointed to by the states for the final ISR for a total of 10727 state times
PTSSRC to the memory location pointed to by (35 + 127 (84) + 59).
PTSDST. PTSSRC and PTSDST are optionally incre-
mented with the SI, SU and DI, DU bits. PTSCOUNT This same task clm easily be accomplished using the
is then decremented. If PTSCOUNT equals 0, the ap- PTS channel associated with the TI interrupt with
propriate PTSSRV bit is set and the PTSSEL bit is much less CPU overhead. The PTS channel is set up to
cleared to disable any further PTS cycles until the End- do a single byte transfer on every TI PTS request. The
of-PTS ISR is executed. PTSDST register always points to SBUF and does not
increment. The PTSSRC register points to the begin-
A single transfer takes 18 states + 3 for each memory ning of the block of memory and is set up to increment
controller reference. ' every PTS cycle. The code to set up the PTS channel
and the End-of-PTS interrupt is shown in Figure 6-6. It
At this time, an example would probably be of great takes 64 state times to set up the PTS channel, 21 state
help. Let's say a 128-byte block of contiguous memory times t9 transfer each byte, and 54 state times for the
needs to be transmitted over the serial port to another End-of-PTS interrupt for a grand total of 2721 state
host processor. Figure 6-7 shows the code necessary to times (64 + 127 (21) + 54). This reduces the software
accomplish this task using the TI interrupt and an In- overhead of this task by 75% compared to an Interrupt
terrupt Service Routine. This code takes 35 state times Service Routine.

CSEG AT 2030H
DCW TI ISR ;SET UP TI INTERRUPT VECTOR

;code to initialize TI interrupt

LDB IOCl,#00100000B ; ENABLE TXD PIN

LDB SPCON,#00001001B ;SET UP SERIAL PORT FOR MODE 0
LDB BAUD_REG, #77
LDB BAUD REG,#80H ;SET UP FOR 9600 BAUD @ 12 MHz
LD POINTER, #BEG_ TABL , ;POINT AT BEGINNING OF TABLE
;TO BE TRANSMITTED.
LDB ;INTIALIZE INTERRUPT MASK REG
EI ;ENABLE INTERRUPTS
LDB SBUF, [POINTER] + ;TRANSMIT FIRST BYTE IN TABLE

TRANSMIT INTERRUPT SERVICE ROUTINE

ROUTINE TAKES 84 STATE TIMES TO TRANSMIT BYTE, 59 IF IT SETS
THE TRANSMISSION DONE FLAG
TI ISR:
, PUSHF
LDB SP_TMP,SP_STAT ;MAKE BACKUP COpy OF SP_STAT
JBC SP_TMP,5,OUT ;CHECK FOR BOGUS INTERRUPTS
ANDB SP TMP,#00100000B ;CLEAR TI BIT INSP TEMP
CMP POINTER,#END_TABL ;CHECK TO SEE IF AT END OF TABLE
JNE TRANS AGAIN
ORB FLAGS;#OOOOOOOOIB ;IF AT END OF TABLE, SET A FLAG
SJMP OUT ;TO INDICATE DONE TRANSMITTING
TRANS AGAIN:
LDB SBUF, [POINTER] + ;SEND ANOTHER BYTE
OUT:
POPF
RET ;RETURN TO MAIN PROGRAM
270704-79

Figure 6-7. Transmit Interrupt Service Routine

5-42
inter 80C196KC USER'S GUIDE

CSEG AT 2030H
OCW TI END PTS_INT ;SETUP END OF PTS INTERRUPT

CSEG AT 2050H
OCW TIPTSCNT ;SETUP PTS VECTOR BY POINTING
;AT THE PTSCON REGISTER

RSEG AT OFOH ;SET UP PTS CONTROL BLOCK

TIPTSCNT: OSB 1 :PTS COUNT REGISTER
TIPTSCON: OSB 1 :PTS CONTROL REGISTER
TIPTSSRC: OSW 1 ;PTS SOURCE REGISTER
TIPTSOST: OSW 1 ;PTS DESTINATION REGISTER

;COOE TO INITIALIZE THE PTS

LOB IOC1,#OOlOOOOOB ;ENABLE TXD PIN
LOB SPCON,#OOOOlOOlB ;SET UP SERIAL PORT MODE 0
LOB BAUD REG,#80H ;9600 BAUD @ 12 MHz
LOB BAUD-REG, #77
LDB TIPTSCON,#10011010B ;PTS CHANNNEL FOR SINGLE BYTE TRANSFER
LD TIPTSSRC,#BEG TABL ;UPDATE SRC, DO NOT UPDATE DT
LD TIPTSDST,*SBU~ ;POINT PTSDST AT TABLE, PTSSRC @ SBUF
LDB TIPTSCNT,#127 ;127 PTS CYCLES BEFORE END-OF-pts INTERRUPT
LOB INT MASK1,#OOOOOOOlB ;SETUP INTERRUPT MASK
LDB WSR;#l ;CHANGE HWINDOW TO 1
LD PTSSEL,#OlOOH ;ENABLE PTS CHANNELOVER INTERRUPT
CLRB WSR ;SWITCH BACK TO WINDOW 0
LDB SBUF, [TIPTSSRC]+ ;TRANSMIT FIRST £YTE MAUALLY
EPTS ;ENABLE PTS
EI

TI ENO_PTS_ISR:
PUSHF
ANDB FLAGS,#OOOOOOOlB ;SET FLAG INDICATING
POPF ;TRANSMISSIONS DONE
RET
270704-80

Figure 6-8. Transmit Interrupt PTS Example

PTS BLOCK TRANSFER MODE Transfer with the SI and DI bits, and using the SU and
DU bits, keep their final value or revert to their value at
For a PTS Block Transfer, the PTSCB (Figure 6-3) the beginning of the PTS cycle. Finally, the
contains all the same registers as the Single Transfer PTSCOUNT register is decremented and if it equals 0,
Mode with the addition of a block count (PTSBLOCK) the PTSSRV bit is set and the PTSSEL bit is cleared to
register. The PTSCON also retains the same format as request the end-of-PTS interrupt.
the Single TranSfer Mode (see Figure 6-6).
A Block Transfer PTS cycle takes 13 states + 7 for
When a Block Transfer is selected, PTSBLOCK deter- each transfer (1 minimum) + 3 for each memory con-
mines how many byte or word transfers will take place troller reference. ,
(N = 1 to 32 transfers). Loading a zero in PTSBLOCK
causes 32 transfers to take place. N transfers take place Care must be taken when using the Block Transfer. A
from the memory pointed to by PTSSRC to the memo- Block Transfer cannot be interrupted. It would be very
ry pointed to by PTSDST. PTSSRC and PTSDST are easy to make a long uninterruptable instruction with a
optionally incremented after each transfer by the SI and Block Transfer. Taking the worst case, a Block Trans-
DI bits. When N transfers have expired, the PTSSRC fer of 32 words from ,external source to external desti-
and PTSDST registers are optionally updated with the nation over an 8-bit bus would take about 500 states
SU and DU. bits. This allows the PTSSRC and (assuming no wait states).
PTSDST registers to be incremellted during a Block

5-43
 80C196KC USER'S GUIDE

PTS AID MODE This makes it easier to save several HSI events in mem-
ory for later processing. The format of the HSI table is
The AID mode al.1ows automatic restart of the AID shown in Figure 6-10. For more information on the
converter while storing the previous result in a table HSI, see Section 9.
located in memory by mapping the AID_DONE in-
terrupt to its PTS channel. Figure 6-9 shows the AID
table format. The User sets up the AID commands in HSI_TIMEJ
the table and the PTSloads the AID with the com- XXX+OA
mahd and stores the result in the appropriate table lo- HSLSTATUSJI HSI_STATUSJ
XXX+8
cation. For more information on the AID Converter, HSI TIME 1
XXX+6
see Section 12. HSI_STATUS_11 HSI_STATUS_1
XXX+4
HSI_TIME_O
XXX+2
AID RESULT 2 HSI_STATUS_O I HSI_STATUS_O
XXX+OA XXX' +-PTSDST
I AID COMMAND 3 'XXX Can Lie anywhere in addressable memory space
XXX+8
AID RESULT 1
XXX+6 Figure 6-10. HSI PTS Table
I AID COMMAND 2
XXX+4
XXX+2
AID RESULT ° The PTSCB is made up of a destination register
I AID COMMAND 1
(PTSDST). a block count register (PTSBLOCK), and
XXX' +-S/D the control register (PTSCON) as shown in Figures 6-3
'XXX Can lie anywhere in addressable memory space and 6-5. PTSDST can be optionally updated at the end
of the PTS cycle by setting the UPDT bit in PTSCON.
Figure 6-9. PTS AID Table Format
When this PTS cycle is initiated, PTSBLOCK is read
The PTSCB contains a sourceldestination register to determine how many HSI transfers will take place
(SID), a register address (REG), and the PTS control (N = I to 7). For each transfer, the HSI_STATUS
register (PTSCON). The PTSCON format for the AID and HSI_TIME registers are written out to consecu-
Mode is shown in Figure 6-5. The SID register points tive words in memory pointed to by the PTSDST.
to the table in memory, and REG will point to the When N transfers have finished, PTSDST is optionally
AD_COMMAND register at location 02H in HWin- updated. Finally the value in PTSCOUNT is decre-
dow O. mented and if it is 0, the PTSSRV bit is set and the
PTSSEL bit is cleared to request the End-of-PTS inter-
In a PTS AID cycle, the word pointed to by SID is rupt.
loaded into a temporary internal register. SID is then
incremented by 2. Next, the AD_RESULT register is The HSI can generate an interrupt or PTS request
stored at the location pointed to by SID. The AID when the FIFO contains I, 5 or 7 entries, so the
command stored in the temporary register is now load- PTSBLOCK register should contain one of these val-
ed into the AD_COMMAND register to initiate an- ues.
other AID conversion. Now the SID is optionally up-
dated to point to the next word in the table with the The HSI mode takes 12 state times + 10 for each block
UPDT bit in PTSCON. If the SID is not updated, the transfer (I minimum) for Internal RAM/SFR space
same AID command is read and the result stored in and 16 states + 10 for each block transfer (I mini-
the same location for every PTS cycle.. Fiqally. mum) with memory controller references.
PTSCOUNT is decremented and if it is zero, t\le
PTSSEL bit is cleared and the PTSSRV bit is set to
request the end-of-PTS interrupt. PTS HSO (HIGH SPEED OUTPUT) Mode

The PTS HSOmode allows the HSO CAM to be load-

The AID mode takes 21 states when the table is in ed from a table located in internal or external memory
internal RAM/SFR space (O-IFFH) and 25 states as shown in Figure 6-11. For further information on the
with memory ..controller references (200H -OFFFFH).
HSO, see Section 10. The HSO mode operates the same
way as the HSI mode except the table is read rather
PTS HSIMODE than written.

The PTS HSI mode allows the FIFO to be dumped out

to a table in ·either internal or external tnemory by map-
ping one of the 3 HSI interrupts to its PTS channel.

5-44
 80C196KC USER'S GUIDE

gram of the circuit is shown in Figure 7-1. The 8-bit

HSO_TIME_2 counter is incremented every state time. When it equals
XXX,+OA 0, the PWM output is set to a one. When the counter
XXX+8
UNUSED I HSO COMMAND_2 matches the value in the corresponding PWM register,
XXX+6
HSO_TIMLl the output is switched low. When the counter over-
XXX+4
UNUSED I HSO COMMAND_l flows, the outputs are once again switched high. A typi-
cal output waveform is shown in Figure 7-2. When the
HSO_TIME_O
XXX+2 PWM register equals 00, the output is always low. Ad-
XXX'
UNUSED I HSO COMMAND_O
<-PTSSRC
ditionally, the PWM register will only be reloaded from
the temporary latch when the counter"overtlows. This
'XXX Can Lie anywhere in addressable memory space means the compare circuit will not recognize, a new
value until the counter has expired preventing missed
Figure 6·11. PTS HSO Table edges.
The, PTSCB contains a PTSSRC, PTSBLOCK, and The 80Cl96KC PWM unit has a prescaler bit (divide
PTSCON register. The PTSCON register for the HSO by 2) which is enabled by setting IOC2.2 = I. ~he
mode is shown in Figure 6-6. The source must always output waveform is a variable duty cycle pulse whIch
be incremented and the source can be optionally updat- repeats every 256 or 512 state times (32 JLS or 64 JLs ,at
ed at the end of the PTS cycle. When this PTS cycle is 16 MHz). Changes in the duty cycle are made by WrIt-,
initiated, PTSBLOCK is read to determine how many ing to the PWM register, PWMO register is at l.ocation
HSO transfers will take place (N ,= I to 8). For each l7H in HWindow 0 and the value programmed mto the
transfer, the two consecutive words pointed to by PWMO register can be read in HWindow 15 (WSR =
PTSSRC are read and loaded into the HSO_COM- 15). PWMO is compatible with the PWM output on the
MAND and HSO_TIME registers, respectively. 80C196KB. PWMI and PWM2 registers are located at
When the N transfers are done, PTSSRC is optionallY location 16H and' 17H in HWindow 1 ,and are read!
incremented and PTSCOUNT is decremented. If writable in HWindow 1. There are several types of mo-
PTSCOUNT equals 0, the PTSSEL bi~ is cleared and tors which require a PWM waveform for more efficient
the PTSSRV is set to request an End-of"PTS interrupt. operation. Additionally, if this waveform is integrated
it will produce a DC level which can be changed in 256
The PTS HSO mode takes II state times + 10 for each steps by varying the duty cycle, as described in the next
block transfer (l minim~m) with internal RAM!SFR section.
space or IS states + II for each block transfer (I mini-
mum) with memory controller references.
XTAL1 = 8MHz 10 MHz 16MHz

PTS Latency IOC2.2 = 0 15.6 KHz 19.6 KHz 31.25 KHz

IOC2.2 = 1 7.8 KHz 9.8 KHz 15.63 KHz
Because the prelude to a PTS request is so much like
that of an Interrupt, the latency is calculated in the Figure 7·3. PWM Frequencies
same manner. PTS latency is therefore defined to be the
longest instruction (NORML - 39 states) + 4 states The PWMO output shares a pin with Port 2, pin 5 so
= 43 states. See Figure 5-5. This does not include any
that these two features cannot be used at the same time.
higher priority PTS requests that may be executing or IOC1.0 equal to 1 selects the PWM function. PWMI
any time that the PTS is disabled via the PSE bit in the and PWM2 are multiplexed on Port 1, pins 3 and 4,
PSW. respectively. IOC3 register bit 2 and 3 in HWindow 1
enables the PWM I and PWM2 outputs over the port
function. All three PWM outputs use the same timer.
Therefore, the outputs go high at the same time. When
7.0 PULSE WIDTH MODULATION the pins are enabled as PWMs, the pin is no longer a
OUTPUT (D/A) quasi bidirectional port but has strong pullups and rull-
Digital to analog conversion can be done with any.of downs. The ports cannot be returned to quasi bidirec-
three Pulse Width Modulation outputs; a block dla- tionals unless the device is reset.

5-45
intJ 80C196KC USER'S.GUIDE

7.1 Analog Outputs

Analog outputs can be generated by two methods, ei-
ther by using the PWM output or the HSO. Either
device will generate a rectangular pulse train that varies
in duty cycle and period. If a smooth analog signal is
desired as an output, the rectangular waveform must be
filtered.

In most cases this filtering is best done after the signal

is buffered to make it swing from 0 to 5 volts since both
of the outputs are guaranteed only to low current lev-
PWM els. A block diagram of the type of circuit needed is
OUTPUT shown in Figure 7-4. By proper selection of compo-
mints, accounting for temperature and power supply
drift, a highly accurate 8-bit D to A converter can be
made using either. the HSO or the PWM output. Figure
7-5 shows two typical circuits. If the HSO is used the
STATE TIME CLOCK accuracy could be theoretically extended to 16-bits,
F(XTALI )/2 however the temperature and noise related problems
would be extremely hard to handle.
270704-12
• Duty Cycle Programmable in 256 Steps
When driving some circuits it may be desirable to use
unfiltered Pulse Width Modulation. This is particularly
Figure 7·1. PWM Block Diagram true for motor drive circuits. The PWM output can
generate these waveforms if a fixed period on the order
of 32 ,...S is acceptable. If this is not the case then the
HSO unit can be used. The HSO can generate a vari-
able waveform with a duty cycle variable in up to 65536
steps and a period of up to 66 milliseconds with
Timer!'

DUTY PWM CONTROL

CYCLE REGISTER VALUE OUTPUT WAVEFORM
HI
0% 00
LO

10% 25
~~.Jl~__~n~____~n~____
HI
50% 128
LO

80% 230
~..J u u
HI
119.8% 255
LO
270704-13

Figure 7·2. Typical PWM Outputs

80C196KC BUFFER
TO MAKE FILTER
HSO
OR
PWM
f-+
OUTPUT
SWING
RAIL
r--+
(PASSIVE
OR
ACTIVE)
----. POWER
AMP
(OPTIONAL)
ANALOG
f-+ OUTPUT
TO (OPTIONAL)
RAIL
270704-14

Figure 7·4. 01 A Buffer, Block Diagram

5-46
inter 80C196KC USER'S GUIDE

Vee

* 1/2 VQ3001P
270' 5.lK
PWM----~~~----. t-____~~----~-----AN;~~G

270704-15

~OC196:Kt ~._________
I- I ~ t" 1-:+--= 270704-16

. Figure 7-5. Buffer Circuits for 01 A

1+----------------P2.7
UP DOWN __
. 't~P2.6
IOC2.1

1 + - - - T2 INTERNAL CLOCK
1+---T2CLK
1+---HSI.l

'------------------T2RST

270704-5

Figure 8-1. Timer Block Diagram

8.0 TIMERS Timer!. Writes to Timerl should be taken into account

in software to -ensure events in the HSO CAM are not
Figure 8-1 shows Timerl and Timer2 missed or occur in an order which may be unexpected.
Changing Timerl with incoming events on the High
Speed Input lines may corrupt relative references be-
8.1 Timer1 tween captured inputs. Further information on the
High Speed Outputs and High Speed Inputs can be
Timerl is a 16-bit free-running timer which is incre- found in Sections 9 and 10 respectively.
mented every eight state times. An interrupt can be
generated in response to an overflow. It is read through
location OAH in HWindow 0 and written in HWindow 8.2 Timer2
15. Care must be taken when writing to it if the High
Speed I/O (HSIO) Subsystem is being used. HSO time Timer2 on the 80C196KC can be used as a reference
entries in the CAM depend on exact matches with for the HSO unit, an up/down counter; an external
event capture or as an extra counter. Timer2 is clocked

5-47
 80C196KCWSER'S GUIDE

externally using either the T2CLK pin or the HSI.l pin Fast Increment Mode
Timer2 counts on both positive and negative tran-
sitions. The maximum transition speed is once per state Timer2 can be programmed to run in fast increment
time in the Fast Increment mode, and once every 8 mode to count transitions every state time. Setting.
states otherwise. New on the80C196KC, Timer2 can IOC2.0 programs Timer2 in the Fast Increment mode.
be clocked internally every 1 or 8 state times. Timer2 IIi this mode, the events programmed on the HSO unit
can be read and written through location OCH in with Timer2 as a reference will not execute properly
HWindow O. Timer2 can be reset by hardware, soft- since the HSO requires eight state times to compare
ware or the HSO unit. Either T2RST or HSI.O can every location in the HSO CAM. With Timer2 as a
reset Timer2 externally depending on the setting of reference for the HSO unit, Timer2 transitioning every
IOCO.5. Figure 8-2 shows the configuration and input state time may cause programmed HSO events to be
pins of Timer2. Figure 8-3 shows the reset and clocking missed. For this reason, Timer2 should not be used as a
options for Timer2. The appropriate control registers reference for the HSO if transitions occur faster than
can be read in HWindow 15 to determine the pro- once every eight state times.
grammed modes. However, IOCO.l (T2RST) is not
latched and will read a 1. Timer2 should not be RESET in the fast increment
mode. All Timer2 resets are synchronized to an eight
Caution should be used when writing to the timers if stat<; time clock. If Timer2 is reset when clocking faster
they are used as a reference to the High Speed Output than once every 8 states, it may reset on a different
Unit. Programmed HSO commands <;ould be missed if count.
the timers do not count continuously in one direction.
High Speed Output events based on Timer2 must be
carefully programmed when using Timer2 as an Internal Clock Mode
up/down counter that can be reset externally. Pro- A new feature on the 80Cl96KC is the ability for
grammed events could be missed or occur in the wrong Timer2 to be clocked internally. Timer2 can be clocked
order. Refer to Section 9 for more information on using every 1 or 8 states. In the 8 state mode, Timer2 incre-
the timers with the High Speed Output Unit. ments at the same time as Timer!. Internal clocking is
enabled by setting IOC3.0 Clocking Timer2 every state
.Capture Register time is controlled by setting IOC2.0 while clearing
IOC2.0 causes Timer2 to count every 8 states.
The value in Timer2 can be captured into the
TZCAPTURE register by a rising edge on Port 2 pin 7.
The logic level must be held for at least one state time Up/Down Counter Mode
as discussed in the next section. T2CAPTURE is locat- Timer2 can be made to count up or down based on the
ed at OCH in HWindow 15. The interrupt generated by
Port 2.6 pin if IOC2.1 = 1. However, caution must be
a T2CAPTURE vectors through location 2036H.

Bit = 1 Bit", 0
IOCO.1 Reset Timer2 each write No action
IOCO.3 Enable external reset Disable
IOCO.5 HSI.O is ext. reset source T2RST is reset source
lOCO.? HSI.1 is T2clock source T2CLK is clock source
IOC1.3 Enable Timer2 overflow int. Disable overflow interrupt
IOC2.0 . Enable fast increment Disable fast increment
IOC2:1 Enable downcount feature Disable down count
P2.6 Count down if IOC2.1 = 1 Count up
IOC2.5 Interrupt on 7FFFH/8000H Interrupt on OFFFFH/OOOOH
P2.7 Capture Timer2 into
T2CAPTURE on rising edge
IOC3.0 Selects Timer2 internal Selects Timer2
clock source external clock source
Figure 8·2. Timer2 Configuration and Control Pins

5-48
 80C196KC USER'S GUIDE

used when this feature is working in conjunction with Interrupts can be generated if Timer2 crosses the
the HSO. If Timer2 does not complete a full cycle it is OFFFFH/OOOOH boundary or .the 7FFFH/8000H
possible to have events in the CAM which never match boundary in either direction. By having two interrupt
the timer. These events would stay in the CAM until points it is possible to have interrupts enabled even if
the CAM is cleared or the chip is reset. Timer2 is counting up and down centered around one
of the interrupt points. The boundaries used to control
the Timer2 interrupt is determined by the setting of
8.3 Sampling on External Timer Pins . IOC2.5. When set, Timer2 will interrupt on the
7FFFH/8000H boundary, otherwise, the OFFFFH/
The T2UP/DN, T2CLK, T2RST, and T2CAP pins are OOOOH boundary interrupts.
sampled during PH1. PHI roughly corresponds to
CLKOUT low externally. For valid sampling, the in- A T2CAPTURE interrupt is enabled by setting INT_
puts should be present 45 ns prior to the rising edge of MASK1.3. The interrupt will vector through location
CLKOUT or it may not be 'sampled until the next 2036H.
CLKOUT. To synchronize the inputs, the rising edge
of CLKOUT should latch the inputs and hold them Caution must be used when examining the flags, as any
until the next rising edge of CLKOUT. T2UP/DN and access (including Compare and Jump on Bit) of 10SI
T2CLK need to be synchronized unless they never clears bits 0 through 5 including the software timer
transition within one state time of each other. Other- flags. It is, therefore, recommended to copy the byte to
wise, Timer2 may count in the wrong direction. a temporary register before testing bits. Writing to
lOS I in HWindow 15 will set the status bits but not
cause interrupts. The general enabling and disabling of
8.4 Timer Interrupts the timer interrupts are controlled by the Interrupt
Mask Register bit O. In all cases., setting a bit enables a
Both Timerl and Timer2 can trigger a timer overflow function, while clearing a bit disables it.
interrupt and set a flag in the I/O Status Register I
(lOS I). Timerl! overflow is controlled by setting
IOC1.2 and the interrupt status is indifated in IOS1.5. 9.0 HIGH SPEED INPUTS
The TIMER OVERFLOW interrupt is enabled by set-
ting INT_MASK.O. The High Speed Input Unit (HSI) can record the time
an event occurs with respect to Timer!. There are 4
A Timer2 overflow condition interrupts through loca- lines (HSI.O through HS1.3) and up tOI a total of 8
tion 2000H by setting IOC1.3 and setting INT_ events can be recorded. HSI.2 and HSI:3 are bidirec-
MASK.O. Alternatively, Timer2 overflow can interrupt tional pins which can also be used as HSO.4 and
through location 2038H by setting INT_MASK1.4. HSO.5. The I/O Control Registers (lOCO and lOCI)
The status of the Timer2 overflow interrupt is indicated determine the functions of these pins. The values pro-
in !OS 1.4. grammed into lOCO and lOCI can be read in HWin-
dow 15. A block diagram' of the HSI unit is shown in
Figure 9-1. .

HSI.1

IOCO.7- - - --
. T2CNT

HSO# 14 ~----,
lOCO. 1 ~---I

,
IOCO.5
270704-17

Figure 8-3_ Timer2 Clock and Reset Options

5-49
inter 80C196KC USER'S GUIDE

1
FIFO
INTERRUPT
&:
CONTROL LOGIC
~lTSIMER
~

4 7x20 BIT
FIFO

HSI Trigger Option 270704-19

~ HITOlO
-r- lOTOHI

~ORlo'""L..

.hnnruuuW
EVERY EIGHTH POSITIVE
TRANSITION

270704-18

Figure 9-1. High Speed Input Unit

HSI Status Register (HSI_Status) 9.1 HSI Modes

There are 4 possible mqdes of operation for each of the
17 sl5 413 2 11 101 06H
HSI pins. The HSI_MODE register at location 03H
L HSI.O STATUS
controls which pins will look for what type of events. In
HWindow 15, reading the register will read back the
HSI.1 STATUS programmed HSI mode. The 8-bit register is set up as
HSI;2 STATUS shown in Figure 9-3.
HSI.3 STATUS
WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
BIT (STATUS BIT) INDICATES WHETHER OR NOT.AN EVENT
HAS OCCURED ON THIS PIN AND THE UPPER BIT (INPUT BIT)
INDICATES THE CURRENT INPUT LEVEL Of" THE PIN.
l7 61 5 41 3 211J oj 03H

270704-20 L HSI•O MODE

HSI.1 MODE
Figure 9-2. HSI Status Register Diagram
HSI.2 MODE
When an HSI event occurs, a 7X20 FIFO stores the 16 HSI.3 MODE
bits of Timerl, and the 4 bits indicating which pins WHERE EACH 2 - BIT MODE CONTROL FIELD
recorded events associated with that time tag. Multiple DEf"lNES ONE OF 4 POSSIBLE MODES:
,
pins can recognize events with the same time tag.
00 8 POSITIVE TRANSITIONS
Therefore, if multiple pins are being used as HSI inputs, 01 EACH POSITIVE TRANSITION
software must check each status bit when processing an 10 EACH NEGATIVE TRANSITION
HSI event. It can take up to 8 state times for this infor- 11 EVERY TRANSITION
(POSITIVE AND NEGATIVE)
mation to reach the holding register. For this reason, 8
state times must elapse between consecutive reads of 270704-21
HSI_TIME. When the FIFO is full, one additional Figure 9-3. HSI Mode Register 1
event, for a total of 8 events, can be stored by consider-
ing the holding register part of the FIFO. If the FIFO
and holding register are full, any additional events will
not be recorded. .

5-50
inter 80C196KC USER'S GUIDE

The maximum input speed is I event every 8 state times

except when the 8 transition mode is used, in which
SOfTWARE TIMER 0 EXPIRED
case it is I transition per state time.
SOfTWARE TIMER 1 EXPIRED
The HSI pins can be individually enabled and disabled SOfTWARE TIMER 2 EXPIRED
using bits in lOCO, as shown in Figure 9-4. If the pin is
disabled, events are not entered in the FIFO. However, SOfTWARE TIMER 3 EXPIRED
the input bits 9f the HSI_STATUS (Figure 9-2) are TIMER 2 HAS OVERfLOW
always valid regardless of whether the pin is enabled to
the FIFO. This allows the HSI pins to be used as gener- TIMER 1 HAS OVERfLOW
al purpose input pins. HSI fifO IS fULL
HSI HOLDING REGISTER DATA AVAILABLE
16H
T2RST--o .'- - IOCO.S 270704-23
, I : > ' o - o / - - - - T 2 RESET
i ~ - - IOCO.3 'Figure 9-5. 1/0 Status Register 1
• - - IOCO.O
HSI.O :>'0------- HSI
will also be indeterminate. The four HSI_STATUS
bits which indicate the current state of the pins will
• - - IOCO.2
always return the correct value.
:>'0-------
~,
HSI
HSI.l m.lER2 It should be noted that many of the status register con-
T2CLK - - 0 • -, IOCO.7 CLOCK ditions are changed by a reset, see Section 13. Writing
.- - IOCO.4 to HSI TIME in HWindow 15 will write to the HSI
FIFO holding register. Writing to HSI_STATUS in
HSI.2 - - 0"'-0......------- HSI HWindow 15 will set the status bits but will not affect
• - - IOCO.6 the input bits.
HSI.3 - - 0"'-0------.,..- HSI
270704-22

Fi9ure 9-4. lOCO Control of HSI Pin Functions

9.3 HSllnterrupts
Interrupts can be generated by the HSI unit in three
ways: each time a value moves from the FIFO into the
9.2 HSI Status holding register, when the FIFO has 4 or more'evcnts
stored; when the FIFO has 6 or more events.
Bits 6 and 7 of I/O Status Register I (lOCI-see Fig-
ure 9-5) indicate the status of the HSI FIFO. If bit 7 is The HSI_DATA~VAILABLE and HSI_FIFO_
set, the HSI holding register is loaded. The FIFO may FULL interrupts are shared on the 8096BH. The
or may not contain 1-5 events. If bit 6 of lOCI is set, source for the HSLDATA-AVAILABLE interrupt
the FIFO contains 6 entries. If the FIFO fills, future is controlled by IOCI.7. When IOC1.7 is cleared, the
events will not be recorded. Reading lOCI clears bits HSI will generate an interrupt when the holding regis-
0-5, so keep an image of the register and test the image ter is loaded. The interrupt indicates at least one HSl
to retain all 6 bits. event has occurred and is ready to be processed. The
interrupt vectors through location 2004H. The in.ter-
The HSI holding register must be read in a certain or- rupt is enabled by setting INT_MASK.2. The genera-
der. The HSI_STATUS Register (Figure 9-2) is read tion of a HSI_DATA~VAILABLE interrupt will
first to obtain the status and input bits. Second, the set lOS 1.7. The HSI_FIFO_ FULL interrupt will
HSI~TIME Register (04H) is read to obtain the time vector through HSI_DATA~VAILABLE if
tag. Reading HSI_TIME unloads one level of the IOC1.7 is set. On the 80C196KC, the HSI_FIFO_
FIFO. If the HSI_TIME is read before HSI_ FULL has a separate interrupt vector at location
STATUS, the contents of HSI_STATOS associated 203CH.
with that time HSI_TIME tag are lost.
A HSI_FIFO_FULL interrupt occurs when the
If the HSI_TIME register is read without the holding HSI~FIFO has six or more entries loaded independent
register being loaded, the returned value will be indeter-
minate. Under the, same conditions, the four bits in
HSI_STATUS indicating which events have occurred

5-51
inter 80C196KC USER'S GUIDE

of the holding register. Since all interrupts are rising 9.5 Initializing the HSI
edge triggered, the processor will not be reinterrupted
until the FIFO first contains 5 or less records, then When starting the HSI, two things need to be done.
contains six or more. The HSI FIFO FULL interrupt The FIFO should first be fl\lshed and the HSI initial-
mask bit is INT_MASKI.6. The occurrence of a HSI ized. The· FIFO should be flushed to clear out any
FIFO FULL interrupt is indicated by IOSI.6. Earlier pending events. The following section of code can be
warning of a impending FIFO full condition can be used to flush the FIFO:
achieved by the HSI FIFO 4th Entry interrupt.
reflush: ld 0., HSLTIME ;clear an event
The HSI_FIFO_4 interrupt generates an interrupt skip ;wait 8 state times
when four or more events are stored in the HSI FIFO skip
independent of the holding register. The interrupt is jbs 100Sl, 7, reflush
enabled by setting·' INT_MASKI.2. The HSI_
FIFO_4 vectors indirectly through location 2034H, When initializing the HSI, interrupt(s) need to be en-
There is no status flag associated with the HSI_ abled and the HSI pins need to be individually enabled
FIFO_4 interrupt since it has its own independent in- to the FIFO through lOCO. It is very important to
terrupt vector. . initialize the interrupts before the HSI pins or a FIFO
lockout condition could occur. For example, if the H~I
The HSI.O pin can generate an interrupt on the rising pins were enabled first, an event could get loaded into
edge even if its not enabled to the HSI FIFO. An inter- the holding register before the HSI_DATA_A VAIL-
rupt generated by this pin vectors through location ABLE interrupt.is enabled. If this happens, no HSI_
2008H. DATA-..:AV AILABLE interrupts will ever OCCljr.

9.4 HSI Input Sampling 10.0 HIGH SPEED OUTPUTS

The HSI pins are sampled internally once each state The High Speed Output unit (HSO) trigger events at
time. Any value on these pins must remain stable for at specific times with minimal CPU overhead. Events are
least I full state time to guarantee that it is recognized. generated by writing commands to the HSO_COM-
The actual sampling occurs during PH I or during MAND register and the relative time at which the
CLKOUT low. The HSI inputs should be valid at least events are to occur into the HSO_TIME register. In
45 ns before the rising of CLKOUT. Otherwise, the HWindow 15, these registers will read the last value
HSI input may be sampled in the next CLKOUT. programmed in the holding register. The programma-
Therefore, if information is to be synchronized to the ble events include: starting an A/D ~onversion, reset-
HSI it should be latched on the rising edge of ting Timer2, setting 4 software flags, and switching 6
CLKOUT. output lines (HSO.O through HSO.S). The. format of

'1 6 5 4 3 I 2 I 1 I 0
HSO_ CAM TMR2/ SET/ INT/
CHANNEL 06H
COMMAND LOCK TMR1 CLEAR INT

CAM Lock - Locks event in CAM if this is enabled bi IOC2.6 (ENA_LOCK)

TMR2/'fMR} - Events Based on Timer2/Basedon Timer! if 0
SET/CI:EAR - Set HSO pin/Clear HSO pin if 0
INT/INT - Cause interrupt/No interrupt if 0
CHANNEL: 0-5: HSO pins 0-5 separately
(in Hex) 6: HSO pins 0 and I together
7: HSO pins 2 and 3 together
8-B: Software Timers 0-3
C: HSO pins 0-$ together
D: Unflagged Event (Do not use. for future compatibility~
E: Reset Timer2
F: Start A/D Conversion

Figure 10-1. HSO Command Register

5-52
 80C196KC USER'S GUIDE

the HSO'_CO'MMAND register is shown in Figure SOFTWARE TIMERS

10-1. Command O'CH, sets or clears all of the HSO'
pins, is new on the 80C196KC O'DH is reserved for use The HSO' can be programmed to generate interrupts at
on future products. Up to eight events can be pending preset times. Up to four such "Software Timers" can be
at one time and interrupts can be generated whenever in operation at a time. As each preprogrammed time is
any of these events are triggered. HSO'.4 and HSO'.5 are reached, the HSO' unit sets a Software Timer Flag. If
bidirectional pins which are multiplexed with HSI.2 the interrupt bit in the HSO' command register was set
and HSI.3 respectively. Bits 4 and 6 of I/O' Control then a Software Timer Interrupt' will also be generated.
Register 1 (IO'C1.4, IO'C1.6) enable HSO'.4 and HSO'.S The interrupt service routine can then examine I/O'
as outputs. The Control Registers can be read in HWin- Status register 1 (IO'S1) to determine which software
,dow IS to determine the programmed modes for the timer expired and caused the interrupt. When the HSO'
HSO'. However, the IOC2.1(CAM; CLEAR) bit is not resets Timer2 or starts an A/D conversion, it can also
latched and will read as a one. Entries can be locked in generate a software timer interrupt.
the CAM to' generate periodic events or waveforms.
If more than one software timer interrupt occurs in the
same time, multiple status bits will be set. Each read of
10.1 HSO Interrupts and,Software lOS 1 (see Figure IO-S) will clear bits 0 through 5. Be .
Timers certain to save the byte before testing it. See also Sec-
tion l2.S.
The HSO' unit can generate two types of interrupts. The
High Speed O'utput execution interrupt can be generat-
ed (if enabled) for HSO' commands which change one 10.2 HSOCAM
or more of the six output pins. The other HSO' inter-
rupt can be generated by any other HSO' command, A block diagram of the HSO' unit is shown in Figure
(e.g. triggering the A/D, resetting Timer2 or a software 10-3. The Content Addressable Memory (CAM) file is
Timer Interrupt). the center of control. O'ne CAM register is compared
with the timer values every state time, taking 8 state
times to compare all CAM registers with the timers.
HSO Interrupt Status This defines the resolution of the HSO to be 8 state
times (1 microsecond at an oscillator frequency of
Register IO'S2 at location I1H displays the HSO' events
16 MHz). '
which have occurred. IO'S2 is shown in Figure 10-2.
The !!vents displayed are HSO'.O through HSO'.S,
Each CAM register is 24 bits wide. Sixteen bits specify
Timer2 Reset and start of an A/D conversion. IO'S2 is
the time the action is to be carried out, and 8 bits define
cleared when accessed. Therefore, the register should
the action to take place. The format of the command to
be saved in an image register if more than one bit is
the HSO' unit is shown in Figure 10-1. Note that bit S is
being tested. Writing to this register in HWindow IS
ignored for command channels 8 through OFH, except
will set the status bits but not cause interrupts. In
for command OCH.
HWindow IS, writing to IOS2 can set the High Speed
O'utput lines to an initial value.
To enter a command into the CAM file, write the 8-bit
"Command Tag" into location 0006H followed by the

IOS2: 7 6 5 4 3 2 1 0
START T2
HSO.5 HSO.4 HSO.3 HSO.2 HSO.1 HSO.O
AID RESET

l1H
read Indicates which HSO' event occcured
START AID: HSO'_CMD IS, start AID
T2RESET: HSO'_CMD 14, Timer2 Reset
HSO'.O-S: O'utput pin's HSO'.O through HSO'.S

Figure 10-2.1/0 Status Register 2

5-53
 80C196KC USER'S GUIDE

16-81T 16-81T

T2CLK
XTAL1/16
T2RST
CONTROL
LOGIC

L~J 24-----t

CAM FILE 8

16

HIGH SPEED OUTPUT CONTROLS

6 PINS .
4 SOFTWARE lilMERS
2 INTERRUPTS
BUS INITIATE AID CONVERSION
RESET TIMER2
270704-24

Figure 10-3. High Speed Output Unit

time the action is to be carried out into word address can also be overwritten. Since it can take up to 8 state
0004H. The typical code would be: times for a command to move from the holding register
to the CAM, 8 states must be allowed between succes-
LOB HSO_COMMAND,#what_to_do sive writes to the CAM.
ADD HSO_TIME,Timerl,#when_to_do_it
To provide proper synchronization, the minimum time
that should be loaded to Timer! is Timerl + 2. Small-
er values may cause the Timer match to occur 65,636
counts later than expected. A similar restriction applies
HSO.O CURRENT STATE
if Timer2 is used.
HSO.1 CURRENT STATE
HSO.2 CURRENT STATE
Care must be taken when writing the command tag for
the HSO, because an interrupt can occur between writ-
HSO.3 CURRENT STATE ing the command tag and loading the time value. If the
HSO.4 CURRENT STATE interrupt service routine writes to the HSO, the com-
mand tag used in the interrupt routine will overwrite
HSO.5 CURRENT STATE
the command tag from the main routine. One way of
CAM ~ HOLDING REGISTER IS FULL aVdiding this problem would be to disable interrupts
HSO HOLDING REGISTER IS FULL
when writing'to the HSO unit.

270704-25
10.3 HSO Status
Figure 10-4.1/0 Status Register 0,
Before writing to the HSO, ensure that the Holding
Writing the time value loads the HSO Holding Register Register is empty.]f it is not, writing to the HSO will
with both the time and the last written command tag. overwrite the value in the Holding Register. I/O Status
The command does not actually enter the CAM file Register 0 (IOSO) bits 6 and 7 indicate the status of the
until an empty CAM register becomes available. HSO unit. If IOSO.6 equals 0, the holding register is
empty and at least one CAM register is empty. If
Commands in the holding register will not execute even IOSO.7 equals O,the holding register is empty. The pro-
if their time tag is reached. Commands must be in the grammer should carefully decide which of thes.e two
CAM to execute. Commands in the holding register flags is the best to use for each application. This register

5-54
inter 80C196KC USER'S GUIDE

also shows the current status of the HSO.O through 10.4 Clearing the HSO and Locked
HSO.5. The HSO pins can be set by writing to this Entries
register in HWindow 15. The format for I/O Status
Register 0 is shown ,in Figure 10·4, All 8 CAM locations of the HSO are compared before
any action is taken. This allows a pending external
event to be cancelled by simply writing the opposite
16H event to the CAM. However, once an entry is placed in
SOFTWARE TIMER 0 EXPIRED the CAM, it cannot be removed until either the speci·
fied timer matches the written value; a chip reset oc-
SOFTWARE TIMER 1 EXPIRED curs or IOC2.7 is set. IOC2.7 clears all entries in the
SOFTWARE TIMER 2 EXPIRED CAM.
SOFTWARE TIMER 3 EXPIRED
Internal events cannot be cleared by writing an oppo-
TIMER 2 HAS OVERFLOW site event. This includes events on HSO channels 8-B
TIMER 1 HAS OVERFLOW
and E-F. The only method for clearing these events is
by a reset or setting IOC2.7.
HSI FIFO IS FULL
HSI HOLDING REGISTER DATA AVAILABLE
HSO LOCKED ENTRIES
270704-26
The CAM Lock bit (HSO_Command.7) can be set to
Figure 10-5. 1/0 Status Register 1 (1051) keep commands in the CAM, otherwise the commands
will clear from the CAM as soon as they cause an
The expiration of software timer 0 through 4, and the event. This feature allows for generation periodic events
overflow of Timer! and Timer2 are indicated in lOS 1. based on Timer2 and must be enabled by setting
The status bits can be set in HWindow 15 but not cause IOC2.6. To clear locked events from the CAM, the en-
interrupts. The register is shown in Figure 10·5. tire CAM can be cleared by writing a 'one to the CAM
clear bit IOC2.7. A chip reset will also clear the CAM.
Whenever the processor reads this register all of the
time· related flags (bits 5 through 0) are cleared. This Locked entries are useful in applications requiring peri-
applies not only to explicit reads such as: odic or repetitive events. Timer2 used as an HSO refer-
ence can generate periodic events with the use of the
LDB AL,IOSI HSO T2RST command. HSO events programmed with
a HSO time less then the Timer2 reset time will occur
but also to implicit reads such as: repeatedly as Timer2 resets. Recurrent software tasks
can be scheduled by locking software timers commands
JB IOSl.3,somewhere_else into the High Speed Output Unit. Continuous sampling
'of the A/D converter can be accompished by program-
which jumps to somewhere_else if bit 3 ofIOSI is set. ming a locked HSO A/D conversion command. One of
In most 'cases this situation can best be handled by hav· the most useful features is the generation of multiple
ing a byte in the register file which maintains an image PWM's on the High Speed Output lines. Locked entries
of the register. Any time a hardware timer interrupt or provide the ability to program periodic events While
a HSO software timer interrupt occurs the byte can be minimizing software overhead.
updated:
Individual external events setting or clearing an HSO
ORB IOSLimage,IOSl pin can by cancelled by writing the opposite event to
the CAM. The HSO events do not occur untU the timer
leaving 10SI_image containing all the flags that were reference has changed state. An event programmed to
set before plus all the new flags that were read and set and clear an HSO event at the same time will cancel
cleared from 10S1. Any other routine which needs to each other out. Locked entries can correspondingly be
sample the flags can safely check lOS I_image. Note cancelled using this method. However, the entries re-
that .if these routines need to clear the flags that they main in the HSO CAM and can quickly fill up the
have acted on, then the modification of lOS I_image available eight locations. As an alternative, all entries in
must be done from inside a critical region. the HSO CAM can be cleared by setting IOC2.7.

5-55
 80C196KC USER'S GUIDE

10.5 HSO Precautions port is functionally compatible with the serial port on
the MCS-5l family of microcontrollers, although the
Timer! is incremented every S state-times. When software controJling the ports is different.
Timer! is being used as the reference timer for an HSO
command, the comparator has a chance to look at all S 'Data to and from the serial port is transferred through
CAM registers before Timer! changes its value. Writ- SBUF(RX) and SBUF(TX), both located at 07H.
ing to, Timer!, which is allowed in HWindow 15, SBUF(TX) holds data ready for transmission and
should be carefully done. The user should ensure writ- SBUF(RX) contains data received by the serial port.
ing to Timer! will not cause programmed HSO events SBUF(TX) and SBUF(RX) can be'read and written in
to be missed or occur in the wrong order. The same HWindow IS.
precaution applies to Timer2.
Mode 0, the synchronous shift register mode, is de-
The HSO requires at least eight state times to compare signed to expand I/O over a serial line. Mode' I is. the
each entry in the CAM. Therefore, the fast increment standard S bit data asynchronous mode used for normal
mode for Timer2 cannot be used as a reference for the serial communications. Modes 2 and' 3 are 9 bit data
HSO if transitions occur faster then once every eight asynchronous modes typically used for interprocessor
state times. communications.

Referencing events when Timer2 is being used as an

up/down counter could cause events to occur in oppo- 11.1 Serial Port Status and Control
site order or be missed entirely. Additionally, locked
entries' could occur several times if Timer2 is oscillating Control of the serial port is done through the Serial
around the time tag for an entry. Port Control (SP_CON) register shown in Figure
II-I. Writing to location IIH accesses SP.-:...CON while
When using Timer2 as the HSO reference, caution reading it accesses SP_STAT. The upper 3 bits of
must be taken that Timer2 is not reset prior to the SP_CON must be written as Os for future compatibil- '
highest value for a Timer2 match in the CAM. If that ity, On the SOCI96KC the SP_STAT regisfer contains
match is never reached, the event will remain in the bits to indicate receive Overrun Error (OE), Framing
CAM until the device is reset or CAM is cleared. Error (FE), and Transmitter Empty (TXE), The bits
which were also present on the S096BHare the Trans-
mit Interrupt (TI) bit, the Receive Interrupt (RI) bit,
10.6 HSO Output Timing and the Received Bit S (RBS) or Receive Parity Error
(RPE) bit. SP_STAT is read-only in HWindowO and
Changes in the HSO lines are synchronized to Timer! is shown in Figure 11-1.
or Timer2. All of the external HSO lines due to change
at a certain vlllue of a timer will change just after the In aU modes, the RI flag is set after the last data bit is
incrementing of the timer. Internally, the timer changes sampled, approximately in the middle of a bit time.
every eight state times during Phase 1. From an external Data is held in the receive shift register until the last
perspective the HSO pin should change just prior to the data bit is received, then the data byte is loaded into
falling edge of CLKOUT and be stable by its rising SBUF (RX), The receiver on the 80CI96KB also
edge. Information from the HSO can be latched on the checks for a valid stop bit. If a stop bit is not found
CLKOUT rising edge. Internal events also occur when within the appropriate time, the Framing Error (FE)
the refere)lce timer increments. bit is set.

Since the receiver is double-buffered, reception on a

11.0 SJ:RIAL PORT second data byte can begin before the first byte is read.
However, if data in the shift register is loaded into
The serial port has one synchronous and 3 asynchro- . SBUR (RX) before the previous byte is read, the Over-
nous modes. The asynchronous modes are full duplex, flow Error (OE) bit· is set. Regardless, the data in SBUF
meaning they can transmit and receive at the same (RX) will aLways be the latest byte received; it will nev-
time. The receiver is double buffered so that the recep- er be a combination of the two bytes. The RI, FE, and
tion of a second byte can begin before the first byte has OE flags are cleared when "SP_STAT" is read. How-
been read. The transmitter on the SOCI96KC is also ever, RI does not have to be cleared for the serial port
double buffered allowing continuous transmissions. The to receive data.

5-56
inter 80C196KC USER'S GUIDE

~-~--+--:-'-+--:--~-T-:-8-r-R-:-N-+-P-~-N-+--M-12~r-M-~~1 11H
TB8 - Sets th~ ninth data bit for transmission. Cleared after each transmission. Not valid
if parity is enabled.
REN - Enables the receiver
PEN - Enables the Parity function (even parity)
M2, MI - Sets the mode. ModeO = 00, Model = 01, Mode2 = 10, Mode3 = 11
7 6 5 4 3 2 1 0
RB8/ ,
RI TI FE /TXE OE X X 11H
RPE
RB8 - Set if the 9th data bit is high on reception (parity disabled)
RPE - Set if parity is enabled and a parity error occurred
RI - Set when the last data bit is sampled
TI - Set at the beginning of the STOP bit transmission
FE - Set if no STOP bit is found at the end of a reception
. TXE - Set if tw~ bytes can be transmitted
OE - Set if receive~ is overwritten

Figure 11-1. Serial Port Control and Status Registers

The Transmitter Empty (TXE) bit is set if the transmit In the asynchronous modes, writing to SBUF (TX)
buffer is empty and ready to take up to two characters. ; starts a transmission. A falling edge on RXD will begin
TXE gets cleared as soon as a byte is written to SBUF. a reception if REN is set to 1. New data placed in
Two. bytes may be written consecutively to SBUF if SBUF (TX) is held and will not be transmitted until the
TXE is set. One byte may be written if TI alone is set. end of the stop bit has been sent.
By definition, if TXE has just been set, a transmission
has completed and TI will be set. The TI bit is reset In all modes, .the RI flag is set after the last data bit is
when the CPU reads the SP_STAT registers. sampled approximately in the middle of the bit time.
For all modes, the TI flag is set after the last data bit
The TB8 bit is cleared after each transmission and both (either 8th or 9th) is sent, also in the middle of the bit
TI and RI are cleared when SP_STAT is read. The RI time. The flags clear when SP_STAT is read, but do
and TI status bits cap. be set by writing to SP_STAT in not have to be clear for the port to receive or transmit.
HWindow 15 but they will not cause an interrupt. The serial port interrupt bit is set as a logical OR of the
Reading of SP_CON in HWindow 15 will read the RI and TI bits. Note that changing modes will reset the
last value written. Whenever the TXD pin is used for Serial Port and abort any transmission or reception in
the serial port it must be enabled by setting IOC1.5 to a progress on the channel.
1. lOCI register 1 can be read in HWindow 15 to deter-
mine the setting.
DETERMINING BAUD RATES

STARTING TRANSMISSIONS AND RECEPTIONS Baud rates in all modes are determined by the contents
of a 8-bit register at location OOOEH. Reading or writ-
In Mode 0, if REN = 0, writing to SBUF (TX) will ing this register in HWindow 15 is reserved by Intel for
start a transmission. A rising edge on REN, or clearing future use. This register must be loaded sequentially
RI with REN = I, will start a reception. Setting with 2 bytes (least significant byte first). The MSB of
REN = 0 will stop a reception in progress and inhibit this register selects one of two sources for the input
further receptions. To avoid a partial reception, REN frequency to the baud rate generator. If it is a I, the
must be set to zero before RI is cleared. This can be XTALl pin is selected, if not, the T2CLK pin is used.
handled in an interrupt environment by using software The maximum input frequency is 4 MHz on T2CLK.
flags or in straight-line code by using the Interrupt
Pending register to signal the completion of a reception.

5-57
 80C196KC USER'S GUIDE

This provides the needed synchronization to the inter- 8096BH shared the TI and RI interrupts on the SERI-
nal serial port clocks. AL interrupt vector. On the 80CI96KC, these inter-
rupts share both the serial interrupt vector and have
The unsigned integer represented by the lower 15 bits 'their own interrupt vectors. Because the interrupts now
of the baud rate register defines a number B, where B have separate vectors, you do not have to sort the inter-
has a maximum value of 32767. The baud rate equa- rupts out in the same interrupt service routine.
tions are shown below.
When the TI bit is set it can cause an interrupt through
Asynchronous Modes 1, 2 and 3: the vectors at locations 200CH or 2030H. Interrupt
through location 2030H is determined by INT_
BAUD REG = XTAL1 -10R T2CLK MASKl.O. Interrupts through the Serial interrupt are
- Baud Rate' 16 - Baud Rate' 8 controlled by the sarrie bit as the RI interrupt (IN'I:_
MASK.6).
Synchronous Mode 0:

BAUD REG = XTAL1 -10R T2CLK 11.3 Serial Port Modes

- Baud Rate' 2 Baud Rate
MODE 0
Note that B cannot equal 0, except when using XTALI
and not in mode O. Mode 0 is a synchronous mode and is commonly used
for shift register based I/O expansion. In this mode the
Common baud rate values, using XTALI at 16 MHz, TXD pin outputs a set of 8 pulses while the RXD pin
are shown below. either transmits or receives data. Data is transferred 8
bits at a time with the LSB first. A diagram of the
Baud Baud Register Value relative timing of these signals is shown in Figure 11-2.
This is the only mode which uses RXD as an output.
Rate Mode 0 Others
9600 8340H 8067H Mode 0 Timings
4800 8682H 80CFH
2400 8D04H 81AOH In Mode 0, the TXD pin sends out a clock train, while
1200 9AOAH 8340H the RXD pin transmits or receives the data. Figure
300 E82BH 8D04H 11-2 shows the waveforms and timing.

In this mode the serial port expands the I/O capability

The maximum baud rates are 4.0 Mbaud synchronous of the 80CI96KC by simply adding shift registers. A
and 1.0 Mbaud asynchronous with 16 MHz on schematic of a typical circuit is shown in Figure 11-3.
XTAL1. This circuit inverts the data coming in, so it must be
reinverted in software.

11.2 Serial Port Interrupts

MODE 1
The serial port generates one of three possible inter-
rupts: Transmit Interrupt TI(2030H), Receive Inter- Mode 1 is the standard asynchronous communications
rupt RI(2032H) and SERIAL(200cH). When the RI mode. The data frame used in this mode is shown in
bit gets set an interrupt is generated through either Figure 11-4. It consists of 10 bits; a start bit (0), 8 data
20DCH or 2032H depending on which interrupt is en- bits (LSB first), and a stop bit (1). If parity is enabled
abled. INT_MASKl.l controls the serial port receive by setting SPCON.2, an even parity bit is sent instead
interrupt through location 2032H and INT_MASK.6 of the 8th data bit and parity is checked on reception.-
controls the RI interrupt through location 2ODCH. Th~

5-58 '
inter 80C196KC USER'S GUIDE

TXD

AXD(OUT) -< DO I D1 I D2 I D3 I D4 I D5 I De I D7 }--

DO D1 D2 D3 D4 D5 De D7
AXD(IN)

EXPANDED:

TXD ~~I--

RXD(OUT) DO x::: D1 C: D2

DO D1
RXD (IN) ---c:J----I,I----IDI---;/F#-I--
270704-27

Figure 11·2. Serial Port Mode 0 Timing

CLOCK INHIBIl
~ ____________ ________-;PX.
~

15K
DATA
)o~~--~---------;AXD

CLOCK
L-____~--____~--__'TXD

INPUTS

80C196KC
SERIAL IN A

ENABLE
11>-----1 PX.X

270704-28

Figure 11·3. I/O Expansion in Mode 0

5·59
intJ 80C196KC USER'S GUIDE

STOP

270704-29

270704-30

Figure 11-4. Mode 1, 2, and 3 Timing

The transmit and receive functions' are controlled by MODE 3

separate shift clocks. The transmit shift clock starts
when the baud rate generator is initialized, the receive Mode 3 is the asynchronous 9th bit mode. The data
shift clock is reset when a 'I to 0' transition (start bit) is frame for this mode is identical to that of Mode 2. The
received. The transmit clock may therefore not be in transmission differences between Mode 3 and Mode 2
sync with the receive clock, although they will both be are that parity can be enabled (PEN = I) and cause the
at the same frequency. 9th data bit to take the even parity value. The TB8 bit
can still be used if parity is not enabled (PEN = 0).
·The TI (Transmit Interrupt) and RI (Receive Inter- When in Mode 3, a reception always causes an inter-
rupt) flags are set to indicate when operations are com- rupt, regardless of the state of the 9th bit. The 9th bit is
plete. TI is set when the last data bit of the m<;ssage has stored if PEN = 0 and can be read in bit RB8. If
been sent" not when the stop bit is sent. If an attempt to PEN = I then RB8 becomes the Receive Parity Error
send another byte is made before the stop bit is sent the (RPE) flag.
port will hold off transmission until the stop bit is com-
plete. RI is set when 8 data bits are received, not when
the stop bit is reCeived. Note that when the serial port 11.4 Multiprocessor Communications
status register is read both TI and RI are cleared.
Mode 2 and 3 are provided for multiprocessor commu-
Caution should be used when using the serial 'port' to nications. In Mode 2 if the received 9th data bit is zero,
connect more than two devices in half-duplex, (i.e. one the RI bit is not set, and will not cause an interrupt. In
wire for transmit and receive). If the receiving proces- Mode 3, the RI bit is set and always causes an interrupt
sor does not wait for one bit time after RI is set before regardless of the value in the 9th bit. The way to use
starting to transmit, the stop bit on the link could be this feature in multiprocessor systems is described be-
corrupted. This could cause a problem for other devices low.
listening on the link.
The master processor is set to Mode 3 so it always gets
interrupts from serial receptions. The slaves are set in
MODE 2 Mode 2 S0 they only have receive interrupts if the 9th
bit is set. Two types of frames are used: address frames
Mode 2 is the asynchronous 9th bit recognition mode.
which have the 9th bit set and data frames which have
This mode is commonly used with Mode 3 for multi" the 9th bit cleared. When the master processor wants to
processor communications. Figure 11-4 shows the data
transmit a block of data to one of several slaves, it first
frame used in this mode. It consists of a start bit (0),_ 9 sends out an address frame which identifies the target
data bits (LSB first), and a stop bit (I). When transmit- slave. Each slave can examine the received byte and see
ting, the 9th bit can be set to a one by setting the TB8
if it is being addressed. The addressed slave switches to
bit in the control register before writing to SBUF (TX). ) Mode 3 to receive the coming data frames, while the
The TB8 bit is cleared on every transmission. During
slaves that were not addressed stllY in Mode 2 continue
reception, the serial port interrupt and the Receive In- executing.
terrupt will not happen unless the 9th bit being received
is set. This provides an easy way to have selective recep-
tion on a data link. Parity cannot be enabled in this
mode.

5-60
 80C196KC USER'S GUIDE

12.0 AID CONVERTER for a shorter conversion time. A significant improve-

ment to the AID Converter is the Sample Window and
Analog Inputs to the 80Cl96KC System are handled the Conversion time are programmable in state times.
by the AID converter System. As shown in Figure
12-1, the converter system has an 8 channel multiplex- Conversions are started by loading the AD_COM-
er, a sample-and-hold, and a 10-bit successive approxi- MAND with the channel number, and whether an 8- or
mation AID converter. Conversions can be performed to-bit conversion is performed, as shown in Figure
on one of eight channels, the inputs of which share pins 12-2. The conversion can be started immediately by set-
,with port O. ting the GO bit to a 1. If the GO bit is set to 0, the
conversion will start when triggered by the HSO. The
The AID converter on the 80C196KC has many im- reSult and status of the conversion is read in the AD_
provements over the 8OC196KB converter. The con- RESULT (High) and AD_RESULT (Low) registers,
verter can perform either 8- or 10-bit conv,ersions. By as shown in Figure 12-3. The AD_RESULT register
perfotn;ling an 8-bit conversion, resolution is traded off can be accessed as a byte or word.

VREF

8 TO 1
ANALOG
MULTIPLEXER

START
CONVERSION
HSO COMMAND "F"
270704-33

Figure 12·1. AID Converter Block Diagram

5-61
 80C196KC USER'S GUIDE

7 0

I....R_SV...' I.....R_SV......' I_R_Sv....I_IMO,..DE..

, I..,' # 1..-......102H
G°r--'--I--'-C.,.H.....

I AID CHANNEL

1 STA,RT NOW
o STARTED BY HSO

o 10-BIT CONVERSION
1 8-BIT CONVERSION
270704-81

Figure 12-2. AID_COMMAND Register

15 8 6 3 o
~1__~~__..L-_M~S~BS__L-~__","-_,~I__L~S~BS__~IR_S_v.IM_O_OE.:I_S~T~1__~C~~_#L-~I02H

" AlOIN USE

o "AI D IDLE
LEAST SIGNIFICANT 2 BITS
OF CONVERSION

MOST SIGNIFICANT 8 BITS

OF CONVERSION
270704-82

Figure 12-3. AID_RESULT Register

5·62
 80C196KC USER'S GUIDE

Programmable Sample and Convert Times Because the 8OCl96KC can run from 3.5 MHz to
16 MHz, it is difficult to optimize both the Sample and
There are two parameters,that define the time an AID Convert times using only the fast and normal conver-
conversion will take; the Saplple Time plus the Convert sion modes on the 8OC196KB. Therefore, an
time. The Sample time is the time the analog input AD_TIME register in HWINDOW 1 was added so
channel. is actually connected to the Sample Capacitor. both the Sample and Convert times could be pro-
If this time is too short, the Sample capacitor will not grammed in number of state times. The fast and normal
charge properly. If the Sample time is too long, the conversions are still present to remain compatib~e with
input may change and errors, occur. The Convert time the 8OC196KB. Figure 12-5 shows the AD_TIME
is defined to be the length of time to convert one bit of register and the equations for calculating the number of
the analog voltage on the Sample Capacitor to a digital state times for an AID conversion. IOC2 is shown in
value. The Convert- time has to be long enough for the Figure 12-6 which enables the different conversion
comparator to settle and resolve the voltage, but short times.
enough so the Sample Capacitor will not discharge and
lose resolution.

7 o

270704-84

For 8 and 10 Bit Conversions T = 4 • SAM + B • (CONY + 1) + 2.5

T = Number of States Times
B = Number of Bits (8 or 10)

80C196KB Compatible Mode TImes

Prescalar On 156.5 States
Prescalar Off 89.5 States

Figure 12·5. AD_TIME Register

5-63
 80C196KC USER'S GUIDE

The AID...:-TIME register only prognup.s the speed the control logic. If an H~O command was used, ,the con-
AID can,run, NOT the speed it pan convert correctly. version will begin when Timerl increments. This aids
The 80CI96KC data sheet will contain the correct val- applications' attempting, to approach spectrally pure
ues for the Sample and Convert times in microseconds. sampling, since successive, samples spaced by _equal
Timerl delays will occur with 'a variance of about ± 50
ns (assuming a stable cl0Ck on XTALl). However, con-
Restrictions on the AID Converter versions initiated by writing a one to the ADCoN reg-
I. ,Fo~ an AID conversion, initiali~e the' AID registers ister GO Bit will start within three state times after the
in the following order; AD_TIME, IOC2, and instruction has completed execution resulting in a vari-
AD_COMMAND. ance of about 0.38 ,..,s,(XTALI = 16 MHz).
2. Do 'not start a conversion using the AD_TIME reg-
ister when Ii conversion using a 80CI96KB compati- To perform the actual analog-to-digital conversion the
ble mode is in progress (and VICE-VERSA). 8OC196KC implements a sucoessive approximation al-
3. Never write zero to the AD_TIME register. gorithm. The converter hlll'dware consists of a 256-ro-
sistor ladder, a comparator, coupling capacitors and Ii
10-bit successive approximation register (SAR) with
logic that guides the process. The resistor ladder pro-
12.1 AID Conversion Process vides 20 mV steps (VREF = 5.12V), while capacitive
The conversion process is initiated by the exe~ution of coupling creates 5 mV steps within the 20 mV ladder
HSO command OFH, or by writing a one to the GO Bit voltages. Therefore, 1024 internal reference voltages are
in the AID Control Register. Either activity causes a available for comparison against the analog input to
start conversion signal to be sent to the AID converter generate a to-bit conversion result. For an 8-bit conver·
sion, there are 256 levels.

7 o
: AID SE<
~~'---'---r-l-.a....-.a....-.a....--, 10C2
I

00 = 80C196KB SLOW MODE

---------.~ ,10 = 80C196KB FAST MODE
Xl = AD_TIME ENABLED 270704-85

Figure 12-6., IOC2

5-64
inter 80C196KC USER'S GUIDE

A successive approximation conversion is performed by may degrade converter accurliCY as a result of the inter-
comparing a sequence of reference voltages, to the ana- nal sample capacitor not being fully charged during the
log input, in a binary search for the reference voltage sample window.
that most closely matches the input. The 1/. full scale
reference voltage is the first tested. This corresponds to If large source impedances degrade converter accuracy
a lO-bit result where the most significant bit is zero, because the sample capacitor is not charged during the
and 'all other bits are ones (0111.1111.1lb). If the ana- sample time, an external capacitor connected to the pin
log input was less than the test voltage, bit 10 of the compensates for this degradation. Since the sample ca-
SAR is left a zero, and a new test voltage of '/. full scale pacitor is 2 pF, a 0.005 J.l-F capacitor will charge the
(00 11.1111.11 b) is tried. If this test voltage was lower sample capacitor to an aecurate input voltage of
than the analog input, bit 9 of the SAR is set and bit 8 ±0.5LSB (2048 * 2 pF). An external capacitor does not
is cleared for the next test (0101.l111.1,lb). This binary compensate for the voltage drop across the source re-
searchcontiilUes until 10 or 8 tests have occurred, at' sistance, but charges the sample capacitor fully during
which time the valid 100bit or 8-bit conversion result the sample time.
resides in the SAR where it can be read by software.
Placing an external capacitor on each analog input will
also reduce the sensitivity to noise, as the capacitor
12.2 AID Interface Suggestions combines with series resistance in the external circuit to
form a low-pass filter. In practice, one should include a
The external interface circuitry to an analog input is small series resistance pridr to the external capacitor on
highly dependent upon the application, and can impact the analog input pin and choose the largest capacitor
converter characteristics. In the external circuit's de- value practical, given the frequency of the signal being
sign, important factors such as input pin leakage, sam- converted. This provides a low-pass filter on the input,
ple capacitor size and multiplexer series resistance from while the resistor will also limit input current during
the input pin to the sample capacitor must be consid- over-voltage conditi0!ls.
ered. The following calculation assumes a 1 ,..,S Sample
Window. Figure 12-S shows a simple analog interface circuit
based upon the discussion above. The circuit in the fig- '
For the 80C196KC, these factors are idealized in Fig- ure also provides limited protection against over-volt-
ure 12-7. The external input circuit must be able to age conditions on the analog input. Should the input
charge a sample capacitor (Cs) through a series resist- voltage inappropriately drop significantly below •
ance (RI) to an accurate voltage given a D.C. leakage ground, diode D2 will forward bias at about O.S DCY:
(IL). On the SOC 196KC, Cs is around 2 pF, RI is This will limit the current sourced by the input pin to
around ± 5 KO and IL is specified as 3 ,..,A maximum. an acceptable amount. However, before any circuit is
In determining the necessary source impedance Rs, the used in an actual application, it should~ be thoroughly
value of YBIAS is not important. \ analyzed for applicability to the specific problem at
hand.

VREF

01
ANALOG
FROM USER CIRCUIT>--4...--j,JV'v-..... -a INPUT PIN
02

270704-34
ANGNO
Figure 12-7. Idealized AID Sampling Circuitry 270704-35 '

External circuits with source impedances of 1 KO or Figure 12-8. Suggested AID Input Circuit
less will be able to maintain an input voltage within a
tolerance of about ±0.61 LSB (1.0 KO X 3.0 ,..,A=
3.0 mY) given the D.C. leakage. So~rce impedances
above 2 KO can result in an external error of at least
one LSB due to the voltage drop caused by the 3 ,..,A
leakage. In addition, source impedances above 25 KO

5-65
 80C196.KC USER'S GUIDE

ANAlOG REFERENCES An. unavoidable error simply results from the conver-
sion of a continuous voltage to an integer digital repre-
Reference supply levels strongly influence the absolute sentation. This error is called quantizing error, and is
accuracy of the conversion. Bypass capacitors should always :to.5 LSB. Quantizing error is the only error
be used between VREF and ANGND. ANGND should seen in a perfect AID converter, and is. obviously pres-
be wjthin abo.llt a tenth of a volt of Vss. VREF should ent in actual converters. Figme 12-9 shows the transfer
be well reMted and used only for the AID converter. fUllction for an ideal 3-bit AID converter (i.e. the Ideal
The VREP supply can be between 4.5V.and 5.5V and Characteristic).
needs to. be able to source around 5 rnA. See Section 13
for the minimum hardware connections. Note that in Figure 12-9 the Ideal Characteristic pos-
sesses unique qualities: .it's first code transition occurs
Note that·if only ratiometric information is desired, wb.en the input voltage is 0.5 LSB; it's full-scale code
VREF can be connected to Vee. In addition, VREP and . transition occurs when the input voltage equals the full-
ANGND must be connected even if the AID converter scale reference minus 1.5 LSB; and it's code widths are
is not being used. Remember that Port 0 receives its all exactly one LSB. These qualities result in a digitiza-
power from the VREP and ANGND pins even when it tion without offset, full-scale or linearity errors. In oth-
is used as digital I/O. er words, a perfect conversion.

Figure 12-10 shows an Actual Characteristic of a hypo-

12.3 The AID Transfer Function thetical 3-bit converter, which is not perfect. When the
Ideal Characteristic is overlaid 'with the imperfect char-
The conversion result is .a 'lO-bit ratiometric representa- acteristic, the actual converter is seen to exhibit errors
tion of the input voltage, so the numerical value ob- in the location of the first and final code transitions and
tained from the conversion will be: code widths. The deviation of the first code transition
from ideal is called "zero offset", and the 'deviation of
INT [1023 x (VIN - ANGND)/(VREF - ANGNP)I. the final code transition from ideal is "full-scale error".
The deviation of the code widths from ideal causes two
This produces a stair-stepped, transfer function when types of errors. Differential Non-Linearity and Non-
the output code is plotted versus input voltage (see Fig- Linearity. Differential Non-Linearity is a local linearity
ure 12-9). The resulting digital codes can t>e taken as error measurement, whereas Non-Linearity is an over-
simple ratio~etric information, or they provide infor- all linearity error measqre. '
.mation . about absolute voltages or relative voltage
changes on the inp~ts. The more demanding the appli- Differential Non-Linearity is the degree to which actual
cation is on the AID converter, the more important i~ code widths differ from the ideal .one LSB width. It
is to fully underst8lld the converter's operation .. For gives the \lser a measure of how much the input voltage
simple applications, knowing the absolute error of the may' h~ve changed in order to produce a one count
converter is sufficient. However, closing a servo-loop change in the conversion result. Non-Linearity is the
with analog inputs necessitates a detailed understand- worst case deviation of code transitions from the corre-
ing of an AID converter's operation and errors. sponding code transitions of the Ideal Characteristic.
Non-Linearity describes how much Differential Non-
The errors inherent in an analog-to-digital conversion Linearities could add up to produce an overall maxi-
process are many: quantizing error, zero offset, full- munl departure from a linear characteristic. If the
scale error, differential non~finearity, and non-linearity. Differential Non-Linearity errors are too large, it is
These are "transfer function" errors related to the AID possible for an AID converter to miss codes or exhibit
converter. In addition, converter temperature drift, non-monotonicity. Neither behavior is desirable ina
Vee rejection, sample-hold feedthrough, multiplexer closed-loop system. A converter has no missed codes if
off-isolation, channel-to-channel matching and random there exists for each output code a unique input voltage
noise should be considered. Fortunately, one "Absolute range that produces that code only. A converter is
Error" specification is available which describeS the monotonic if every subsequent code change represents
sum total of all deviations between the actual conver- an input'voltage change in the same direction.
sion process and an ideal converter. However, the vari- I

ous sub-components of error are important in many Differential Non-Linearity anll Non-Linearity are
applications. These error components are described in quantified. by m!l8suring the Terminai.Based Linearity
Section 12.5 and in the text below where ideal and actu- Errors. A Terminal Based Characteristic results when
al converters are compared. . an Actual Characteristic is shifted and rotated to elimi-
nate zero offset and full-scale error (see Figure·12-11).
'The Terminal Based Characteristic is similat to the Ac-

5-66
 80C196KC USER'S GUIDE

I FINAL CODE TRANSITION OCCURS 1

WHEN THE APPLIED VOLTAGE IS
EQUAL TO (Vre! - 1 1/2 (LSB». 1
1---_.
6

I ACTUAL CHARACTERISTIC OF"

AN IDEAL A/D CONVERTER
I
4

a
3
~ THE VOLTAGE CHANGE
BETWEEN ADJACENT CODE
TRANSITIONS (THE "CODE
WIDTH") IS = 1 LSB.

j FIRST CODE TRANSITION OCCURS

....-----1 WHEN THE APPLIED VOLTAGE IS
I
1 EQUAL TO 1/2 LSB.

O~---L---.----~---.---------r--------~--------r---~----r----r---'---------.
1/2 2 3 4 5 6 61/2 7 B

INPUT VOLTAGE (LSBs)

270704-36

Figure 12-9. Ideal AID C;:haracteristic

tual Characteristic that would be seen if zero offset and Undesired signals come from three main sources. First,
full-scale error were externally trimmed away. In prac- noise on Vee-Vee Rejection. Second, input signal
tice, this is done by using input circuits which include changes on the channel being converted after the sam-
gain and offset triJhming. In addition, VREF on the ple window has closed-Feedthrough. Third, signals •
80C196KC could also be closely regulated and applied to channels not selected by the multiplexer-
trimmed within the specified range to affect full-scale Off-Isolation.
error.
Finally, multiplexer on-channel resistances differ slight-
Other factors that affect a real A/D Converter system ly from one channel to the next causing Channel-to-
include sensitivity to temperature, failure to completely Channel Matching errors, and random noise in general
reject all un~anted signals, multiplexer channel dissim- results in Repeatability errors.
ilarities and random noise. Fortunately these effects are
small.

Temperature sensitivities are described by the rate at

which typical specifications change with a change in
, temperature.

5-67
 7

- --{!U~ ;~~lE ERROR ,I

l
.6 IDEAL
CHARACTERISTIC

5 ABSOLUTE ERROR
~
C
ACTUAL
~
..... CHARACTERISTIC
co
~
.....
? .4
8....

'f
-
~
c
!t
III
:::J
o
CD
0')

"~
(")

(l)
CO
Q.
3
rn
ii ::D
CD (I)
!t G)
0 c:
~
...
III
6
rn
~ 2
;-
:l-
In
~
In

.-4 H ZERO OFFSET I

o I I I I I 1 i i ' i
1/2 2 3 4 5 6 61/2 7 8

INPUT VOLTAGE (lSBs)

270704-37
 7
IDEAL FULL-SCALE CODE
TRANSITION
ACTUAL
(
FULL-SCALE CODE
TRANSITION
6

ACTUAL
5 CHARACTERISTIC
"'1'1
c·
c TERMINAL BASED
...
GJ CHARACTERISTIC
~
......
~
4
o....
';;}
3
Q ....~
o
<f -~ c:
O'l
co m ~
:
Q.
(')
3

NON-LiNEARllY
l:I
u)
G)
::r c:
I»
ji; 6
m
~
:::!.
2

g.
!DEAL CODE WIDTH

ACTUAL FIRST TRANSITION

IDEAL FIRST TRANSITION

oK
1/2 2 3 4 5 6 61/2 7 B

INPUT VOLTAGE(LSBs) 270704-38

 80C196KC USER'S GUIDI:

12~4 AID Glossary of Term$ FULL SCALE ERROR-The difference betwee~ the
expected and actual input voltage corresponding to the
Figures 12-9. 12-10. and 12-11 display many of these full scale code· transition.
terms. Refer to AP-406 'MCS-96 Analog Acquisition
Primer' for additional information on the AID terms. IDEAL CHARACfERISTIC-A characteristic with
its first code transition at VIN = 0.5 LSB. its last code
ABSOLUTE ERR9R-The maximum difference be- transition at VIN = (VREF - 1.5 LSB) and all code
tween corresponding actual and ideal code transitions. widths equal to one LSB,
Absolute Error accounts for all deviations of an actual '
converter from an ideal converter. INPUT RESISTANCE-The effective series resistance
from the analog input pin to the sample capacitor~ ,
ACfUAL CHARACfERISTIC-The characteristic of
an actual converter. The characteristic of a given con- LSD-LEAST SIGNIFICANT BIT: The voltage value
verter may vary over temperature. supply voltage. and corresponding to the full scale voltage divided by 2n.
frequency conditions. An Actual Characteristic rarely where n is the number of bits of resolution of the con·,
has ideal first and last transition locations or ideal code verter. For a lO-bit converter with a reference voltage
widths. It may even vary over multiple conversion un- of 5.12 volts. one LSB is S.OmV. For an 8-bit conver·
der the same conditions. sion. one LSB equals 20 mY. Note that this is different
than digital LSBs.
BREAK-BEFORE-MAKE-The property of a multi-
plexer which guarantees that a previously selected MONOTONIC-The property of successive approxi-
channel will be deselected before a new channel is se- mation converters which guarantees that increasing in-
lected. (e.g. the converter will not short inputs put voltages produce adjacent codes of increasing value.
together.) and that decreasing input voltages produce adjacent
codes of decreasing value.
CHANNEL-TO-CHANNEL MATCHING-The dif-
ference between corresponding code transitions of actu- NO MISSED CODES-For each and every output
al characteristics taken from different channels under code. there exists a unique input voltage range which
the same temperature, voltage and frequency condi- produces that cod~ only.
tions.·
NON-UNEARITY-The maximum deviation of code
CHARACfERISTIC-A graph. of input voltage ver- transitions of the terminal based characteristic from the
sus the resultant output code for an AID converter. It corresponding code transitions of the ideal characteris-
describes the transfer function of the AID converter. tics. '

CODE-The digital value output by the converter. . OFF-ISOLATION-Attenuation of a voltage applied

on a deselected channel of the AID converter. (Also
CODE CENTER-The voltage corresponding to the referred to as Crosstalk.)
midpoint between two adjacent code transitions.
REPEATABIUTY-The difference between corre-
CODE TRANSITION-The 'point at which the con- sponding code transitions from different actual charac-
. verter changes from an output code of Q. to a code of teristics taken from the same converter on the same
Q+ 1. The input voltage corresponding to a: cQde tran- channel at the same temperature. voltage and frequency
sition is defined to be tha,t voltage which is equally like- conditions.
ly to produce either of two adjacent codes.
RESOLUTION-The number of input voltage levels
CODE WIDTH-The voltage corresponding to the that the converter can unambiguously distinguish be-
difference between two adjacent code transitions. tween. Also defines the number of useful bits of infor-
mation which the converter can return.
CROSSTALK-See "Off-Isolation".
SAMPLE DELAY-The delay from receiving the start
D.C. INPUT LEAKAGE-Leakage current to ground conversion signal to when the sample window ope!1s.
from an analog input pin.
SAMPLE DELAY UNCERTAINTY-The variation
DIFFERENTIAL NON-UNEARITY-The differ- in the Sample Delay.
ence between the ideal an,d actual code widths of 'the
terminal based characteristic of a converter. SAMPLE TIME-The time that the sample window is
open.
FEI<;DTHROUGH-Attenuation of a voltage applied
on the selected channel of the AID ,converter after the
sample window closes.
5·70
inter 80C196KC USER'S GUIDE

SAMPLE TIME UNCERTAINTY-The variation in While discussing the characteristics of the 1/0 pins
the sample time. some approximate current or voltage specifications will
be given. The exact specifications are. available in the
SAMPLE WINDOW-Begins when the sample capac- latest version of the data sheet that corresponds to the
itor is attached to a selected channel and ends when the device being used.
sample capacitor is disconnepted from the selected
channel. ALTERNATE CONTROL
PI!!! FUNC.
FUNCTION REG.
SUCCESSIVE APPROXIMATION-An AID con-
version method which uses a binary search to arrive at 2.0 Output TXO (Serial Port Transmit) IOC1.5
the best digital representation of an analog input. 2.1 Input RXO (Serial Port Receive) SPCON.3
TEMPERATURE COEFFICIENTS-Chang~ in the 2.2 Input Extint IOC1.1
stated, variable per degree centigrade temperature
change. Temperature coefficients are added to the typi- 2.3 Input' T2CI,..K (Timer2 Clock & Baud) IOC9· 7
cal values of a specification to see the effect of tempera- 2.4 Input T2RST (Timer2 Reset) , IOCO.5
ture drift. '
2.5 Output PWMOutput IOC1.0
TERMINAL BASED CHARACTERISTIC-An Ac- 2.6 OBO· Timer2 up/down select IOC2.1
tual Characteristic which as been rotated and translat-
ed to remove zero offset and full-scale error. 2.7 OBO· Timer2 Capture N/A
·OBD =
..
QuaSI-bidirectional
Vee REJECTION-Attenuation of naise on the Vee Figure 13·1. Port 2 Multiple Functions
line to the AID converter.

ZERO OFFSET-The difference between the expected 13.1 Input Ports

and actual input voltage corresponding to the first code
transition. Input ports and pins can only be read. There are no
output drivers on these pins. The input leakage of these
pins is in the microamp range. The specific values can
13.0 1/0 PORTS be found in the data sheet for the device being consid-
ered. Figure 13-2 shows the input port structures.
There are five 8Cbit 1/0 ports on the 80C196KC. Some
of these ports are input only, some are output only, In addition to acting as a digital input, each line of Port
some are bidirectional and some have alternate func- o can be selected to be the input of the AID converter
tions. In addition to these ports, the HSI/O unit pro- as discussed in Section 12. The capacitance on these
vides extra I/O lines if the timer related features of pins is approximately 1 pF and will instantaneously in-
these lines are not needed. crease by around 2 pF when the pin is being sampled by
the AID converter.
Port 0 is an input port which is also used as the analog
input for the AID converter. Port 0 is read at location Port 0 pins are special in that they may individually be
OEH. Port 1 is a quasi-bidirectional port and is read or used as digital inputs and analog inputs at the same
written to through location OFH. The 3 Most Signifi- time. A Port 0 pin being used as a digital input acts as
cant bits of Port 1 are multiplexed with the control the high impedance input ports just described. Howev-
signals for the HOLD/HLDA bus. Port pins 1.3 and er, Port 0 pins being used as analog inputs are required
1.4 are multiplexed with the 2 extra PWM outputs. to provide current to the internal sample capacitor
Port 2 contains three types of port lines: quasi-bidirec- when a conversion begins. This means the input charac-
tional,input and output. Port2 is read or written from teristics of a pin will change if a conversion is being
location lOH. The ports cannot be read or written in done on that pin. VREF and ANGND must always be
HWindow 15. The input and output lines are shared connected for Port 0 to function.
with other functions in the 80C196KC as shown in Fig-
ure 13-1. Ports 3 and 4 are open.drain bidirectional Port 0 is only sampled when the SFR is read to reduce
ports which share their pins with the addressldata bus. the noise in the AID converter. The data must be stable
On EPROM and ROM parts, Port 3 and 4 are'read and one state time before the SFR is read. '
written through location lFFEH. < •

5.-71
 80C196KC USER'S GUIDE

13.2 Quasi-Bidirectional Ports Quasi-bidirectional pins can be' used as input and out~
put pins without the need for a data direction register.
Port 1 and Port 2 have quasi-bidirectional 1/0 pins. They output a strong low value and a' weak. high value.
When used as inputs the data on these pins must be The weak high value can be externally pulled low pro-
stable one state time prior to reading the 'SFR. This , viding an input.function. Figure 13.-3 shows the config-
timing is also valid for the input-only pins o(Port 2 and uration of a CHMOS q\lasi-bidirectional port.
is similar to the HSI in that the sample occurs during
'PHI '0,{ during CLKOUT low. When used as outputs,
the quasi-bidirectional pins will change state shortly af-
ter CLKOUT 'falls. If the change was from '0' td a 'I'
the low impedance pullup will remain on for one state
time after the change. '

Port I, Port 2.6 and Port 2.7,are quasi-bidirectional

ports. When the processor writes to the pins of a quasi-,
bidirectional port it actually writes into a register 'which
in turn drives the port pin. When the processor reads
these ports, it reads the pin direct~y. If a port pin is to
be used as an input then the software should write a one
to its associated SFR bit, which will tum the low-im-
pedance pull-down device off and leave the pin pulled BUS
up with a high impedance pullup device. This device
can be easily driven down by the device driving the
input.

If some pins of a port are to be used as inputs and some

are to be used as outputs the programmer should be SAMPLE
27070,\-86
careful when writing to the port.
NOTE:
Particular care should be exercised when using read- , *01 and 02 are ESD Protection Devices
modify-write instruction. It is possible for a Quasi-Bidi-
rectional Pin to be written as a one, but read back as a Figure 13-2., Input Port Structure
zero if an external device (i.e., a transistor base) is pull-
ing the pin below VIR.

Vee vee

o
rROMPORT~~~----~~------~------~~~~
LATCH,

INPUT ~"1------c.~ 1-...-6-~~

DATA
READC>-__......
PORT PIN
, " 270704-39
CHMOS Configuration. pFET 1 is turned on for 2 'osc. periods after Q makes a' O-to-l transition. During th,is time, pFET 1
also turns on pFET 3 through the inverter to form a latch which holds the 1. pFET 2 is alsq on. '

Figure 13-3. CHMOS Quasi-Bidirectional Port Circuit

5-72
 80C196KC USER'S GUIDE

Outputting a 0 on a quasi-bidirectional pin turns on the ecutes. The first is that even though Pl.l is being driv~
strong pull-down and turns otT all of the pull-ups. en high by the 80CI96KC it is possible that it is being
When a I is output the pull-down is turned otT and 3 held low externally. This typically happens when the
pull-ups (strong-PI, weak-P3, very weak-P2) are turned port pin drives the base of an NPN transistor which in
on. Each·time a pin switches from 0 to I transistor PI turn drives whatever there is in the outside world which
turns on for two oscillator periods. ~2 remains on until needs to be toggled. The base of the transistor will
a zero is written to the pin. P3, is used as a latch, so it is clamp the port pin to the transistor's Vbe above
turned on whenever the pin is above the threshold.value ground, typically 0.7V. The 80CI96KC will input this
(around 2 volts). value as a zero even if a one has been written to the port
pin. When this happens the XORB instruction will al-
To reduce the amount of current which flows when the ways write a one to the port pin's SFR and the pin will
pin is externally pulled low, P3 is turned otT when the not toggle.
pin voltage drops below the threshold. The current re-
quired to pull the pin from a high to a low is at its The second problem, which is related to the first, is that
maximum just prior to the pull-up turning otT. An ex- if P1.0 happens to be driven to Ii zero when Port I is
ternal driver can switch these pins easily. The maxi- read by the XORB instruction, then the XORB will
mum current required occurs at the threshold voltage write a zero to P1.0 and it will no longer be useable as
and is approximately 700 microamps. an input. .

When the Port I pins are used as their alternate func- The first situation can best be solved by the external
tion, (HOLD, HLDA, BREQ, PWMs), the pins act like driver design. A series resistor between the port pin and
a standard output port. the base of the transistor often works by bringing up
the voltage present on the port pin. The second case can
be taken care of in the software fairly easily:
HARDWARE. CONNECTION HINTS

When using the quasi-bidirectional ports as inputs tied LDB AL, rOPORTl
to switches, series resistors may be needed if the ports XORB AL, #OlOB
will be written to internally after the part is initialized. ORB AL, #OOlB
The amount of current sourced to ground from each STB AL, rOPORTl
pin is typically 7 rnA or more. Therefore, if. all 8 pins
are tied to ground, 56 rnA will be sourced. This is A software solution to both cases is to keep a byte in
equivalent to instantaneously doubling the power used RAM as an image of the data to be output to the port;
any time the software wants to modify the data on the
by the chip and may cause noise in some applications.
port it can then modify the image byte and copy it to
This potential problem can be solved in hardware or the port.
software. In software, never write a zero to a pin being
If a switch is used on a long line connected to a quasi-
used as an input.
bidirectional pin, a pullup resistor is recommended to
In hardware, a IK resistor in series with each pin will reduce the possibility of noise glitches and to decrease
limit current to a reasonable value without impeding the rise .time of the line. On extremely long lines that
the ability to override the high imped~nce pullup. If all are handling slow signals, a capacitor may be helpful in
8 pins are tied together a 120n resistor would be rea- addition to the resistor to reduce noise.
sonable. The problem is not quite as severe when the
.inputs are tied to electronic devices instead of switches,
as most external pulldowns will not hold 20 rnA to 0.0 13.3 Output Ports
volts. Output pins include the bus control lines, the HSO
lines, and some of Port 2. These pins can only be used
Writing to a Quasi-Bidirectional Port with electronic as outputs as there are no input butTers connected to
devices attached to the pins requires special attention. them. The output pins are changed before the rising
Consider using P 1.0 as an input and trying to toggle edge of PHI and is valid some time during PH1. Exter-'
PI. I as an output: nally, PHI corresponds to CLKOUT low. It isnot pos-'
sible to use immediate logical instructions such as XOR
ORB rOPORT1, #OOOOOOOlB Set PLO to toggle these pins.
for input
XORB rOPORT1, #OOOOOOlOB Complement The control outputs and HSO pins have output butTers
Pl.l with the same output characteristics as those of the bus
pins. Included in the category of control outputs are:
The first instruction will work as expected but two TXD, RXD (in Mode 0), PWM, CLKOUT, ALE,
problems can occur when the second instruction ex- BHE, RD, and WR. The bus pins have 3 states: output

5-73
inter 80C196KC USER'S GUIDE

high,output low, and high impedance. 'Figure 13-4 To read Port 3 and 4 requires that "ones" be written to
shows. the internal configuration of an output pin. the port registers to first setup the input port configura-
tion circuit. Note that the ports are reset to this input
condition, but if zeroes have been written to the port,
13.4 Ports 3 and 41ADO-15 then ones must be re-written to any pins which are.to
be used as inputs. Reading Port 3 and 4 from a previ-
These pins have two functions. They are either bidirec- ously written zero condition is as follows ...
tion~l ports with open-drain outputs or System Bus
pins which the memory controller uses when it is ac- LD intregA,' #OFFFFH setup port
cessing off-chip memory. If the EA line is low, the pins change mode
always act as the System Bus. Otherwise they act as bus pattern
pins only during a memory access.
ST intregA, lFFEH register ~
Accessing Port 3 and 4 as 1/0 is easily done from inter- Port 3 and 4
nal registers. Since the LD and ST instructions require LD &: ST not
the use of internal registers, it may be necessary to first needed if
move the port information into an internal location be- previously
fore utilizing the data. If ·the data is already internal, written as ones
the LD is unnecessary. For instance, to write a word
value to P!lrt 3 and 4 ... LD intregB, lFFEH register~
Port 3 and 4 '
LD intreg, portdata register ~
data When acting as the system bus the pins have strong
not needed if drivers to both Vee and Vss. These drivers are used
already whenever data is being output on the system bus and
internal are not used when data is being output by Ports 3 and
4. The pins, external input buffers and pulldowns are
ST intreg, lFFEH register ~ shared between the bus. and the ports. The ports use
Port 3 and 4 different output buffers which are configured as open-
drain, and require external pullup resistors. (open-drain
is the MOS version of open-collector.) The port pins
and their system bus functions are shown in Figure
13-5. .

BUS

ALT.
F'UNCT. ---1"-----1

BUS PORT fCN SELECT RESET

270704-87

Figure 13-4. Output Port

5-74
inter 80C196KC USER'S GUIDE

BUS

ADDR _-4-_+-___-1
DATA

PIN---t---t---t--+------1K"'- 1 - - - - - - - - '
PORT BUS SAMPLE RESET
BUS PORT FCN SELECT
270704-40

Figure 13·5~ Port 3 and 4

Ports 3 and 4 on the 80C196KC are open drain ports. 14.1 Power Supply
A diagram of the output buffers cormected to Ports 3
and 4 and the bus pins is shown in Figure 13-5., Power to the 80C196KC flows through 6 pins. Vee
supplies the positive voltage to the digital portion of the
When Ports 3 and 4 are to be used as inputs, they must chip while VREF supplies the A/D converter and
first be written with a '1'. This will put the ports in a Port 0 with a positive voltage. These two pins need'to
high impedance mode. When they are used as outputs, be connected to a 5 volt power supply. When using the
a pullup resistor must be used externally. A 15K pullup A/D converter, it is desirable to connect VREF to a
resistor will source a maximum of 0.33 milliamps, so it separate power supply, or at least a separate trace to
would be a reasonable value to choose if no other cir- minimize the' noise in the A/D converter.
cuits with pullups were connected to the, pin,
The four common return pins, VSSl, VSS2, Vss3, and
Ports 3 and 4 are, addressed as off-chip memory- Angd, must all be nominally at 0 volts. Even if the
mapped I/O. The port pins will change state shortly A/D converter is not being used, VREF and Angd must
after the falling edge of CLKOUT. When these pins are still be connected for PortO to function.
used as Ports 3 and 4 they are open drains, their struc-
ture is different when they are used as part of the bus.
14.2 NOise Protection Tips
Port 3 and 4 can be reconstructed as I/O ports from the
Address/Data bus. Due to the fast rise and fall times of high speed CMOS
logic, noise glitches on the power supply lines and out-
puts at the chip are not uncommon, The 80C196KC is
14.0 MINIMUM HARDWARE no exception. So it is extremely important to follow
CONSIDERATIONS good design and board layout techniques to keep noise
to a minimum. Liberal use of deco\lpling· capacitors,
The 80C196KC requires several external connections to Vee and ground planes, and transient absorbers can all
operate correctly. Power and ground must be connect- be of great help. It is much easier to design a board
ed, a clock source must be generated, and a reset circuit with these features then to search for random noise on
must be present. We will look at each of these areas in a poorly designed PC board. For more information on
detail. noise, refer to Applications Note AP-125, 'Designing
Microcontroller Systems for Noisy Environments' in
the Embedded Control Application Handbook.

5-75
 80C196KC USER'S GUIDE

14.3 Oscillator and Internal Timings INTERNAL TIMINGS

Internal operation of the chip is based on the oscillator

ON-CHIP OSCILLATOR frequency divided by two, giving the basic time unit,
known as a 'state time'. With a 16 MHz crystal, a state
The on~chip oscillator circuitry for the SOCI96KC, as
time is 125 ns. Since the SOCI96KC can operate at
shown in Figure 14.1, consists of a crystal"controlled, many frequencies, the times given throughout this over-
positive reactance oscillator. In this application, the view will be in state times.
crystal is operated in its fundamental response mode as
an inductive reactance in parallel resonance with capac-
itance external to the crystal.
TO INTERNAL
CIRCUITS
Rf

.--------1--_ To Intemal
circuitry'
XTAL1 XTAL2
QUARTZ CRYSTAL---i==±'-I
Rf OR CERAMIC
RESONATOR

XTAL1

V-;s
270704-42

Figure 14-2. External Crystal Connections

To drive the SOCI96KC with an external clock source,

Vss
270704-41
apply the external clock signal to XTALl and let
XTAL2 float. An example of this circuit is shown in
Figure 14-1. On-chip Oscillator Circuitry Figure 14,-3. The required voltage levels on XTALI are
specified in the data sheet. The signal on XTALl must
The feedback resistor, Rf, consists of paralleled n-chan- be clean with good solid levels. .
nel' and p-channel FETs controlled by the PD (power-
down) bit. Rf acts as an open when in Powerdown It is important that the minimum high and low times
Mode. Both XTALl and XTAL2 also have ESD pro- are met to avoid having the XTALl pin in the tran-
tection on the pins which is not shown in, the figure. sition range for long periods of time. The longer the
signal is in the transition region, the higher the proba-
The crystal specifications and capacitance values in bility that an external noise glitch could be seen by the
Figure 14-2 are not critical. 20 pF is adequate for any clock generator circuitry. Noise ,glitches on the
frequency above 1 MHz with good quality crystals. Ce- SOCI96KC internal clock lines will cause unreliable op-
ramic resonators can be used instead of a crystal in cost eration.
sensitive applications. For ceramic resonators, the man-
ufacturer should be contacted for values of the capaci-
tors. DIVIDER CIRCUITRY
Vee
An external oscillator may encounter as much as a
100 pF load at XTALI when it starts-up. This is due to
interaction between the amplifier and its feedback ca-
pacitance. Once the external signal meets the VIL and
VIH specifications the capacitance will not exceed
20 pF.

XTAL2 XTAL2
rLOAT

270704-91

Figure 14-3. External Clock Drive

5-76
 80C196KC USER'S GUIDE

Two non-overlapping internal phases are created by the 14.4 Reset and Reset Status
clock generator: phase 1 and phase 2 as shown in Fig-
ure 14-4. CLKOUT is generated'by the rising edge of Reset starts the SOC196KC off in a known state. To
phase 1 and phase 2. This is not the same as the reset the chip, the RESET pin must be held low for at
8096BH, which uses a three phase clock. Changing least 16 state times after the power supply is within
from a three phase clock to aJwo phase speeds up oper- tolerance and the oscillator has stabilized. As soon as
ation for a set oscillator frequency. Consult the latest the RESET pin is hel,d low, the 1/0 and control pins
data sheet for AC timing specifications. are asynchronously driven to their reset condition.

After the RESET pin is brought high, state reset se-

quence occurs as shown in Figure 14-5. During this'
PHASE1~ time the CCB (Chip Configuration Byte) is read from
,
location 2018H and stored in the CCR (Chip Configu-
,,: r.--\. ration Register). The EA (External Access) pin quali-
PHASE 2 '-!----J : ~ fies whether the CCB is read from external or internal
, memory. Figure 14-6 gives the reset status of all the
, pins and Special Function Registers.
CLKOUT~
270704-43

Figure 14-4. Internal Clock Phases

80C196KC Reset Sequence

INTERNAL - - - ,_ _ _ _ _ _ _ _ _ _ __
RESET

RESET PIN ~m,....----------.,...--

CASE I
CLKOUT
CASE II
CLKOUT
ALE----I._____rL-
Rii ------..,ul"-------,L
AID BUS ------C>-Of-----cr
cca 201 BH 20BOH
270704-44

Figure 14-5. Reset Sequence

5-77
 80C196KC USER'S GUIDE

Pin Multi~lexed Value of the Register Name Value

Name Port Pins Pinon Reset AD_RESULT 7FFOH
RESET Mid-sized Pull up AD_TIME OFFH
ALE Weak Pullup HSI_STATUS xOxOxOx08
RD WeakPuliup S8UF(RX) .. OOH
8HE Weak Pullup INT_MASK 000000008
WR I WeakPuliup INT_PENDING 000000008
INST Weak Pulldo.wn TIMER1 OOOOH
EA Undefined Input • TIMER2 OOOOH
READY .Undefined Input • IOPORT1 111111118
NMI Undefined Input • IOPORT2 110000018
8USWIDTH Undefined Input • SP S1:AT/SP_CON 000010118
CLKOUT CLKOUT 1·IMASK1 000000008
System 8us PS.0-P4.7 Weak Pullups IPEND1 000000008
ACHO-7 PO.0-PO.7 Undefined Input • WSR XXXXOOO08
PORT1 P1.0-P1.7 Weak Pullups HSI_MODE 111111118
TXD P2.0 Semi-Weak Pullup IOC2 XOOOOOO08
RXD P2.1 Undefined Input • lOCO 000000X08
EXTINT P2.2 Undefined Input • IOC1 001000018
T2CLK P2.S Undefined Input • PWM_CONTROLS OOH
T2RST P2.4 Undefined Input • 10PORTS 111111118
PWM P2.5 Semi-Weak Pulldown IOPORT4 111111118
- P2.6-P2.7 Weak Pullups 10SO 000000008
HSI0-HSI1 Undefined Input' IOS1 000000008
HSI2/HS04 Undefined Input • IOS2 000000008
HSIS/HS05 Undefined Input • 10CS" 111100108
HSOO-HSOS Weak Pulldown
,
NOTES:
'These pins must be driven and not left floating.
"'Was previously called T2CONTROL or T2CNTC.

Figure 14-6. Chip Reset Status

5-78
inter 80C196KC USER'S GUIDE

WATCHDOG TIMER Figure 14-7 shows what the RESET pin looks like in-
ternally. The RESET pin functions as an input and as
There are three ways in which the 80Cl96KC can reset an output to reset an entire system with a watchdog
itself. The watchdog timer will reset the 80C 196KC if it timer overflow; or by executing a RST instruction. For
is not cleared in 64K state times. The watchdog timer is a system reset application, the reset circuit should be a
enabled the first time it is cleared. To clear the watch- one-shot with an open collector output. The reset pulse
dog, write a 'IE' followed immediately by an 'EI' to may have to be lengthened and buffered since RESET
location OAH. Once enabled, the watchdog can only be is only asserted for 16 state times. A capacitor cannot
disabled by a reset and on the 80C196KC. ' be connected directly to RESET if it is to drive the reset
pins of other chips in the circuit. The capacitor may
keep 'the voltage on the pin from going below guaran-
RST INSTRUCTION teed VIL for circuits connected to the RESET pin. Fig-
Executing a RST instruction will also reset the ure 14-8 shows an example of a system reset circuit.
80C196KC. The opcode for the RST instruction is
OFFH. By putting pullups on the Addr/data'bus, unim-
plemented areas of memory will read OFFH and cause 14.5 Minimum Hardware Connections
,the 80Cl96KC to be reset. Figure 14-9 shows the minimum connections needed to
get the 80C196KC up and running. It is important to
RESET CIRCUITS tie all unused inputs to Vee or Vss. If these pins are
left floating, they can float to a mid voltage level and
The simplest way to reset an 80C196KC is to insert a draw excessive current. Some pins such as NMI or
capacitor between the RESET pin and Vss. The EXTINT may generate spurious interrupts if left un-
80Cl96KC has an internal pullup. A 5 uF or greater connected.
capacitor should provide sufficient reset time as' long as
Vee rises quickly. '

Vce

80C196KC CHIP RESET

RESET PIN

WATCHDOG TIMER
OVERFLOW
RESET INSTRUCTION
(OFFH)
270704-45

Figure 14·7. Reset Pin

5-79
 80C196KC USER'S GUIDE

80C196KC
OPTIONAL OTHER
CIRCUITRY
Vee RESET 1-.....-1 ONE-SHOT
74AC123

lOOK

l l .0 J.l.F'

270704-46

NOTE:
1. The diode will provide a faster eycle time repetitive power-on,-resets.

Figure 14-8. System Reset Circuit

r
20

+5V +5V

Vee VREF
lJ.1.F' lJ.1.F'
V SS1 ANGND
VSS2
VSS3 - +5V

BUSWIDTH
READY
RESET
5 J.l.F .::r:. BUS
CONTROL

RXD ADO-AD15
EXTINT
T2CLK PO.O - PO.7
T2RST
HSI.O - HSI.3 EA
NMI

BOC196KC
270704-47

NOTE:
'Inputs must be driven high or low.

"Figure 14-9. 80C196KC Minimum Hardware Connections

5-80
inter 80C196KC USER'S GUIDE

15.0 SPECIAL MODES OF Ports 3 and 4 will retain the value present in their data
OPERATION latches if being used as I/O ports. If these ports are the
ADDR/DATA bus, the pins will float.
The 80C196KC has Idle and Powerdown Modes to re-
duce the amount of current consumed by the chip. The It is important to note the Watchdog Timer continues
80C196KC also has an ONCE (ON-Circuit-Emulation) to run in the Idle Mode if it is enabled. So the chip
Mode to isolate itself from the rest of the components must be awakened every 64K state times to clear the
in the system. Watchdog or the chip will reset.

15.1 Idle Mode 15.2 Powerctown Mode

The Idle Mode is entered by executing the instruction The Powerdown Mode is entered by executing the in-
'IDLPD # 1'. In the Idle Mode, the CPU stops execut- struction, 'IDLPD #2'. In the Powerdown Mode, all
ing. The CPU clocks are frozen at logic state zero, but internal clocks are frozen at logic state zero and the
the peripheral clocks and CLKOUT continue to be ac- oscillator is shut off. All 232 bytes of registers plus the
tive. Power consumption in the Idle Mode is reduced to 256 bytes of extra RAM and most peripherals hold
about 40% of the active Mode. ' their values if Vee is maintained. Power is reduced to
the device leakage and is in the uA range.
The CPU exits the Idle Mode by any enabled interrupt
source or a hardware reset. Since all of the peripherals In Powerdown, the bus control pins go to their inactive
are running, the interrupt can be generated by the HSI, states. All of the output pins will assume the value in
HSO, AID, serial port, etc. When an interrupt brings their data latches. Ports 3 and 4 will continue to act as
the CPU out of the Idle Mode, the CPU vectors to the ports in the single chip mode or will float if ·acting as
corresponding interrupt service routine and begins exe- the ADDR/DATA bus.
cuting. The CPU returns from the interrupt service
routine to the next instruction following the 'IDLPD To prevent accidental entry into the Powerdown Mode,
# l' instruction that. put the CPU in the Idle Mode. this feature may be disabled at reset by clearing bit 0 of
the CCR (Chip Configuration Register). Since the de-
A PTS cycle also causes the CPU to exit the IDLE fault value of the CCR bit 0 is I, the Powerdown Mode
mode. The CPU begins executing the instruction fol- is normally enabled.
lowing the "IDLE # 1" instruction that put the device
into IDLE mode. The Powerdown Mode can be exited by a chip reset or
a high level on the external interrupt pin. If the RESET
In the Idle Mode, the system bus control pins (ALE, pin is used, it must be asserted long enough for the
RD, WR, INST, and BHE), go to their inactive states. oscillator to stabilize.

XTALI

CLKOUT
,
.,
PHI

INTERNAL'
POWERDOWN : ,r '---i-"';"--o-!I ~------""';--+--i
SIGNAL ~i_...,._...,._....;_....;~....J.
r

--i--.;.-.....;~....;.-....;..-~'1r-flL....---"";"-";"'-+--';'-"""';
EXTINT ;.:-...;..-.....

Vpp :
,,

TIMEOUT .: -------..;.--..;.--.;...---~I~
270704.,.48

Figure 15-1. Power Up and Power Down Sequence

5-81
inter 80C196KC USER'S GUIDE

When exiting Powerdown with an external interrupt, a at a logical 1 during reset. Exter!).al circuitry' must \lot
positive level on the pin mapped to INT7 (either pull the pin low or the ONCE mode will be entered. All
EXTINT or portO. 7) will bring the chip out of Power· pins except XTALI and XTAL2arefloated. Some of
down Mode. The interrupt does not have to be un· the pins are not truly high impedance as they have
masked to exit Powerdown. An interll'al timing circuit weak pullups or pulldowns. The ON<;E Mode is useful
ensures that the oscillator hils time to stabilize before in electrically removing the 8OC196KC from the rest of
turning on the internal clocks. Figure 15·1 shows the the system. A typical application of the ONCE Mode
power down and power up sequence using an external would be to program discrete EPROMs onboard with·
interrupt. out removing the 80Cl96KC from its socket.

During normal operation, before entering Powerdown

Mode, the Vpp pin will rise to Vee through an internal 16.0 EXTERNAL MEMORY
pullup. The user must connect a capacitor between Vpp INTERFACING
and VS8. A positive level on the external interrupt pin
starts to discharge this capacitor. The internal current
source that discharges the capacitor can sink approxi· 16.1 Bus Operation
mately 100 uA. When the voltage goes below about 1 There are several different external operating modes on
volt on the Vpp pin, the chip begins executing code. A the 80C196KC. The standard bus mode uses a 16 bit
1uF capacitor would take about 4 ms to discharge to 1 multiplexed address/data bus. Other bus modes include
volt. an 8 bit extetnal bus mode and a mode in which'the bus
size can be dynamically switched between 8·bits and
If the external interrupt brings the chip out of Power· 16·bits. In addition, there are several options available
down, the corresponding bit will be set in the interrupt on the type of bus control signals which make an exter·
pending register. If the interrupt is unmasked, the. de· nal bus simple to design.
vice will immediately execute the interrupt service rou·
tine, and return to the instruction following the IDLPD In the standard mode, external memory is addressed
instruction that put the chip into Powerdown. If the through lines ADO·ADI5 which form a 16 bit multi·
interrupt is masked, the chip will start at the instruc· plexed bus. The address/data bus shares pins with ports
tion following the IDLPD instruction. The bit in the 3 and 4. Figure 16·1 shows an idealized timing diagram
pending register will remain set, however. for the external bus signals.
All peripherals should be in an inactive state before Address Latch Enable (ALE) provides a strobe to
entering Powerdown. If the AID converter is in the transparent latches (74AC373s) to demultiplex the bus.
middle of a conversion, iris aborted. If the chip comes To avoid confusion, the latched address signals will be
out of Powerdown by an external interrupt, the serial called MAO·MAIS and the data signals will be named
port will continue where it left off. Make sure that the MDO·MDI5.
serial port is done transmitting or receiving before en·
tering Powerdown. The SFRs associated with the A/D The data returned from external memory must be on
and the serial port may also contain incorrect informa· the bus and stable for a specified setup time before the
tion when returning from Powerdown. rising edge of RD (read). The rising edge of RD signals
the end of the sampling window. Writing to external
When the chip is in Powerdown, it is impossible for the memory is controlled with the WR (write) pin, Data is
watchdog timer to time out because its clock has valid on MDO-MDlS, ~m the rising edge of WR. At
stopped. Systems which must use the Watchdog and this time data must be latched by the external system.
Powerdown, should clear the Watchdog right before The 80C196KB has ample setup and hold times for
entering Powerdown. This will keep the Watchdog writes.
from timing out when the oscillator is stabilizing after
leaving Powerdown. When BHE is asserted, the memory connected to the
high byte of the data bus is selected. When MAO is a 0,
.the memory connected to the low byte of the data bus is
15.3 ONCETM and Test Modes selected. In this way accesses to a 16·bit wide memory
can be to the low (even) byte only (MAO =0, BHE= I),
Test Modes can be entered on the 80C196KC by hold· to the high (odd) byte only (MAO = 1, BHE = 0), or the
ing ALE,WR, HLDA or RD in their active state on the both bytes (MAO = 0, BHE = AD).
rising edge of RESET. For this reason the IOL and IOH
in Reset Specifications must be carefully verified. The When a block of memory is decoded for reads only, the
only Test Mode not reserved for use by Intel is the system does not have to decode BHE and MAO. The
ONCE, or ON·Circuit·Emulation Mode. 80C196KB will discard the byte it does not need. For
systems that write to external memory, a system must
ONCE is entered by driving TXD pin low on the rising generate separate write strobes to both the high and low
edge of RESET. The TXD pin will source about 1 rnA byte o(memory, This is discussed in more detail later.
5·82
 80C196KC USER'S GUIDE

XTAL1

CLKOUT

ALE J\""'-________
READY

BUS WIDTH

BUS -< ADDRESS OUT ) ( OUT »)

READ------------~~

WRITE ---------"'\~
270704-49

Figure 16·1. Ideaiized Bus Timings

All of the external bus signals are gated by the rising The CCR is shown in Figure 16-2.
and falling edges of CLKOUT. A zero waitstate bus
cycle consists of two CLKOUT periods. Therefore, Bits 7 and 6 of the CCR contra! ROM/EPROM pro-
there are 4 clock edges that generate a complete bus tection. ROM/EPROM protection is covered in Sec-
cycle. The first falling edge of CLKOUT asserts ALE tion 17. The next two bits control the internal READY
and drives an address on the bus: The rising edge of mode. The three next bits determine the. bus control
CLKOUT drives ALE inactive. The next falling edge signals. The next bit enables or disables the Powerdown
of CLKOUT asserts RD (read) and floats the bus for a Mode.
read cycle. During a WR (write) cycle; this edge asserts
WR and drives valid data onthe bus. 'On the last rising
edge of CLKOUT, data is latched into the 80C196KB
for a read cycle, or data is valid for a write cycle. CHIP CONFIGURATION REGISTER

ENABLE POWER DOWN FEATURE

BUS WIDTH SELECT
16.2 Chip Configuration Register . (16-8IT BUS/""8--B""IT""'B"'"U"'S)

The CCR (Chip Configuration Register) is the first WRITE STROBE MODE SELECT
(WR AND BHE/WRL AND WRH)
byte fetched from memory following a chip reset. The
CCR is fetched from the CCB (Chip Configuration L----ADDRESS VALID STROBE SELECT
Byte) at location 2018H in either internal or external (ALE/ADV)
memory depending on the EA pin. The CCR is only (IRCO) } INTERNAL READY
loaded once during the reset sequence. Once loaded, the .....- - - - ( I R C 1 ) CONTROL MODE
CCR cannot be changed until the next reset. During
CCB fetch, strong drivers are active on AD8-AD15 (LOCO) )PROGRAM LOCK
only during the address portion of the cycle. Weak .....- - - - - - ( L O C 1 ) MODE
drivers are applied during the read portion of the cycle 2~0704-50
to avoid bus contention in 16-bit systems. Pull up resis-
tors should not be installed on AD8-ADI5 in 8-bit Figure 16·2. Chip Configuration Register
systems.

5-83
 80C196KC USER'S GUIDE

READY control This feature gives very simple and flexible. ready con-
trol. For example, every slow memory chip select line
The uSer has two options for ready control. He can use could be ORed together and connected to the READY:
the READY pin and/or the internal ready control bits. pin with Internal Ready Control programmed to insert
Ready control is only valid for external memory. On- the desired number of waitstates into the. bus cycle.
chip RAM/SFR space and on-chip ROM/EPROM is
always accessed with 0 waitstates. The modes are cho-
sen by bits 4 and 5 of the CCR and are shown in Figure Bus' control
16-3. Using .the CCR, the 80CI96KC can generate several
types of control signals designed to reduce external
IRC1 IRCO Description hardware. The ALE, WR, and BHE pins serve dual
functions. Bits 2 and 3 of the CCR specify the function
0 0 Limit to one waitstate
performed by these control lines.
0 1 Limit to two waitstates
1 0 Limit to three waitstates
1 1 Wait states not limited internally Standard bus control
Figure 16-3. Ready Control Modes If CCR bits 2 and 3 are Is, the standard bus control
signals ALE, WR, and BHE are generated as shown in
The internal ready control logic limits the number of Figure .16-4. ALE rises as the address starts to be driv-
waitstates that slow devices can insert into the bus cy- en, and falls to externally latch the address. WR is driv-
cle. When the READY pin is pulled low, waitstates are en for every write. BHE and MAO can be combined to
inse~ted into the bus cycle until the READY pin goes fO.rm WRL and WRH for even and odd byte writes.
high, or the number of waitstate equal the number pro-
grammed into the CCR. So the ready control is a logi-
calOR between the READY pin and the internal ready
control.

ALE.Jl
IL ALE J l , , - '_ _ IL
WRiTE
LJ u
BHE VALID ADO-71 ADDR LOW DATA OUT r
ADO'. 15 1 ADDR
·1 DATA OUT
r
2,70704-51
AD8 -15 r
~..._ _ _A_D_D_RE_S_S_H_IG_H_ _ _...
270704-.52
16-BII Bus Cycle 8-BII Bus Cycle

Figure 16-4. Standard Bus Control

5-84
infef 80C196KC USER'S GUIDE

BHE ----<T'""'" WRITE HIGH

WRITE LOW

MAO
270704-53

Figure 16-5. Decoding WRL and WRH

Figure 16-5 is an example of external circuitry to de- Address Valid Strobe Mode
code WRL and WRH.
Address Valid strobe replaces ALE if the CCR bit 3 is
0. When Address valid Strobe mode is selected, ADV
Write Strobe Mode will be asserted after an external address is setup. It will
The Write Strobe Mode eliminates the need to external- stay asserted until the end of the bus cycle as shown in
ly decode odd and even byte writes. If the CCR bit 2 is Figure 16.7. ADV can be used as a simple chip select
0, arid the bus is a 16-bit cycle, WRL and WRH are for external memory. ADV looks exactly like ALE for
generated in place of WR and BHE. WRL is asserted back to back bus cycles. The only difference is ADV
for all byte writes to an even address and all word will be inactive when the external bus is idle.
writes. WRH is asserted for all byte writes to odd ad-
dresses and all word writes. The Write 'Strobe mode is Address Valid with Write Strobe
shown in Figure 16-6.
If the CCR bits 2 and 3 are 0, the Address Valid with
In the eight bit mode, WRL and WRH are asserted for Write Strobe mode is enabled. Figure 16-8 shows,the
both even and odd addresses. signals.

ALE Jl rL ALE

WRL VALID
I
WRH VALID
I ADO -7 ~ ADDR LOW DATA OUT r--
ADD -15
~ ADDR DATA OUT

16-BII Bus Cycle

r--
270704-54
ADS -15 ~.._ _ _A_D_D_RE_S_S_H_IG_H_ _~r--
8-BII Bus Cycle
270704-55

Figure 16-6. Write Strobe Mode

5-85
 8(1C196KC USER'S GUIDE

ADV
I ADV
I
WRITE WRITE
U
BHE VALID ADO-7 --4ADDR LOWI DATA OUT
~
ADO-15 --4 ADDR DATA OUT
~ AD8-15 --4 ADDRESS OUT HIGH
~
270704-56 270704-57
16-Blt Bus Cycle 8-Blt Bus Cycle

Figure 16·7. Address Valid Strobe Mode

16.3 Bus Width During 16-bit bus cycies, Ports 3 and 4, contain the
address multiplexed with data.using ALE to latch the
The 80C196KC external bus width can be run-time address, In 8-bit bus cycles, Port 3 is multiplexed with
configured to operllte as a 16-bit multiplexed address/ address/data but Port 4 only outputs the upper 8 ad-
data bus, or a mUltiplexed 16-bit address/8-bit data dress bits. The Addresses on Port 4 are valid through-
bus. out the entire bus cycle. Figure 16-9 shows the two bus
width options.

WRITE LOW VALID WRITE

WRITE HIGH VALID ADO -7 -1 ADDR LOW I DATA OUT ~

ADO -15 --I ADDR DATAOJT ~ AD8 -15 ~",_ _A_D_D_RE_S_S_H_IG_H_ _~,~
270704-58 270704-59
16-Blt Bus Cycle 8-Blt Bus Cycle

Figure 16·8. Address Valid with Write Strobe Mode

5-86
inter 80C196KC USER'S GUIDE

BUS CONTROL

8DC196KC 80C196KC

8-BIT
PORT 4 LATCHED
ADDRESS HIGH

PORT 4
PORT 3

PORT 3

270704-60 270704-61
(8) 16-BII Bus (b) 8-Bil Bus

Figure 16-9_ Bus Width Options

The external bus width can be changed every bus cycle ed, or high for the entire bus cycle. For data reads and
if a I was loaded into bit CCRI at reset. The bus width writes; the INST pin is low. The INST pin is low for
is changed on the fly by using the BUSWIDTH pin. If the Chip Configuration Byte fetch and for interrupt
the BUSWIDTH pin is a I, the bus cycle is 16-bits. For vector fetches. '
an 8-bit bus cycle, the BUSWIDTH pin is a O. The
BUSWIDTH pin is sampled by the 80CI96KC after
the address is on the bus. The BUSWIDTH pin has 16.4 HOLD/HLDA Protocol
about the same timing as the READY pin.
The 80CI96KC supports a bus exchange protocol, al-
Applications for the BUSWIDTH pin are numerous. lowing other devices to gain control of the bus. The
For example, a system could have code fetched from 16 protocol consists of three signals, HOLD, HLDA, and
bit memory, while data would come from 8 bit memo- BREQ. HOLD is an input asserted by a device which
ry. This saves the cost of using two 8 bit static RAMS if requests the 80CI96KC bus. Figure 16-10 shows the
the capacity of only one is needed. This system could be timing for HOLD/HLDA. The. 80Cl96KC responds
easily implemented by tying the chip select input of the by releasing the bus and asserting HIDA. When the
8-bit memory to the BUSWIDTH pin. device is done accessing the 8OCl96KC bus; it relin-
quishes the bus by deasserting the HOLD pin. The
If the CCR bit I is a 0, the 80CI96KC is locked into 80CI96KC will remove its HDLA and assume control
the 8 bit mode and the BUSWIDTH pin is ignored. of the bus. The third signal, BREQ, is asserted by the
80Cl96KC during the hold sequence when it has a
When executing code from a 8-bit bus, some perform- pending external bus cycle. The80Cl96KC deasserts
ance degrada~ion is to pe expected. The prefetch queue BREQ at the same time it deasserts HDLA.
cannot be kept full under all conditions from an 8-bit
bus. Also, word reads and writes to external memory The HOLD, HLDA, and BREQ pins are multiplexed
take an extra bus cycle. with Pl.7, Pl.6, and Pl.5, respectively. To enable
HOLD, HLDA an,d BREQ, the HLDEN bit (WSR.7)
must be set. HLDEN is cleared during reset. Once this
INST PIN bit is set, the portl pins cannot be returned to being
quasi-bidirectional pins until the device is RESET, but
The INST pin is useful for decoding more than 64K of can still be read as inplJts. The HOLD/HLDA feature,
addressing space. The I1'lST pin allows both 64K of however, can be disabled by clearing the HLDEN bit
code space and 64K of data space. For instruction for locked bus cycles.
fetches from external memory, the INST pin is assert-

5-87
 80C196KC USER'S GUIDE

CLKOUT

__________________ ~r_

\~------------~;-
ADDR/DATA _ _ _ _ _ _ _ _ --JXI..______.....;F.;;;lo:.;at;;.d:....._ _ _ _ _ _.....X
ALE. RD. ViR.
BHE. INST
-------"'"'X X
. \"._ _ _ _ _ _,...w,;,.;.,;;;ak~ly~d;;.rlv,;,.;.,;,.;n_ _ _ _ _ _ _•
270704-62

Figure 16-10. HOLD/HLDA.Timings

HOLD is sampled on phase I, or when CLKOUT is If HOLD is asserted asynchronously, the minimum
low. hold latency increases by one state time and = THVCL
+ 1.5 states + TCLHAL.
When the 80CI96KC acknowledges the hold request,
tqe output buffers for the addrldata bus are floated. Figure 16-11 summarizes the additional hold latency
ALE and INST are weakly held LOW and ADV, RD. added to the minimum latency for the 3 types of bus
WR, WRL, WRH are weakly held high during HOLD. cycles. When accessing external memory, add one state
The request to hold latency is dependent on the state of for each waitstate inserted into the bus cycle. For ·an 8-
the bus' controller. bit bus, worst case hold latency is for word reads or
writes. For this case, the bus controller must access the
bus twice. which increa,ses latency by two states.
MAXIMUM HOLD LATENCY

The time between HOLD being asserted and HLDA For exiting Hold. the minimum hold latency times ap-
being driven is known as Hold Latency. After recogniz- ply for when the 80C196KC will deassert HLDA in
response to HOLD being removed.
ing aOLD, the 80CI96KC waits for any current bus
cycle to finish, and then asserts HLDA.' There are 3 Max Hold Latency
types bus cycles; 8-bit external cycle, 16-bit external
cycle, and an idle bus. Accessing on-chip ROMI Idle Bus Min
EPROM is an idle bus. 16-bit External Access Min + 1 State
HOLD is an asynchronous input. There are two differ- 8-bit External Access Min + 3 States
ent system configurations for asserting HOLD. The Min ~ THVCL + 0.5 states + TCLHAL if T HVCL is met
80CI96KC will recognize HOLD internally on the next ~ THVCL + 1.5 states + TCLHAL for asynchronous HOLD

clock edge if the system meets THVCH (HOLD valid to Figure 16-11. Maximum HOLD Latency
CLKOUT high). IfTHVCH is not met (HOLD applied
asynchronously), HOLD may be recognized one clock REGAINING BUS CONTROL
later (see Fig\lre 16-12). Consult the latest 80CI96KC
data sheet for the THVCH specification. There is no delay from the time the 80CI96KC re-
moves HLDA to the time it takes control of the bus.
Figure 16-12 shows the 80C196KC entering HOLD After HOW is removed, the 80CI96KC drops HLDA
when the bus is idle. This is the minimurrl hold latency in the following state and resumes control of the bus.
for both the synchronous and asynchronous cases. If
THVCH is met, HLDA is asserted about on the next BREQ is asserted when the part is in hold and needs to
falling edge of CLKOUT. See the data sheet for perform an external memory cycle. An external memo-
ry cycle can be a data access or a request from the
TCLHAL (CLKOUT low to HLDA low) specification.
For this case, the minimum hold latency = THVCL + prefetch queue for a code request. A request comes
0.5 .states + TCLHAL. from the queue when it contains two bytes or less. Once
asserted, it remains asserted until HOLD is removed.
At the earliest, BREQ can be asserted with HLDA.
5-88
infef 80C196KC USER'S GUIDE

Case 1. Meeting THVCL

I one slale lime

CLKOUT

270704-92

Case 2. Asserting HOLD Asynchronously,

270704-93

Figure 16~12

Hold requests do not freeze the SOC196KC when exe- DISABLING HOLD REQUESTS
cuting out of internal memory. The device continues
executing as 10l1cg as' the resources it needs are located Clearing the HLDEN bit (WSR.7), can disable HOLD
internal to the SOCI96KC. As soon as the device needs requests when consecutive memory cycles are required.
to access external memory, it asserts BREQ and waits Clearing the HDLEN bit, however, does not cause the
for the HOLD to be removed. At this time, the device SOC196KC to take over the bus immediately. The,
cannot respond to any interrupt requests until HOLD 80C196KC waits for the current HOLD ,request to fin-
is removed. ish. Then it disables the bus hold feature, causing any
new requests to be ignored until the HLDEN bit is set
When executing out of external memory during a again. Since there is a delay from the time the code for
HOLD, the SOC196KC keeps running until the queue clearing this bit is fetched to the time it is actually exe-
is empty or it needs to perform an external data cycle. cuted, the code that clears HLDEN needs to be a few
The 80C196KC cannot servic.e any interrupts until instructions ahead of the block that needs to be protect-
HOLD is removed. ed from HOLD requests.

The 80C196KC will also respond to hold requests in The safest way is to add a .IBC instruction to check the
the Idle Mode. The latency fQr entering bus hold from status of the HLDA pin after the code that clears the
the Idle Mode is the same as when executing out of HLDEN bit. Figure 16-13 is an example of code that
internal memory. prevents the part from executing a new instruction until
both current HOLD requests are serviced and the hold
Special consideration must be given to the bus arbiter feature is disabled.
design if the SOC196KC can be reset while in HOLD.
For example, a CPU device would try and fetch the
CCR from external memory after RESET is brought
16.5 AC Timing Explanations
high. Now there would be two parts attempting to ac- Figure 16-14 shows the timing of the ADDR/DATA
cess SOC196KC memory. The simplest solution is to bus and control signals. Refer to the latest data sheet
make the RESET pin of the SOC196KC a system reset. for the AC timings to make sure your system meets
This way the other bus master would also be reset. Ex- specifications. The major timing specifications are ex-
amples of system reset circuits are given in Section 13. plained in Figure 16-15.

5-89
 80C196KC USER'S GUIDE

DI disable interrupts
ANDB WSR, #OEFH disable hold request
WAIT: JBC PORTI, S, WAIT; Check the HLDA pin
• If set, execute
• protected instructions,
•
ORB WSR,#80h enable HOLD requests
EI enable interrupts
NOTE:
Interrupts should be disabled to prevent code interruption

Figure 16-13. HOLD code

XTALI

CLKOUT

ALE

READ

BUS

WRITE

BUS

BHE.INST -< VALID

270704-63

XTALI

CLKOUT

ALE

READY

BUS WIDTH

BUS -< F tAVGv~1

j
tAvyv
'tCLG,X

tLLGV

ADDRESS OUT ) ( DATA »>

\~ ____ ________-Jr-
~
270704-64

Figure 16-14. AC Timing Diagrams

5-90
,

inter 80C196KC USER'S GUIDE

TIMINGS THE MEMORY SYSTEM MUST MEET: TCLDY - CLKOUT Low to Input Data Valid:
Maximum time the memory system has
TAYYY - ADDRESS Valid tl> READY Setup: to output valid data after the CLKOUT
Maximum time the memory system has falls.
to decode READY after ADDRESS is - RD High to Input Data Float: Time af-
output by the 80C196KC to guarantee ter RD is inactive until the memory sys-
at least one-wait ",tate will occur. tem must float the bus. If this timing is
TLLYY - ALE Low to READY Setup: Maximum not met, bus contention will occur.
time the memory system has to decode - Data Hold after RD Inactive: Time after
TRXDX
READY after ALE faUs to guarantee at RD is inactive that the memory system
least one wait state will occur. must hold Data on the bus. Always 0 ns
TYLYH -READY Low to READY HIGH: On the 80C196KC.
Maximum amount of nonREADY time
or the maximum number of wait states
that can be inserted into a bus cycle. TIMINGS THE 80C196KC WILL PROVIDE:
Since the 80C196KC is a completely FXTAL - Frequency on XTALl: Frequency ofsig-
static part, T YLYH is unbounded. nal input into the 80C196KC. The
80CI96KC runs internally at '/2 FXTAL.
TCLYX - READY Hold after CLKOUT Low:
Minimum time the level on the READY T0SC - l/FXTAL: All A.C. Timings are refer-
pin must be valid after CLKOUT falls. enced to T OSC.
The minimum hold time is always 0 ns. TXHCH - XTALl High to CLKOUT High or
If maximum value is exceeded, addition- Low: Needed in systems where the sig-
. al wait states will occur. nal driving XTALl is also a clock for
T LL YX - READY Hold AFI'ER ALE Low: external devices.
Minimum time the level on the READY T CLCL - CLKOUT Cycle Time: Nominally 2
pin must be valid after ALE falls. If Tosc·
maximum value is exceeded, additional T CHCL - CLKOUT High Period: Needed in sys-
wait states will occur. tems which use CLKOUT as clock for
TAYGY - ADDRESS Valid to BUSWIDTH Val- external devices.
id: Maximum time the memory system - CLKOUT Falling Edge to ALE/ADV
has to decode BUSWIDTH after AD- TCLLH
Rising: A help in deriving other timings.
DRESS is output by the 80C196KC. If
exceeded, it 1S not guaranteed the - ALE/ ADV Falling Edge to CLKOUT
80C196KC will respond with an 8- or Rising: A help in deriving other timings.
16-bit bus cycle. - ALE Cycle Time: Time between ALE
- ALE Low to BUSWIDTH Valid: pulses.
Maximum time after ALE/ ADV falls - ALE/ADV High Period: Useful in de-
until BUSWIDTH must be valid. If ex- termining ALE/ ADV rising edge to
ceeded, it is not guaranteed the ADDRESS valid. External latches must
80C196KC will respond with an 8- or also meet this spec.
16-bit bus cycle. - ADDRESS Setup to ALE/ADV Falling
TCLGX - BUSWIDTH Hold after CLKOUT Edge: Length of time ADDRESS is val-
Low: Minimum time BUSWIDTH must id before ALE/ ADV falls. External
be held valid after CLKOUT falls. Al- latches must meet this spec.
ways 0 ns of the 80C196KC. - ADDRESS Hold after ALE! ADV Fall-
TAYDY - ADDRESS Valid to Input Data Valid: ing Edge: Length of Time ADDRESS is
Maximum time the memory system has valid after ALE! ADV falls. External
to output valid data after the 80Cl96KC latches must meet this spec.
outputs a valid address. -- ALE!ADV Low to RD Low: Len~ of
- RD Low to Input Data Valid: Maximum time after ALE! ADV falls before RD is
time the memory system has to output asserted. Could be needed to insure
valid data after the 80C196KC asserts proper memory decoding takes place be-
RD. fore a device is enabled.

Figure 16·15. AC Timing Explanations

5-91
 80C196KC USER'S GUIDE ~; ,

TRt,CL- RD Low to CLKOUT Falling Edge: TCHWH ~

CLKOUT High to WR Rising Edge:
Length of time from RD asserted to Time between CLKOUT going high and
CLKOUT falling edge: Useful for sys- WR going inactive. Useful in systems
tems based on CLKOUT. based on CLKOUT.
TRLRH - RD Low to RD High: RD pulse width. TWLWH- WR Low to WR High: WR pulse width.
- RD High to ALE/ADV Asserted: Time . Memory devices must meet this spec.
between RD going inactive and next TWHQX - Data Hold after WR Rising Edge:
ALE/ADV, also used to calculate time Amount of time data is valid on the bus
between inactive and next ADDRESS after WR gofng inactiv~. Memory devic-
valid. es must .meet this spec.
TRLAZ - RD Low to ADDRESS Float: Used to TWHLH - WR Rising Edge to ALE/ADV Rising
calculate when the 80Cl96KC stops Edge: Time between WR going inactive
driving ADDRESS on the bus. and next ALE/ADV. Also used to cal-
- ALE/ADV Low Edge to WR Low: culate WR inactive and next ADDRESS
Length of time ALE/ADV falls before valid.
WR is asserted. Could be needed to en- TWHBX - BHE, INST, Hold after WR Rising
sure proper memory decoding takes Edge: Minimum time these signals will
place before a device is enabled. be valid after WR inactive.
TCLWL - CLKOUT Falling Edge to WR Low: - BHE, INST, Hold after RD Rising
Time between CLKOUT going low and Edge: Minimum time these signals will
WR being asserted. Useful in systems be valid af~er RD inactive. .
based on CLKOUT. TWHAX - ADS·IS Hold after WR Rising Edge:
- Data Valid to WR Rising Edge: Time Minimum time the high byte of the ad-
between data being valid on the bus and dress in 8-bit mode will be valid after
WR going inactive. Memory devices WR inactive.
must meet this spec. TRHAX - ADS-IS Hold after RD Rising Edge:
Minimum time the high byte of the ad-
dress in 8-bit mode will be valid after
RD inactive.

Figure 16·15. AC Timing Explanations (Continued)

RD or
AD8-15 HIGH ADDRESS
DATA
80C196KC
ADO-.7
I ~

74AC
373
EPROM
LOW ADDRESS

ADV
T-\ Cs
\
OPTIONAL IF
LATCHED EPROM
IS USED
270704-65

Figure 16·16. 8·Bit System with EPROM

5-92
intJ 80C196KC USER'S GUIDE

16.6 Memory System Examples Figure 16-18 shows a 16 bit system with 2 EPROMs.
Again, ADV is used to chip select the memory. Figure
External memory systems for the 80C196KC can be set 16-19 shows a system with dynamic bus width. Code is
up inmany different ways. Figure 16-16 shows a simple executed from the two EPROMs and data is stored in
8 bit system with a single EPROM. The ADV Mode the single RAM. Note the Chip Select of the RAM also
can be selected to provide a chip select to the memory. is input to the BUSWIDTH pin to select an eight bit
By setting bit CCR.l to 0, the system is locked into the cycle.
eight bit mode. An' eight bit system with EPROM and
RAM is shown in Figure 16-17. The EPROM is decod-
ed in the lower half of memory, and the RAM in the
upper half. '

AD15

AD8-15 ~ _ _...._ _..

HIGH ADDRESS
. ._ _ _..... DATA DATA
80C196KC , EPROM RAM
ADO-7!-__.j LOW ADDRESS LOW ADDRESS

ADV 1-----1

RD I---------~-----~
WR
270704-66

Figure 16-17. 8-Bit System with EPROM and RAM

Cs
AD8-15 HIGH ADDRESS
EPROM

DATA

ADO-7 LOW ADDRESS

80C196KC

RD ~------~~----~

270704-67

Figure 16-18. 16-Bit System with EPROM

5-93
intJ 80C196KC USER'S GUIDE

EPROM RAM

ADV r~~~::JDATA
LOW ADDRESS
80C196KC OE

~ ~------------~~----------~------------~
WR ~--------------------------------------------~
270704-68

Figure 16-19. 16-Bit System with Dynamic Buswidth

WRL-----C(

MDO-MD7--------4---~~~ P3

WRH----t~

8 74HCT 74HCT
8
MD&-MD'5--------~--~~~ ~ 05 P4
(x, ....., (X, .....)

~-----~ __------------L--J INPUT

ADDR = P3, P4 - - - -....cr,Jo-______________--,
RD ------aL~
ADO-AD7

AD8-AD1S

270704-69

Figure 16-20.1/0 Port Reconstruction

5-94
inter 80C196KC USER'S GUIDE

16.7 1/0 Port Reconstruction Three flexible EPROM programming modes are avail-
able on the '87CI96KC; Auto, Slave, and Run-time.
When a single-chip system is being designed using a These modes can program the 87C196KC in a stand
multiple chip system as a prototype, it may be neces- alone or run-time environment.
sary to reconstruct I/O Ports 3 and 4 using a memory
mapped I/O technique. The circuit to reconstruct the For ROM parts, a ROM dump mode allows the ROM
Ports is shown in Figure ,16-20. It can be attached to a contents to be verified by the user.
80C196KC system which has the required address de-
coding and bus demultiplexing.
17.1 Programming the 87C196KC
The output circuitry is a latch that operates, when
IFFEH or IFFFH are placed on the MA lines. The The EPROM is ~ped into mem.ory locations
inverters surrounding the latch create an open-collector 2000H-SFFF.!!.. if EA is at logical 1. By applying
output to emulate the open-drain output found on the + 12.S0V to EA when RESET is asserted places the
80C196KC. The RESET line sets the ports to all Is 87C196KC in Programming M.ode. The Programming
when the chip is reset. The voltage and current specifi- Mode supports programming and verification of
cations of the port will be different from the 87C196KC EPROMs.
80C196KC, but the functionality will be the same.
The Auto Programming Mode enables an 87C196KC
The input circuitry is a bus transceiver that is addressed to program itself with the 16K bytes of code beginning
at IFFEH and IFFFH. If the ports are going to be at address 4000H on its external bus. The Slave Mode
either inputs or outputs, but not both, some of the cir- provides a standard interface for an EPROM program-
cuitry can be eliminated. mer. The Run-time Mode allows individual EPROM
locations to be programmed at run-time under com-
plete software control.
17.0 USING ROM AND EPROM
PARTS In the Programming Mode, some I/O pins have new
functions. These new pin functions determine and sup-
The 87C196KC contains 16K bytes of ultraviolet Eras- port the different programming modes. Figure 17-1
able and Electrically Programmable Read Only Memo- shows how the pins are renamed and Figure 17-2 de-
ry (EPROM). The 83C196KC contains 16K bytes .of scribes in detail each new pin function.
Read Qnly Memory (ROM).

SELEC
t PROGRAMMING VOLTAGE
TSL
PROGRAMM ING
MO DE _ VPP ...
EA
PC.7
PORT 4 ADDRESS
PORT 3 'I
COMMAND DATA PATH
-y
"
~DE "
PC.6
-y PC.S
P2.7 PACT

PC.4 P2.1 PALE

P2.2 PROG

P2.C PVER
87C196KC
P2.4 AINC
P2.6 CPVER
270704-70

Figure 17·1. Programming Mode Pin Functions

5-95
inter 80C196KC USER'S GUIDE

N~me Function
PMODE Programming Input Mode Select. Determines the EPROM programming algorithm that is
performed. PMODE is sampled after a chip reset and should be static while the part is
operating.
PALE Programming ALE Input. Accepted by an 87C196KC that is in Slave Programming Mode.
Used to indicate that Ports 3 and 4 contain a command/ address.
PROG Programming Input. Falling edge indicates valid data on PBUS and the beginning of
programming. Rising edge indicates end of programming.
PACT Programming Active. Output indicates when programming activity is complete.
PVER Program Verification. Output signal is low after rising edge of PROG if the programming was
not successful.
AINC· Auto Increment. Active low input Signal indicates that the auto increment mode is enabled.
Auto Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
PORTS Address/Command/Data Bus. Used to pass commands, addresses and data to and from
87C196KCs. Also used in the Auto Programming Mode as a regular system bus to access
external memory.
CPVER Cummulative Program Output Verification. Pin is high if all locations since entering a
programming mode have programmed correctly.
Figure 17-2. Programming Mode Pin Definitions

While in Programming Mode, the PMODE value se- ming Chip Configuration Byte). The PCCB is a sepa-
lects the programming function (see Figure 17-3). Run- rate EPROM location that is not mapped I:Inder normal
time programming can be done at any time during nor- operation. PCCB has implications in some of the pro-
mal execution. gramming modes, and also for the memory protection
options, discussed hit'er. Therefore, the PCCB must cor-
PM ODE Programming Mode rectly correspond to the memory system in the pro-
gramming setup, which is not necessarily the memory
0-4 Reserved system of the application.
5 Slave Programming The following sections describe the 87C196KC pro-
6 ROM Dump gramming modes in detail.
7-8 Reserve~

9 UPROM Programming 17.2 Auto Programming Mode

OAH-OBH Reserved The Auto Programming Mode allows an 87C196KC
Auto programming
EPROM to be programmed without a special EPROM
OCH
programmer. In this mode, the 87C196KC simply pro-
ODH PCCB Programming grams itself with the data found at external locations
4000H - 7FFFH. Figure 17-4 shows a minimum config-
OEH-OFH Reserved urationusing an 16K X 8 EPROM to program an
Figure 17-3. Programming 87C196KC in the Auto Programming Mode.
Function Pmode.Values
To start the Auto Programming Mode, PACT is assert-
To guarantee proper functionality, the pins of PMODE ed and the word at external location 4014H is read to
must be in their desired state before RESET rises. Once determine the programming pulse width. This allows
the part is reset, it should not be ,switched to another Auto Programming to be done at several different .fre-
mode without a new reset sequence. quencies. The formula for calculating the pulse width
is:
When EA selects the Programming Mode, the chip re-
set sequence loads the CCR from the PCCB (Program- Pulse Width = XTAL1/t,600,OOO - t

5·96
inter 80C196KC USER'S GUIDE

The MSB of this word also must be set. For example, PCCS Programming Mode
with a 10 MHz Clock, the word at 4014H should be
loaded with 8005H for .the correct pulse width. For The PCCB (Programming Chip Configuration Byte)
8 MHz It is 8004H and for 6 MHz it is 8003H.· can be treated just like any other EPROM location.
When in the Slave Programming Mode, the PCCB can
The 87CI96KC then reads a word from external mem- be programmed at location 2018H. .Butthe PCCB Pro-
ory, and the Modified Quick-Pulse Programming Algo- gramming Mode is a simple way to program the PCCB
rithm (described later) programs the corresponding when no other locations need be programmed. Figure
EPROM location. Since the erased state of a byte is 17-5 shows a block diagram for using the PCCB Pro-
OFFH,~ the Auto Programming Mode skips locations gramming Mode:
containing OFFH. PVER will go low anytime there is a
programming error. When all 16K have been pro- WithPMODE' = ODH and OFFH on Port 4, the
grammed, PACT goes high. PCCB will be programmed with the data on Port 3
when a 0 is placed ,on PALE. Afterprograri1ihing is
In the Auto Programming Mode, CCR is loaded with complete, PVER is driven high if the PCCB was pro-
the PCCB. The PCCB must correspond to the memory grammed correctly, and low if the programming failed.
system of the programming setup, which is not neces- PALE can be pulsed to repeat programming.
sarily the same as the memory system of the actual
application.

Vpp and EA must be kept noise-free and must never go

above 12.7SV at any time. Do not put pull up resistors
on AD8-AD1S.

+5V A15

lOOK
~------------~~--~OE

1--------=---1 A8-A13
100}-" I. HAC AO-A7
373
G EN
27C128

~ _ _ _ _ _~-iDO-D7

+5V

+5V

87C196KC

270704-71
-Inputs must be driven high or low.

Figure 17-4. Auto Programming Mode

5-97
inter 80C196KC USER'S GUIDE

In this mode, the 87CI96KC programs like'a simple

+12.50V EPROM device. The 87CI96KC responds to two dif-
ferent commands while in this mode: data program,
Vce and word dump. These commands, along w.ith the
EA vpp
transfer of appropriate data and addresses are selected
pO.1
po.s using Ports 3 and 4 and five other pins for handshak-
PO.5 ing. The least significant bit selects a Data Program or
Word Dump and the upper 15 bits contain the address
1'0.4 nn.",...-. Vcc to be programmed or dumped. The address ranges from
2000H-5FFFH and refers to internal EPROM space.
87C19SKC
PALEI-.....W ..... Data Program Command

A Data Program Command is illustrated in Figure

17-6. The data program command is selected by setting
the LSB of the address to a I. For example, an address
of 350lH would program the word location at 3500H.
270704-72
Asserting PALE latches the command and address to
NOTES: be programmed from Ports 3 and 4. PROG also asserts
Tie Port 3 to the value desired to be programmed into to latch the data. The width of the PROG pulse deter-
peGs. mines the length of the programming pulse.
Make all necessary minimum connections for power,
ground and clock. After the rising edge' of PROG, the 87C196KC auto-
matically performs a verification of the address just
Figure 17-5. The PCCB Programming Mode
programmed. PVER is asserted if the location pro-
grammed correctly. This gives verification information
t6 programmers which can not use the Word Dump
17.3 Slave Programming Mode Command. CPVER is a cummulative program verify
A 87C196KC can be programmed by a master pro- that will remain low if a location did not verify correct-
grammer through the Slave Programming Mode. ly. The AINC pin can optionally be toggled in order to
increment to the next location or a new Data Program
Command can be issued.

PORTS
3/4 «AOOR/COMMANO:> G G
PALE
~ I
PROG
\ I .\ I
AINC
U
PVER
0 270704-73

Figure 17~6. Data Program Command

intJ 80C196KC USER'S GUIDE

Figure 17.-6 shows the relationship of PALE, PROG, 17.4 Run-Time Programming
PVER, AINC and CPVER to the Command/Data
path on Ports 3 and 4 for the Data Program Command. In Run-Time Programming, the user can program an
EPROM location during the normal execution of code.
Ifhe only additional requirement of Run-Time Pro-
Word Dump Command gramming is programming voltage is ~lied Vpp.
When the Word Dump Command is issued, the Run-Time Programming is done with EA at a TTL
87C196KC places the value at the requested address on high.
Ports 3 and 4. A Word Dump command is selected by a
o on Port pin 3.0. For example, sending the command To Run-Time Program. the user writes to the location
2100H to a slave results in the slave placing the word at to be programmed. Figure 17-8 is the recommended
internal address 2100H on Ports 3 aIid 4. PROG gov- code seqll,ence for Run-Time Programming. The
erns when the 87C196KC drives the bus. The Timings EPROM cannot be accessed during Run-Time Pro-
are shown in Figure 17-7. In the Word Dump mode, gramming. Therefore, the part must enter the IDLE
the AINC pin can remain active and toggling. The mode immediately after writing to the EPROM or be-
PROG pin will automatically increment the address. gin executing immediately from external memory. The
Modified Quick Pulse algorithm guarantees the pro-
grammed EPROM cell for the life of tbe part.

PORTS _ _ _ _ _ -<
3/4

\~---------------------- 270704-74

Figure 17-7. Word Dump Command

PROGRAM: POP ADDRESS. TEMP ;Load program data

POP DATA.TEMP ;and address
PUSHF
LD COUNT, #25T ;program USing Modified
Quick Pulse
LOOP; LDB INT.MASK,#ENABLE.SWT ;program SWT for
LDB HSO.COMMAND,#SWTO.OVF ;program pulse width
ADD HSO.TIME,TIMER1,#PROGRAM.PULSE
EI
ST DATA.TEMP,[ADDR.TEMP], ;enter idle mode until
IDLPD 1 ;swt expires
DJNZ COUNT, LOOP ;loop 25 times
POPF
RET
;service swt and return
RET
Figure 17-8. Run-Time Prog~amming Algorithm Example

5-99
 8OC196KC USER'S GUIDE
"
"
; ~'

17.5 ROM/EPROM Memory Protection The OED (disable external Data fetch) bit disables the
Options bus controller from executing external data reads and
writes if the bit is O. If a data access is requested from
Write protection is available for EPROM parts, and the bus controller, the part will Reset itself.
read protection is provided for both' ROM and
EPROM parts. For more information on UPROMs, ~ Section '17.5.

Write protection is enabled by setting the LOCO bit in Authorized Access of Protected Memory
either CCR or the PCCB to zero. Figure 17-9 summa-
rizes the different write protection options. When write A "Security! Key" mechanism has been implemented
protection is enabled, the bus controller will cycle for authorized access of protected internal memory to
through the write sequence but will not actually drive test internal ROM/EPROM. This allows users to veri-
data to the EPROM or enable Vpp. This protects the fy the EPROM array and still keep their code protect-
entire EPROM 2000 ... 5FFFH from inadvertent or un- ed. '
authorized programming; With write protection en-
abled, the PTS cannot read the internal EPROM. ' The security key is a 128-bit number located in internal
memory at locations 2020H-202FH. The user pro-
CCB PCCB grams his own security key into these locations. Figure
Protection 17-10 shows the different programming modes and
LOCO LOCO
whether a security key verification is performed to al-
1 . 1 Unprotected EPROM. Writes to low entry into the programming mode. '
Internal M~mory always allowed.
1 0 Run-Time Programming Allowed. Programming , Key-
No programming modes allowed Mode Verification
0 1 Run-Time programming not Slave Programming If Protected·
allowed. Programming modes
allowed after key verification (if ROM Dump Always
needed). UPROM Programming Never
0 0 All programming unconditionally AUTO Programming If Protected·
disabled.
PCCB Programming Never
Figure 17-9. Write Protection Options
•If read or Wrtte protected In GGA.
Read protection is enabled by setting the LOci bit of Figure 17-10. Security Key Verification
I '
CCR to a zero. When read protection is selected, the
bus controller will only perform a data read from the The ROM Dump Mode is an easy way to verify the
address range 2020H-202FH and 2050H-5FFFH if contents of the EPROM or ·ROM array. The ROM
the Slave Program Counter is in the range 2000H- Dump writes out the entire EPROM or ROM to loca-
5FFFH. Since the Slave PC can be as many as 4 bytes tions 4OOOH-7FFFH in external memory. If the DED
ahead of the CPU program counter, an instruction after (Disable External Datil Fetches) bit has been pro-
address 5FFAH'may not access protected memory. grammed in the USFR, this mode is disabled entirely
The interrupt vectors and CCB are not read protected (see Section 17.5).
since interrupts can occur even when executing out of
external memory. LOCI in the PCCB can be pro- The ROM Dump Mode is selected with PMODE =
grammed, b'ut has no memory protection implications. 06H and always begins with a security key verification.
The user puts the same security key at external loca-
Also, two UPROM (Unerasable PROM) bits are im- tions 4020H-402FH that he has programmed in inter-
plemented on the 87C196KC for additional memory nal lpcations 2020H.202fH. Before doing a ROM
protection. The DEI (Disable External Instruction dump, the 80C196KC compa'r~s the two security keys.
fetch) bit disables the bus controller from executing ex- If they match, the80C196KC dumps the array to ex-
ternal instruction fetches if the bit is a O.If an attempt ternal memory. If they do not match, the 8OC196KC
is made to load the Slave PC with an external address, enters an endless loop of internal execution which can
the part will Reset itself. The automatic Reset also be exited only by a chip reset.
I
gives extra protection against runaway code. . '
When using the Auto Program1lling Mode, a security
Because of the prefetch queue in the bus controlier, key verification is done if the CCB has read and or
code cannot be executed from the last four bytes of write protection enabled. The security key must reside
internal memory if this feature is enabled. "

5-100
inter 80C196KC USER'S GUIDE

in external memory locations 4020H-402FH and the programming a UPROM bit, it can be verified to make
two keys must match or the 80C196KC enters an end- sure that it did indeed program. Customers are advised
less internal loop. that devices with programmed UPROM bits cannot be
returned to Intel for failure analysis.
In the Slave Programming Mode, a security key verifi-
cation is also performed if CCB has read and or write
protection enabled. The key verify is done 'somewhat Programming UPROMs
differently in the Slave Programming Mode. The user
The UPROM bits in the USFR can be programmed
must "program" the correct key into the array at loca- using the Slave Programming Mode, or with the sepa-
tions 2020H-202FH using the Data Program Com-
rate UPROM Programming Mode. Figure 17-12 shows
mand described in Section 17.3. The locations are not the locations to program a UPROM bit and the data in
actually programmed, but the da~a is compared to the the Slave Programming Mode.
internal security key. The key must be entered sequen-
tially, and if any of the locations is "programmed" in-
correctly, the 80C196KC will enter the elusive endless Bit Address Data
internal loop.
DED 0758H OOO4H
If CCB has any protection enabled, the security key is DEI 0718H 0008H
write protected to keep unauthorized users from over-
Figure 17-12. Programming UPROMs
writing the key with a known security key.
in the Slave Programming Mode
If the PCCB is programmed with any read or write
protection, there is no way to enter any of the program- The UPROM Programming mode works much the
ming modes. So the last thing that should be done to same way as the PCCB Programming Mode (see Figure
protect the part from unauthorized access, is to pro- 17-5). PMODE must be 09H, the value to program the
gram the PCCB. USFR is forced onto port 3, OFFH is forced on port 4,
and PALE is pulled low to begin programming. A 1 in
a bit location means to program the associated
17.6 UPROMs UPROM bit. PACT remains low while programming
and PVER indicates if the data was programmed cor-
Unerasable PROM (UPROM) devices are implement- rectly.
ed on the 87C196KC for some additional security fea-
tures. The USFR (UPROMSpecial Function Register) The Modified Quick Pulse Algorithm
along with what bits are available for the .ROM and
EPROM versions is shown in Figure 17-11. The The Modified Quick Pulse Algorithm must be used to
UPROM bits act as fuses, i.e., they can be pro- guarantee programming ov.er the life of the EPROM in
grammed, but not erased. Run-Time and Slave Programming Modes.
7 0 The Modified Quick-Pulse Algorithm calls for each
*IRSvIRSvIRSvIRSVIDEIIDEDIRSVIRSvl EPROM location to receive 25 separate 100 /bs
(± 5 /bs) programming cycles. Verification is done after
USFR the 25th pulse. If the location verifies, the next location
is programmed. If the location fails to verify, the loca-
DEI DED tion fails the programming sequence.
87C196KC UPROM Bit UPROM Bit Once all locations are programmed and verified, the
83C196KC N/A N/A entire EPROM is again verified.
,
*Always program reserved (RSV) bits to 1 Programming of 87C196KC EPROMs is done with
Figure 17-11. USFR Vpp = 12.50V ±0.25V and Vee = 5.0V ±0.5V.

Because the UPROM bits cannot be erased, the bits

cannot be tested by Intel prior to shipment. Intel does, Signature Word
however, test the different features enabled by UPROM
bits. Therefore, only defects within the UPROM cells The 87C196KC contains a signature word. The word
themselves (rather unlikely) will be undetectable. When can be accessed in the Slave Mode by executing a Word
Dump Command at memory location 70H. The pro-

5-101
inter 80C196KCUSER'S GUIDE

gramming voltages are determined by reading locations 1S.0 SOC196KC to SOC196KB

72H and 73H in Slave Frogramming Mode. The volt-
ages are calculated by using the following equation.
1S.1 New Features of the SOC196KC
Voltage = 20/256 x (test ROM data)
1. The 80C196KC has 488 bytes of RAM and is avail-
The values for the signature word and voltage levels are able with 16K of EPROM/ROM. The 80C196KB
shown in Figure 17-13. has 232 bytes of RAM and 8K of EPROM/ROM. A
Vertical Windowing scheme has been implemented
Description Location Value to allow the extra 256 bytes of RAM to be accessed
as Registers. See Section 3.3.
Signature Word 70H 879CH
2. The 80CI96KC has an additiomil 2 PWM outputs
Programming Vee 72H 040H over the SOCI96KB. See Section S.O.
5.0V
3. The SOCI96KC has the Peripheral Transaction Serv-
Programming Vpp 73H OAOH
er (PTS), which can greatly reduce interrupt servic-
12.50V ing overhead. See Section 6.0.
Figure 17-13. Signature Word and Voltage Levels 4. Timer2 can now be clocked internally as well as ex-
ternally. Timer2 can clock internally every I or S
states selectable by software. See Section 7.0.
Erasing the 87C196KC
5. The HSO has one new command that allows all of
After each erasure, all bits pf the 87C 196KC are logical the pins to be addressed simultaneously. See Section
"Is". Data is introduced by selectively programming 10.0.
"Os". The only way to change a "0" to a "I" is by 6. The A/D on the SOCI96KC has an S-bit conversion
exposure to ultraviolet light. mode as well as IO-bit. Also, the A/D has selectable
sample and convert times. See Section 12.0.
The erasure characteristics of the 87C196KC are so
that erasure begins upon exposure to light with wave- 7. The SOC196KC has 2 UPROM (unerasable pro-
lengths shorter than approximately 4OOOA. It should be grammable read only memory) for additional securi-
noted that sunlight and certain tYl?es of fluorescent tyenhancements. See Section 17.5.
lamps have wavelengths in the 3000A-4000A range.

Opaque labels must always be placed over the Window 1S.2 Converting SOC196KB Designs to
to prevent unintentional erasure. In the Powerdown SOC196KC Designs
Mode, the part will draw more current than specified if
the EPROM window is exposed to light. 1. Clock Detect Enable Pin (CDE) -The CDE pin on
the SOCI96KB is a Vss pin on the SOCI96KC. An
The recommended erasure procedure for the extra VSS pin was needed on the SOC196KC to sup-
87C196KC is exposure to ultraviolet light which has a port the higher clock rates.
wavelength of 2537A.

5-102
 BOC196KC USER'S GUIDE

2. DJNZW tnstruction -The DJNZW will work 6. EPROM Programming Modes -Gang Program-
properly on the SOC196KC. However, it will take 6/ ming with the Slave Programming Mode is no longer
10 state times rather than 5/9 state times as on thj: supported. Also, the Auto-Programming and Slave
SOC196KB. Programming Modes have been modified to support
3. Internal Reset Pulse -The Reset pulse on' the the 16K of onboard memory. This should only affect
SOC196KC has been increased to 16 state times. manufacturers of EPROM programmers, and should
There are 2 ways a SOC196KB or SOC196KC can not have an impact on the end user.
internally assert the RESET pin; Watchdog Timer 7. AID Converter -An AID conversion takes 1.5
Overflow, and a RST instruction. On the KB, the state times less on the SOC196KC in both the fast
Reset Pulse is 4 state times. Because the SOC196KC and slow conversion modes.
and future proliferations will run at much higher fre- S. HOLDIHLDA -The RD, WR, WRC, INST,
quencies, a 4 state time reset pulse was deemed un- BHE, ADV arid ALE pins are weakly held in their
reasonably small. This should cause no problems in inactive states during HOLD on the SOC19,6KC. On
most applications. the SOC 196KB, only ALE is weakly held during
4. Memory Map -Because the' SOC196KC has 16K of HOLD.
EPROM/ROM and 512 bytes of RAM, twice that of 9. The PSW -The PSW on the SOC196KC has an ex-
the SOC196KB, the memory map is different to ac- tra bit (PSE) to support the PTS. This bit was re-
commodate the extra memory. Locations 100- served on the SOC196KB.
1FFH contain the additional 256 bytes of RAM on
the SOC196KC. On the EPROM/ROM versions,lo- 10. HSO -HSO commands OCH and ODH were re-
cations 4000-5FFFH contain the extra SK of served on the SOC196KB. On the SOC196KC, OCH
EPROM. becomes a new command.
5. ONCE Mode Entry -The SOC196KC enters the 11. WSR -WSR bits that were reserved to 0 on the
ONCE mode by holding the TXD pin low on the SOC196KB must be 0 to be SOC196KC compatible.
rising edge of RESET. See Section 15.3.

5-103
 8XC196KC
; 16.-BITHIGH·PERFORMANCE CHMOS
MICROCONTROLLER
87C196KC-16 Kbytes of On-Chip EPRO,.,
." 80C196KC-ROMless .

• 232
16 MHz 0p,eratI9n
• Dynamically Conflgurable 8-Bit or
16~Blt Buswidth
• 256 Byte Register File
• Full Duplex Serial Port
• Register-ta-Reglster
Bytes of Additional R~M

•
• 28 Interrupt Sources/16 Architecture
•
High Speed I/O Subsystem
16-Bit Timer
• Peripheral Transaction Server
Vectors
• 16-Bit Up/Down Counter with Capture
• 1.75 ,."s 16 x 16 Multiply (16 MHz) • 3 Pulse-Width-Modulated Outputs
•• 13.0,."s 32/16.Divide (16 MHz) • Four 16~Bit Software Timer:s

• Five
Powerdown and Idle Modes • 8- or 10-Bit A/D Converter with·
Sample/Hold
• 16-Bit8-Blt I/O Ports
• HOLD/HLDA Bus 'Protocol
• VVatchdog Timer • OTP One-Time Programmable Version
The 80C196KC 16-bit microcontroller is a high performance member of. the MCS®-96 microcontroller family.
The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM, 16 MHz operation ~nd an optional
16 Kbytes of ROM/EPROM. Intel's CHMOS IV process provides a high performance procesSor along with low
power consumption.
The 87C196KC is an 80C196KC with 16 Kbytes on-chip EPROM. In this document, the 80C196KC will refer to
all products unless otherwise stated.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
'.,,' available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an AID conversion. Events can be based on the timer or up/down counter.

VREF ANGND

CONTROL
SIGNALS

PORT 3

} ~~:
BUS •

PORT 4

I;~~~~PWMI
~PWM2
HSO
270942-1
Figure 1. 80C196KC Block Diagram

MCS$-96 is a regist~red trademark of Intel Corporation ..

November 1990
Order Number: 270942-001
inter 8XC196KC

80C196KC Enhanced Feature Set over the 80C196KB

1. The 80C196KC has twice the RAM and twice the ROM/EPROM of the 80C196KB. Also, a Vertical Register
Windowing Scheme allows the extra 256 bytes of RAM to be used as registers. This greatly reduces the
context switching time.
2. Peripheral Transaction Server (PTS). The PTS is an alternative way to service an interrupt, reducing latency
and overhead. Each interrupt can be mapped to its PTS channel, which acts like a DMA channel. Each
interrupt can now do a single or block transfer, without executing an Interrupt service routine. Special PTS
modes exist for the AID converter, HSI, and HSO.
3. Two extra Pulse Width Modulated outputs. The 80C196KC has added 2 PWM outputs that are functionally
compatible to the 80C196KB PWM.
4. Timer2 Internal Clocking. Timer2 can now be clocked with an internal source, every 1 or 8 state times.
5. The AID can now perform an 8- as well as a ,10-bit conversion. This trades off resolution for a faster
conversion time. '
6. Additional On-chip Memory Security. Two UPROM (Uneraseable Programmable Read Only Memory) bits
can be programmed to disable the bus controller for external code and data fetches. Once programmed,' a
UPROM bit cannot be erased. By shutting off the bus controller for external fetches, no one can try and
gain access to your code by executing from external memory.
7. New Instructions. The 80C196KC has 5 new instructions. An exchange (XCHB/XCHW) instruction swaps
two memory locations, an Interruptable Block Move Instruction (BMOVI), a Table Indirect Jump (TIJMP)
instruction, and two instructions for enabling and disabling the PTS (EPTS/DPTS).

The 80C196KC User's Guide contains a complete desCiription of the feature set, order # 270704.

PACKAGING
QFP PLCC QFP PLCC QFP PLCC
Description Description Description
Pin# Pin# Pin# Pin# Pln# Pin#
1 59 AD1/P3.1 28 15 EXTINT IP2.2 55 36 VSS
2 60 ADO/P3.0 29 Vcc 56 37 Vpp
3 61 RD 30 16 RESET 57 38 P2.7/T2CAPTURE
4 62 ALE/ADV 31 17 RXD/P2.1 58 39 PWMO/P2.5
5 63 INST 32 18 TXD/P2.0 59 40 WR/WRL
6 64 BUSWIDTH 33 Vss 60 41 BHE/WRH
7 65 CLKOUT 34 19 P1.0 61 42 T2RST/P2.4
8 66 XTAL2 35 20 P1.1 62 43 READY
9 67 XTAL1 36 21 P1.2 63 N.C.
10 Vss 37 22 P1.3/PWM1 64 44 T2CLK/P2.3
11 68 Vss 38 23 P1.4/PWM2 65 45 AD15/P4.7
12 Vec 39 24 HSI.O 66 46 AD14/P4.6
13 1 Vcc 40 25 HSI.1 67 47 AD13/P4.5
14 2, EA 41 26 HSO.4/HSI.2 68 48 AD12/P4.4
15 3 NMI 42 N.C. 69 49 AD11/P4.3
16 4 ACH3/PO.3 43 27 HSO.5/HSI.3 70 50 AD10/P4.2
17 5 ACH1/PO.1 44 28 HSO.O 71 51 AD9/P4.1
18 6 ACHO/PO.O 45 29 HSO.1 72 52, AD8/P4.0
19 7 ACH2/PO.2 46 30 P1.5/BREQ 73 53 AD7IP3.7
20 8 ACH6/PO.6 47 31 P1.6/HLDA 74 54 AD6/P3.6
21
22
9 ACH7/PO.7
N.C.
48
49
32
33
P1.7/HOLD
P2.6/T2UP-DN
75
76 55
N.C.
AD5/P3.5 .
23 10 ACH5/PO.5 50 34 HSO.2 77 56 AD4/P3.4
24 11 ACH4/PO.4 51 Vss 78 57 AD3/P3.3
25 12 ANGND 52 Vce 79 N.C.
26 13 VREF 53 35 HSO.3 80 58 AD2/P3.2
27 14 Vss 54 Vss

N.C. = No Connection
Figure 2. Pin Definitions
5-105
inter 8XC196KC

"- CD
'" C! 0 '"0
0 00..
00. ~ 0 :t:
I~«
Q..'Q.. 0- 0-
'- '- '- '- '- '-, 5 Q , ,
"-
u u '"
:J:
CD
:J: '"
:J:
0
:J: ,:J: :J:
:;
11)« '" 0 i::>
...J
~ ""U
(I) 0-'-
« « « « « ~ ~
U U U
I~ ~ 11)1-
> x x
...J
III ~ ~Ifi

ACH5/PO.5 ADO/P3.0
ACH4/PO.4 AD1/P3.1
ANGND AD?/P3.2
VREF AD3/P3.3
VSS AD4/P3.4
EXTINTjP2.2 AD5/P3.5
RESET AD6/P3.6
RXD/P2.1 AD7/P3.7
TXD/P2.D AD8/P4.0
PI.O 51 AD9/P4.1
Plol TOP VIEW AD10/P4.2
PI.2 ADll/P4.3
LOOKING DOWN ON
PWMI/Pl.3 ADI2/P4.4
PWM2/PI.4
COMPONENT SIDE ADI3/P4.5
HSIO OF PC BOARD ADI4/P4.6
HSII ADI5/P4.7
HSI2/HS04 T2CLK/P2.3
27 28 29 30 31 32 33 34 35 3637 38 39 40 41 42 43

o(I)
"' 0
0
(I)
~:t:

'"iii
J:

270942-2

Figure 3. 6a·Pin PLCC Package

Table 1. Prefix Identification

QFP PLCC
80C196KC I S80C196KC I N80C196KC
87C196KC
'OTP Version
I S87C196KC' I N87C196KC •

5-106
inter 8XC196KC

aD-Pin Quad Flat Pack (EIAJ)

Contacts Contacts
Facing Up Facing Down
PIN NO.1 IotARK
65 80 80 65

64 64

41 41

40 25 25 40
270942-39

Top View

1111111111111111
., ....'" .,.... .... <D on ... ., .... on
0
.... .... '" ....N ;;: ....0
.... .... .... '"
<D <D <D
<D
<D
'" 64 T2CLK/P2.3
AD1/P3.1
63 Vss
ADO/P3.0
62 REAQY
RD 61 T2RST/P2.4
ALE/ADV 4
60 BHE/WRH
INST
59 iVR/WRL
BUSWIDTH
58 PWt.40/P2.5
CLKOUT
57 P2. 7/T2CAPTURE
XTAL2
56 Vpp
XTAL1
55 Vss
VSS 10
54 Vss
Vss 11
53 HSO.3
Vee 12
52 Vee
Vee 13
51 Vss
EA 14
50 HSO.2
Nt.41 15
. 49 P2.6/T2UP/DN
ACH3/PO.3 , 16
48 P1.7/HOLD
ACH1/PO.1 17
47 P1.6/HLDA
ACHO/PO.O 18
46 P1.5/BREO
ACH2/PO.2 19
45 HSO.1
ACH6/PO.6 20
44 HSO.O
ACH7/PO.7 21
43 HSO.5/HSI.3
N.C. 22
42 Vss
ACH5/PO.5 23
., .... ., ... on .... ., 41 HSO.4/HSI.2

'" '"'" '" '" '"'" '" '" '"'" ...

'" 0
;;; N 0

'"'" '"
ACH4/PO.4 24 N N N N

lllllllllllllll!
270942-40

Figure 4. aD-Pin Quad Flat Pack (QFP)

5-107
inter 8XC196KC

PIN DESCRIPTIONS
Symbol Name and Function
Vee Main supply voltage (5V).
Vss Digital circuit ground (OV). There are three Vss pins, all of which must be connected.
VREF Reference voltage for the A/D converter (5V). VREF is also the supply voltage to the analog
portion of the AID converter and the logic used to read Port O. Must be connected for A/D
and Port 0 to function.
ANGND Reference ground for the AID converter. Must be held at nominally the same potential as
Vss·
Vpp Timing pin for the,return from powerdown circuit. Connect this pin with a 1 p.F capacitor to
Vss and a 1 M!l resistor to Vee, If this function is not used Vpp may be tied to Vee. This pin
is the programming voltage on the EPROM device.
XTAL1 Input of the oscillator inverter and of the internal clock generator.
XTAL2 Output of the oscillator inverter.
GLKOUT Output of the internal clock generator. The frequency of CLKOUT is % the oscillator
frequency.
RESET Reset input to the chip.
BUSWIDTH Input for buswidth selection. If GGR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an
8-bit cycle occurs, If GGR bit 1 is a 0, the bus is always an 8-bit bus.
NMI A positive transition causes a vector through 203EH.
INST Output high during an external memory read indicates the read is an instruction fetch. INST
is valid throughout the bus cycle. INST is activated only during e)(ternal memory accesses
and output low for a data fetch.
EA Input for memory select (External Access). EA equal to a TTL-high causes memory
. accesses to locations 2000H through 5FFFH to be directed to on-chip ROM/EPROM. EA
equal to a TTL-low causes accesses to those locations to be directed to off-chip memory.
ALE/ADV Address Latch Enable or ACldress Valid output, as selected by CGA. Both pin options
provide a signal to demultiplex the address from the address/data bus, When the pin is
ADV, it goes inactive high at the end of the bus cycle. ALE/ ADV is activated only during
external memory accesses.
RD Read signal output to external memory. RD is activated only during external memory reads,
WR/WRL Write and Write Low output to external memory, as selected by the GCA. \iVA will go low for
every external write, while WRl will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.
BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCA. BHE =
o selects the bank of memory that is connected to the high byte of the data bus. AO = 0
selects the bank of memory that is connected to the low byte of the data bus, Thus
accesses to a 16-bit wide memory can be to the low byte.only (AO == 0, BHE = 1), to the
high byte only (AO = 1, BHE = 0), or both bytes (AO = 0, SHE = 0), If the WRH function is
selected, the pin will go low if the bus cycle is writing to an odd memory location. SHE/WRH
is valid only during 16-bit external memory write cycles,

5-108
 8XC196KC

PIN DESCRIPTIONS (Continued)

Symbol Name and Function
READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. When the external memory is not being used, READY has no effect.
HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2, and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1, HSO.2,
HSI.3, HSO.4, and HSO.5. Two of them (HSOA and HSO.5) are shared with the HSI Unit.
PortO a-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter.
Port 1 a-bit quasi-bidirectional I/O port.
Port 2 a-bit multi-functional port. All of its pins are shared with other functions in the BOC196KC.
Ports 3 and 4 a-bit bi-directionall/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
HOLD Bus Hold input requesting control of the bus.
HLDA Bus Hold acknowledge output indicating release of the bus.
BREQ Bus Request output activated when the bus controller has a pending external memory
cycle.

5-109
 8XC196KC

MEMORY MAP
OFFFFH
EXTERNAL MEMORY OR I/O
6000H
INTERNAL ROM/EPROM OR
EXTERNAL MEMORY
2080H
RESERVED
205EH
PTSVECTORS
2040H
UPPER INTERRUPT VECTORS
2030H
ROM/EPROM SECURITY KEY
2020H
RESERVED
20l9H
CHIP CONFIGURATION BYTE 0
20l8H
RESERVED
20l4H
LOW~R INTERRUPT VECTORS
2000H
PORT 3 AND PORT 4
lFFEH
EXTERNAL MEMORY
200H
ADDITIONAL RAM
100H
REGISTER FILE AND
EXTERNAL PROGRAM MEMORY
o

19H SP(HI) 19H SP(HI) 19H SP(HI) 19H SP(HI)

18H SP(LO) 18H SP(LO) 18H SP(LO) l8H SP(LO)
17H IOS2 l7H PWMO_CONTROL 17H PWM2_CONTROL l7H
16H 10Sl l6H 10Cl 16H PWM1_CONTROL 16H
15H 10SO l5H , lOCO l5H RESERVED 15H
14H WSR 14H WSR 14H WSR 14H WSR
13H INT_MASKl 13H INT_MASKl 13H INT_MASKl 13H INT_MASKl
12H INT_PENDl 12H INT_PENDl 12H INT_PENDl 12H INT_PENDl
l1H SP_STAT llH SP_CON llH RESERVED l1H
10H PORT2 10H PORT2 10H RESERVED 10H RESERVED
OFH PORTl OFH PORTl OFH RESERVED OFH RESERVED
OEH PORTO OEH BAUD RATE OEH RESERVED OEH RESERVED
ODH TIMER2(HI) ODH TIMER2 (HI) ODH RESERVED ODH T2CAPTURE(HI)
OCH TIMER2 (LO) OCH TIMER2(LO) OCH IOC3' OCH T2CAPTURE(LO)
OBH TIMERl (HI) OBH IOC2 OBH RESERVED OBH
OAH TIMER1 (LO) OAH WATCHDOG OAH RESERVED OAH
09H INT_PEND 09H INT_PEND 09H INT_PEND 09H INT_PEND
08H INT MASK 08H INT MASK 08H INT MASK 08H INT_MASK
07H SBUF(RX) 07H SBUF(TX) 07H PTSSRV (HI), 07H
06H HSI_STATUS 06H HSO_COMMAND 06H PTSSRV(LO) 06H
05H HSI_TIME (HI) 05H HSO_TIME (HI) OSH PTSSEL(HI) 05H
04H HSI_TIME (LO) 04H HSO_TIME (LO) 04H PTSSEL(LO) 04H
03H AD_RESULT (HI) 03H HSI_MODE 03H AD_TIME 03H
02H AD_RESULT (LO) 02H AD_COMMAND 02H RESERVED 02H
01H ZERO_REG (HI) 01H ZERO_REG (HI) 01H ZERO_REG (HI) 01H ZERO REG (HI)
OOH ZERO_REG (LO) OOH ZERO_REG (LO) OOH ZERO_REG (LO) OOH ZERO_REG (LO)
HWINDOW 0 HWINDOW 0 HWINDOW1 HWINDOW15
when Read when Written Read/Write
'Formerly labeled T2CONTROL. or T2CNTC

5-110
inter 8XC196KC

SFR BIT SUMMARY

AD_RESULT LO (02H) HSLMode (03H)

I7 6 15 41 3 2 11 1 0 I
AID CHANNEL NUMBER L HSI•O MODE
HSI.1 MODE
STATIlS:
0= AID CURRENTLY IDLE HSI.2 MODE
X 1 = CONVERSION IN PROCESS HSI.3 MODE
WHERE EACH 2 - BIT MODE CONTROL FIELD
5 X
DEFINES ONE OF 4 POSSIBLE MODES:
AID RESULT:
LEAST SIGNIFICANT 2 BITS 00 8 POSITIVE TRANSITIONS
01 EACH POSITIVE TRANSITION
10 EACH NEGATIVE TRANSITION
270942-3 11 EVERY TRANSITION
(POSITIVE AND NEGATIVE)
270942-6
AD_COMMAND (02H)

HSI_Status (06H)
r-;;'"] CHANNEL # SELECTS WHICH OF THE 8
1 ANALOG INPUT CHANNELS IS TO BE
CONVERTED TO DIGITAL FORM. ,
2
fo- GO = 1 START NOW HSI.O STATUS
~ fo- GO = 0 START BY HSO COMMAND
4 fo-
I--
=0 10- BIT CONVERSION
= 1 8 - BIT CONVERSION
'-----HSI.1 STATUS
' - - - - - - - - H S I . 2 STATUS
X
' - - - - - - - - - - H S I . 3 STATUS
f0-
X
WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
f0- BIT INDICATES WHETHER OR NOT AN EVENT HAS
X SET UPPER THREE BITS TO ZERO
"- OCCURED ON THIS PIN AND THE UPPER BIT INDICATES
270942-4
THE CURRENT STATUS OF THE PIN.
270942-7

CCR (2018H)
HSO_COMMAND (06H)
IL7161514131211 10 ICHIP CONFIGURATION REGISTER
CHANNEL: 0-5 HSO.O - HSO.5 INDIV1DUALLY
~~OWERDOWN MODE ENABLE 6 HSO.O AND HSO.1
BUS WIDTH SELECT BIT: 0 7 HSO.2 AND HSO.3
(16- BIT BUS/8- BIT BUS) 8-B SOFTWARE TIMERS
'---WRITE STROBE MODE SELECT C HSO -HS05 SIMULTANEOUSLY
(WR ANDBHE IWRL AND WRH) 2 D RESERVED FOR FUTURE USE
E RESET TIMER2
ADDRESS VALID STROBE SELECT F START AID CONVERSION
(ALE I ADV)
INTERRUPT I NO INTERRUPT
(IRCO) }'NTERNAL READY CONTROL SET I CLEAR
(lRC1) MODE
TIMER 2/TIMER 1
(LOCO) }
(LOC1) PROGRAM LOCK MODE LOCK CAM
270942-8
270942-5

5-111
 8XC196KC

SP_CON (llH)
BIT. 1,BIT.O SPECIFY THE MODE
0.0 = MODE 0 1.0 = MODE 2
0: 1 = MODE 1 1. 1 = MODE3

PEN ENABLE THE PARITY FUNCTION RECEIVE OVERRUN ERROR

W
R 'REN ENABLES THE RECEIVE FUNCTION: TRANSMITIER' EMPTY
I
T 4 TBB PROGRAMS THE 9TH DATA BIT FRAMING ERROR
E
5 TRANSMIT, INDICATOR

6 RECEIVE INDICATOR

7 RECEIVE PARITY ERROR

270942-9 270942-30

10SO (15H) 10Sl (l~H)

HSO.O CURRENT STATE SOFTWARE TIMER 0 EXPIRED

HSO.l CURRENT STATE SOFTWARE TIMER 1 EXPIRED

HSO.2 CURRENT STATE SOFTWARE TIMER 2 EXPIRED

HSO.3 CURRENT STATE SOFTWARE TIMER 3 EXPIRED

HSO.4 CURRENT STATE TIMER 2 HAS OVERFLOW

HSO.5 CURRENT STATE TIMER 1 HAS OVERFLOW'

CAM ~ HOLDING REGISTER IS FULL HSI FIFO IS FULL

HSO HOLDING REGISTER IS FULL HSI HOLDING REGISTER DATA AVAILABLE

270942-10 270942-12

lOCO (15H) 10Cl (16H)

HSI.O INPUT ENABLE / DISABLE SELECT PWM / SELECT P2.5

TIMER 2 RESET EACH WRITE EXTERNAL INTERRUPT ACH7 / EXTINT

HSI.l INPUT ENABLE / DiSABi:E TIMER 1 OVERFLOW INTERRUPT ENABLE / DISABLE

TIMER 2 EXTERNAL RESET ENABLE / DISABLE TIMER 2 OVERFLOW INTERRUPT ENABLE / DISABLE

HSI.2 INPUT ENABLE / DISABLE HSO.4 OUTPUT ENABLE / DISABLE

TIMER 2 RESET SOURCE HSI.O / T2RST SELECT TXD / SELECT P2.0

HSI.3 INPUT ENABLE / DISABLE HSO.5 OUTPUT ENABLE / DISABLE

TIMER 2 CLOCK SOURCE HSI.l / T2CLK HSI INTERRUPT

FIFO FULL / "'HO"'L"D""IN"'G"R""E"'GI"'ST""E""R'L"O""ADME"'D
270942-11
270942-13

5-112
 8XC196KC

WSR(14H) IOC2(OBH)

ENABLE FAST INCREMENT OF T2

ENABLE T2 AS UP/DOWN COUNTER
ENABLE /2 PRESCALER ON PWMs
SWITCHES BETWEEN HWINDOWS
AND VWINDOWS ENABLE 80C196KC A/D MODES
A/D CLOCK PRESCALER DISABLE
T2 ALTERNATE INTERRUPT @ 8000H
ENABLE LOCKED CAM ENTRIES
ENABLES HOLD/HOLDA CLEAR ENTIRE CAM
270942-31 270942-33

IOC3 (OCH IN HWINDOW 1) IOS2(17H)

INDICATES WHICH HSO EVENT OCCURED
ENABLE T2 INTERNAL CLOCKING
HSO.O
HSO.l
ENABLE PWMl
ENABLE PWM2 HSO.2
HSO.3

x HSO.4

X HSO.5

X T2RESET

270942-32 START A/D

270942-34

INLPEND/INLMASK (09H/08H) INLPEND1/INLMASKl (12H/13H)

TIMER OVERFLOW TRANSMIT INTERRUPT

A/D CONVERSION COMPLETE RECEIVE INTERRUPT
HSI DATA AVAILABLE , HSI FIFO 4

HIGH SPEED OUTPUTS TIMER 2 CAPTURE

HSI.O PIN TIMER 2 OVERFLOW
SOFTWARE TIMER EXTINT PIN
SERIAL PORT HSI nFO FULL
EXTERNAL INTERRUPT (EXTINT NMI (SET TO 0)
OR PO.7 PIN)
270942-38
270942-37

5-113
 8XC196KC

ELECTRICAL CHARACTERISTICS NOTICE: This data sheet contains information on

products in the sampling and initial production phases
of development. It is valid for the devices indicated in
Absolute Maximum Ratings* the revision history. The specifications' are subject to
change without notice.
Ambient Temperature
• WARNING:. Stressing the, device beyond tlJe "Absolute
Under Bias .............. ; ....... O·C to + 70·C Maximum Ratings" may cause permanent damage.
, Storage Temperature .......... - 65·C to + 150·C These are stress ratings only. Operation beyond the
Voltage On Any Pin to Vss ........ - 0.5V to + 7.0V "Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operating Conditions"
Power Dissipation .......................... 1.5W may affect device reliability.

Operating Conditions
Symbol Description Min Mal( Units
TA Ambient Temperature Under Bias 0 +70 'C
Vee Digital Supply Voltage 4.50 5.50 V
VREF Analog Supply Voltage 4.00 5.50 V
fose Oscillator Frequency 8 16 MHz
NOTE:
ANGND and Vss should be nominally at the same potential.

D.C. Characteristics (Over specified operating conditions)

Symbol Description Min Max Units Test Conditions
Vil Input Low Voltage -0.5 0.8 V
VIH Input High Voltage (Note 1) 0.2 Vee + 1.0 Vee + 0.5 V
VHYS HysteresiS on RESET 150 mV Vee = 5.0V
VIH1 Input High Voltage on XTAL 1 0.7 Vee Vee + 0.5 V
VIH2 Input High Voltage on RESET 2.2 Vee + 0.5 V
VOL Output Low Voltage 0.3 V IOl = 200/J-A
0.45 V IOl = 2.8mA
1.5 V IOl'"' 7 mA
VOL1 Output Low Voltage IOl = +0.4 mA
0.8 V
in RESET on P2.5 (Note 2)
VOH Output High Voltage Vee - 0.3 V IOH = -200/J-A
(Standard Outputs) Vye - 0.7 V IOH = -3.2 mA
Vee - 1.5 V IOH = -7mA
VOH1 Output High Voltage Vee - 0.3 V IOH = -10/J-A
(Quasi-bidirectional Outputs) Vee - 0.7 V IOH = -30 p.A
Vee- 1.5 V IOH =; -60/J-A
VOH2 Output High Voltage IOH = -0.8 mA
2.0 V
in RESET on P2.0 (Note 2)
III Input Leakage Current (Std. Inputs) ±10 /J-A o< VIN < Vee - 0.3V
ILI1 Input Leakage Current (Port 0) ±3 /J-A 0< VIN < VREF
NOTES:
1. All pins except RESET and XTAL 1.
2. Violating these specifications in Reset may cause the part to enter test modes.

5-114
inter 8XC19~KC

D.C. Characteristics (Over specified operating conditions) (Continued)

Symbol Description Min Typ Max Units Test Conditions
ITL 1 to 0 Transition Current (OBO Pins) -650 f!-A VIN = 2.0V
IlL Logical 0 Input Current (OBO Pins) -70 f!-A VIN = 0.45V
IIL1 AD Bus in Reset -70 f!-A VIN = 0.45V

Icc Active Mode Current in Reset 50 70 mA XTAL 1 = 16 MHz

AID Converter Reference Current 2 5 mA Vcc = Vpp = VREF = 5.5V
IREF
IIDLE Idle Mode Current 15 30 mA

IpD PowerdQwn Mode Current 15 TBO f!-A Vcc = Vpp = VREF = 5.5V

RRST Reset Pullup Resistor 6K 65K n Vcc = 5.5V, VIN = 4.0V

Cs Pin Capacitance (Any Pin to VSS) 10 pF

NOTES:
(Notes apply to all specifications)
1. QSD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.
2. Standard Outputs include ADO-15, RD, WR, ALE, SHE, INST, HSO pins, PWM/P'2.5, CLKOUT, RESET, Ports 3 and 4,
TXD/P2.0, and RXD (in serial mode 0). The VO H specification is not valid for RESET. Ports. 3 and 4 are open-drain outputs.
3. Standard Inputs include HSI pins, READY, SUSWIDTH, NMI, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3, and T2RST/P2.4.
4. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below Vcc - 0.7V:
IOL on Output pins: 10 mA
IOH on quasi-bidirectional pins: self limiting
IOH on Standard Output pins: 10 mA
5. Maximum current per bus pin (data and control) during normal operation is ±3.2 mA.
6. During normal (non-transient) conditions the following total current limits apply: .
Port 1, P2.6 IOL: 29 mA IOH is self limiting
HSO, P2.0, RXD, RESET IOL: 29 mA IOH: 26 mA
P2.5, P2.7, WR, SHE IOL: 13 mA IOH: 11 mA
ADO-AD15 IOL: 52 mA IOH: 52 mA
RD, ALE, INST -CLKOUT IOL: 13 mA IOH: 13 mA

70 Icc Max

60

50 IcC Typ

40
mA
30 10LE Max

20
IDLE Typ
10
. 0
4 10 16
ICC Max = 3.88 x FREQ + 8.43 Freq (MHz)
IIDLE Max = 1.65 x FREQ + 2.2 270942-17

Figure 5. Icc and IIDLE vs Frequency

5-115
inter ' 8XQ196KC

A.C. Characteristics
For use .over specified operating conditions. ,
Test Conditions: Capacitive load on all pins = 100 pF, Rise and fall times,., 10 ns, fose = 16 MHz

The system must meet these specifications to work with the 80C196KC- -,
Symbol Description Min Max Units Notes
TAVYV Address Valid to READY Setup 2 Tose - 68 ns

hLYV ALE Low to READY Setup Tose - 70 ns

TYLYH Non READY Time No upper limit ns
TeLYX READY Hold after CLKOUT Low 0 Tose - 30 nsi (Note 1)

hLYX READY Hold after ALE Low Tose - 15 2 Tose - ,40 ns (Note 1)
TAVGV Address Valid to Buswidth Setup 2 Tose - 68 ns
TLLGV ALE Low to Buswidth Setup Tose - 60 ns
TeLGX Buswidth Hold after CLKOUT Low 0 ns
TAVDV Address Valid to Input Data Valid 3 Tose - 55 ns (Note 2)
TRLDV RD Active to Input Data Valid Tose - 22 ns (Note 2)
TeLDV CLKOUT Low to Input Data Valid Tose'- 50 ns
TRHDZ End of RD to Input Data Float Tose ns
TRXDX Data Hold after RD Inactive 0 ns

NOTE:
1. If max is exceeded, additional wait states will occur.
2.lf wait states are used, add 2 Tosc • N, where N = number of wait states.

5-116
inter SXC196KC

A.C. Characteristics (Continued)

For user over specified operating conditions.
Test Conditions: Capacitive load on all pins = 100 pF, Rise and fall times = 10 ns, fosc = 16 MHz

The 80C196KC will meet these specifications:

Symbol Description Min Max Units Notes
FXTAL Frequency on XTAL1 8 16 MHz (Note 1)
Tosc I/FxTAL 62.5 125 ns
TXHCH XTAL 1 High to CLKOUT High or Low 20 110 ns
TCLCL CLKOUT Cycle Time . 2Tosc ns
TCHCL CLKOUT High Period Tosc - 10 Tosc+15 ns
TCLLH CLKOUT Falling Edge to ALE Rising -5 15 ns
TLLCH ALE Falling Edge to CLKOUT Rising -20 +15 ns
TLHLH ALE Cycle Time 4Tosc ns (Note 4)

TLHLL ALE High Period Tosc - 10 Tosc+10 ns

TAVLL Address Setup to ALE Falling Edge Tosc - 15
TLLAX Address Hold after ALE Falling Edge Tosc - 40 ns
TLLRL ALE Falling Edge to AD Falling Edge Tosc - 30 ns
TRLCL RD Low to CLKOUT Falling Edge 4 30 ns
TRLRH . RD Low Period Tosc - 5 ns (Note 4)
TRHLH RD Rising Edge to ALE Rising Edge Tosc Tosc + 25 ns (Note 2)

TRLAZ RD Low to Address Float 5 ns

TLLWL ALE Falling Edge to WR Falling Edge Tosc - 10 ns
TCLWL CLKOLJT Low to WR Falling Edge 0 25 ns
TOVWH Data Stable to WR Rising Edge Tosc - 23 (Note 4)

TCHWH . CLKOUT High to WR Rising Edge -10 15 ns

TWLWH WR Low Period Tosc - 20 ns (Note 4)

TWHOX Data Hold after WR Rising Edge Tosc - 25 ns

TWHLH WR Rising Edge to ALE Rising Edge Tosc - 10 Tosc + 15 ns (Note 2)

TWHBX SHE, INST after WR Rising Edge Tosc - 10 ns

TWHAX AD8-15 HOLD after WR Rising Tosc - 30 ns (Note 3)

TRHBX SHE, INST after RD Rising Edge Tosc - 10 ns

TRHAX AD8-15 HOLD after RD Rising Tosc - 30 ns (Note 3)

NOTES:
1. Testing performed at a MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Assuming back-to-back bus cycles.
3. a-Bit bus only.
4. If wait states are used, add 2 Tose • N, where N = number of wait states.

5-117
 8XC196KC

System Bus Timings

XTAL1

CLKOUT

ALE

BUS

BUS --< ADDRESS OUT

~I-----~
DATA OUT ~\.l(....._A_D_D_RE_S_S_ _ _ __
L tRHBX.
itWHBX '

BHE,INST VALID

AD8-1S ADDRESS OUT

270942-18

5-118
 8XC196KC

READY Timings (One Waitstate)

XTAL1

, CLKOUT

ALE

READY

_-t-_ _ _ _ _ _' - \ . I + - - - tRLRH + 2Tosc ----i---------

tRLDV + 2TOSC =:--:J
1--------- t AvDV + 2Tosc -------1-+1
ADDRESS OUT ) , (~D-A~~)~m~@~-----
~--------.J I

_-t-___________ ~~:.:~~~~--tw-~-H-+--2T-O-SC---~
114-'-- t QVWH + 2Tosc ~
JX
~---AD-D-RE-S-S-OU-T----ft~~(_________D_A_~_O_U_T________ ADDRESS
~----------~l ~-------
270942-20

Buswidth Timings

XTALI

c~:. ~~: Jr-~. )

BUSWIDTH ~------------------------...;...
- .\"""1'----t~AV-r;v.;..-.~-, I
BUS ~ H'-__.J})-------
270942-35

5-119
 eXC196KC

HOLO/HLDA Timings
Symbol . I)escrlptlon Min Max Units Notes
THVCH HOLD Setup 55 ns (Note 1)
TCLHAt: CLKOUT Low to HLDA Low -15 15 ns
TCLBRL CLKOUT Low to BREQ ,Low -15 15 ns
THALAZ HLDA Low to Address Flo~t 10 ns
THALBZ HLDA Low to BHE, INST, RD, WR Weakly Driven 15 ns
TCLHAH CLKOUT Low to HLDA High -15 15 ns
TCLBRH CLKOUT Low to BREQ High -15 15 ns •
THAHAX HLDA High to Address No Longer Float -15 ns
THAHBV HLDA High to BHE, INST, RD, WR Valid -10 ns
TCLLH CLKOUT Low to ALE High -5 15 ns

NOTE:
1. To guarantee recognition at next clock.

D.C. SPECIFICATIONS IN HOLD

Description Min ,Max Units
Weak Pullups on ADV, RD, 50K 250K VCC = 5.5V, VIN = 0.45V
iiVR, iiVRL, BHE
Weak Pulldowns on
10K SOK VCC = 5.SV, VIN = 2.4' '
,I, , ALE,INST

BUS -<'-____
iiilE,lNST ,,
RD,WR

ALE ~r-I~_ _~SII-_ _ _Ic_L_LH_h______

270942-36

S'-120
infeF 8XC196KC

EXTERNAL CLOCK DRIVE

Symbol Parameter Min Max Units
1/TxLXL Oscillator Frequency 8 16.0 MHz
TXLXL Oscillator Period 62.5 125 ns
TXHXX High Time 22 ns
TxLxx Low Time 2~ ns'
TXLXH Rise Time 10 ns
TXHXL Fall Time 10 ns

EXTERNAL CLOCK DRIVE WAVEFORMS

, 270942-21

A.C. TESTING INPUT, OUTPUT WAVEFORM FLOAT WAVEFORM

2.4
0.45~0.8
V 2.0> TEST POINTS < 0.8~
V--2.0

270942-22
A,C, Testing inputs' are driven at 2AV for a Logic "1" and OA5V' 270942-23
for a Logic "0" Timing measurements are made at 2,OV for a For Timing Purposes a Port Pin is no Longer Floating when a
Logic "1" and O,BV for a Logic "0", 100 mV change from Load Voltage Occurs and Begins to Float
when a 100 mV change from the Loaded VOHIVOl Level occurs
IOl/loH ~ ± 15 mA,

EXPLANATION OF AC SYMBOLS

Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.

Conditions: Signals: L- ALE/ADV

H- High A- Address BR-BREO
L- Low B- BHE R- RD
V- Valid C- CLKOUT W- WR/WRH/wRL
x- No Longer Valid D- DATA X- XTAL1
z- Floating G- Buswidth y- READY
H- HOLD 0- Data Out
HA-HLDA

,.5-121
 \ 8XC196KC

A.C. CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE

SERIAL PORT TIMING-SHIFT REGISTER MODE

Symbol Parameter Min Max· Units
TXLXL Serial Port Clock Period (BRR ~ 8002H) 6 Tose ns
TXLXH Serial Port Clock Falling Edge 4 Tose ±50 ns
to Rising Edge (BRR ~ 8002H)
TXLXL Serial Port Clock Period (BRR = 8001 H) 4 Tose ns
TXLXH Serial Port Clock Falling Edge 2 Tose ±50 ns
to Rising Edge (BRR = 8001 H)
TQVXH Output Data Setup to Clock Rising Edge 2 Tose - 50 ns
TXHQX Output Data Hold after Clock Rising Edge 2 Tose - 50 ns
TXHQV Next Output Data Valid after Clock Ri!?ing Edge 2 Tose + 50 ns
TOVXH Input Data Setup to Clock Rising Edge Tose +50 ns
TXHOX Input Data Hold after Clock Rising Edge· 0 ns
TXHQZ Last Clock Rising to Output Float 1 Tose ns

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE

SERIAL PORT WAVEFORM-SHIFT REGISTER MODE

RXD --" ....-ccc".".r .. ·_.".,'.:cc

(IN)_J'-~
270942-24
 8XC196KC

EPROM SPECIFICATIONS

A.C. EPROM Programming Characteristl~s

Auto, Slave Mode Operating Conditions: Load Capacitance = 150 pF, TA = +25·C ±5·C, Vee, VREF =5V,
Vss, ANGND = OV, Vpp = 12.50V ±0.25V, EA = 12.50V ±0.25V

Run Time Programming Operating Conditions: Fosc = 6.0 MHz to 12.0 MHz, VREF = 5V ±0.50V. TA =
+ 25·C to ± 5·C and Vpp = 12.50V. For run·time programming over a full operating range, contact the factory.
Symbol Descrlptlqn . .. Min Max Units
TSHLL Reset High to First PAIl: Low 1100 Tose
TLLLH PALE Pulse Width 50 Tose'
TAVLL Address Setup Time 0 Tose
TLLAX Address Hold Tir:ne 100 Tose
TpLDV ~ Low to Word Dump Valid 50 Tose
TpHDX Word Dump Data Hold 50 Tosc
TDVPL Data Setup Time 0 Tose
TpLDX Data Hold Time 400 Tose
TpLPH(1) ~ Pulse Width 50 Tose
TpHLL ~ High to Next PALE Low 220 Tose
TLHPL PALE High to PRC:m" Low 220 Tose
TpHPL ~ High to Next ~ Low 220 Tose

•
·TpHIL ., ~ High to AINC Low 0 Tose
TILIH 7iJiiIe Pulse Width 240 Tose
TILVH PVER Hold after 7iJiiIe Low 50 Tose
"
TILPL AINC Low to ~ Low 170 Tose
TpHVL PROG High to PVER Valid 220 Tosc

NOTE:
1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm.

D.C. EPROM Programming Characteristics

Symbol Description
Ipp Vpp Supply Current (When Programming)

NOTE:
Vpp must be within 1V of Vee while Vee < 4.5V. Vpp must not have a low impedance path to ground of VSS while
Vee> 4.5V.

5-123
 EPROM PROGRAMMING WAVEFORMS

SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITt! S.INGLE PROGRAM PULSE

PORTS
3/4
--+-0---<
----r---- ADDR/COt.tt.tAND ,

PVER

270942-27

SLAVE PROGRAM MODE IN WORD DUMP WITH AUTO INCREMENT

.
RESEt
I,
--'
I ADDR I ADDR+2
P(lRTS
3/4
ADDR/COMMAND VER BITS/WD DUMP VER BITS/WD DUMP
-
I--- tSHLL - - tPLDV -
~ -00 tPHDX 1-, KtPLDV - tPHDX -

PALE
\

I V
-" "
PROO
tlLPL -tPHPL-
"

AINC
\ ' " "

270942-28

5·124
inter 8XC196KC

SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITWREPEATED PROGPULSE AND

AUTO INCREMENT . .

PO:;~ ---_-« AOOR/COMMANO' >---< AOOR

OATA
AOOR '

>>----~
AOOR + 2

OATA >--

PVER

27Q942-29

5-125
 8XC196K:C

10-811 AID CHARACTERISTICS of VREF. VREF must be close to Vcc since it supplies
both the resistor ladder and the digital section of the
The speed of the AI D' converter in the 10-bit mode converter.
can be adjusted by setting a clock prescaler on or'
off. At high frequencies more time is needed for the
comparator to settle. The maximum frequency with AID CONVERTER SPECIFICATIONS
the clock prescaler disabled is 6 MHz. The conver-
sion times' with the prescaler turned on or off is The specifications given below assume adherence
shown in the table below. The following specifica- , to the Operating Conditions section of this data
tions are tested @ 16 MHz with OC7H in AD_TIME. , sheet. Testing is performed with VREF = 5.12V.

The converter is ratiometric, so the absolute accura-

cy is dependent on the accuracy and stability

Clock Prescaler On Clock Prescaler Off Sample Time I Conv~rt Time

IOC2.4 = 0 IOC2.4 = 1 24 States 80 States
156.5 States 89.5 States C7H in AD __TIME
19.5 JLS@ ,16 MHz 29.8 JLs @ 6 MHz 13.3125 JLs @ 16 MHz

Parameter Typical(3) Minimum Maximum Units· Notes

Resolution 1024 1024 Levels
10 10 Bits
Absolute Error' 0 ±3 LSBs
Full Scale Error 0.25 ± 0.5 LSBs
Zero Offset Error 0.25 ± 0.5 LSBs
Non-Linearity 1.0 ± 2.0 0 ±3 LSBs
Differential Non-Linearity Error > -1 +2 LSBs
Channel-to-Channel Matching ±0.1 0 ±1 LSBs
Repeatability ±0.25 LSBs
Temperature Coefficients:
Offset 0.009 LSBrc
Full Scale 0.009 LSBrC
Differential Non-Linearity 0.009 LSB/oC
Off Isolation -60 dB 1,2
Feedthrough -60 dB 1
Vcc Power Supply Rejection -60 dB 1
Input Resistance 750 1.2K n
D.C. Input Leakage 0 3.0 JLA
Sample Time: Prescaler On 16 States
Prescaler Off 8 States
Input Capacitance 3 pF

NOTES:
'An "LSB", as used here, has a value of approximately 5 mY.
1, DC to 100 KHz,
2. Multiplexer Break-Before-Make Guaranteed.
3, Typicalvalues are expected for most devices at 25'C.

5-126
 8XC196KC

8-BIT MODE AID CHARACTERISTICS Sample Time Convert Time

The 8-bit mode trades off resolution for a faster con- 20 States 56 States
version time. The AD_TIME register must be used A6H in AD_TIME
when performing an 8-bit conversion. 9.8125 JA-S@ 16 MHz

The following specifications are tested @ 16 MHz

with OA6H in AD_TIME.
Parameter Typical Minimum Maximum Units· Notes
Resolution 256 256 Levels
8 8 Bits
Absolute Error 0 ±1 LSBs
Full Scale Error ±0.5 LSBs
Zero Offset Error ±0.5 LSBs
Non-Linearity 0 ±1 LSBs
Differential Non-Linearity Error > -1 +1 LSBs
Channel-to-Channel Matching ±1 LSBs
Repeatability ±O.25 LSBs
Temperature Coefficients:
Offset 0.003 LSBI"C
Full Scale 0.003 LSBI"C
Differential Non-Linearity 0.003 LSBI"C

NOTES:
'An "LSB", as used here, has a value of approximately 20 mY.
1. Typical values are expected for most devices at 25'C.

80C196KB TO 80C196KC DESIGN 5. During the bus HOLD state, the 80C196KC weak-
CONSIDERATIONS ly holds RD, WR, ALE, BHE and INST in their
inactive states. The 80C196KB only holds ALE in
1. Memory Map. The 80C196KC has 512 bytes of its inactive state.
RAM/SFRs and 16K of ROM/EPROM. The extra 6. A RESET pulse from the 80C196KC is 16 states
256 bytes of RAM will reside in locations 100H- rather than 4 states as on the 80C196KB (Le., a
1FFH and the extra 8K of ROM/EPROM will re- watchdog timer overflow). This provides a longer
side in locations 4000H-5FFFH. These locations RESET pulse for other devices in the system.
are external' memory on the 80C196KB.
2. The CDE pin on the KB has become a VSS pin on
the KC to support 16 MHz operation. 80C196KC ERRATA
3. EPROM programming. The 80C196KC has a dif- 1. Absolute maximum voltage on Port 0 is -0.5V to
ferent programming algorithm to support 16K of 9.0V relative to AVss.
on-board memory. When performing Run-Time 2. The HSI unit has two errata: one dealing with res-
Programming, use the section of code on page olution and the other with first entries into the
3-91 of the 1989 16-bit Embedded Controller FIFO.
Handbook. The HSI resolution is 9 states instead of 8 states.
4. ONCETM Mode Entry. The ONCE mode is en- Events on the same line maybe lost if they occur
tered on the 80C196KC by driving the TXD pin faster than once every 9 state times. '
low on the rising edge of RESET. The TXD pin is There is a mismatch between the 9 state time HS"i
held high by a pullup that is specified at 1.4 mA resolution and the 8 state time timer. This causes
and remain at 2.0V. This Pullup must not be over- one time value to be unused every 9 timer counts.
ridden or the 80C196KC will enter the ONCE
mode.
inter " 8XC,196KC

Events may receive's time:tagon one count later later than the firs~ ,time tag. If this is the ':skipped"
than expected because of this '''skipped;' time val- time value, tlie second event's time-tag is 2
ue. counts later than the first's.
If the first two eventsintb an empty FIFO (not If the FIFO and Holding Register are empty, the
including the Holding Register) occur in the same first event will transfer into the Holding Register
internal phase, both are recorded with one time- atter8 state times, leaving the FIFO empty again.
tag. Otherwise, if the second event occurs within If the second event occurs after this time, it will
9 states after the first, its time-tag is one count act as a new first event into an empty FIFO.

DATA SHEET REVISION HISTORY

This data sheet is valid for devices with a "C" at the end of the topside tracking number. Data sheets are
changed as new device information becomes available. Verify with your local Intel sales office that you have
the latest version before finalizing a design or ordering devices.

The following differences exist between this data sheet and 270741-003.
1. ONCE MODE VIL errata removed.
2. VREF Min changed from 4.5V to 4.0V.

The following differences exist between the -002 and -003 versions of data sheet 270741.
1. 80-Pin QFP package added, 68-pin Cerquad package deleted.
2. The following D.C. Characteristics were added:
VHYS RESET Hysteresis spec added
IIL1, AD BUS in RESET current Max added
3. The following A.C. Characteristics were changed:
TAVYV Max from 2Tasc-75 to 2Tasc-68
T AVGV Max from 2Tasc-7 5 to 2Tasc-68
TWLWH Min from Tasc-30 to T asc-20
TXHCH Min changed from 30 ns to 20 ns
'rHALBZ Max changed from 10 ns to 15 ns
4. Under 10-bit AID Characteristics:
Sample Time/Convert Time Testing Conditions added.
Typical values added for Full Scale Error, Zero Offset Error, Non-Linearity, and Channel-to-Channel Match-
ing.
Max Absolute Error changed from ± 8 to ± 3 LSBs
Max Non-Linearity changed from ± 8 to ± 3 LSBs
5. Under 8-bit Mode AID Characteristics;
Max Absolute Error changed from ± 2 to ± 1 LSBs
Max Non-Linearity changed from ± 2 to ± 1 LSBs
Typical Full Scale Error changed from ± 1 to ±0.5 LSBs
Typical Zero Offset Error changed from ± 2 to ± 0.5 LSBs
6. The minimum freqUency at which the device is tested was changed to 8.0 MHz from 3.5 MHz. Thus, data
sheet specifications are guaranteed from 8 MHz to 16 MHz. However, the device is static and will function
below 1 Hz.
7. The T2CONTROL (T2CNTC) SFR was renamed IOC3.
S. ONCE MODE VII: errata added. Other errata removed.
9. The A:Step device corresponding to data sheet 270741-002 had bits IOC1.4 and IOC1.6 reversed. The
problem was corrected in the B-1 Step device corresponding to data sheet 270741-003.

5-128
 8XC196KC

DATA SHEET REVISION HISTQRY (Gon~inued~,

The following are the important differences between the -001 and -002 versions of data sheet 270741. Please
review this revision history carefully. " '
1. The 83C196KC (ROM) was added to the product line.
2. The OTP version of the EPROM was added to the product line.
3. RClli5/HLOA Specifications were ,added.
4. The IOL test condition on VOl1 has changed to -0.5 mA from -0.4 mAo
5. The IOH test condition VOH2 has changed to 0.8 mA from 1.4 mA.
6. BMOVi errata w~s added.,
7. Errata was added for the 'HSI resolution arid first event anomalies.
8. Errata was added for the serial port Framing Errbr anomaly.
(" 1

5-129
 ','. "

8XC196KC
16-BIT MICROCONTROLLER
. EXPRESS
87C196KC-16 Kbytes of On-Chip EPROM
80C196KC-ROMless
83C196KC-16 Kbytes of On-Chip ROM

• (-Extended Temperature Range

40°C to + 85°C) • Dynamically Configurable 8-Bit or
16-Bit Buswidth .

• 232
16 MHz Operation
• Full Duplex Serial Port

• 256 Byte Register File

• High Speed I/O Subsystem

• Register-to-Register Architecture
Byles of Additional RAM
• 16-Bit Up/Down Counter with Capture
16-BitTimer

• 28 Interrupt Sources/16 Vectors • 3 Pulse-Width-Modulated Outputs

• Peripheral Transaction Server • Four 16-Bit Software Timers
• 1.75 J-ts 16 x 16 Multiply (16 MHz) • 8- or 10-Bit A/DConverter with
• 3.0 • Sample/Hold
• Powerdown
J-ts 32/16 Divide (16 MHz)
• HOLD/HLDA Bus Protocol
• Five 8-Bit I/O Ports
and Idle Modes
•
• OTP One-Time Programmable Version

• 16-Bit Watchdog Timer

With the commercial standard temperature range operational characteristics are guaranteed over the temper-
ature range of O°C to + 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40°C to + 85°C.

Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.

All A.C. and D.C. parameters in the commercial data sheets apply to the Express devices.

CONTROL
SIGNALS

PORT 3

} ~f:
BUS

PORT"

1~~~~~PW~l
~PW~2
270794-1
Figure 1. 8XC196KC Block Diagram

MCS®-96 is a registered trademark of Intel Corporation.

November 1880
5-130 Order Number: 270794-001
intJ 8XC196KC EXPRESS.

PACKAGING
The 80C196KC is 8vailablein a 68-pin PLCC package and 87C196KC is available fn a 68-pin Cerquad pack-
age. Contact your looal sales office to determine the ~xact orde~ing code for., the part desired. .

Pin Description Pin. Description Pin Description

9 ACH7/PO.7, ,
. - 54 AD6/P3.6
'.
.. 31 P1.61HLDA
8 . ACH6/PO.6 53 AD7/P3.7 30 , P1.5/BFiEO
7 ACH2/PO.2 52 AD8/P4.0 29 HSO.1
6 ACHO/PO.O 51 AD9/P4.1 28 HSO.0
5 ACH1lPO.1 50 \", A010(P4,2 . 27 ,-'.I .HSQ.Sj'1SI.3
4 ACH3/PO.'3 49 AD11/P4.3 .26 HSO.4/HSI.2
3 NMI 4$ AD12/P4.( , 25 HSI.1.
2 EA 47 AD13/P4.5. 24 HSI.O
1 'vdc ' 46 AD·14/P4.6 23 P1A/PWM2
68 Vss 45 AD15/P4.7 ~2 P1.3tPWM1
67 XTAL1 44 T2CLK/P2.3 21 P1.2
66 "X-r:AL2 43 . READY 20 P1.1
65 CLKOUT 42 T2RST/P2.4, 19 P1.0'
64 SUSWIDTH 41 SHE/WRH 18 TXD/P2.0
63 INST 40 WR/WRL 17 RXD/P2.1
62 ALE/ADV' 39 PWMO/P2.5 16 RESET
61 Pm: 38 P2.7/T2CAPTURE 15 . EXTINT/P2.2
60 ADO/P3.n' 37. Vpp 14 Vss
59 AD1/P3.1 36 Vss' 13 'VREF
58 AD2JP3.2 35 HSO.3 12 ANGND'
57 AD3/P3.3 34 HSO.2 11 ACH4/P.04
56 AD4/P3.4 33 P2.6/T2UP-DN 10 ACH5/P.05
55 AD5/P3.5 32 P1.7/HOLD
Figure 2. Pin Definitions

Table 1. Prefix Identification

Cerquad PLCC

98765.3, I~D~~~~~~
80C196KC TN80C196KC
ACHS/PO.5 60 ADO/P30
ACH4/PO ...
83C196KC TN83C196KC
ANGND 12
87C196KC TJ87C196KC TN87C196KC'
Vss 'OTP VersIon
EXTINT/P2.2 15
RESET 16 AD6/P3.e
RXD/P2.1 17 "'07/P3.?
TXOjP2.Q 18 52 AD8/P4.0
P1.0 51 AD9/P4.1
Pl.1 TOP VIEW 50 ADIO/P.2
ADfl/P •. 3
LOOKING DOWN ON
PWW1/P13 22 AD12/P44
COMPONENT SIDE 47 ...OI3/P45
OF PC BOARD 46 ADI4/P4.6
HSI1 25 45 AOISiP4.?
HS12/HS04 26 44 T2CLK/P2".3
D~~~~.~M~~D~~~~aa

270794-2

Figure 3. 68-Pin Cerquad and PLCC Package

5-131
 EV80C196KC FEATURES·
• Zero Wait-State 16 MHz Execution Speed
• 24K Bytes of ROMsim
• Flexible Wait-State, Buswidth, Chip-Select Controller
• Totally CMOS, Low Power Board
• Concurrent Interrogation of Memory and Registers
• Sixteen Software Breakpoints
• Two Single Step Modes
• High-Level Language Support
• Symbolic Debug .
• RS-232-C Communication Link
LOW COST CODE EVALUATION TOOL
Intel's EV80C196KC evaluation board provides a hardware environment for code
execution and software debugging at a relatively low cost. The board features the
80C196KC advanced, CHMOS*, 16-bit microcontroller, the newest member of the
industry standard MCS®-96 family. The board allows the user to take full advantage of
the power of the MCS-96. The EV80C196KB provides zero wait-state, 16 MHz execution
of a user's code. Plus, its memory (ROMsim) can be reconfigured to match the user's
planned memory system, allowing for exact analysis of.code execution speeds in a
particular application.
~CHMOS is a patented Intel process.
"IBM PC, XT, AT and DOS are regIstered trademarks of Intemahonal Busmess Machines Corporation.

inter---------'----'--------
Intel Corporation assumes no responsibihty for the use of any circuitry other than circuitry embodies in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
APRIL 1989
@ Intel Corporation 1989 Order number: 270802-001
5-132
Popular features such as a symbolic single line assembler1disassembler, single-step
program execution, and sixteen software breakpoints are standard on the EV80C196KC
Intel provides a complete code development environment using assembler (ASM-96) as
well as high-level languages such as Intel's iC-96 or PL/M-96 to, accelerate development
schedules.

The evaluation board is hosted on an IBM PC·· or BiOS-compatible clone, already a

standard development solution in most of today's engineering environments. The source
code for the on-board monitor (written in ASM-96) is public domain. The program is
about 1K, and can be easily modified to be included in the user's target hardware, In this
way, the provided PC host software can be used throughout the development phase.

FULL SPEED EXECUTION

The EV80C196KC executes the user's code from on-board ROMsim at 16 MHz with zero
wait-states. By changing crystals on the 80C196KC any slower execution speed can be
evaluated. The boards host interface timing is not affected by this crystal change.

24K BYrES OF ROMSIM

The board comes with 24K bytes of SRAM to be used as ROMsim for the user's code and
as data memory if needed. 16K bytes of this memory are configured as sixteen bits wide,
and 8K bytes are configured as eight bits wide. The user can therefore evaluate the speed
of the part executing from either buswidth.

FLEXIBLE MEMORY DECODING

By changing the Programable Logic Device (PLD) on the board, the memory on the board
can be made to look like the memory system planned for the user's hardware application.
The PLD controls the buswidth of the 80C196KC and the chip-select inputs on the board.
It also controls the number of wait ~ates (zero to three) generated by the 80C196KC
during a memory cycle. These feafures can all be selected with 256 byte boundaries
of resolution.

TOTAtLY CMOS BOARD

The EV80C196KC board is built totally with CMOS components. Its power consumption
is therefore very low, requiring 5 volts at only300 rnA. If the on board LED's are
disabled, the current drops to only 165 rnA. The board also requires + 1- 12 volts at
15mA.

CONCURRENT INTERROGAT10N OF MEMORY AND REGISTERS

The mo~itor for th~ EV80C196KC allows the user to read and modify internal registers
and ext~rnal memory while the user's code is running in the board,

SIXTEEN SOFTWARE BREAKPOINTS

There are sixteen breakpoints available which automatically substitute Ii TRAP
instruction for a user's instruction at the breakpoint location. The substitution occurs
when execution is started. If the code is halted or a breakpoint is reached, the user's cod~
is restored in the ROMsim: ,

5·133
TWO STEP MODES
There are two single-step modes available. The first stepping mode locks out all
interrupts which might occur during the step. The second mode enables interrupts, and
treats subroutine calls and interrupt routines as bne indivisible instruction.

HIGH LEVEL LANGUAGE SUPPORT

The host software for the EV80C196KC board is able to load absolute object code
generated by ASM-96, iC-96, PL/M-96 or RL-96 all of which are available from Intel.

SYMBOLIC DEBUG
The host has a Single Line Assembler, and a Disassmbler, wl;1ich recognize symbolics
generated by Intel software tools. .

RS-232-C COMMUNICATION LINK

The EV80C196KC communicates with the host using an Intel 82510 DART provided on
board. This frees the on-chip DART of the 80C196KC for the user's application.

PERSONAL COMPUTER REQUIREMENTS

The EV80C196KC Evaluation Board is hos~ed on an IBM PC, XT, AT** or BIOS
compatible clone. The PC must meet the following minimum requirements:

• 512K Bytes of Memory

• One 360K Byte floppy Disk Drive
• PC DOS** 3.1 or Later
• A Serial Port (COMI or COM2) at 9600 Baud
• ASM-96, iC-96 or PL/M-96
• A text editor such as AEDIT

RS-232
BUFFERS 80C196K~

CPU
II-----...,Txd
~'-------I Rxd ADDRESS
82510
UART
DIGITAL I/O CONTROL

.Block Diagram of the 80C196KC Board

5-134
MCS®-96 Development 6
Support Tools
 _
I
J1TMSOFTWARE----

ACEi9lP'M SOFTWARE MAKES YOU AN ARCHITECTURAL WIZARD

··-INSTANTLY.
If you want to learn 80C196KB architecture as fast as possible, so that you can
develop hardware and software in parallel, Intel has the perfect solution.
We call it ACE 196TlII Software.
\

PC·BASED SOFTWAR~ TRAINING SPEEDS LEARNING

ACE196™ Software is a PC·Based Expert System that uses artificial intelligence
technology and your PC's high-resolution monitor to guide you through detailed
documentation training. ..
Its ~asy to use and highly graphic, designed to speed up your learning curve - and
. reduce your total design time, no matter what level ofMCS-96 experience you have.
ACE196TlII Software includes:
• A hypertext manual
, . Peripheral design modules
• An assembler editor
It uses "Hypertext" to efficiently present 80C196KB documentation by providing
·highlighted links to related topics. You can follow these links several layers into the
documentation - without having to search through hundreds of cross-referenced
pages.

CONCENTRATE ON APPLICATIONS INSTEAD OF BIT·BY·BIT

PROGRAMMING
After learning the basics of the architecture, you can use the ACE 196Tl11 desigil.
module to program peripherals. So, you can concentrate on application needs versus
bit by bit programming materials. You'll save design time and minimize
programming errors.
Also, ACE196TlII Software generates fully commented initialization code and features
scoreboards to document just how each peripheral has been programmed.
ACE196TlII Software's Assembler editor makes you syntax-literate right away. It
provides templates of over 100 instructions, on line help and automated register
programming and testing.
$ystem requirements: IBM compatible XT or AT**, EGA Monitor, hard disk. 1.2 meg·
floppy drive, 640K memory.

inter~~__~~·.___
. ___.__. _.______ ~_.. _______~_____\_ _
*IBM PC, XT, AT and DOS are registered trademarks of InternatlOnal Business Machines Corporation
Intel CorporatIOn assumes no responSIbility for the use of any cirCUItry other than cirCUItry embodies In an Intel
product. No other Circuit patent licenses are lmplIed InfonnatlOll contamed herem supersedes preVIOusly pubhshed
specifications on these devi«es from Intel
© Intel Corporation 1989

6-1
18096/196 SOFTWARE DEVELOPMENT' PACKAGES 1

280799-1

COMPLETE SOFTWARE DEVELOPMENT SUPPORT FOR THE

8096/196 FAMILY OF MICROCONTROLLERS
Intel supports application development for its 8096 and 80C196 family of
microcontrollers with a complete set of development languages and utilities. These tools
include a macroassembler, a PL/M compiler, a C compiler, linker/relocator program,
floating point arithmetic library, a librarian utility, and an object-to-hex utility. Develop
code in the language(s) you desire, then combine object modules from different languages
into a single, fast program.

FEATURES
• Software Tools support all members of code for execution in target with a
Intel's MCS®-96 family simple, one-step operation
• ASM-96/196 macroassembler for speed • 32-bit Floating Point Arithmetic Library
critical code to reduce your development effort and to.
• PL/M-96/196, packag~ for the allow fast, highly optimized numerics-
maintainability and reliability of a high- intensive processing ,
level language with support for many • Library utility for creating and
low-level hardware functions maintaining software object module
• iC-961196 package for structured C libraries' .
language programming, with many • PROM building utility that converts
hardware specific extensions object modules into standard
• Linker/Relocator program for linking , hexadecimal format for easy download
modules generated in assembler, PL/M into a non-Intel PROM Programmer
or C and assigning absolute addresses to • Hosted on IBM PC XTI AT with PC-DOS
relocatable code. RL-96 prepares your 3.0 or above

November 1990
6-2 Order Number: 280793-001
intJ
.FEATURES

Create and
Molntaln
Llbrories WIth

Compile
WIth I Lli6' VLSICE-96

ICE 196 PC

I
Include
rloatlng Point
LibrarIes With

280793-2

Figure 1. MCS®-96 Application Development Process

ASM·961196 MACROASSEMBLER • Built-in functions. PL/M-96/196 includes
an extensive list offunctions, including
ASM-96/196 is the macroassembler for the
TYPE CONVERSION functions, STRING
MCS-96 family of microcontrollers, incJuding
manipulations, and functions for
the 8OC196. ASM-96/196 translates symbolic
interrogating MCS-96 hardware flags.
assembly language mnemonics into relocatable
object code.
• Interrupt handling. The INTERRUPT
attribute allows you to define interrupt
The macro facility in ASM-96/196 saves handling procedures. The compiler generates
development and maintenance time, since code to save and restore the program status
common code sequences need only be word for INTERRUPT procedures.
developed once. The assembler also supports • Compiler controls. Compile-time options
symbolic access to the many features of the increase the flexibility ofthe PL/M-961196
8096/196 and provides an "include" file with compiler. These controls include: _
all 8096/196 registers defined. optimization, conditional compilation, the
inclusion of common PL/M source files from
PLIM·961196 SOFTWARE disk, cross-reference of symbols, and optional
PACKAGE 'assembly language code in the listing file ..
PL/M-96/196 is a high-level programming • Data types. PL/M-96/196 supports seven
language designed to support the software data types, allowing PL/M-96/196 to perform
requirements of advanced 16-bit three different kinds of arithmetic: signed,
microcontrollers. The PL/M-96/196 compiler unsigned, and floating point.
translates PL/M high-level language • Language compatibility. PL/M-96/196
statements into 8096/196 relocatable object object modules are compatible with all other
code. Major features of the PL/M-96/196 object modules generated by Intel MCS-96
compiler include: translators.
• Structured programming. The PL/M
language supports modular and structured
programming, making programs easier to
understand, maintain, and debug.

6-3
I. FEATURES
/
'iC-961196 SOFTWARE PACKAGE Modules can be written in ASM-96/196,
Intel's iC-96/196 is a structured programming PL/M-96/196, or iC-96/196. The RL-96/196
lltility also promotes programmer producti~ity
language designed to support applications for
by ~ncouraging modular programming.
the 16-bit family of MPS-96 microcontrollers. Because applications can be broken into
iC-96/196 implements the C language as
separate modules, they're easier to design, test
describe,d in the Kernighan and Ritchie book,
The C Programming Language, and includes and maintain. Standard modules can be reused
in different applications, saving software
many of the enhancemen~ as defined by the development time.
proposed ANSI C standard. Major features of
the iC-96/196 compiler include: FPA~96/196 FLOATING POINT
• Symbolics. The iC-96/196 compiler boosts ARITHMETIC UBRARY
. programmer productivity by providing
extensive debug information, including FPAL-961 1~6 is a library of single-precision 32-
symbols. The debug information can be used bit floating point arithmetic functions. These
to debug the code using either the VLSiCE-96 functions are compatible with the IEEE
emulator or the ICETM_196PC emulator. floating point standard for accuracy and
• Architecture Support. iC-96/196 generates reliability and include an error-handler
cOde which is fully optimized for the MCS-96 .library. .
architecture. iC-96/196 provides an UB-96/196
.INTERRUPT attribute, allowing you to
define interrupt handling functions in C, and The Intel LIB-96/196 utility creates and
library routines which allow you to enable maintains libraries of software object modules.
and disable interrupts directly from C (mid- Standard modules can be placed in a librllry,
1989). A REENTRANT/NOREENTRANT and linked into your applications programs
control is alsq included, allowing the using RL-96/196.
compiler to identify non-reentrant OH-£!6/196 .
procedures. This gives you full access to the
large MCS-96 register !let. The OH-96/196 utility converts Intel OMF-96
• Standard language. iC-96J196 accepts object modules into standard hexadecimal
standard C source code. iC-96/196 code is format. This allows the code to be loaded
fully linkable with both PLlM-96/196 and . directly into a P~OM via non-Intel PROM
ASM-96/196modules via an "alien" 'Programmers.
attribute, allowing programmers to utilize
the optimallangilage for any appljcation. In SERVICE, SUPPORT, AND
addition, programmers can quickly begin . TRAINING .
program~ing with iC-96/196 because it Intel augments its 'MCS-96 architec~ure family
conforms to accepted C language standards. development tools with a full array of
seminars, classes, and· workshops; on-site
R~96/19.6 L{NKER/RELOCATOR consulting services; field application
Intel's RL-196 utility is used to link multiple engineering expertise; telephone hot-line
MCS-96 object modules into a single program support; and software and hardware
and then assign absQIute addresses to all maintenance contracts. This full line of
relocatable addresses in the new program. services will ensure your design success.

ORDERING lNFORMATIONI
D86ASM96* 961196 Assembler for PC XT or D86C96· iC-96/196 Software package fQr
AT system (or compatible), PC XT or AT system (or .
running DOS 3.0 or higher compatible), ru~ing.DOS 3.0 or
D86PLM96" PL/M-96/196 Software Package higher. . .
for PC XT or AT system (or
compatible), running DOS 3.0 or
higher'
•i\Jso I~cludes: Relocator/LiDke~, Objecf;.to-hex converter, Floating Point Arithmetic Library, and Librarian.

6-4
 VLSiCETM-96 IN-CIRCUIT EMULATOR

280794-1

IN-CIRCUIT EMULATOR FOR THE 8X9 X FAMILY OF

MICROCO!VTROLLERS I

The VLSiCETM-96 emulator is a complete hardware/software debug environment for

developing systems based on the Intel 8 X 9 X family of microcontrollers. The VLSiCE-96
emulator supports all NMOS members ofIntel's MCS-96 microcontrollers, including the
8096BH, the 8098, the 8095, the 8097, and the 8096-90. With high performance 12 MHz
emulation, symbolic debugging, and flexible memory mapping, the VLSiCE-96 emulator
expedites all stages of development: software development, hardware development,
system integration: and system test.

FEATURES
• Real-time transparent emulation, up to • Symbolic debugging for faster and easier
12 MHz access to memory location and program
• 64K of mappable memory to allow early variables
software debug and (EP)ROM • Fast breaks and dynamic trace to allow
simulation, even before any target the user to modify and interrogate
hardware is available memory, and access the trace buffer
• Trace contains execution address, without stopping emulation
opcode, symbolics, and bus information • On-line Help me to speed development
• 4K frame trace buffer for storing real- • Shadow Registers can read many write-
time execution history only registers and write to many read-
• Ability to break. or trace on execution only registers, allowing enhanced
addresses, opCodes, data values, or flags debugging over component features
values

, November 1990
Order Number: 280794-001
inter
FEATURES
~ Includes 68-pin PGA adaptor; optional 68-pin simply added to the prototype and tested in
I;'LCC and 48-pin DIP adaptors are, also real-time. When the prototype is complete, it is
available ' tested with the final version ,of the system
• Serially hosted on IBM PC AT/XT or software. The VLSiCE-96 emulator'can then be
compatibles with DOS 3.0 or greater used'to verify or debug the target system as a
completed unit.
ONE TOOL FOR ENTIRE Because it SUPPOrtB the ROMlelillil, ROM and
DEVELO~MENTCYCLE ' EPROM versions ofIntel's microcontrollers,
The VLSiCE-96 emulator speeds target system the VLSiCE-96 emulatOr can debug a prototype
develOPment by allowing hardware and or production product at any stage in its
software design to proceed simultaneously; development without introdUcing extraneous
'You can develop software even before hardware or software test tools.
prototype hardware is finished. And becauB,e'
the VLSiCE-96 emulator precisely matches the'
component's electrical and timing ,
characteristics, it's a vaLuable tool for
hardware development and debug.
The VLSiCE-96 emulator also s~plifies and
expediteS system .integratjonand, test. As each
section o( the hl:\rdware is completf;!(i, 'it is
,. ~ " , ',",'

6-6
inter
SPECIFICATIONS I'
HOST REQUIREMENTS Electrical CharacteriBticB
An IBM PC AT/XTor compatible with 512 Power Supply
Kbytes RAM and hard disk. Intel recommends 100V -120V or 200V -240V (selectable)
an IBM PC AT or compatible with 640 Kbytes 50Hz-60Hz
of RAM, one floppy drive and one hard disk 2 amps (AC max) @ 120V
running PC-DOS 3.1 or later. 1 amp (AC max) @ 240V
SYBtem Performance PhYBical CharacteriBticB
l\:Iappable zero wait Mappable to user Controller Pod
state (up to 12 MHz), memory or ICE Width: 8'1." (21 cm)
Min 0 Kbytes, Max memory in 1K blocks Height: 1'/." (4 cm)
64 Kbytes on 1K boundaries Depth: 13'1." (34cm)
Weight: 4lbs (2 kg)
Trace Buffer 4 Kbytes X 48 bits
Power Supply
Virtual Symbol Table A maximum of61 Width: 7%" (18 cm)
Kbytes of host memory Height: 4" (10 cm)
space is available for Depth: 11" (28 cm)
the virtual symbol Weight: 15 lbs (7 kg)
table (VST)._ The rest of
the VST resides on disk User Cllble: 3' (1 m)
and is paged in and out
of host memory as
needed.

Vee BOOSTER MODULE

USER
CABLE
POWER
SUPPLY

TARGET
ADAPTER

280794-2

Figure 1. The VLSiCE·96™ Emulator

6-7
intJ
SPECIFICATIONS

.~.

PIN 1
, !
"-+ •
.0. . . ·
i
.:
:
68 PIN
PLCC ADAPTOR

,
i
.!•
.:
:
: ................. =

~1~L3" yyyyyyyyyyy .

1
0 ,.." ,.."
68 PIN PGA
ADAPTOR

...... ......
C
.......... ::...
PIN 1 ::
3.2"
48 PIN DIP
ADAPTOR

J
L. ...........

0 !.-.J !.-.J

PIN 1
II---' -4.8"---1.1
280794-3

Figure 2. Dimensions for the Emulator Processor Board and Adaptors

Environmental Characteristics SERVICE SUPPORT AND
Operating Temperature: O°C to + 400C ( - 32"F TRAINING
to + 104°F) . Intel augments its MCS-96 architecture family
Operating Humidity: Maximum to 85% development tools with a full array of .
relative humidity, seminars, classes and workshops; on-site
non-condensing consulting services; field application
engineering expertise; telephone hot-line
support; and software and hardware
maintenance contracts. This full line of
services will ensure your design success.

6-8
 ORDERING INFORMATION
V096-KITA VLSiCE-96 Power supply SA096D Software for host, pr~be,
cable, emulation base, user diagnostic and tutorial on 5'/."
cable, Crystal Power Accessory media for use with the PC AT I
(CPA), serial cables for PC AT I XT under PC-DOS VS.O or
XT,a 68-pin PGA target later. (Requires software
adaptor, ASM-96, AEDIT Text license.) (Included with
Editor. Host, probe,diagnostic V096KITA and V096KITD.)
and tutorial software OQ 5,/•• D86C96NL C-96Compiler·
. . media for DOS hosts running
. DOS VS.O or later. (Requires D86PLM96NL PL/l'rf-96 CoI;npiler·
software license.) . D86ASM96NL ASM-96 Macroassembler·
V096KITD Same as V096KITA withou~ • Also Includes: Relocator/Linker, object-tp-hex converter,
librarian, and Floating Point Arithmetic· Library. .
ASM-96 and AEDIT text
editor.
TA096E Optional 68-pin PLCC Target
Adaptor Board
TA096B Optional 48-pin DIP Target
Adaptor Board
MSA96 Optional Multi-Synchronous
Accessory for multi-ICE
capability

6-9
 REAL-TtME TRANSPARENT 80C196 IN-CIRCUIT
EMULATOR

280127-1

REAL-TIME TRANSPARENT 80C196 IN·CIRCUIT EMULATOR

The ICETM-196KB/PC in-circuit emulator delivers real-time high-level debugging
capabilities for developing, integrating and testing 80C196-based designs. Operating at
the full speed of the 8OC196KB microcontroller, the ICE-196KB/PC provides precise 110
pin timings and functionality. The ICE-196KB/PC also allows you to develop code before
prototype hardware is available. The in-circuit emulator represents a low-cost
development environment for designing real-time r.aicrocontroller-based applications
with minimal investment in time and resources.

ICETM·196KBIPC IN·CIRCUIT EMULATOR FEA'rURES

• Real-Time Emulation ofthe 80C196KB • Symbolic Support and Source Code
Microcontroller Display
;, 64K Bytes of Mappable Memory • Standalone Operation
• 2K-entry Trace Buffer • Versatile and Powerful Host Software
• 3 Breakpoints or 1 Range Break • Hosted On IBM PC, XT, AT, or
Compatibles With DOS 3.x

November 1990
6-10 Order Number: 280727-004
 FEATURES
REAL-TIME EMULATION SYMBOLIC SUPPORT AND
The ICE-196KB/PC provides real-time SOURCE CODE DISPLA Y
emulation with the precise input/output pin Full ASM-96, PL/M-96 and iC-96 language
timings and funCtions across the full operating symbolics, including variable typing and scope,
frequencies of the 8OC196KB microcontroller. are supported by the rCE-196KB/PC memory
The ICE-196KB/PC connects to the intended accesses, trace buffer display, breakpoint
8OC196KB microcontroller socket via a 16" specification, and assembler/disassembler.
flex cable, which terminates in a 68-pin PLCC Additionally, iC-96 and PL/M-9~ source code
probe. can be displayed to make development and
debug easier.
MAPPABLE MEMORY
The ICE-196KB/PC has 64K bytes of ze.ro wait- STANDALONE OPERATION
state memory that can be enabled or mapped Product software can be developed prior to
as read-only, write-only or read/write in 4K hardware availability with the optional
byte increments to simulate the internal Crystal Power Accessory (CPA) and the
(EP)ROM ofthe 80C196KB or external ICE-196KB/PC mappable memory. The CPA
program memory. also provides diagnostic testing to assure full
functionality of the ICE-196KB/PC.
TRACE BUFFER
The ICE-196KB/PC contains a 2K entry trace VERSATILE AND POWERFUL
buffer for keeping a history of actual HOST SOFTWARE
instruction execution. The trace buffer can be The ICE-196KB/PC comes equipped with an
conditionally turned off to collect a user on-line help facility, a dynamic command
specified number of trace frames. Trace entry and syntax guide, built-in editor,
information can be displayed as disassembled assembler and disassembler, and the ability to
instructions or, optionally, disassembled customize the command set via literal
instructions and the original iC-96 and definitions and debug procedures.
PL/M-96 source code.
HOSTING
BREAK SPECIFICATION
The ICE-196KB/PC is hosted on the IBM PC·
Three execution address breakpoints or one XT, AT or compatibles with PC-DOS 3.x.
range of addresses can be active at any time.
The ICE-196KB/PC allows any number of
breakpoints to be defined and activated when
needed.
 inter
SPECIFICATIONS
REQUIREMENTS"' ENVIRONMENTAL
, Host CHARACTERISTICS
IBM PC XT, AT (or compatjble) operating Temperature 10·C to 40·C
2K bytes RAM, Hard Disk 37.5·F to 104°F
PC·DOS3.x Operating Humidity Maximum 55%
One Unused Peripheral Slot Relative Humidity,
DC Current 2.5A non-condensing
Note: ICE·196KB/PC uses two bytes ofthe user
stack. ORDERING INFORMATION
TARGET INTERFACE BOARD Order Code Description
Length 2.0" (5.1cm) ICE196KBPC Emulation Board, user.
cable, target interface
Height 1.2" (3.0cm) board (PLCC), host,
Width 2.3" (5.8cm) diagnostic, and tutorial
software on 5 'I." DOS
USER CABLE diskette, and Crystal
Length 15.6" (39.6cm) Power Accessory with
power cable
PROBE ELECTRICAL . ICE196KBPCB Same as above except
80C196KB plus per pin . 50 pf loading does not include Crystal ,
Power Accessory
5ns propagation delay
CPA196KAKB Crystal Po~er Accessory
Icc (from target system) 50 rnA @ 12 MHz and power cable only
Operating Frequency 3.5 to 12 MHz, TA196PLCC68PGA 68-Pin PGA Target
12 MHz only with Adaptor
CPA

6·12
 ICETM_196KB/HX IN~CIRCUIT EMULATOR

280847-1

MODULAR IN-CIRCUIT EMULATOR FOR THE 8xC196KB

FAMILY OF MICROCONTROLLERS
The ICETM_196KB/HX in-circuit emulator delivers a complete, real.time, hardware/
software debug environment for developing, integrating, and testing 8xC196KB-based
designs. The ICE-l96KB/HX emulator is a high-performance modular debugging system '
featuring real-time and transparent 12 MHz emulation, high-level symbolic debugging,
complete execution and bus break/trace capabilities, 128 Kbytes zero-waitstatE! mappable
memory, and emulation trace. The ICE-196KB/MX emulator, a companion entry~level
system, is also available. The ICE-196KB/MX emulator can be upgraded to an ICE-
196KB/HX emulator with optional add-in boards. Both systems feature an identical
human interface, utilize the same base chassis, and are serially hosted on IBM PC XTs,
ATs, and 100% compatibles.

JCETM-196KBlxX IN-CIRCUIT EMULATORS CORE FEATURES

• Precisely matches the component's
electrical and timing characteristics
,. Supports the ROMless and (EP)ROM
versions of the 8xCl96KB
• Does not introduce extraneous hardware
or software overhead
• Modular base for future growth and
migration

ICETM and ONCETM are trademarks of Intel Corporation.

. IBM- and PC AT- are registered trademarks of International Busineaa Machine. Corporation.
PC XTTM i. a tradamark of International Busine.s Machines Corporation.

November 1990
6-13 Order Number: 280847-002
inter, ;

ICETM .. 196KB/HX IN.. CIRCUIT EMULATOR

ICETM-196KBIMX IN-CIRCUIT ICETM-196KBIHX IN-CIRCUIT
EMULATOR FEATURES EMULATOR FEATURES
• Real-time transparent 8xC196KB emulation Includes all features of the ICETM.196KBI
to 12 MHz; inQluding ROM and EPROM MX emulator plus the following;
versions, either in-target or stand,alone • Recognition of bus events (either instruction
• Use of eithertarget system or 64 Kbytes of fetch, data read or write at a specific address
zero-waltsta~e emulator memory for program or range of addresses, or a specific value or
execution range of values)
• Event recognition of up to 255 execution • OR combinations of execution/bus events or
addre~s specifications, either specific or strictly bus events, plus AND combinations
ranges" " of bus events
• Fastbreaks; wherein emulation is • Event counters
immediately broken only for the 'duration of • Conditional arming and disarming of break
a requested memory access specifications
• Single-step execution of machine • A deferred Fastbreak option whereby
instructions, high-level language statements, emulation is broken only after reaching a
or procedure call blocks sp~cified address ,
• Execution trace, 2K frames deep, including • Additional 64 Kbytes (128 Kbytes total) of
address, opcode in hex and mnemonic zero-waitstate emulation memory
formats, and operands in hex and symbolic • The addition of bus address/data, processor
formats ' status bits, and logic clips information in the
• Functions to disassemble/ assemble memory trace buffer
in the form of machine instructions and to • Conditional arming and disarming of trace
display/modify program variables iind specifications '
specialfunCtioJ;1 registers • Reprogrammability of break and trace
• Symbolicrefere,ncing to memory locations specifications during emulation
and microcontroller objects and the output of • Eight logic clips input lines may be used to
symbolic information in trace and memory trigger an action and are captured in the
disassembly displays trace buffer
• Automatic display of source statements • Qualification of events with an external
when memory is disassembled, the trace input SYSIN line
buffer is displayed, or emulation is broken • Asynchronous break based on a signal from
• Automatic update of selected variables an external device
displayed in a Watch Window • Eight logic clips output lines are settable to
• Dynamic display of the trace buffer during simulate a condition in the target system
emulation • SYSOUT output may be used to stimulate an
• A command line user interface with context- action in the target system based on a
sensitive hlillp in pop-up windows recognized event
• User-definable function keys and procedures • An event timer calculating time between
with variables and literal definitions specified conditions
• On-circuit emulation of surface mount
components
• An emulation timer returning the ,time from
entering until leaving emulation
• Synchronized multi-emulator start and
break and a trigger out for synchronization
with external logic analyzer or other device

6-14
inter
ICETM·196KB/HX IN· CIRCUIT EMULATOR,

FEATURE COMPARISON OF INTEL'S axC196KB IN·CIRCUIT

EMULATORS
ICETM·196KB/PC ICE-196KB/MX ICE·l96KB/HX
Re~-time, transparent Yes Yes Yes
Hosting PCXTBus PC XT, AT Serial PC XT, AT Serial
Expandable/U pgradable No Yes Yes
Mapped Memory (bytes) 64K 64K 128K
Trace Buffer (frames) 2K 2K ' 2K
Execution Breaks Yes Yes Yes
Breakpoints 3 255 255
Fastbreaks No Abrupt only Yes,
Bus Break/Trace No No Yes
Complex Break/Trace Events No No Yes
Reprogrammable Break/Trace No No Yes
'Symbolic Debug Yes Yes Yes
Source Code Display Yes Yes Yes
Watch Windows Yes Yes Yes
Dynamic Trace Display No Yes, Yes
Emulation Timer No Yes Yes
Event Timer No No Yes
Logic Analysis Clips No No Yes
Multi-ICE Support No ' Yes Enhanced'
COMPLETE FAMILY OFax196 emula~or. In addition, the ICE-l96KB/MX and
DEVELOPMENT TOOLS ICE-196KB/HX. emulators have been designed
ICE-196KB/MX and ICE-196KB/HX
to support future proliferations within the '
8xC196 family of microcontrollers.
emulators are complemented by Intel's low-
cost ICE-l96KB/PC emulator. All three WORLDWIDE SERVICE AND
emulators utilize an upward-compatible
human interface to preserve your learning SUPPORT
investment and to allow multiple emulators Intel augments its MCs-96 architecture family
for large design teams. Each emulator has development tools with a full array of
been designed to work'in conjunction with seminars, classes, and workshops; on-site
Intel's MCS-96 software tools, including a consulting services~ field application
macro assembler, a PL/M-96 compiler, an iC- engineering expertise; telephone hot-line
96 compiler, and various utilities. suppOrt; and software and hardware
Optional boards are available to upgrade an maintenance contracts. This full line of
, services will ensure your design- success.
ICE-196KB/MX emulator with some or a:ll of
the functionality of an ICE-196KB/HX

6-1-5
 I· SPECIFICATIONS' I
'HOSTREQUIREMENTS, • ONCE support: If ONCE (on-circuit
emulation) mode is selected, the RD# and
Emulators require an IBM PC AT, XT, or INSr pins are driven low while RESET# is
100% compatible with 512 Kbytes RAM and active (low).
hard d~ running DOS 3.x.

ELECTRICAL PROCESSOR MODULE

CHARACTERISTICS DIMENSIONS-
Power SUpply: 1OOV-120V or 200V-240V
50Hz-60Hz
5 amps (AC max) @ 120V I
'3J~
2 amps (AC max) @ 240V

ELECTRICAL
CONSIDERATIONS
lIT.'"
II08T
L
TARGET INTERfACE BOARD
The emulator processor's user-pin timings and
loadings are identical to the 8xC196KB
component except as follows:
PLCCPROBE
• Additional pin capacitance: 280847-2

Target interface board (TIB) Approximately

12pf '
(30pf PHYSICAL CHARACTER!STICS
maximum) Target Probe
Pin 32 (Pl. 7/HOLD # ) Approximately Width: 6.9 cm (2.7" )
70pf Height: 3.0 cm (1.2" )
Pin 43 (READY) Approximately Length: 11.0 cm (4.3")
70pf Package: 68-pin PLCC (optional 68-pin PGA
Pins 6 (RD # ) Approximately ad~ptor available)
60pf
Pin 63 (INST) Approximately Emulator Chassis Power Supply
60pf Width: 34 cm (13%") Width: 18 cm (7Ya" )
Pin 16 (RESET #) Approximately Height: 12cm(4%") Height: lOcm(4")
~' , '
325pf . Depth: 28 cm (10%") Depth: 28 cm (U" )
All pins when using ~ hinge 10pf Weight: 3.2 kg (7Ib) Weight: 7 kg (15Ib)
cable Probe Cable Length: 40 cm (17")
• DC loading: Pin l(VCC) can draw an Serial Cable Length: 3.65 m (12')
additional 5 mA (15mA worst case @ 5.5V)
due to power, sensing circuitry. ENVIRONMENTAL '
Sensing,circuitry may also draw CHARACTERISTICS'
approximately ± O.lmA (± 0.4 mA Operkting Temperature: O"C to 40"C
maximum) DC current from any 8xC196KB Operating Humidity: Maximum 85%
output pin. , relative humidity,
non-condensing
• AC timings:
Pin 32 (P1.7/HOLD#) Degraded Ins
Pin 43 (READY) Degraded Ins
Pin 63 (INST) if jumper Degraded Ins
El-Ji:3 is installed
Pin 16 (RESET '#) Degraded 15ns

. I
6-16
 ORDERING INFORMATION
ICE196KBHX ICE in-circuit emulator ICEBTB Enhanced break/trace
base chassis, 196 board (BTB) for upgrading
emulation control board an ICE-l96KB/MX
(ECB), 196KB target probe, system
196KB crystal power ICEOMB Optional memory board
accessory (CPA), enhanced with 64K zero-waitstate
break/trace board (BTB), mapped memory for
64K optional memory upgrading an ICE-l96KB/ \
board (OMB), clips in/out, MXsystem
power supply and cable,
serial cables for PC XT / ICECLIPS Clips in/out for upgrading
AT, 68-pin PLCC target an ICE-196KB/MX
adapter. Host, 196KB system (requires an
probe, diagnostic, and enhanced break/trace
tutorial software on 5Y4· board)
media for DOS hosts ADPTCA68PGA Hinge cable for 68 pin
running DOS a.x. PGA component
(Requires software packaging
license.)
ADPTCA68PLCC Hinge cable for 68 pin
ICE196KBMX. Same as ICEl96KBHX PLCC component
except ~thout enhanced packaging
break/trace board (BTB),
without 64K optional ADPTONC68PLCC Adaptor to support 68 pin
memory board (OMB), and PLCC component
without clips in/out packaging ONCE (on-
circuit emulation)

6-17
Memories Data Sheet 7
·'i
 87C257
256K (32K x 8) CHMOS EPROM
• CHMOS/NMOS Microcontroller and • Noise Immunity Features
Microprocessor Compatible - ± 10% Vee Tolerance
- 87C257-1ntegrated Address Latch - Maximum Latch-up Immunity
- Universal 28 Pin Memory Site, 2-line Through EPI Processing
Control .
• New Quick-Pulse Programming™
• Low Power Consumption Algorithm
• High Performance Speeds, - 4 Second Programming
-150 ns Maximum At:cess Time • . 28-Pin Cerdip and 32-Lead PLCC
Packages
(See Packaging Spec., Order # 231369)

Intel's 87C257 EPROM is a 5V-only, 262,144-bit Erasable Programmable Read Only Memory, organized as
32,768 words of 8 bits. It employs advanced CHMOS*III-E circuitry for systems requiring low power, high
speed performance, and noise immunity. The 87C257 is optimized for compatibility with multiplexed address/
data bus microcontrollers such as Intel's 16 MHz 8051- and 8096- families.

The 87C257 incorporates latches on all address inputs to minimize chip count, reduce cost, and simplify
design of multiplexed bus systems. The 87C257's internal address latch allows address and data pins to be
tied directly to the processor's'multiplexed address/data pins. Address information (inputs Ao-A14) is latched'
early in the memory-fetch cycle by the falling edge of the ALE input. Subsequent address information is
ignored while ALE remains low. The EPROM can then pass data (from pins 00-07) on the same bus during
the last part of the memory-fetch cycle.

The 87C257 is offered in ceramic DIP (CERDIP) and Plastic Leaded Chip Carrier (PLCC) packages. The
CERDIP package provides flexibility in prototyping and R&D environments while the PLCC version is used.in
surface mount and automated manufacturing. The 87C257 employs the Quick-Pulse Programming™ Algo-
rithm for fast and reliable programming.
'CHMOS is a patented process of Intel Corporation.

DATA OUTPUTS
0 0-0 7

Of OUTPUT ENABLE
PROG LOGIC
OUTPUT BUffERS
cr CHIP ENABLE
ALE ADDRESS LATCH ENABLE

Y DECODE Y-GATING
:x:
~
:s )( DECODE 262,144 BIT
VI CELL MATRIX
Ao-A I4 VI
w·
ADDRESS
INPUTS '"g
...:
290135-1
Figure 1. Block Diagram

September 1990
7-1 Order Number: 290135-007
inter Q7'C257

Pin Names 87C257

Ao-AI4 ADDRESSES ALE/Vpp vee

OUTPUTS A11 A14
00-0 7
A7 A13
OE OUTPUT ENABLE At As
As ,AI
CE CHIP ENABLE
A4 A11
ALE/vpp ADDRESS LATCH OE
AI
ENABLE/vpp A2 A10
NC NO CONNECT A1 fE
Ao 07
DU DON'T USE
00 06
01 0&
02 04
OND 03
290135-2
Figure 2, DIP Pin Configuration

N87C257

4 2 32 31 30
As 5 0 29 As

A5 6 28 Ag

A4 7 27 All

A3 8 32 LEAD PLCC 26 NC

A2 9 0.450" X 0.550" 25 OE
(11.430 X 13.970)
(MILLIMETERS)
Al 10 24 AIO
TOP VIEW
Ao ,11 23 CE

NC 12 22 °7

290135-13
Figure 3. PLCC Lead Configuration
7·2
 87C257

EXTENDED TEMPERATURE
(EXPRESS) EPROMs .
The Intel EXPRESS 'EPROM family receives addi-
tional processing to enhance product characteris-
tics. EXPRESS processing is available for several
densities allowing the appropriate memory, size to
match system requirements. EXPRESS EPROMs
are available with 168 ± 8 hour, 125°C dynamic
burn-in using Intel's standard bias configuration.
This processing meets or exceeds most industry
burn-in specifications. The EXPRESS product family
is available in both O°C to + 70°C and - 40°C to
+ 85°C operating temperature range versions. Like
all Intel EPROMs, the EXPRESS EPROM family is
inspected to 0.1 % electrical AQL. This allows reduc-
tion or elimination of incoming testing.

EXPRESS EPROM FAMILY

290135-4
OE = 5V R = 1 Kil vee = + 5V
OPTIONS ALElVpp = + 5V GND = OV CE = GND

Packaging
Speed 30 )J.S
CERDIP I PLCC H
-200V10 L I T AO.nJLS
PRODUCT DEFINITIONS' Al..JLf
•
Operating Burn-in 125°C •
Type
Temperature eC) (hr)
290135-5
Q O°C to 70°C 168 ±8 Binary Sequence from Ao to A14
T - 40°C to 85°C NONE
Burn-In Bias and Timing Diagrams
L -40°C to 85°C 168 ±8

7-3
inter 87C257

ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi.
cations are subject to change without notice.' .
Operating Temperature .•.......... o·e to 70·e(1)
Temperature Under Bias •..•...••.. - 10°C to 80·e • WARNING: Stressing the device beyond the "Absolute
Storage Temperature .. ,........... '- 65·e to 125·e Maximum Ratings" may Cause permanent damage.
These are stress ratings only. Operation beyond the
Voltage on any Pin "Operating Conditions" is not recommended and ex-
(except A9, Vcc and Vpp) tended ,exposure beyond the "Operating Conditions"
with Respectto GN D ............. - 2V to 7V(2) may affect device reliability.
Voltage on A9 with
Respect to GND •.............. :"'2V to 13.5V(2)
Vpp Supply Voltage with
Respect to GND .' .............. - 2V to 14.0V(2)
Vcc Supply Voltage with
Respect toGND ................ -2V to 7.0V(2)

READ OPERATION DC CHARACTERISTICS(1) Vcc = 5 OV +

- 10%
Symbol Parameter Notes Min Typ Max Unit Test Condition
III Input Load Current 7 0.01 1.0 p.A VIN = OV to 5.5V
ILO Output Leakage Currerit ±10 p.A VOUT = OV to 5.5V
ISB Vee Standby Current Switching 10 mA CE = ALE = VIH
with Inputs- 6 mA CE = ALE = Vcc ±0.2V
Stable 1.0 mA CE = VIH, ALE = Vil
100 p.A CE = Vee ±0.2v,ALE = GND
Ice Vee Operating eurrent 3 30 mA CE = Vil. ALE = VIH
f = 5 MHz. lOUT = 0 mA
los Output Short Circuit Current 4.6 100 mA
Vil Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 2.0 Vee + 0.5 V
VOL Output Low Voltage 0.45 V 10l = 2.1 mA
VOH Output High Voltage 2.4 V 10H = - 400 p.A

NOTES:
1. Operating temperature is for commercial product defined by this specification. Extended temperature options are available
in EXPRESS versions. .
2. Minimum DC input voltage is -;-0.5V on input/output pins. During transitions. this level may undershoot to -2.0V for
periods < 20 ns. Maximum DC voltage on input/output pins is Vce + 0.5V which. during transitions. may overshoot to Vee
+ 2.0V for periods < 20 ns. .
3. Maximum current value is with outputs 00 to 07 unloaded.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. Vee must be applied simultaneously or before ALElVpp and removed simultaneously or after ALElVpp.
6. Sampled, not 100% tested.
7. Typical limits are at Vee = 5V. TA = 25'C.

7-4
intJ 87C257

READ OPERATION AC CHARACTERISTICS(1)vcc = S.OV ±10%

. 87C257-150V10 87C257-200V10
Verslons(4) Vee ±10%
N87C257-150V10 . N87C257·200V10 Unit

Symbol Parameter Notes Min Max Min Max

tACC Address to Output Delay 150 200 ns

tCE CE to Output Delay 2 150 200 ns

tOE OE to Output Delay 2 58 75 ns

tOF OE High to Output High Z . 3 35 40 ns

toH Output Hold from Addresses, CE or 3 0 0 ns

OE Change-Whichever is First
tLL Latch Deselect Width 35 50 ns

tAL Address to Latch Set-Up 3 7 15 ns

tLA Address Hold from LATCH 23 30 ns

tLOE ALE to Output Enable 23 30 ns

NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE may be delayed up to tCE-toE after the falling edge of CE without impact on tCE.
3. Sampled, not 100% tested.
4. Model Number Prefixes: No Prefix = CERDIP, N = PLCC.

AC WAVEFORMS

V1H
ALE
V1L

VIH----of-,~--+~
cr V
1L

VIH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...!:!!~L_{::§~~~~!£:~~
OUTPUT
V1L
290135-6

7-5
 87C257

CAPACITANCE(1) TA = 25°C,f =1.0 MH?

Symbol Parameter Max Units Conditions

CIN Address/Control Capacitance 6 pF VIN = OV
COUT· Output Capacitance 12 pF VOUT =; OV

NOTE:
1. Sampled. not 100% tested.

AC INPUT/OUTPUT REFERENCE WAVEFORM AC TESTING LOAD CIRCUIT

. l.:.3~

~ .. lN914
IH OUTPUT
V1L
RL
DEVICE
290135-7 UNDER OUT
TEST
.I. CL

AC test inputs are driven at VOH (2.4 VnL) for a Logic CL = 100 pF
- 290135-S
"1" and VOL (0.45 Vnu for a Logic "0". Input timing CL Includes Jig Capacitance
begins at 1.5V. Output timing ends at VIH (2.0 Vnu RL = 3.3 KO
and VIL (0.8 Vnu. Input rise and fall times (10% to
,
90%) s: 10 ns.

DEVICE OPERATION
The Mode Selection table lists 87C257 operating modes. Read mode requires a single 5V power supply. All
inputs, except Vcc and ALElVpp, and A9 during inteligent Identifier Mode are TTL or CMOS.

Table I. Mode Selection .

ALE/
Mode Notes CE OE As Ao Vpp
Vee Outputs

Read 1 VIL VIL X X X Vcc DOUT

Output Disable VIL VIH X X X VCC HighZ
Standby VIH X X X X Vcc HighZ
Program 2 VIL VIH X X Vpp Vcp DIN
Program Verify VIH VIL X X Vpp Vcp DOUT
Optional program VIL VIL X X Vcp Vcp DOUT
Verify
Program Inhibit VIH VIH X X Vpp Vcp HighZ
intelig~nt Identifier 2,3 VIL VIL VID VIL X Vcc 89 H
-Manufacturer
inteligent Identifier 2,3 VIL VIL VID VIH X Vce 24 H
-87C257

NOTES:
1. X can be VIL or VIH.
2. See DC Programming Characteristics for VCP, Vpp and VIO voltages.
3. AI-As, AlO-14 = VIL.

7-6
inter 87C257

Read Mode Two Line Output Control

The 87C257 has two control functions; both must be EPROMs are often used in larger memory arrays.
logically enabled to obtain data at the outputs. CE is Intel provides two control inputs to accommodate
the power control and the device-select. DE gates multiple memory connections. Two-line control pro-
data to the output pins by controlling the output buff- vides for:
er. When the address is stable (ALE = V'H) or a) lowest possible memory power dissipation
latched (ALE = V,Ll, the address access time (tACe)
equals the delay from CE to output (tCE). Outputs b) complete assurance that data bus contention will
display valid data tOE after the falling edge of DE, not occur
assuming tAce and teE times are met.
To efficiently use these two control inputs, an ad-
The 87C257 reduces the hardware interface in multi- dress decoder should enable CE, while OE should
plexed address-data bus systems. Figure 4 shows a be connected to all memory devices and the sys-
low power, small board space, minimal chip tem's READ control line. This assures that oilly se-
87C257/microcontroller design. The processor's lected memory devices have active outputs while
multiplexed bus (ADo-7) is tied to the 87C257's ad- deselected memory devices are in Standby Mode.
dress and data pins. No separate address latch is
needed because the 87C257 latches all address in-
puts when ALE is low. Standby Mode

ALE controls the 87C257's internal address latch. StandbLmode substantially reduces Vee current.
When CE = V'H, the outputs are in a high imped-
As ALE transitions from V'H to V'L, the last address
ance state, independent of OE.
present at the address pins is retained. OE can then
enable EPROM data onto the bus.

Vee must be applied simultaneously or before Program Mode

ALE/Vpp and removed simultaneously or after Caution: Exceeding 14Von Vpp will permanently
ALE/Vpp. damage the device.

vss vee RST Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Al-
though only "Os" are programmed, the data word
can contain both "1s" and "Os". Ultraviolet light era-
sure is the only way to change "Os" to "1s".

Program Mode is entered when Vpp is raised to

12.75V. Data is introduced by applying an 8-bit word
to the output pins. Pulsing CE low while OE = V'H
programs that data into the device.

290135-9

Figure 4. 80C31 with 87C257

System Configuration

7-7
Program Verify SYSTEM CONSIDERATIONS
A verify should, be .performed following a program EPROM power switching characteristics require
operation to determine that bits have been correctly careful device decoupling. System designers are in-
programmed. With Vee at 6.25V, a substantial pro- terested in 3 supply current issues: standby current
9!!m margin in ensured. The verify is performed with levels (Iss), active current levels (Icc), and transient
CE at V,H. Valid data is available tOE after OE falls current peaks produced by falling and rising edges
low. . of CE. Transient current magnitudes depend on the
device output's capacitive and inductive loading.
Two-line control and proper de'coupling capacitor
Option;al Program Verify selection will suppress transient voltage peaks.
Each device should have a 0.1 /-,-F ceramic capacitor
The optional verify allows parallel programming and connected between its Vee and GND. This high fre-
verification when several devices share a common quency, low inherent-inductance capacitor should
bus. It is performed with CE = OE = V,L and Vpp = be placed as close as possible to the device. Addi-
Vee = 6:2.5V. The normal read mode is then used tionally, for every 8 devices, a 4.7 /-,-F electrolytic
for program verify. Outputs will tri-state depending capaCitor should be placed at the array's power sup-
on OE and CEo ply connection between Vee and GND. The bulk ca-
pacitor will overcome voltage slumps caused by PC
board trace inductances.
Program Inhibit
Program Inhibit Mode allows parallel prQ9!'amming ERASURE CHARACTERISTICS
of multiple EPROMs with different data. CE-high in-
hibits programming of non-targeted devices. Except Erasure begins when EPROMs ilre exposed to light
for CE and OE, parallel EPROMs may have common with wavelengths shorter than approximately 4000
"inputs. Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000-4000A range. Data shows that constant expo-
inteligent Identifier™ Mode sure to room level fluorescent lighting can erase an
EPROM in approximately 3 years, while it takes ap-
The inteligent Identifier Mode will determine an proximately 1 week for direct sunlight. If the device
EPROM's manufacturer and device type, allowing is exposed to these lighting conditions for extended
programming equipment to automatically match a periods, opaque labels should be placed over the
device with its proper programming algorithm. window to prevent unintentional erasure.

This mode is activated when a programmer forces The recommended erasure procedure is exposure
12V ± 0.5V on Ag. With CE, OE, A1-AS and A1O- to ultraviolet light of wavelength 2537 A . The inte-
A14 at V'L, Ao = V,L will present the the manufactur- grated dose (UV intensity x exposure time) for era-
er code and Ao = V'r! the device code. When Ag = sure should be a minimum of 15 Wsec/cm 2. Erasure
VID, ALE need not be toggled to latch each identifier time is approximately 15 to 20 minutes using an ul-
address. This mode functions in the 25°C ± 5°C am- traviolet lamp with a 12000 /-,-W/cm 2 power rating.
bient temperature range required during program- The EPROM should be placed within 1 inch of the
ming. lamp tubes. An EPROM can be permanently dam-
aged if the integrated dose exceeds 7258
Wsec/cm 2 (1 week @ 12000 /-,-W/cm2).

7-8
inter 87C257

290135-10

Figure 5. Quick-Pulse Programming™ Algorithm

Quick-Pulse Programming™ Algorithm The entire program-pulse/byte verify sequence is

performed with ALElVpp = 12.75V and Vee =
The Quick-Pulse programming algorithm programs 6:25V.When programming is complete, all bytes are
Intel's 87C257. Developed to substantially reduce compared to the original data with Vee = 5.0V.·
programming throughput, this algorithm can program
the 87C257 as fast as four seconds. Actual pro- Alternate Programming
gramming time depends on programmer overhead.
Intel's 27C256 and 27256 Quick-Pulse Programming
The Quick-Pulse programming algorithm employs a algorithms will also program the 87C257. Byoverrid-
100 ,...S pulse followed by a byte verificat.ion to deter- ing a ch~ck for the inteligent Identifier, older or non-
mine when the addressed byte has been successful- upgraded PROM programmers can program the
ly programmed. The algorithm terminates if 25 at- 87C257. See Intel's 27C256 and 27256 data sheets
tempts fail to program a byte. for programming waveforms of these alternate algo-
rithms.

7-9
 87C257

DC PROGRAMMING CHARACTERISTICS TA = 25°C ±5°C

Symbol Parameter . Notes Min Typ Max Unit Test Condition
III Input Load Current 1.0 /LA VIN = Vil or VIH
ICp Vcc Program Current 1 30 mA CE = Vil
Ipp Vpp Program Current 1 50 mA CE = Vil
Vil Input Low Voltage -0:2 0.8 V
VIH Input High Voltage 2.0 . VCC + 0.5 V
Val Output Low Voltage (Verify) 0:4 V IOl = 2.1 mA
VOH Output High Voltage (Verify) Vcc - 0.8 V IOH = - 400 /LA
VIO A9 inteligent Identifier Voltage 11.5 12.0 12.5 V
Vpp Vpp Program Voltage 2,3 12.5 12.75 13.0 V
VcP Vcc Supply Voltage Program 2 6.0 ·6.25 6.5 V

AC PROGRAMMING CHARACTERISTICS(4) TA = 25°C ±5°C

Symbol Parameter Notes Min' Typ Max Unit
tvcs VCP Setup Time 2 2 /Ls
tvps Vpp Setup Time 2 2 /Ls
tAS Address Setup Time 2 /LS
tos Data Setup Time 2 /Ls
tpw CE Program Pulse Width 95 100 105 fLs
- -- I - - '
tOH Data Hold Time 2 /Ls
. - - r--'
tOES OE Setup Time 2 /Ls
tOE Data Valid from OE 5 150 ns
tOFP OE High to
5,6 0 130 ns
Output High Z I
--,- ~-~
tAH Address Hold Time 0 /Ls

NOTES:
1. Maximum current value is with outputs 00 to 07 unloaded. .
2. VCP must be aRplied simultaneously or before Vpp and removed simultaned~sly or after Vpp. .
3. When programming; a 0.1 ,..,F capacitor is required between Vpp and GNO to suppress spurious voltage transients which
can damage the device.
4. See AC Input/Output Reference. Waveform for timing measurements.
5. tOE and tOFP are device characteristics but must be accommodated by the programmer.
6. Sampled, not 100% tested.
7. During programming, the addrEjss latch function is'bypassed whenever Vpp = 12.75V or ~g "' VH. When Vpp and Ag are
at TTL levels, the address latch function is enable<;l, and the device functions' in read mode.
8. Vpp can be 12.75V during Blank Check and Final Verify; if so, CE must be VIH.

7-10
inter 87C257

PROGRAMMING WAVEFORMS

V,H
Address V1l. _ _"""_"'::--:=--"""",+-~"':'::' __"';:;""""';';;=;';";';;;;;;-J}-_ _......;A.;;;D;;,;DR;;;;ES;.;S..;S.;;.TA;;,;BL;;.E+_ _"'n",,"",A;;;;DD;;,;R;;,;ES..;;,S.;.;VA.;;;LI..;;,D-'I~_
Data

12.75V - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --,--....,----1---+-+--....,-+......+----+----..
ALE/Vpp V,H - - --,----+------11---'1
tyPS

6.2SV
5.0V
Vee

V..
Ci'

V,H - - - ' - \ .
DE

290135-11

REVISION HISTORY
Number Description
07 Revised general datasheet structure, text to improve clarity.
Combined TIL/NMOS and CMOS Read Operation DC Characteristics.
Deleted -250 EXPRESS option.
Added -150 speed bin.
Deleted -170 speed bin.

7-11
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