IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO.

9, SEPTEMBER 2017 6677

Letters
Design and Implementation of a Sensorless Multilevel Inverter
With Reduced Part Count
N. Sandeep, Student Member, IEEE, and Udaykumar R. Yaragatti, Senior Member, IEEE

Abstract—This letter proposes a single-phase nine-level (9L) In general, for low power and residential applications with a
inverter topology suitable for grid-connected renewable energy rating less than 10 kW, a single-phase grid-connected inverter
systems. The proposed inverter is realized using a T-type is preferred [3], [4]. A three-level (3L) inverter proposed by
neutral-point-clamped inverter connected in cascade to a floating
capacitor (FC) H-bridge. Additionally, two low-frequency switches Nabae et al. [5] is one of the standard topologies that has gained
are added across the dc-link enabling the inverter to generate a attention. However, factors like increased switching frequency,
9L waveform. A sensorless voltage control based on redundant acoustic noise and power loss necessitated the use of multilevel
switching state is developed and embedded with PWM controller, dc–ac power converters with voltage levels greater than three [6].
which is responsible for regulating the FC voltage at one-quarter The significant features of multilevel inverters, like their ability
of the dc source voltage. The proposed PWM technique employs
the generation of 9L waveform without using any voltage sensor, to handle high voltages with reduced stress across individual
thereby reducing the complexity of the overall control scheme. devices, low switching and conduction losses, transformerless
This, in turn, will make the overall system appealing for various operation and enhanced power quality with lower harmonic dis-
industrial applications. In comparison to conventional and recent tortion have made them an attractive and competent solution
topologies, generation of the 9L waveform using a lower number for many applications [7], [8]. Currently, some of the popular
of components is the notable contribution. Another important
feature of the proposed inverter is that if FC H-bridge fails, it can topologies that are considered as applicable multilevel invert-
be bypassed, and the inverter can still operate as a 5L inverter at its ers are the cascaded H-bridge (CHB), neutral-point-clamped
nominal power rating. Furthermore, a comprehensive comparison (NPC), modular multilevel converter (MMC), a flying capaci-
study is included which confirms the merits of the proposed tor, and their variants [9], [10]. Increasing the number of levels
inverter against those of other state-of-the-art topologies. Finally, intending to reduce harmonic distortion with superior waveform
simulation and experimental results are included for validating
the feasibility of the proposed system. quality profoundly impacts the inverter size and cost. In this
context, several innovative inverter topologies with a claim of a
Index Terms—Floating capacitor (FC), nine-level (9L) inverter, reduced part count (RPC) are reported in literature [11], [12].
power quality, sensorless voltage control.
The topology proposed in [13] can generate a 7L output volt-
age with RPC. However unbalancing in the front-end capacitor
I. INTRODUCTION voltage divider circuit increases the control complexity which is
not addressed. A detailed survey of applicable 9L inverters for
HE depletion of fossil fuels, rising environmental con-
T cerns and day-by-day increasing demand for electrical
energy has elevated the need for generating energy from al-
distributed generation is presented in [14]. Also, a new topology
with a cascade connection of 5L active neutral-point-clamped
(ANPC) and 3L floating capacitor (FC) H-bridge is proposed.
ternate sources. Wind and solar photovoltaic (PV) technology
A combination of CHB with FC H-bridge presented in [15]
has gained a lot of attention among renewable energy sources
consists of one dc source and eight switches only. However,
as they are environment-friendly. This quick growth has created
regulation of FC voltage at 1/3Vdc requires additional circuit,
an arena in view of exploiting the wind and PV energy fully,
while mere experimental results are presented. A configuration
wherein many expeditious technologies in the field of power
which includes 5L double flying capacitor multicell (DFCM)
electronic converter structures for enabling the integration of
converters cascaded with FC H-bridge is recommended in [16]
renewable energy based system for electric power generation
to overcome the increased diversity factor in a DFCM con-
have emerged [1], [2].
verter. A 9L cross-connected intermediate level unit integrated
Manuscript received January 31, 2017; revised February 24, 2017; accepted with ANPC is introduced in [17]. Most of these topologies
March 7, 2017. Date of publication March 13, 2017; date of current version are hybrid combinations of one or more converter families
April 24, 2017.
The authors are with the Department of Electrical and Electronics Engineer- (NPC, FC, and CHB). Many such hybridizations resulting in
ing, National Institute of Technology Karnataka (NITK), Surathkal 575025, 9L RPC inverter are reported in literature [18]–[20]. Although
India (e-mail: [email protected]; [email protected]). for identical voltage levels, the topologies mentioned require
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. a lesser number of components, the drawbacks associated are
Digital Object Identifier 10.1109/TPEL.2017.2681739 high-frequency switching of power devices, a lot of feedback

0885-8993 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
6678 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 9, SEPTEMBER 2017

TABLE I
SWITCHING STATES AND THEIR IMPACT ON FC VOLTAGE OF THE
PROPOSED INVERTER

States S1 S2 S3 S4 S5 Output voltage FC voltage

L4+ 1 0 1 1 0 Vd c No effect
L31+ 0 0 0 1 0 3V d c /4 Discharging
L32+ 1 0 1 0 0 3V d c /4 Charging
L2+ 0 0 1 1 0 V d c /2 No effect
L11+ 0 1 0 1 0 V d c /4 Disharging
L12+ 0 0 1 0 0 V d c /4 Charging
L0+ 0 1 1 1 0 0 No effect
L0− 1 0 1 1 1 0 No effect
Fig. 1. Circuit topology of the proposed inverter. L11− 1 0 1 0 1 −V d c /4 Discharging
L12− 0 0 0 1 1 −V d c /4 Charging
L2− 0 0 1 1 1 −V d c /2 No effect
L31− 0 0 1 0 1 −3V d c /4 Discharging
sensors, increased voltage diversity factor and higher control L32− 0 1 0 1 1 −3V d c /4 Charging
L4− 0 1 1 1 1 −V d c No effect
complexity.
From the industrial point of view, use of a high number of part
counts in conventional multilevel inverters increases both the in-
tricacy of the circuitry as well as the complexity of the control
scheme involved. This eventually leads to higher cost impli- inclusion of two LFS units across the dc-link, it is possible to
cations and reduced reliability. Therefore, this letter presents obtain full value of the dc-link voltage, i.e., ±Vdc for both posi-
a novel hybrid 9L inverter on the basis of reduced part count tive and negative half cycles of the output voltage. As a result, it
and using sensorless PWM technique. A detailed comparison can synthesize output voltage with additional levels: ±Vdc and
is carried out and is presented to illustrate the distinctive char- ±3Vdc /4. For this, power switches are to be gated appropriately
acteristics and benefits of the proposed inverter. First, a single- in a sequence. Table I summarizes all the possible switching
phase grid-connected system comprising the proposed topology combinations and their effect on the FC voltage. Assuming the
is simulated, and then its loss evaluation is manifested through devices to be ideal, FC is large enough and load as pure resistive,
the simulation results. Further, a laboratory scale prototype of the active current path over a positive half cycle of the output
the proposed inverter is built. Simulation waveforms and exper- voltage for each level is obtained as follows:
imental measurements are elucidated both for steady-state and 1) Maximum positive output (Vdc ): This voltage is desig-
transient operating conditions to validate the proposed hybrid nated as L4 + . Switches S1 , S3 , and S4 are ON, connecting
inverter. the terminal a to Vdc , and S̄5 is ON, connecting the ter-
minal b to ground. Thus, the voltage across the load is
II. PROPOSED 9L INVERTER OPERATING PRINCIPLE V0 = Vdc + 0 = Vdc .
AND CONTROL 2) Three-fourth positive output (3Vdc /4): Two switching
combinations are available. For L31 + , switches S̄1 , S̄2 ,
A. Circuit Description S̄3 , and S4 are ON, connecting the terminal a to Vdc /4,
Fig. 1 shows the power circuit topology of the proposed 9L and S̄5 is ON, connecting the terminal b to ground. Thus the
inverter. It comprises mainly three units; a 3L TNPC cascaded voltage across the load is V0 = Vdc /2 + Vdc /4 = 3Vdc /4.
with 3L FC H-bridge unit and two low-frequency switches (LFS) For L32 + , switches S1 , S̄2 , S3 , and S̄4 are ON, connecting
across the dc-link. With Vdc being the total input voltage, the the terminal a to −Vdc /4, and S̄5 is ON, connecting the
voltages across the dc-link capacitors and FC are equal to Vdc /2 terminal b to ground. Thus the voltage across the load is
and Vdc /4, respectively. The idea of cascading TNPC with FC V0 = Vdc − Vdc /4 = 3Vdc /4.
yields in the following advantage of fewer number of power 3) Half-level positive output (Vdc /2): This voltage is des-
devices, power diodes, and capacitors, and more importantly it ignated as L2 + . Switches S̄1 , S̄2 , S3 , and S4 are ON,
is modular in comparison with other inverters generating same connecting the terminal a to Vdc /2, and S̄5 is ON, con-
number of levels. The resulting topology is adaptable for a necting the terminal b to ground. Thus the voltage across
higher number of voltage levels by appending more FC H- the load is V0 = Vdc /2 + 0 = Vdc /2.
bridges as per the level requirement. Ideally, the inverter is capa- 4) One-fourth positive output (Vdc /4): Two switching com-
ble of generating nine levels of output voltage: ±Vdc , ±3Vdc /4, binations are available. For L11 + , switches S2 , S̄3 , and
±Vdc /2, ±Vdc /4, 0. At a first glance, the cascade configuration S4 are ON, connecting the terminal a to Vdc /4, and S̄5
of TNPC and FC with two LFS might seem inconspicuous. In is ON, connecting the terminal b to ground. Thus, the
the absence of a LFS unit, with the dc-link midpoint being the voltage across the load is V0 = 0 + Vdc /4 = Vdc /4. For
return path for the output current, the cascade combination of L12 + , switches S1 , S̄2 , S3 , and S̄4 are ON, connecting
TNPC and FC can only generate five levels: ±Vdc /2, ±Vdc /4, the terminal a to +Vdc /4, and S̄5 is ON, connecting the
0. Also, in this case, the peak values of the output voltages are terminal b to ground. Thus, the voltage across the load is
only half of the dc-link voltage, i.e., ±Vdc /2. However, with V0 = Vdc /2 − Vdc /4 = Vdc /4.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 9, SEPTEMBER 2017 6679

5) Zero output: Two switching combinations are available.

For L0 + , switches S2 , S3 , and S4 are ON, connecting the
terminal a to ground, and S̄5 is ON, connecting the terminal
b to ground. For L0 − , switches S1 , S3 and S4 are ON,
connecting the terminal a to Vdc , and S5 is ON, connecting
the terminal b to Vdc . In both cases, the terminal ab is short
circuited, and the voltage across the load is zero.
The number of power switches conducting the circuit current Fig. 2. (a) Multilevel PWM reference and carrier signals. (b) PWM modulator.
plays a crucial role in determining the efficiency of the inverter.
In the proposed inverter, this figure ranges from four switches TABLE II
to five switches, with one of the switches operating at low- BINARY INTERPRETATION OF THE LOGIC EMBEDDED IN SWITCHING
frequency (50 Hz). Consequently, the number of active power PULSE DECODER
switches in the circuit current path is lower in comparison to
[21], [22], and hence, this topology has a better efficiency. Switching state to be selected

L0 L1 L2 L3 L4 CI = 1 CI = 0
B. Sensorless Voltage Balancing of FC
1 0 0 0 0 L0+ L0−
One of the key targets of the proposed inverter control is to 0 1 0 0 0 L12+ L11−
0 0 1 0 0 L2+ L2−
regulate FC voltage to one-quarter of the dc source voltage.
0 0 0 1 0 L32+ L31−
It is clear from Table I that 14 switching states can provide 0 0 0 0 1 L4+ L4−
different paths for load current among which ten states are ben-
eficial in producing five levels, comprising −3Vdc /4, −Vdc /4,
0, Vdc /4, and 3Vdc /4. This implies that there are a few switching
states that provide a different path for the current through the on symmetric charging/discharging times, other factors like
system while maintaining the same output voltage level. This grid voltage distortion in the case of grid-connected renew-
redundancy in switching states can be effectively utilized for able systems and the nonidealities present in the real power
charging and discharging the FC voltage, thereby allowing it to devices/components do not affect its performance significantly.
balance around its requisite value. In order to arrive at an effi-
cient design for the PWM controller, the effect of each possible C. Multilevel PWM With Integrated Voltage Balancing Control
and valid switching state on FC voltage is studied and reported To reduce the implementation issues related to FC voltage bal-
in Table I. It is worth mentioning here that all the switching ancing and to generate a multilevel output voltage, a novel PWM
states do not result in deviation of the FC voltage. At each level modulation technique developed from [24], [25] is introduced.
of output voltage (except ±Vdc /2 and ±Vdc ), switching state In contrast to [23], the proposed PWM technique employs a
redundancies exist. Contrary to the general philosophy of volt- sensorless FC voltage balancing control in which four reference
age balancing using voltage sensor for sensing the FC voltage, signals (Vref1 (t), Vref2 (t), Vref3 (t), and Vref4 (t)) are compared
a sensorless approach as proposed by [23] is slightly adapted with a single carrier signal (Vcarrier (t)). These reference signals
and used in this proposed topology. This makes the proposed differ only in terms of an offset added, apart from that they all
system more cost effective. In order to stabilize and regulate the are in phase, and have the same frequency and amplitude. The
FC voltage, it is decided to charge FC during the positive half value of the offset added is equal to the maximum amplitude of
cycles of the fundamental voltage (viz., switching states L12 + the Vcarrier (t). Since the proposed inverter utilizes four reference
and L32 + ) and discharge during the negative half cycles (viz., signals, the modulation index is given by
switching states L11 − and L31 − ), respectively. The charging and
discharging time period of the FC is kept similar to one com- Vm
ma = (2)
plete cycle of the fundamental output voltage, which leads to 4 × Vc
equalization of energy into and from the FC in every cycle of the where Vm is the peak-to-peak value of the reference signal and
output voltage and consequently, the voltage across the FC is Vc is the peak-to-peak value of the carrier signal.
maintained at the desired level in all conditions. Regarding the Fig. 2(a) shows the sinusoidal reference signals and the car-
sizing of FC, the parameters to be considered for its design are; rier signal while Fig. 2(b) depicts the schematic diagram of the
voltage ripple (ΔVC ), switching frequency (fsw ), and the max- developed PWM modulator. Each of the four reference signals
imum value of load current (Ipk ). Thus, its value is calculated is compared with the carrier for generating the PWM signals.
using the following formula: By employing suitable logic operation on the output of the
Ipk comparators, the level of output voltage to be generated is ex-
C= . (1) tracted. The binary interpretations of the logic associated with
ΔVC × fsw
voltage levels are shown in Table II. CI is the cycle identifier;
Selection of a higher switching frequency leads to shorter CI = 1/0, indicates that the levels to be generated correspond
charging/discharging time thereby enhancing the balancing per- to positive/negative half cycle of the fundamental output volt-
formance. While the voltage balancing concept is dependent age respectively. The level information data (L0 , L1 , L2 , L3 ,
6680 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 9, SEPTEMBER 2017

TABLE III
COMPARISON OF THE PROPOSED INVERTER WITH OTHER TOPOLOGIES

Multilevel inverter type

[5] [14] [16] [17] [19] [20] [21] [26] [27] [28] Proposed

LSR 0.56 0.75 0.9 0.64 0.64 0.75 0.56 0.9 0.75 0.64 0.9
Number of FCs – 2 2 2 2 3 – 2 3 3 1
Number of DC sources 8 2 1 2 2 2 4 2 2 2 1
Voltage diversity factor – 0.75 0.75 0.75 0.75 0.375 – 0.58 3 0.625 0.25
Total blocking voltage (p.u.) 6 7 3.5 7.5 9 3.5 6 8 6 4 2.5
% Reduction of devices 37.5 16.66 0 28.57 28.57 16.66 37.5 0 16.66 28.57 –
Number of sensors – 3 0 3 3 4 – 3 4 4 0

and L4 ) forms the row index and the cycle identifier output
forms the column index of the lookup table. This data is stored
in the switching pulse decoder to select a particular switching
state. For example, L3 = 1 and CI = 1 indicates that output
voltage level to be generated is 3Vdc /4 and output voltage is
in its positive half cycle. Hence, the switching state L32 + is
selected and gating pulses are generated accordingly. Moreover,
redundant switching states L0 + and L0 − are used for generat-
ing level zero of output voltage during its positive and negative
half cycles respectively, to minimize switching losses (owing
to switching transitions). As mentioned earlier, application of
this PWM technique generates a 9L output voltage waveform at
the output without need for any voltage sensor, thereby reduc-
ing complex control computations. Practical implementation of
this method is simple and economical since the PWM is real-
ized using a single high-frequency carrier signal, level-shifted
sinusoidal reference signals, logic gates, and a lookup table.
Furthermore, this technique is independent of modulation in-
dex, system nonlinearities, switching frequency, and feedback
measurement sensors.

D. Comparative Study
A generalized comparison, taking into consideration various
prominent figures of merit of the proposed inverter, with some of
the recent classic multilevel topologies, is drawn and tabulated
in Table III. The proposed inverter has the highest level/switch
ratio (LSR) except the topologies presented in [16] and [26]
wherein both have the same LSR value. In a FC-based inverter
system, the number of FCs used and their ratings determine the
size and reliability of that system and hence serve as a major
contributor to the overall cost of the system. Therefore, practical
implementation of the proposed inverter is highly economical
in view of significant reduction in the costs involved owing to
only one in number FC being employed. This number is least
among all other topologies wherein more FCs (between 2 and Fig. 3. Simulation results: (a) Grid voltage, grid current, FC voltage, output
voltage for step change in dc-link voltage, and reference grid current. (b) Sim-
3) are being used. In addition to reducing the number of FCs, ulated switching, conduction, and total loss distribution. (c) Inverter efficiency
there is a considerable decrease in voltage diversity factor as and grid current THD for varying output power. (d) Voltage across dc-link
well, in comparison to other topologies. Further, the sensorless capacitors for a step change in dc source amplitude.
technique based FC voltage controller completely eliminates
requirement for costly voltage feedback sensors, thereby obvi- a higher frequency. This greatly enhances the overall efficiency
ating need for complex control algorithms like common mode of the proposed inverter. From the reliability point of view, if the
control, model predictive control, and rule-based algorithms. FC H-bridge fails, the defective cell can be bypassed, and the
Besides, all the power devices are not required to be operated at inverter can be operated at its full power with reduced number
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 9, SEPTEMBER 2017 6681

Fig. 4. Experimental results: (a) Voltage across FC, inverter output voltage, and load current for m a = 1. (b) Voltage across FC, inverter output voltage, and
load current for m a = 0.74. (c) Voltage across FC, inverter output voltage, and load current for m a = 0.49. (d) Voltage across FC, inverter output voltage, and
load current for m a = 0.24. (e) Voltage across FC, inverter output voltage, and current for step change in m a . (f) Voltage across FC and load current with step
increase of load. (g) Voltage across FC and load current with step decrease of load. (h) Voltage regulation during a fast 33% increase in dc source amplitude. (i)
Voltage regulation during a fast 33% decrease in dc source amplitude. (j) Voltage across dc-link capacitors. (k) 9L inverter output voltage FFT analysis.

of levels. On the whole, the proposed hybrid inverter is therefore the proposed inverter with its sensorless control. A proportional
superior to most of the other inverter topologies, qualifying it resonant controller is employed to regulate the grid current at
as a preferred alternative for grid-connected renewable energy its set value. The main parameters are: rated power Pg = 3 kW;
applications. dc source voltage Vdc = 400 V; fundamental grid frequency
fg = 50 Hz; carrier frequency fsw = 2.5 kHz; grid voltage
III. SIMULATION AND EXPERIMENTAL RESULTS Vg = 230 V; FC capacitance C1 = 2.5 mF; filter inductance
Lf = 1.5 mH; dc-link capacitance Cdc,1 = Cdc,2 = 2.2 mF. A
A. Simulation Results balance booster/filter with series RLC configuration is employed
A single-phase grid connected setup shown in Fig. 1 is sim- for expediting the FC voltage balancing process. At t = 0.8
ulated using MATLAB/Simulink to verify the performance of s, a step change of 360–400 V in Vdc is applied. The results
6682 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 9, SEPTEMBER 2017

in Fig. 3(a) clearly illustrate the satisfactory performance of value (12.5 V) against variations in the modulation indices. Fur-
the proposed sensorless control in regulating the FC voltage to ther, the dynamic performance of the proposed inverter control
Vdc /4 in spite of variation in dc-link voltage. Further, at t = 1 with step increase and decrease in the load is shown in Fig. 4(f)
s, a step change in reference grid current is applied. It is appar- and (g), respectively. The capacitor voltage ripple is found to
ent from the resulting waveform that the actual inverter current be less than 8%. Fig. 4(h) shows that no precharged capacitor
tracks the new reference value, as commanded within a cycle is required during startup. Also, the voltage across FC settles to
time, exhibiting high dynamic performance. At t = 1.1 s, the its new value (10 V) smoothly, hence confirming its satisfactory
inverter is controlled to inject grid current at nonunity power performance. Fig. 4(i) illustrates the response of FC voltage for
factor, while exchanging reactive power with the grid, thereby a rapid 33% decrease in dc source amplitude from 40 to 30 V.
proving its stable operation. Meanwhile, the FC voltage is ob- The voltage across the dc-link capacitors depicting the natural
served to be well within its set value at all times. Further, an- balancing property of the proposed inverter is shown in Fig. 4(j).
alytical estimation of the switching losses, conduction losses, The 9L output voltage THD is about 6% without any additional
and total losses for the proposed inverter is carried out. The filters, as depicted in Fig. 4(k). The above mentioned simula-
method described for power loss calculation in [29], which is tions and experimental results confirm the applicability of the
based on extrapolation of the manufacturer’s datasheet is em- proposed inverter for all possible real-time operating conditions.
ployed. The power device used for the study is SKM100GB12T4
(SEMIKRON) with a rating of 1200 V, and 100 A. The simulated IV. CONCLUSION
current through each device and their blocking voltage data are
considered for the loss calculation. Fig. 3(c) depicts the loss dis- Multilevel inverters are being developed and extensively ex-
tribution in the proposed inverter. The critical operating points ploited for generating high quality output voltages for numer-
of the converter are the maximum and minimum modulation in- ous medium-voltage application fields. Applications urging a
dices at power factor PF = 1 and PF = −1, respectively. The loss higher number of voltage levels escalate the number of com-
distribution exhibits the biggest lack of balance at these points ponents required. But use of high number of part counts in
[30]. Moreover, the operating point at PF = 1 at rated power is conventional multilevel inverters increases both the circuit intri-
considered since the typical operating PF of the grid-connected cacies as well as the control scheme involved, thereby resulting
renewables is unity. As mentioned earlier, it can be observed that in higher cost implications and reduced reliability. Therefore, to
the LFS unit has negligible switching losses. This distinct loss subdue these disadvantages, this letter proposes a novel hybrid
distribution pattern aids in optimizing the proposed inverter by 9L inverter topology formed by cascading a TNPC and FC with
decreasing the semiconductor area of the lightly loaded device, two LFS connected across the dc-link. This is achieved using
resulting in further cost reduction. Fig. 3(d) shows the efficiency only ten power switches (among which two are operated at line
curve and the grid current THD over the percentage rated out- frequency). Only one FC is incorporated in the circuit for gen-
put power. From the plots, it can be inferred that the proposed erating the 9L output voltage. Further, it is confirmed that the
inverter exhibits an improved efficiency over the RPC topology proposed inverter structure has improved reliability and by cas-
proposed in [14] and the injected grid current is in compliance cading additional FCs, it can be effortlessly extended to obtain
with the harmonic limit specified by IEEE 519 Standard. The even higher number of voltage levels. In addition, a sensorless
calculated inverter losses at unity power factor result in an in- PWM technique based on the principle of energy balance for
verter efficiency of 98.9%. Fig. 3(e) depicts the voltage across regulating the voltage of FC is suggested. An exhaustive re-
dc-link capacitors for a step change in dc source amplitude from view of recently proposed multilevel inverter topologies with
400 to 320 V. The symmetrical switching of the inverter results RPC applicable for grid integration of renewable sources is car-
in the natural balancing of dc-link capacitors without the need ried out and the ensuing comparison certifies the merits of the
for additional circuitry. proposed topology over conventional inverters. Comprehensive
simulation results followed by hardware experimental results
corresponding to steady state as well as transient conditions are
B. Experimental Results presented to validate the practicability and potential prospects
A down-scaled prototype of the proposed inverter is built for extensive utilization of the proposed inverter with its sen-
to validate its performance. Discrete IRFP250N MOSFETS are sorless voltage control for several grid-integrated applications
used as switching devices gated with TLP250 drivers. dSPACE using renewable energy systems.
DS1104 DSP is used as a core controller to implement the pro-
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