IJSRD - International Journal for Scientific Research & Development| Vol.

5, Issue 10, 2017 | ISSN (online): 2321-0613

Review on Different Types of Binary Code Converters

Parampreet Bhatia1 Chandradatta Verma2
1
Student 2Assistant Professor
1,2
Department of Electronics and Telecommunication
1,2
Faculty of Engineering & Technology, SSITM, Bhilai
Abstract— In digital electronic, analog to digital converter is on this paper. On the basis of obtained results the best
most important fundamental in wide variety of digital solution will be chosen to implement in silicon micro
system. Adiabatic logic brings about a great deal of power system. The main target of this work was to simplify design
minimization in digital circuits. The digital circuits and process of the integrated circuits.
digital signals provide greater advantages when compared to P.Iyappan et al. (2009) proposed “Design of
analog circuits in processing efficient transmitting and Analog to Digital Converter Using CMOS Logic” –The
speed. This research paper presents the analog to digital signals in the real are all analog in nature. The digital
converter (ADC) for low power applications, so selection of circuits and digital signals provide greater advantages when
suitable architecture is extremely difficult. compared to analog circuits in processing efficient
Key words: Analog to Digital Converter, Power transmitting and speed. The System on Chip (SoC) forces
Minimization the integration of analog circuits with digital circuits. A new
type of encoder (fat tree encoder) has been developed for
I. INTRODUCTION advanced TIQ flash ADCs. The TIQ flash ADC offers
Adiabatic Logic is the term given to electronic circuits with higher data conversion rates while maintaining comparable
low-power consumption that implement reversible logic. power consumption level so that it is also highly suitable for
The term adiabatic is obtained from the aspect that an the complete SoC integration using the standard digital
adiabatic process is one in which the total energy or heat in CMOS process. The simulation test results showed that the
the system remains constant. Research in this area has fat tree encoder outperformed the commonly used ROM
mainly been fueled by the fact that as circuits gets faster and type encoder in terms of speed.
smaller, a problem of a huge increment in their energy Ashwini V. Kale et al. (2012) proposed
dissipation that an adiabatic circuit promises to solves. “Comparative analysis of 6 bit Thermometer-to-Binary
Analog to digital converters are one of the most important Decoders for Flash Analog-to-Digital Converter- This
elements in processing of signal and communication system. research paper describes different topologies of decoder
It is a mixed system which converts the analog signals into suitable for Flash ADCs. A comparative analysis among
the digital signals for transformation of sensor data. There them is presented in terms of power consumption, hardware
are several types of ADC’s available such as, delta sigma required, & propagation delay. Implementation of different
ADC, successive approximation ADC, and pipeline ADC thermometer to binary decoders show that MUX based
etc. Whenever analog signal is needed back, digital to decoder is more efficient in terms of power consumption.
analog converter is required. Analog to digital converters are Fat tree decoder requires less propagation delay but its
important block in many recent systems that require the layout design is more complex & time consuming. Wallace
combination of analog signals with digital systems. In tree decoder requires more power but there is no need of
various mixed-signal systems, Analog-to-Digital Converters extra BEC circuit. MUX based decoder has less hardware &
(ADC) are necessary for interfacing of analog signals to lower critical path compared with others. Hence MUX based
digital circuits. decoder is a compact & fast decoder for Flash ADC
implementation. However integrating bubble error detection
& correction circuit for MUX based decoder will be more
II. LITERATURE REVIEW
promising for future designs.
A number of research papers of various journals and Wei-Hsin Tseng and Pao-Cheng Chiu (2014)
conference were studied and survey of existing literature in proposed “A 960MS/s DAC with 80dB SFDR in 20nm
the proposed area is reported below: CMOS for Multi-Mode Baseband Wireless Transmitter”-
Michat Szermer et al.(2003) proposed “Modeling this DAC is fabricated in a 20nm CMOS process and
and Simulation Sigma-Delta Analog to Digital Converters operates from a single 1.8V supply.The measured DNL/INL
using VHDL-AMS”- The aim of this research paper is to comparison between calibrated and non-calibrated results.
introduce the technique of modeling and simulation of the After calibration, DNL is improved from -1.1/+0.7 to -
sigma-delta modulators using VHDLAMS. A few ligma- 0.2/+0.2LSB and INL is improved from -2.1/+0.3 to -
delta modulators structures are presented. From 1" to 41h 0.3/+0.2LSB. The calibrated INL drift over temperature is
order sigma delta modulator and also a triple cascade smaller than +/-0.3LSB, using the calibration values derived
structures are shown. The optimal solution is submitted to at 40oC.The measured SFDR after calibration is 80.2dB for
use as a part of silicon micro system. The analog to digital a 235 kHz tone. The calibration improves SFDR by 18dB.
conversion is performed using sigma-delta method. The two channel 10-bit I/Q DACs occupy only 0.01mm2
Modulators are modeled and tested with application of which is 12.5% of the area for an uncalibrated I/Q DACs.
VHDLAMS simulator. The sigma-delta converters The calibration technique presented here is extremely
presented in this paper had been fully described in VHDL- effective in reducing DAC area. The total current
AMS language. Results of the simulations were presented consumption is 5mA and 9mW from 1.8V power domain.

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 Review on Different Types of Binary Code Converters
(IJSRD/Vol. 5/Issue 10/2017/046)

Anshul Pathak and Shyam Akashe (2014) proposed effective. Proposed work will achieve efficient successive
“An effective 3-bit Flash Analog to Digital Converter using approximation analog to digital converter having medium
45-nm Technology”- This research paper using 45-nm bit resolution of the data convertor with efficient power
technology, a 0.7-V, 3-bit CMOS flash analog to digital consumption and moderate sampling rate.
converter is presented. In this paper a design and simulation M. S. Yenuchenko (2016) proposed “Thermometric
of 3-bit flash ADC have been presented by using 45-nm Decoders for High Resolution Digital-to-Analog
technology. Simulation shows that with no digital Converters”- Digital-to-analog converters with High-
calibration performance the proposed 3-bit flash ADC resolution frequently use segmented architecture. The design
achieves ENOB of 0.689 at consuming low power. This process for high resolutions is becoming a challenge due to
work conventional flash ADC and proposed Flash ADC is complexity of decoder. In this research paper, common
compared in table 1. The proposed flash ADC substantially design techniques for a thermometric decoder have been
reduced the power and leakage at different supply voltage. discussed in details. Generalizing of a 2-D structure is
Active power of flash ADC is 218.9-μW and leakage current proposed. These techniques can simplify a design process of
is 68.47-pA at 0.7-V power supply and input voltage is 0.5- a thermometric decoder for high-resolution DACs. The rule
V at 5-MHz and SNR of 2.39-dB. This structural design is for getting logical functions of thermometric decoder
able to extensive medium-to-high resolution appliances outputs is presented. It helps to design a thermometric
because it is easiness for circuit. decoder by individual forming of output logical functions.
Shruti Konwar (2014) proposed “power efficient Formulas for a transistor number and estimation for delay
code converters using adiabatic logic”-Adiabatic logic time are given. The results of the simulation confirm the
brings about a great deal of power minimization in digital ratio of characteristics for decoders and the tendency that a
circuits. An application of the same is presented here by more complex design technique provides a decoder with a
proposing a new design of some code converters-BCD to smaller transistor number and delay time.
Excess-3, Binary to Gray and Gray to Binary, using the Vishal Moyal and Dr. Neeta Tripathi (2016)
Adiabatic Array Logic. The main aim behind the whole proposed Implementation of Stacked-CMOS Inverter based
work was to design and propose new low power digital TIQ Comparator for FADC. this research paper proposes a
circuits for the common code converters- BCD to excess-3, Threshold Inverter Quantizer (TIQ) for implementation of a
binary to gray and gray to binary employing the adiabatic 3-bit, 1.2V Flash Analog to Digital Converter (FADC). A
logic. A close look into the total power dissipation reveals Stacked-CMOS Inverter which is based on Threshold
that the proposed circuits dissipate only about a quarter Inverter Quantizer is utilized for implementing Comparator
amount of power in comparison to the conventional CMOS section in the Flash ADC; the comparator is operating on
in each of the converters Thus, the cumulative power saving different reference voltages, which is obtained by systematic
when used in large scale will be very high. So, the proposed adjustment of aspect ratio of each stacked CMOS TIQ
circuits are a promising candidate for ultra-low energy comparator. In this research work, flash type ADC is
computing and telecommunication domain where they find designed as well as simulated using stacked-CMOS inverter
widespread applications. based Threshold Inverter Quantizer. The key goal of this
Hao Huang et al. (2014) proposed “An 8-bit 100- research work is to minimize the power dissipation
GS/s distributed DAC in 28-nm CMOS”, This paper requirement in an ADC. This proposed design provides the
presents an 8-bit 100-GS/s digital-to-analog converter total power dissipation of ADC simulated at Vdd of 1.2V
(DAC) using a distributed output topology in 28-nm low- and a capacitive load of 1fF for an input frequency ranges
power CMOS. This design achieves a -3dB bandwidth from 1 Hz to 1 MHz is observed as 5.98μW.
which is greater than 10 GHz. With 1-kbyte on-chip T. Durga Prasad et al. (2016) proposed “Design
memory the DAC can convert 1k symbols cyclically, which and Implementation of Energy Efficient Code Converters” -
is sufficient for characterizing the DAC performance. The One of the major concerns of power dissipation in CMOS
DAC consumes 2.5 W from a 1.1V/1.5V/2V power supply. circuits is charging and discharging of capacitor. The power
The area of the test chip is 1.5mm². It suppresses the dissipation can be reduced by restoring this energy back to
frequency image introduced by the 50 GS/s sub-DACs and the source instead of discharging. An observation shows that
thus increases the usable frequency band utilization. if we charge the capacitor slowly the energy requirements
Therefore it is best suited for frequency domain modulation are lesser as compared to the faster charging method.
schemes like OFDM. Adiabatic circuits use this methods viz. slow charging and
Nikhil A. Bobade et al. (2014) proposed “A discharging of capacitor, and recycling of charge to
Review: Design of Successive Approximation Analog to minimize the power consumption. Simulation is done using
Digital Converter”- This research paper presents the analog mentor graphics tool with TSMC 180nm technology for the
to digital converter (ADC) for low power applications, so designing of circuits. In this research paper Gray to Binary,
selection of suitable architecture is extrmely difficult. Day Binary to Excess-1 and Binary to Gray code converters are
by day number of applications is built on the basis of designed using adiabatic logic techniques at 180nm
efficient power consumption with moderate sampling rate. technology. The PFAL logic gives more efficiency than
This SAR ADC will be utilized for high speed with low ECRL logic at both low and high frequencies.
power consumption and medium resolution. A SAR ADC is
suitable for medium bit resolution with higher sampling rate
from kS/s to MS/s. In future, SAR ADC using minimum
capacitor technique will be energy efficient and cost-

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 Review on Different Types of Binary Code Converters
(IJSRD/Vol. 5/Issue 10/2017/046)

III. CONCLUSION [10] Vishal Moyal and Dr. Neeta Tripathi “Implementation
In this paper, we presented a review on different code of Stacked-CMOS Inverter based TIQ Comparator for
converters necessary in digital logic design. The PFAL logic FADC”, International Journal on Recent and Innovation
gives more efficiency than ECRL logic at both low and high Trends in Computing and Communication, ISSN: 2321-
frequencies. Fat tree decoder requires less propagation delay 8169 Volume: 4 Issue: 4 304 - 307 2016.
but its layout design is more complex & time consuming. [11] T. Durga Prasad, K. Srilakshmi, Assistant Professor,
Wallace tree decoder requires more power but there is no and Y. Syamala, Associate Professor “Design and
need of extra BEC circuit. MUX based decoder has less Implementation of Energy Efficient Code Converters”,
hardware & lower critical path compared with others. Hence IRACST - International Journal of Computer Science
MUX based decoder is a compact & fast decoder for Flash and Information Technology & Security (IJCSITS),
ADC implementation. However integrating bubble error ISSN: 2249-9555 Vol.6, No4, July-August 2016.
detection & correction circuit for MUX based decoder will
be more promising for future designs.

ACKNOWLEDGMENT
With a deep sense of gratitude I am thankful of Mr.
Chandradatta Verma for sharing his best of knowledge with
me and providing a great approach to perform my task in a
better way. I am also grateful to SSITM Bhilai which helped
me to complete my work by giving encouraging
environment.

REFERENCES
[1] Michat Szermer, Marcin Daniel, and Andrzej
Napieralski “Modeling and Simulation Sigma-Delta
Analog to Digital Converters using VHDL-AMS”,
CADSM'2003, February, 2003.
[2] P.Iyappan, P.Jamuna and S.Vijayasamundiswary
“Design of Analog to Digital Converter Using CMOS
Logic”, International Conference on Advances in
Recent Technologies in Communication and
Computing, 2009
[3] Ashwini V. Kale et al. “Comparative analysis of 6 bit
Thermometer-to-Binary Decoders for Flash Analog-to-
Digital Converter”, International Conference on
Communication Systems and Network Technologies,
2012
[4] Wei-Hsin Tseng and Pao-Cheng Chiu “A 960MS/s
DAC with 80dB SFDR in 20nm CMOS for Multi-Mode
Baseband Wireless Transmitter” 2014
[5] Anshul Pathak and Shyam Akashe “An effective 3-bit
Flash Analog to Digital Converter using 45-nm
Technology”, ICTCS '14, November 14 – 16, 2014
[6] Shruti Konwar “power efficient code converters using
adiabatic logic” Fourth International Conference of
Emerging Applications of Information Technology,
2014.
[7] Hao Huang Johannes Heilmeyer, Markus Grözing,and
Manfred Berroth “An 8-bit 100-GS/s distributed DAC
in 28-nm CMOS”, IEEE Radio Frequency Integrated
Circuits Symposium, 2014
[8] Nikhil A. Bobade Prof. Jayshr ee D. Dhande and Dr.
Mahen dra A. Gaikwad et al. “A Review: Design of
Successive Approximation Analog to Digital
Converter”, International Journal of Engineering
Research & Technology (IJERT), Vol. 3 Issue 1,
January - 2014
[9] M. S. Yenuchenko “Thermometric Decoders for High
Resolution Digital-to-Analog Converters”, IEEE, 2016.

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