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Assignment-1 DFT Basics: PART-1

The document discusses DFT (Design For Test) basics and concepts. It explains that DFT is a technique that makes integrated circuits more testable after production by adding extra logic. This allows testing to detect faults without running full functional tests. The document also discusses different types of testing like verification, manufacturing test, functional test, IDDQ test, and at-speed test. It describes different DFT methods like logic DFT, structured DFT, BIST, and boundary scan. Faults and defects occurring during manufacturing are also defined.

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184 views

Assignment-1 DFT Basics: PART-1

The document discusses DFT (Design For Test) basics and concepts. It explains that DFT is a technique that makes integrated circuits more testable after production by adding extra logic. This allows testing to detect faults without running full functional tests. The document also discusses different types of testing like verification, manufacturing test, functional test, IDDQ test, and at-speed test. It describes different DFT methods like logic DFT, structured DFT, BIST, and boundary scan. Faults and defects occurring during manufacturing are also defined.

Uploaded by

senthilkumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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ASSIGNMENT- 1

DFT Basics

PART-1

1. Why we need DFT? Advantage of DFT?

A simple answer is DFT is a technique, which facilitates a design to become


testable after production. It’s the extra logic which we put in the normal
design, during the design process, which helps its post-production testing.
Post-production testing is necessary because, the process of manufacturing is
not 100% error free. There are defects in silicon which contribute towards
the errors introduced in the physical device. Of course a chip will not work
as per the specifications if there are any errors introduced in the production
process. But the question is how to detect that. Since, to run all the
functional tests on each of say a million physical devices produced or
manufactured, is very time consuming, there was a need to device some
method, which can make us believe without running full exhaustive tests on
the physical device, that the device has been manufactured correctly. DFT is
the answer for that. It is a technique which only detects that a physical is
faulty or is not faulty. After the post-production test is done on a device, if it
is found faulty, trash it, don’t ship to customers, if it is found to be good,
ship it to customers. Since it is a production fault, there is assumed to be no
cure. So it is just detection, not even a localization of the fault. That is our
intended purpose of DFT. For the end customer, the DFT logic present on
the device is a redundant logic.
Example
To further justify the need of DFT logic, consider an example where a
company needs to provide 1 Million chips to its customer. If there isn’t any
DFT logic in the chip, and it takes for example, 10 seconds (Its very kind
and liberal to take 10 seconds as an example, in fact it can be much larger
than that) to test a physical device, then it will take approx. three and a half
months just to test the devices before shipping. So the DFT is all about
reducing three and a half months to may be three and a half days. Of course
practically many testers will be employed to test the chips in parallel to help
reduce the test time.
The benefits of testing are quality and economy. These two attributes are
notindependent and neither can be defined without the other. Quality means
satisfying the user’s needs at a minimum cost. A good test process can weed
out all bad productsbefore they reach the user. However, if too many bad
items are being producedthen the cost of those bad items will have to be
recovered from the price charged for the few good items that are produced. It
willbe impossible for an engineer to designa quality product without a
profound understanding of the physical principlesunderlying the processes of
manufacturing and test.

2. Difference between verification and test?

Ans. Verification is a functional check of the abstract model created in RTL.


Testing is an Actual check of the silicon created from abstract model.

Verification Testing
Verify correctness of design Test the correctness of manufactured
device
Done by simulation or formal Two step process Test generation and
method, hardware emulation test application
Performed only once Applied to manufactured device
Responsible for quality of design Responsible for quality of device
Functional vectors are more Test vector are less
Functional coverage less Test coverage more

3. What is manufacturing Test and list down the goals?

Ans. Manufacturing Test:Factory testing of all manufactured chips for


parametric faults and for random defects. Main goals of manufacturing test
are enlist
1. Identify and separate defective chips from being used in actual
products.
2. Prevent catastrophic failures of critical electronic systems by providing
an early warning of failure.
3. Objectives of manufacturing test are to facilitate/simplify fail data
collection and diagnostics to an extent that can enable intelligent failure
analysis (FA) sample selection, to identify the source of failure.
4. Improve the cost, accuracy, speed, and throughput of testing,
diagnostics, and FA.
5. In addition to being useful for manufacturing "go/no go" testing, scan
chains can also be used to "debug" chip designs which have already been
mounted on a PCB.

4. What is Test Plan? What are requirements for Test plan?


5. Different types of faults?

A manufacturing defect is a physical problem that occurs during the manufacturing process,
causing device malfunctions of some kind. The purpose of test generation is to create a set of
test patterns that detect as many manufacturing defects as possible. Each of these defects has
an associated detection strategy. The following subsection discusses the three main types of
test strategies. Figure shows three main categories of defects and their associated test types:
Functional, IDDQ, and at-speed.

Functional Test
Functional test continues to be the most widely-accepted test type. Functional test typically
Consists of user-generated test patterns, simulation patterns, and ATPG patterns. Functional
testing uses logic levels at the device input pins to detect the most common manufacturing
process-caused problem, static defects (for example, open, short, stuck-on, and stuck-open
conditions). Functional testing applies a pattern of 1s and 0s to the input pins of a circuit and
then measures the logical results at the output pins Functional testing checks the logic levels
of output pins for a “0” and “1” response.

IDDQ Test
IDDQ testing measures quiescent power supply current rather than pin voltage, detecting
device failures not easily detected by functional testing—such as CMOS transistor stuck-on
faults or adjacent bridging faults. IDDQ testing equipment applies a set of patterns to the
design, lets the current settle, and then measures for excessive.IDDQ testing measures the
current going through the circuit devices.

At-Speed Test
Timing failures can occur when a circuit operates correctly at a slow clock rate, and then fails
When run at the normal system speed. Delay variations exist in the chip due to statistical
Variations in the manufacturing process, resulting in defects such as partially conducting
Transistors and resistive bridges. At speed testing checks the amount of time it takes for a
device to change logic states.
6. What are the different types of DFT methods?
Electronic systems contain three types of components:
a) Digital logic
b) Memory blocks
(c) Analog or mixed-signal circuits.

There are specific DFT methods of each type of component.


Built-in self-test (BIST), which is also used for digital logic as well as for memory
blocks Special techniques, known as boundary-scan and analog test bus, provide test
access to components embedded in a system.

Logic DFT takes one of two possible routes: ad-hoc and structured. The adhoc
DFT relies on “good” design practices learned from experience. Some of these
are
• Avoid asynchronous logic feedbacks. A feedback in the combinational logic can
give rise to oscillation for certain inputs. This makes the circuit difficult to
verify and impossible to generate tests for by automatic programs. This is
because test generation algorithms are only known for acyclic combinational
circuits.
• Make flip-flops initializable. This is easily done by supplying clear or reset
signals that are controllable from primary inputs.
• Avoid gates with a large number of fan-in signals. Large fan-in makes the
inputs of the gate difficult to observe and makes the gate output difficult to
control.
• Provide test control for difficult-to-control signals. Signals such as those produced
By long counters require many clock cycles to control and hence increase
The length of the test sequence. Long test sequences are harder to generate.

There are difficulties with the use of ad-hoc DFT methods. First, circuits are
Too large for manual inspection. Second, human testability experts are often hard to
find, while the algorithmically generated testability measures are approximate and do
not always point to the source of the testability problem

As the size and complexity of digital systems grew, an alternative form of DFT,
Known as structured DFT gained popularity.
In structured DFT, extra logic and signals are added to the circuit so as to allow the
test according to some predefined procedure.
Apart from the normal functional mode, such a design will have one or more test
modes. Commonly used structured methods are scan and built-in self-test

What are the cons of DFT?

PART-2
1. Explain ASIC design flow?
2. Explain FPGA design flow?
3. What is difference between ASIC and FPGA?

4. Which scenarios ASIC is preferred? Which scenarios FPGA is preferred?


5. DFT can be done in which all phases of ASIC flow?
6. What is problem if we do not have DFT?
7. ASIC consists of which all components? How all those can be tested using DFT?
8. What is meaning of Fault and Defect?
Defect
A defect is the unintended difference between the implemented
Hardware and its intended design.
Defects occur either during manufacture or during the use of
Devices Fault
A representation of a defect at the abstracted function level.
1. What is functional code coverage versus Structural Testcoverage?

2. What is Yield? What is DPPM?


Fraction (or percentage) of good chips produced in a manufacturing process is called the
yield.
1. DPPM should be lesser or more, which is better?

DPPM is stand for Defect part per million. Definitely it should be less which is better
2. How Test coverage plays role?

3. Why achieving good test coverage is important?

4. Who all are the major DFT tool vendors and what all are the names of DFT tools
(vendor wise)?

TEESENT - Mentor Graphics


DFT ADVISOR

DC COMPLIER
TETRA MAX SYNOPSIS

MODUS -CADENS
GENESIS - CADENS

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