FPGA DEVELOPMENT OF BPSK & QPSK

MODULATOR AND DEMODULATOR

Student name
 FPGA DEVELOPMENT OF BPSK & QPSK MODULATOR AND DEMODULATOR

PART 1 – BPSK MODULATION & DEMODULATION

ABSTRACT

Digital modulation is a process that impresses a digital symbol on to a signal suitable for transmission

on a wired or wireless medium in order to receive that signal at receiving end correctly with out any loss

of information. Quadratic phase shift keying (QPSK) modulation and Binary phase shift keying

technique are the most widely used modulation scheme in modern digital communication system; it

provides high performance on bandwidth efficiency and bit error rate. In this paper the complete model

of Quadrature Phase Shift Keying (QPSK) and Binary phase shift keying modulator and demodulator

has been developed. The model has been simulated XILINX ISE simulator. Complete results are tested

and verified.

INTRODUCTION

Internet has converted this world into global village. Now people want to communicate while on move.

Wireless is the technology that makes it possible. In last few years, the mobile radio communication

industry has grown exponentially. By the fabrication of high density low power, low noise, small size

and reliable digital and RF chips make radio equipment smaller, cheaper and more reliable. Due to this

explosive growth of mobile and wireless users there are so many problems created, the most critical

problem is frequency spectrum, Bit Error Rate (BER) and Bandwidth. In this paper the Quadrature

Phase Shift Keying and Binary phase shift keying are addressed as modulator and demodulator for the

wireless modem.

EXISTING SYSTEM

In the existing system of this paper shows a complete model of Quadrature Phase Shift Keying

(QPSK ) , Binary phase shift keying (BPSK) modulator and demodulator has been developed. The
model has been simulated in Matlab using Simulink. Complete results are tested and verified. In final

hardware design and implementation of QPSK for Wireless Modem has been proposed. QPSK

modulation has various applications particularly in the design of wireless modem, cellular

CDMAcommunication.

PROPOSED SYSTEM

In the proposed system of this paper uses a XILINX ISE simulator for the Quadrature Phase Shift

Keying (QPSK ) , Binary phase shift keying (BPSK) modulator and demodulator development. The

model has been designed using VERILOG language in XILINX ISE. Complete results are tested and

verified in the XILINX ISE SIMULATOR.

BLOCK DIAGRAM

BLOCK DESCRIPTIONS

BPSK Modulation

In digital modulation techniques a set of basis functions are chosen for a particular modulation

scheme.Generally the basis functions are orthogonal to each other. Basis functions can be derived using
'Gram Schmidt orthogonalization' procedure.Once the basis function are chosen, any vector in the signal

space can be represented as a linear combination of the basis functions In Binary Phase Shift Keying

(BPSK) only one sinusoid is taken as basis function modulation. Modulation is achieved by varying the

phase of the basis function depending on the message bits. The following equation outlines BPSK

modulation technique The constellation diagram of BPSK will show the constellation points lying

entirely on the x axis. It has no projection on the y axis. This means that the BPSK modulated signal will

have an in-phase component (I) but no quadrature component (Q). This is because it has only one basis

function.

A BPSK modulator can be implemented by NRZ coding the message bits (1 represented by +ve voltage

and 0 represented by -ve voltage) and multiplying the output by a reference oscillator running at carrier

frequency ω.

In this modulation one has as possible results two exit phases for the carrier with a single frequency. An

exit phase represents a logical 1 and the other one a logical 0. As the input digital signal changes the

state, the phase of the exit carrier moves between two angles that lie 180° outside of phase.

To generate random stream of data for BPSK modulator, a non-periodic uniformly-distributed data

source was created. The BPSK modulator itself consists of a 1-bit D/A converter, an oscillator, and a

mixer. A D/A converter essentially shifts voltage levels of the source data and maps a logic '0' to -1V

and a logic '1' to +1V. Multiplied by the oscillator frequency, this results in a BPSK-modulated signal.

The modulator blocks are implemented in an ideal manner with no non-linearities or noise sources.

Amplifers, Antennas/Propagation Channel

The power ampli_er (PA) and the low-noise amplifer (LNA) are implemented as ideal pure gain blocks

so that the functionality of the algorithm and relation to the theoretical system is quickly con_rmed in

simulation. The channel that contains both the effects of transmitting and receiving antennas and

propagation effects is implemented as an ideal gain block with an additive white Gaussian noise
(AWGN). Although other types of noise and interference are possible in a realistic RF environment,

AWGN is most common and also allows one to compare BER simulation results to the theoretical

calculations.

White Gaussian Noise Generator

Noise generator is necessary for calculating one of the most fundamental characteristics of a complete

RF system: bit error rate (BER) vs. signal-to-noise ratio (SNR). Not all simulator platforms support

functions for automatically generating white noise. In our case, we used Box-Muller transformation to

create a Gaussian distributed variable from two independent, uniformly distributed random variables. A

periodic process computes a new noise value at regular intervals and outputs that value scaled to the

requested average power level. Since a new noise value is produced at a given rate, one must make sure

that in the transient simulation a new noise value is assigned to each original signal sample. For that, the

sample rate of the original signal must be less than or equal to the rate at which noise is produced. In our

VHDL-AMS implementation of WGN generator, we found that with 105 samples, the mean and the

variance of generated signal differ from ideal theoretical values by less than 3%, making this a very

effective means of introducing AWGN into VHDL-AMS

BPSK MODULATION

Demodulator

BPSK Demodulation:

For BPSK demodulator , a coherent demodulator is taken as an example. In coherent detection technique

the knowledge of the carrier frequency and phase must be known to the receiver. This can be achieved

by using a Costas loop or a PLL (phase lock loop) at the receiver. A PLL essentially locks to the

incoming carrier frequency and tracks the variations in frequency and phase. For the following

simulation , neither a PLL nor a Costas loop is used but instead we simple use the output of the PLL or

Costas loop. For demonstration purposes we simply assume that the carrier phase recovery is done and

simply use the generated reference frequency at the receiver (cos(ωt)) .

In the demodulator the received signal is multiplied by a reference frequency generator (assuming the

PLL/Costas loop be present). The multiplied output is integrated over one bit period using an integrator.

A threshold detector makes a decision on each integrated bit based on a threshold. Since an NRZ

signaling format is used with equal amplitudes in positive and negative direction, the threshold for this

case would be '0' .

The BPSK demodulator consists of down-converter, oscillator, a low-pass _lter (to eliminate aliases),

and A/D converter (which works by sensing zero-crossings). Note that BPSK requires a coherent

detection. For illustration simplicity, we use a transmitter's oscillator to provide a reference signal for the

demodulator. In the next level of architectural complexity, a coherent detector needs to be added. After

demodulation, the signal is low-pass filtered and sampled at the middle of each bit period. Low-pass

filter was implemented using Laplace transform package. BER was calculated by comparing

demodulated signal to the original data stream.

SOFTWARE DESCRIPTIONS

XILINX ISE

The Integrated Software Environment (ISE®) is the Xilinx® design software suite that allows you to

take your design from design entry through Xilinx device programming. The ISE Project Navigator

manages and processes your design through the following steps in the ISE design flow.

Design Entry

Design entry is the first step in the ISE design flow. During design entry, you create your source files

based on your design objectives. You can create your top-level design file using a Hardware Description
Language (HDL), such as VHDL, Verilog, or ABEL, or using a schematic. You can use multiple

formats for the lower-level source files in your design.

Note If you are working with a synthesized EDIF or NGC/NGO file, you can skip design entry and

synthesis and start with the implementation process.

Synthesis

After design entry and optional simulation, you run synthesis. During this step, VHDL, Verilog, or

mixed language designs become netlist files that are accepted as input to the implementation step.

Implementation

After synthesis, you run design implementation, which converts the logical design into a physical file

format that can be downloaded to the selected target device. From Project Navigator, you can run the

implementation process in one step, or you can run each of the implementation processes separately.

Implementation processes vary depending on whether you are targeting a Field Programmable Gate

Array (FPGA) or a Complex Programmable Logic Device (CPLD).

Verification

You can verify the functionality of your design at several points in the design flow. You can use

simulator software to verify the functionality and timing of your design or a portion of your design. The

simulator interprets VHDL or Verilog code into circuit functionality and displays logical results of the

described HDL to determine correct circuit operation. Simulation allows you to create and verify

complex functions in a relatively small amount of time. You can also run in-circuit verification after

programming your device.

Device Configuration

After generating a programming file, you configure your device. During configuration, you generate

configuration files and download the programming files from a host computer to a Xilinx device.
Additional Resources

VERILOG CODE

SIMULATION OUTPUT