M.Jagadeesh Kumar et al, / (IJCSIT) International Journal of Computer Science and Information Technologies, Vol.

5 (6) , 2014, 7609-7613

Design of New Low Power –Area Efficient Static

Flip-Flops
M.Jagadeesh Kumar 1, Dr. R Ramana Reddy 2
1
M.Tech (Student), VLSI,
2
Professor & Head of Department,
1, 2
Department of Electronics and Communication,
M.V.G.R College of engineering,Chintalavasala,
Vizianagaram, Andhra Pradesh, India

Abstract— System on chip (SOC) design integrates many sequential circuitry. Delay or Data Flip-Flop (DFF) [4] has
complex modules in one chip. As number of modules per chip been the integral part of many digital systems to construct
is increasing, number of transistors in a chip increases the sequential part of it. To achieve low power dissipation
resulting in increase in area and power dissipation. Area and along with area efficiency, two new D Flip-Flop
power dissipation problems can be most effectively addressed architectures are proposed and are compared with the
if the basic building blocks of the circuit are designed for conventional Flip-Flops.
lower power dissipation and occupy less space. Flip-Flop,
which is basic building block, plays a major role in design of II. POWER DISSIPATION
complex systems. From the open literature, C2MOS Flip-Flop
and PowerPC 603 Flip-Flops are classic structures that The design of portable devices requires
dissipate less power. In this paper, two new low power consideration for peak power consumption to ensure
dissipating Flip-Flop architecture are proposed and compared reliability and proper operation. However, the time
with conventional Flip-Flops. In the proposed Flip-Flop averaged power is often more critical as it is linearly related
architectures, power dissipation is reduced up to 30% to 40% to the battery life. There are four sources of power
compared with conventional Flip-Flops and area is also dissipation in digital CMOS circuits: switching power,
reduced. Johnson counter is designed with the proposed Flip- short-circuit power, leakage power and static power. The
Flops which exhibit low power dissipation. The simulation is
following equation describes these four components of
done in MENTOR GRAPHICS, Schematic editor, Generic
GDK, 130nm technology. power:
Pavg = αCLVddVsfck+IscVdd + IleakageVdd + IstaticVdd (1)
Keywords— Power dissipation, Flip-Flop, C2MOS, PowerPC
603, Johnson counter. Here Pstatic = αCLVddVsfck ,
Pdynamic = IscVdd ,
I. INTRODUCTION Pleakage= IscVdd
With the widespread use of mobile devices in modern and Pshort-circuit = IstaticVdd .
society, power efficiency and energy savings become
extremely important issues for designers. CMOS has been III. CONVENTIONAL FLIP-FLOPS
the dominant technology for VLSI implementations. As A. C2MOS FLIP-FLOP
VLSI circuits continue to grow and technologies evolve,
the level of integration is increased and higher clock speeds The C2MOS Flip-Flop [5] is a pseudo-static Flip-Flop,
are achieved. Higher clock speeds, increased levels of which is obtained by the addition of a weak C2MOS
integration and technology scaling are causing unabated feedback at the outputs of the master and the slave latches
increases in power consumption. As a result, low power in a dynamic C2MOS Flip-Flop as shown in the Fig. 1.
consumption [1-3] is becoming a critical issue for modern When the clock is at logic ‘high’, the clocked inverter
VLSI circuits. Furthermore, power dissipation, dynamic CLKI1 latches the input at D to an intermediate node N.
and static, has become a limiting factor for transistor The feedback consisting of clocked inverter CLKI2 and
performance, long term device reliability, and increasing inverter I1 maintains this logic level at node N when clock
integration. is at logic ‘HIGH’. Similarly when CLK changes to logic
Flip-Flops, which is a basic building block of ‘LOW’, the slave latches gets functional and clocked
many electronic circuits that stores a logical state of one or inverter CLKI4 and inverter I2 maintains this logic level at
more data in response to a clock pulse. Flip-Flops are often output Q when clock is grounded. There is no Vt-drop at
used in computational circuits to operate in selected intermediate circuit nodes.
sequences during recurring clock intervals to receive and The circuit is more robust to noise with high noise
maintain data for a limited time period. At each rising margins .There are 20 transistors in this circuit. Even the
orfalling edge of a clock signal, the data stored in Flip- area occupied by C2MOS is more, the power dissipation in
Flops can be applied as inputs to other combinational or the circuit is less.

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 M.Jagadeesh Kumar et al, / (IJCSIT) International Journal of Computer Science and Information Technologies, Vol. 5 (6) , 2014, 7609-7613

Fig. 1 C2MOS Flip-Flop

Fig. 2 PowerPC 603 Flip-Flop

B. POWERPC 603 FLIP-FLOP IV. PROPOSED FLIP-FLOP ARCHITECTURES

Power PC means Performance Optimization with A. Proposed model –I
Enhanced RISC Performance Computing. The power The proposed model-I is the modified version of
dissipation is low and also having low clock-to output PowerPC 603 which acts like a static Flip-Flop as shown in
(CLK-Q) delay. In synchronous systems, the latching the Fig. 3. It uses a low-power keeper [7] structure in the
elements have the delay overhead which is expressed by master and slave mode. In the proposed model- I the master
the data-to-output (D-Q) delay rather than CLK-Q delay. mode is modified. Because of the drop due to the threshold
Here, D-Q delay is the combination of CLK-Q delay and of the transistors, PowerPC 603 suffers with short circuit
the setup-time of the Flip-Flop. But the static designs lack power dissipation. An NMOS transistor with
the low D-Q delay due to their large positive setup-time, complemented clock signal is used to make feedback path
and also most of them are susceptible to flow through functional only during OFF cycle of the clock. This reduces
resulting from CLK overlap. short circuit current during ON cycle. To reduce the
number of transistor, only NMOS transistor is used in
The PowerPC 603 master-slave [6] latch in Gerosa et al.’s master latch as shown in Fig. 3. If PMOS transistor with
experiment is shown in Fig. 2. It has the advantages of clock signal is used in feedback, the logic level at the node
having a low-power keeper structure and a low latency X would be maintained when the clock is in the logic level
direct path. It is one of the fastest classical structures and its ‘HIGH’ rather than the logic level ‘LOW’. Hence, when
main advantage is the short direct path and low power the clock is stopped (grounded), the circuit would show a
feedback. The large load on the clock will greatly affect the dynamic behaviour instead of static behaviour. This
total power consumption of the Flip-Flop. This Flip-Flop is limitation is overcome by using a NMOS transistor in
the transmission gate Flip-Flop, it has a fully static master– feedback instead of PMOS transistor.
slave structure, which is constructed by cascading two
identical pass gate latches and provides a short clock to When the data D is arrived at the input, when the clock is
output latency. It does have a worse data-to-output latency high, the nMOS transistor N1 will be ON and the data is
because of the positive setup time and its sensitivity to transferred to the inverter-1 and the nMOS transistor in the
clock signal slopes and data feed through is another feedback will OFF and eliminates the feedback .When the
concern when using it. The large D-Q delay resulting from clock is low, the nMOS transistor N2 will be ON and the
the positive setup time is one of the disadvantages of this data at the node X will be retained until the next clock
design. Also, the large data and CLK node capacitances pulse.
make the design inferior in performance. Despite all these
shortcomings, static designs still remain as the low power
solution when the speed is not a primary concern.

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Fig. 5 Proposed Model-II Flip-Flop with reset

Fig. 3 Proposed Model-I Flip-Flop A Johnson up-down counter is designed with modified
version of proposed model –II. The architecture of Johnson
B. Proposed model –II counter is shown below Fig. 6.
The proposed model-II is the modified version of
proposed model-1. In the proposed model –II shown in Fig.
4, the transmission gate is replaced with nMOS. Since the
circuit is operated as master-slave. The slave is
disconnected from the master when the clock is high. By
using nMOS (N3) as a path, the average power dissipation
is improved by 20%. When the slave is disconnect from
the master, the N4 and N5 in the power keeper provides the
feedback and ensures that the data is retained till the next
clock cycle.
In digital logic and computing, a counter is a device which
stores the number of times a particular event or process has
occurred, often in relationship to a clock. Among different
types of counters, Johnson counter needs half the number
of Flip-Flops.
Johnson counter requires a reset to initialize the count. So
the proposed model-II is modified as shown in the Fig.5 Fig. 6 Johnson up-down Counter architecture using Proposed model-II

V. RESULTS
Simulation are carried out using MENTOR GRAPHICS,
generic GDK, 130-nm CMOS technology at nominal
conditions with clock frequency 10MHz. The simulated
waveform of the Proposed Model –I Flip-Flop is shown in
Fig. 7. As the circuit works like a master-slave Flip-Flop
the data D is provided at the output Q only in the negative
half cycle of the clock. This reduces the Race through
problem. The average power dissipation and area required
is reduced compared to PowerPC 603 Flip-Flop.

The simulated waveform of the Proposed Model –II Flip-

Flop is shown in Fig. 8.

Fig. 4 Proposed Model-II Flip-Flop

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 M.Jagadeesh Kumar et al, / (IJCSIT) International Journal of Computer Science and Information Technologies, Vol. 5 (6) , 2014, 7609-7613

Fig. 7 Proposed model I waveform

Fig. 9 Johnson counter waveform designed with Proposed model II

The performance comparisons of the Johnson counter with

conventional and proposed Flip-Flops are given in the table
II.

TABLE-II
PERFORMANCE COMPARISON OF JOHNSON COUNTERS WITH DIFFERENT
FLIP-FLOPS
Fig. 8 Proposed model II waveform
Flip-Flop Power Dissipation(nW)
The performance comparisons of the Flip-Flops are given C2MOS 3.7
in the Table I. PowerPC 603 3.2
TABLE –I Proposed model –I 3.05
PERFORMANCE COMPARISON OF VARIOUS FLIP-FLOPS Proposed model-II (with reset) 2.547

Flip-Flop
Power No. of VI. CONCLUSION
Dissipation(pW) transistors
C2MOS 815.0527 20 A new low power dissipating Flip-Flop architectures
PowerPC 603 925.0929 18 was proposed. A comparison of the proposed Flip-Flop
Proposed model –I 763.7391 14 with the conventional Flip-Flops showed that it exhibits
Proposed model-II 583.1645 13 lower power dissipation and occupies less area. The
Proposed model-II with reset 582.113 14 proposed Flip-Flop architecture exhibits reduction in
the power dissipation up to 30-40% than the
The proposed models exhibits up to 30% reduction in conventional Flip-Flops. A Johnson counter is designed
total power dissipation and area compared to C2MOS and using conventional and proposed Flip- Flops. The
PowerPC 603 Flip-Flop. Johnson counter designed with proposed models
Since proposed model – II exhibits less power exhibits reduction in the power dissipation up to 30%.
dissipation and area efficient, A Johnson counter [8] is Hence the proposed architectures are well suited for
designed with the Proposed Model-II, the waveform shown modern high performance designs where area and
in Fig. 9 represents the transient response of the Johnson power dissipation are the major concern.
counter.

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 M.Jagadeesh Kumar et al, / (IJCSIT) International Journal of Computer Science and Information Technologies, Vol. 5 (6) , 2014, 7609-7613

REFERENCES AUTHORS
[1] N.Weste and D. Harris, CMOS VLSI Design. Reading, MA:
1
M.JAGADEESH KUMAR received his B.Tech degree from Al-Ameer
Addison Wesley, 2004. college of Engineering and IT, Visakhapatnam in the year 2011 and
[2] A. Chandrakasan, W. Bowhill, and F. Fox, Design of High- presently pursuing M.Tech degree in VLSI Design in MVGR College,
Performance Microprocessor Circuits, 1st ed. Piscataway, NJ: IEEE, Vizianagaram. His interests include Digital IC Design & Verification,
2001. Mixed Signal Design.
[3] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated
Circuits: A Design Perspective, 2nd ed. Englewood Cliffs, NJ:
2
Dr. R. RAMANA REDDY did AMIE in ECE from The Institution of
Prentice- Hall, 2003. Engineers (India) in 2000, M.Tech (I&CS) from JNTU College of
[4] V. Stojanovic and V. Oklobdzija, “Comparative analysis of master– Engineering, Kakinada in 2002, MBA (HRM & Marketing) from Andhra
slave latches and flip-flops for high performance and low power University in 2007 and Ph.D in Antennas in 2008 from Andhra
system,” IEEE J. Solid State Circuits, vol. 34, no. 4, pp.536–548, University. He is presently working as Professor & Head, Dept. of ECE in
Apr. 1999. MVGR College of Engineering, Vizianagaram. Coordinator, Center of
[5] R. Ramanarayanan, V. Degalahal, N. Vijaykrishnan, M.J. Irwin and Excellence – Embedded Systems, Head, National Instruments LabVIEW
D.Duarte, “Analysis of Soft Error Rate in Flip-Flops and Scannable academy established in Department of ECE, MVGR College of
Latches”,IEEE International Systems-on-Chip (SOC) Conference, Engineering. Convener of several national level conferences and
2003, pp. 231-234 workshops. Published about 32 technical papers in National/International
[6] G. Gerosa, S. Gary, C. Dietz, P. Dac, K. Hoover, J. Alvarez, H. Journals / Conferences. He is a member of IETE, IEEE, ISTE, SEMCE(I),
Sanchez, P. Ippolito, N. Tai, S. Litch, J. Eno, J. Golab, N. IE,ISOI. His research interests include Phased Array Antennas, Slotted
Vanderschaaf, and J. Kahle, “A 2.2 W, 80 MHz superscalar RISC Waveguide Junctions, EMI/EMC, VLSI and Embedded Systems.
microprocessor,” IEEE J. Solid-State Circuits, vol. 29, no. 12, pp.
1440–1452, Dec. 1994.
[7] J. Kao and A. Chandrakasan, "MTCMOS sequential circuits,"
Proceedings of European Solid State Circuits Conference, pp 332-
335, September 2001.
[8] Low-power dual dynamic node pulsed hybrid Flip-Flop featuring
efficient embedded logic ,kalarikkal absel, lijo manuel, and R. K.
Kavitha, member, IEEE, IEEE transactions on very large scale
integration (vlsi) systems, vol. 21, no. 9, September 2013.
[9] Peiyi Zhao, Jason McNeely, WeidongKuang, Nan Wang, and
Zhongfeng Wang “Design of Sequential Elements for Low Power
Clocking System” IEEEtransactions on Very Large Scale
Integration (VLSI) systems, vol. 19, no. 5, May 2011

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