Compactpci 9056Rdk-860: Rapid Development Kit For Pci 9056 With Motorola Powerquicc Designs
Compactpci 9056Rdk-860: Rapid Development Kit For Pci 9056 With Motorola Powerquicc Designs
Flexible Hardware
Development Platform
■ PICMG 2.0 r3.0 compliant
CompactPCI 9056RDK-860
CompactPCI 6U form factor
■ The PCI 9056 I/O Accelerator
– Supports 32-bit, 66MHz Rapid Development Kit For PCI 9056 with Motorola PowerQUICC Designs
CompactPCI bus operation
– Supports 32-bit, 50MHz
PowerQUICC bus
■ 4Kb EEPROM, 8.5 MB Flash, An Invaluable Development Aid
and 64MB SDRAM The PLX CompactPCI 9056RDK-860 RDK provides a comprehensive PCI 9056
design and development environment for PICMG 2.0 r3.0 CompactPCI-compliant
■ CPLD Local Bus memory adapters based on the Motorola PowerQUICC processor. The RDK supports PICMG
controller and 512KB SBSRAM 2.1 r2.0 Hot Swap and provides reusable hardware and software components to
■ One 10/100 Mbit Ethernet port shorten the design cycles of both hardware and software based on the PCI 9056
and two RS-232 serial ports and MPC850/860 PowerQUICC combination. The CompactPCI 9056RDK-860’s
software and hardware registers are backward-compatible with PLX’s CompactPCI
■ PLX Option Module (POM) 9054RDK-860, allowing designers to migrate their existing 32-bit, 33MHz PCI bus
expansion connector PowerQUICC designs into 32-bit, 66MHz PCI solutions. The RDK includes the PLX
■ MPC860 BDM development port Software Development Kit Professional Edition (SDK-PRO) to provide a comprehen-
sive host-side and local-side (embedded) software development platform. The
■ Includes 0.1" through hole grid
SDK-PRO is also compatible with Motorola's MPC850/860 PowerQUICC software
space for through hole devices development tools.
Complete Design A Complete Package
Documentation The CompactPCI hardware reference board serves as both a hardware and software
■ OrCAD schematics development platform for PCI 9056 based designs. The board is configured for
■ Bill of Materials (BOM) Motorola PowerQUICC Processor bus operation with a MPC860T processor on board.
Its local bus CPLD memory controller and SBSRAM demonstrates PCI 9056 long burst
■ OrCAD layout source with capability. It also has two RS232 serial ports and one 10/100Mbit Ethernet port which
Gerber output files can be used for embedded OS development purpose. A 0.1" through hole grid can be
■ CPLD memory controller used for through hole devices.
Verilog source code The Hardware Development Kit (HDK) CD-ROM includes complete documentation
of the reference board hardware design, making its components easily reusable
■ Allhardware manuals in in your designs. This documentation includes the OrCAD schematics, the OrCAD
PDF format layout source and
Comprehensive Software Gerber output files,
Development Environment BOM, the Verilog source
■ Windows 98/Me/NT/2000 code for the memory
32-bit/50MHz, Local Bus SRAM controller CPLD and
device drivers with source code Controller
CPLD manuals in PDF format.
■ PCI 9656 Host and Local APIs SDRAM The SDK-PRO is a
and object code libraries with Ethernet
SBSRAM comprehensive software
source code tool providing complete
32-bit/66MHz, CompactPCI Bus
■ PLXMon Windows GUI debug MPC860 Flash host and local side
tool for monitoring, debugging, software programming
PCI 9056
configuration, and code down- RS-232 capability. It includes
RS-232 Windows 98/Me/NT/2000
load J1
EEPROM drivers for the reference
■ VxWorks and Linux support board, PCI 9056 specific
■ Compatiblewith Motorola APIs and object code
MPC860 software libraries, the PLXMon
CompactPCI 9056RDK-860
development tools Windows GUI debug
Block Diagram tool, and VxWorks and
Linux OS supports. The
drivers and APIs source code are included so that you can easily modify them to fit
your special project needs. The APIs are backward compatible with the PCI 9054,
enabling the easy migration of PCI 9054 software to the PCI 9056.
CompactPCI 9056RDK-860 Board
Function Description
PCI Bus Interface PLX PCI 9056 I/O Accelerator
Processor Motorola MPC860T PowerQUICC
Processor Speed 32-bit, 50MHz Max
PCI Bus Speed 32-bit, 66MHz Max
Local Bus Speed 32-bit, 50MHz
SDRAM 64 Mbytes (16 M x 32)
SDRAM Controller MPC860 internal memory controller
Sync Burst SRAM 512 Kbytes (128K x 32)
Sync Burst SRAM Controller Lattice ispLSI 2064 V
Boot ROM Flash 512 Kbytes (512K x 8)
BULK Flash 8 Mbytes (8M x 8)
10/100 Mbit Ethernet port MPC860 10/100 NIC
Two RS-232 Serial Ports MPC860 SCC1 and SCC2
BDM Port MPC860 debug port
MPC860 Peripheral Port PLX Option Module 2 (POM2)
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trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this
material. PLX Technology reserves the right, without notice, to make changes in product design or specification.