UNIVERSITY VISVESVARAYA COLLEGE OF ENGINEERING

Digital System Design Lab (18CIPC307)

Faculty: Dr. Venkatesh
Course outcomes: After the completion of laboratory the student will be able to,
1. Simplify, design and implement Boolean expression/half and full adders using basic/universal
gates.
2. Design and implement the various combinational circuits using MSI components.
3. Implement and verify the truth tables of various flip-flops.
4. Design and implement the counters.
5. Design and implement the sequential circuits such as registers and sequence generator.
Lab experiments list:
1. Design code conversion circuit that converts Binary to Gray code using logic gates.
2. Design and implementation Binary to Excess-3 and vice versa using 7483 IC and Gates.
3. Design and implementation half adder and full adder circuit using NAND gates

4. Design and implementation of full adder/subtracter using 74153 IC

5. Design and implementation 4:1 multiplexer circuit using NAND gates.
6. Implementation of i) priority encoders and ii) LED decoder driver circuit.
7. Design and implementation of shift register to function as i) SISO, ii) SIPO, iii) PISO, iv)
PIPO.
8. Design and implementation BCD to seven segment using gates/IC
9. Design and implementation J K Master/Slave Flip Flop using NAND Gates and verify its
truth table
10. Design and Implement circuit that compare two binary number using 7485 comparator
11. Design and implementation R i n g counter and using 4-bit shift register.
12. Design and implementation of Asynchronous counter using decade counter IC.

1
 Practice Lab
Simplify the given Boolean expression and to realize them using logic gates/universal gates.
AIM: To simplify the given expression and to realize it using basic gates and universal gates.
LEARNING OBJECTIVE:
i) Simplify the Boolean expression and build the logic circuit.
ii) For a given truth table derive the Boolean expressions and build the logic circuit to
realize it.
COMPONENTS REQUIRED:
IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, Patch cards and IC Trainer Kit.
THEORY:
A Karnaugh map (K-map) is a pictorial method used to minimize Boolean expressions
without having to use Boolean algebra theorems and equation manipulations. A K-map can be
thought of as a special version of a truth table. Using a K-map, expressions with two to four
variables are easily minimized.
Canonical Forms (Normal Forms): Any Boolean function can be written in disjunctive
normal form (sum of min-terms) or conjunctive normal form (product of max-terms). A Boolean
function can be represented by a Karnaugh map in which each cell corresponds to a minterm.
The cells are arranged in such a way that any two immediately adjacent cells correspond to two
minterms of distance 1. There is more than one way to construct a map with this property.
Karnaugh Maps
For a function of two variables, say, f(x, y),

For a function of three variables, say, f(x, y, z)

2
For a function of four variables: f (w, x, y, z)

Realization of Boolean expression:

Y=A'B'CD'+A'BCD'+ABCD'+AB'CD'+AB'C'D'+AB'C'D+AB'CD

After simplifying using K-Map method we get Y=AB’+CD’

INPUTS OUTPUT
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0

3
Realization using NOR gates

2) For the given Truth Table, realize a logical circuit using basic gates and NAND gates

PROCEDURE:
 Check the components for their working.
 Insert the appropriate IC into the IC base.
 Rig up the circuit as shown in the logic circuit diagram.
 Apply various input data to the logic circuit via the input logic switches.
 Note down the corresponding output and verify the truth table.

Note: Write the pin numbers of each gate and also write the intermediate expressions.
RESULT:

4
 EXPERIMENT: 1
Design and implement Code Converter that converts Binary to Excess 3

AIM: Design and Implementing BCD TO Gray Code conversion.

Theory

In Gray Code only one bit changes at a time.

Writing truth table showing the relation between Binary as input and Gray code as output.
Since input is BCD, only 10 combinations can be made using 4 bits. (0 to 9).
For each Gray code output D3, D2, D1 and D0, write Karnaugh-Map.
From the K-Map, obtaining a simplified expression for each Gray Code output in terms of BCD inputs.
Realize the code converter using the Logic Gates.
By following actual process to convert BCD into Gray Code, Truth Table can be written as given below.

Truth Table relating BCD to Gray Code

Decimal BCD input Gray Code output

B3 B2 B1 B0 D3 D2 D2 D0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1

Boolean expression for each BCD bits can be written as

D3= m(8, 9)
D2= m(4, 5, 6, 7, 8, 9)
D1= m(2, 3, 4, 5)
D0= m(1, 2, 5, 6, 9)

5
Realizing code conversion using Logic Gates

6
 EXPERIMENT: 2
Design and implementation BCD to Excess and vice versa Using 7483 gates

Procedure:
 Check the components for their working.
 Insert the appropriate IC into the IC base.
 Rig up the circuit as shown in the logic circuit diagram.
 Apply various input data to the logic circuit via the input logic switches.
 Note down the corresponding output and verify the truth table.
Result:

BCD to Excess 3 Code Conversion:

Learning objective:
 To learn to realize BCD to Excess-3 code using adder IC 7483.
 To learn to realize Excess-3 to BCD Code using adder IC 7483.

Theory:
Code converter is a combinational circuit that translates the input code word into a new
corresponding word. The excess-3 code digit is obtained by adding three to the corresponding
BCD digit. To Construct a BCD-to-excess-3-code converter with a 4-bit adder feed BCD-code to
the 4-bit adder as the first operand and then feed constant 3 as the second operand. The output is
the corresponding excess-3 code.

To make it work as a excess-3 to BCD converter, we feed excess-3 code as the first operand and
then feed 2's complement of 3 as the second operand. The output is the BCD code.

Circuit Implementation:

7
Truth table:
BCD code Excess 3 Code
A4 A3 A2 A1 S4 S3 S2 S1
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

Excess 3 to BCD Code Conversion:

Truth table:
Excess 3 Code BCD code
A4 A3 A2 A1 S4 S3 S2 S1
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

Procedure:
 Check the components for their working.
 Insert the appropriate IC into the IC base.
 Rig up the circuit as shown in the logic circuit diagram.
 Apply various input data to the logic circuit via the input logic switches.
 Note down the corresponding output and verify the truth table.

Result:

8
 EXPERIMENT: 3
Design and implementation of half and full adder using logic and universal gates
AIM: To design and verify
i. Half adder and Full adder
ii. Half subtractor and Full subtractor using basic and NAND gates.

LEARNING OBJECTIVE:
 To design, realize and verify the adder and subtractor circuits using basic gates and
universal gates.
 To design, realize and verify full adder using two half adders.
 To design, realize and verify a full subtractor using two half subtractors.

COMPONENTS REQUIRED: IC 7400, IC 7408, IC 7486, and IC 7432, Patch cards and IC
Trainer Kit.

THEORY:
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B,
is called a half-adder. Addition will result in two output bits; one of which is the sum bit, S, and
the other is the carry bit, C. The Boolean functions describing the half-adder are:

S =A ⊕ B C=AB
Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This
carry bit from its previous stage is called carry-in bit. A combinational logic circuit that adds
two data bits, A and B, and a carry-in bit, Cin, is called a full-adder. The Boolean functions
describing the full-adder are:

S = (x ⊕ y) ⊕ Cin C = xy + Cin (x ⊕ y)
Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B) produces a
difference bit D and a borrow out bit B-out. This operation is called half subtraction and the
circuit to realize it is called a half subtractor. The Boolean functions describing the
halfSubtractor are:
S =A ⊕ B C = A’ B
Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A
produces a difference bit D and a borrow out Br bit. This is called full subtraction. The Boolean
functions describing the full-subtracter are:
D = (x ⊕ y) ⊕ Cin Br= A’B + A’ (Cin) + B (Cin)

9
 I. TO REALIZE HALF ADDER

II. TO REALIZE FULL ADDER

TRUTH TABLE BOOLEAN EXPRESSIONS:

1
0
 BASIC GATES

i) NAND GATES

III. HALF SUBTRACTOR

TRUTH TABLE BOOLEAN EXPRESSIONS:

INPUTS OUTPUT
A B D Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

1
1
IV. FULL SUBTRACTOR

TRUTH TABLE BOOLEAN EXPRESSIONS:

1
2
PROCEDURE:
 Check the components for their working
 Insert the appropriate IC into the IC base
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

RESULT:

13
 EXPERIMENT 4
Design and Implement Full adder and Full Subtractor Using 74153IC
Aim: To design Half and Full Adder using IC 74153

HALF ADDER USING MUX:

DESIGN:
SUM CARRY TRUTH TABLE
I0 I1 I0 I1 Input
0 1 0 1 s Outputs
2 3 2 3
A A’ 0 A A B S C
0 0 0 0
CIRCUIT: 0 1 1 0
1 0 1 0
1 1 0 1

FULL ADDER USING MUX:

DESIGN:
SUM CARRY
I0 I1 I3 I3
0 1 2 3 I0 I1 I3 I3
4 5 6 7 0 1 2 3
A A’ A’ A 4 5 6 7
0 A A 1
TRUTH TABLE
Inputs Outputs
A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

21
FULL ADDER CIRCUIT

HALF SUBTRACTOR USING MUX:

DESIGN:

DIFFERENCE BORROW
I0 I1 I0 I1
0 1 0 1
2 3 2 3
A A’ 0 A’

CIRCUIT: TRUTH TABLE

Inputs Outputs
A B D Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

22
 FULL SUBTRACTOR USING MUX:

DESIGN:
DIFFERENCE BORROW
I0 I1 I2 I3 I0 I1 I2 I3
0 1 2 3 0 1 2 3
4 5 6 7 4 5 6 7
A A’ A’ A 0 A’ A’ 1
TRUTH
TABLE

Inputs Outputs
A B C D Br
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

PROCEDURE:
• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.

RESULT:

23
 EXPERIMENT: 5
Design and Implement 4:1 MULTIPLEXER

LEARNING OBJECTIVE:
 To learn and understand the working of IC 74153

THEORY:
Multiplexers are very useful components in digital systems. They transfer a large
number of information units over a smaller number of channels, (usually one channel)
under the control of selection signals. Multiplexer means many to one. A multiplexer is
a circuit with many inputs but only one output. By using control signals (select lines)
we can select any input to the output. Multiplexer is also called as data selector because
the output bit depends on the input data bit that is selected. The general multiplexer
circuit has 2n input signals, n control/select signals and 1 output signal.

COMPONENTS REQUIRED:
IC 7400, IC 7410, IC 7420, IC 7404, IC 74153, IC 74139, Patch Cords & IC Trainer Kit.

ii) 4:1 MULTIPLEXER

4:1
Inputs MUX
Y

E’
Select
inputs
Output Y= E’S1’S0’I0 + E’S1’S0I1 + E’S1S0’I2 + E’S1S0I3

24
 TRUTH
REALIZATION USING NAND GATES TABLE

Select Enable Out

Inputs
Inputs Input put
s
S1 S0 E I0 I1 I2 I3 Y
X X 1 X X X X 0
0 0 0 0 X X X 0
0 0 0 1 X X X 1
0 1 0 X 0 X X 0
0 1 0 X 1 X X 1
1 0 0 X X 0 X 0
1 0 0 X X 1 X 1
1 1 0 X X X 0 0
1 1 0 X X X 1 1

VERIFY IC 74153 MUX (DUAL 4:1 MULTIPLEXER)

25
ii) DE-MUX USING NAND GATES
Enabl Data Select
Outputs
e Inpu Input
Inputs t s
E D S1 S0 Y3 Y2 Y1 Y0
1 0 X X X X X X
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 1 0 0
0 1 1 1 1 0 0 0

VERIFICATION OF IC 74139 (DEMUX)

TRUTH TABLE

Inputs Outputs
Ea S1 S0 Y3 Y2 Y1 Y0
1 X X 1 1 1 1
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 1

20
 Experiment 7
BCD to Seven Segment Display

A digital or binary decoder is a digital combinational logic circuit which can convert one form
of digital code into another form.
BCD to 7-segment display decoder is a special decoder which can convert binary coded
decimals into another form which can be easily displayed through a 7-segment display.

BCD
BCD stands for binary coded decimal. It is a digital numbering system in which we can
represent each decimal number using 4 bits of binary numbers.
There are 10 digits in the decimal system. To represent all 10 digits we need 10 combinations
of 4 binary bits.

A digital system like a computer can understand and easily read a large number in binary
format. However, a human cannot read large binary numbers. To solve this problem we need to
display it as a decimal digit using 7-segment display.

Output A

20
20
20
20
20
 EXPERIMENT 6

AIM: To realize and study of Shift Register.

1) SISO (Serial in Serial out)
2) SIPO (Serial in Parallel out)
3) PIPO (Parallel in Parallel out)
4) PISO (Parallel in Serial out)
LEARNING OBJECTIVES:
To illustrate the operation of shift registers
To study different shift register configurations
COMPONENTS REQUIRED: IC 7495,IC 7474, Patch Cords & IC Trainer Kit.
Theory:
Shift registers are a type of sequential logic circuit, mainly for storage of
digital data. They are a group of flip-flops connected in a chain so that the
output from one flip-flop becomes the input of the next flip-flop. All the flip-flops
are driven by a common clock, and all are set or reset simultaneously.
The serial in/serial out shift register accepts data serially – that is, one bit at a
time on a single line. It produces the stored information on its output also in
serial form.
The serial in/parallel out shift register accepts data serially – that is, one bit at a
time on a single line. It produces the stored information on its output in parallel
form.
The parallel in/serial out shift register accepts data in parallel. It produces the
stored information on its output also in serial form.
The parallel in/parallel out shift register accepts data in parallel. It produces the
stored information on its output in parallel form.

20
SERIAL IN SERIAL OUT:
LOGIC DIAGRAM:

OUTPUT WAVEFORM:

TRUTH TABLE:
CLK Serial in Serial out
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

20
SERIAL IN PARALLEL OUT:
LOGIC DIAGRAM:

OUTPUT WAVEFORM:

TRUTH TABLE:
OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

Lab Manual EC37L Page 50

PARALLEL IN SERIAL OUT:

LOGIC DIAGRAM:

OUTPUT WAVEFORM:

TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
PARALLEL IN PARALLEL
OUT: LOGIC DIAGRAM:

TRUTH TABLE:
DATA INPUT OUTPUT
CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

PROCEDURE:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Rig up the circuit as shown in the logic circuit diagram.
4. Apply various input data to the logic circuit via the input logic switches.
5. Note down the corresponding output and verify the truth table.
Shift Registers using

IC 7495 PIN

DIAGRAM
 EXPERIMENT 8

MOD 4-BIT BINARY UP/DOWN COUNTER

AIM: To design IC 74193 as a up/down counter

COMPONENTS REQUIRED:
IC 74193, Patch Cords & IC Trainer Kit
PIN DETAILS OF IC 74193

1. P1,P2,P3 and P0 are parallel data inputs

2. Q0,Q1,Q2 and Q3 are flip-flop outputs
3. MR: Asynchronous master reset
4. PL: Asynchronous parallel load(active low) input
5. TCd : Terminal count-down output
6. TCu : Terminal count-up output
Up counter Down counter

CLK QD QC QB QA CLK QD QC QB QA

0 0 0 0 0 0 1 1 1 1
1 0 0 0 1 1 1 1 1 0
2 0 0 1 0 2 1 1 0 1
3 0 0 1 1 3 1 1 0 0
4 0 1 0 0 4 1 0 1 1
5 0 1 0 1 5 1 0 1 0
6 0 1 1 0 6 1 0 0 1
7 0 1 1 1 7 1 0 0 0
8 1 0 0 0 8 0 1 1 1
9 1 0 0 1 9 0 1 1 0
10 1 0 1 0 10 0 1 0 1
11 1 0 1 1 11 0 1 0 0
12 1 1 0 0 12 0 0 1 1
13 1 1 0 1 13 0 0 1 0
14 1 1 1 0 14 0 0 0 1
15 1 1 1 1 15 0 0 0 0
16 0 0 0 0 16 1 1 1 1

Design up/ down counter using presettable counter

CIRCUIT DIAGRAM
PROCEDURE:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Rig up the circuit as shown in the logic circuit diagram.
4. Apply the parallel input to p0 to p3 and Give the Load pin to logic LOW.
5. To start counting connect Load input to logic HIGH.
6. Apply the clock pulse to observe the output.( For up-counter make clock down to
be at logic 1 and give the clock input to Clock up input, for down counter make
clock up to be at logic 1 and give the clock input to Clock down input)

Note:
1. For up-counter make clock down to be at logic 1 and give the clock input to
Clock up input.
2. For down counter make clock up to be at logic 1 and give the clock input to
Clock down input
3. Write the pin numbers of each gate and also write the intermediate expressions.

RESULT:
 II. STUDY OF 7490 BCD COUNTER

AIM: To design IC 7490 as a decade counter with BCD count sequence

COMPONENTS REQUIRED:
IC 7490, Patch Cords & IC Trainer Kit

DECADE COUNTER:

TRUTH TABLE:
QD QC QB QA
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
0 0 0 0

PROCEDURE:

2. Check the components for their working.

3. Insert the appropriate IC into the IC base.
4. Rig up the circuit as shown in the logic circuit diagram.
5. Apply various input data to the logic circuit via the input logic switches.
6. Note down the corresponding output and verify the truth table.
 EXPERIMENT: 10
BINARY NUMBERS COMPARATORS

AIM: To realize One & Two Bit Comparator and study of 7485 magnitude comparator.

LEARNING OBJECTIVE:
 To learn about various applications of comparator
 To learn and understand the working of IC 7485 magnitude comparator To learn to
realize 8-bit comparator using 4-bit comparator

THEORY:
Magnitude Comparator is a logical circuit, which compares two signals A and B and
generates three logical outputs, whether A > B, A = B, or A < B. IC 7485 is a high
speed 4-bit Magnitude comparator , which compares two 4-bit words . The A = B
Input must be held high for proper compare operation.

COMPONENTS REQUIRED:
IC 7400, IC 7410, IC 7420, IC 7432, IC 7486, IC 7402, IC 7408, IC 7404, IC 7485,
Patch Cords & IC Trainer Kit.

1) 1- BIT COMPARATOR TRUTH TABLE

_
A>B = A B
_
A<B = A B INPUTS OUTPUTS
_ _
A=B = A B +AB A B A >B A =B A<B
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

2) 2- BIT COMPARATOR
_ _ _ _
(A>B)= A1 A0 B1 B B 0 A1A0
B1 + 0+
(A=B) = (A0 ⊕ B0) B1)
(A1 ⊕
− _ _ _
(A<B) = B1 A1 +B0 A1 A 0 + A 0B1B0
 TRUTH TABLE

INPUTS OUTPUTS
A1 A0 B1 B0 A >B A =B A <B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
T
O

C
O
M A B Result
P A3 A2 A1 A0 B3 B2 B1 B0
A 0 0 0 1 0 0 0 0 A>B
R
E 0 0 0 1 0 0 0 1 A=B
0 0 0 0 0 0 0 1 A<B
T
H PROCEDURE:
E • Check all the components for their working.
• Insert the appropriate IC into the IC base.
G • Make connections as shown in the circuit diagram.
I • Verify the Truth Table and observe the outputs.
V
E
N
Comparator using 7485
D
A
T The Integrated Circuit (IC) available for 4 bit digital comparator is IC 7485.
A For more bit comparison, more than one such ICs can be cascaded. This IC
has three terminals, labeled as (A in, (A = B)in and (A > B)in and other three
U terminals labeled as, as (A out, (A = B)out and (A > B)out. During cascading of
S two 7485 ICs, (A out, (A = B)out and (A > B)out of lower order IC would be
I connected to (A in, (A = B)in and (A > B)in of higher order IC, respectively.
N
G

7
4
8
5

C
H
I
P
.