A

INDUSTRIAL TRAINING
PROJECT REPORT
ON
“VHDL Coding for Decade Counter on Xilinx and create Test Waveform”

In partial fulfillment for the award of the Degree of

BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING

Submitted by
MOHD SHADAN KHAN

Under the Guidance of

Mr. Krishan Kumar Singh Yadav Sir

CERTIFICATE OF ORIGINALITY
This is to certify that the project titled “VHDL Coding for Decade Counter on Xilinx and

create Test Waveform”is an original work of the student and is being submitted in partial

fulfillment for the award of the Bachelor of technology Degree of DIBRUGARH

UNIVERSITY INSTITUTE OF ENGINEERING AND TECHNOLOGY. This report has not

been submitted earlier either to this university or to any other University/Institution for the

fulfillment of the requirement of a course of study.

SIGNATURE OF SUPERVISOR SIGNATURE OF STUDENT

(Mr. Krishan Kumar Yadav) (Mohd. Shadan Khan)

Place: Place:

Date: Date:

CONTENTS
Serial no. Topic

1 Abstract

2 Introduction To VLSI

3 Project Description

4 Conclusion

5 References

ABSTRACT
VHDL stands for VHSIC Hardware Description Language. VHSIC means Very
High Speed Integrated Circuits. VHDL is an industry-standard language for
modeling and synthesizing digital hardware, particularly for
programmable logic or Application Specific Integrated
Circuits. The VHDL simulation serves as a basis for testing
complex designs and validating the design prior to
fabrication. As a result, the redesign is reduced, the design
cycle is shortened, and the product is brought to market
sooner. A VHDL program can be considered as a
description of a digital system; the associated simulator will
use this description to produce behavior that will mimic that
of the physical system.

Xilinx ISE means Xilinx Integrated Software Environment (ISE). This Xilinx
design software suite allows you to take your design from design entry through
Xilinx device programming. The ISE Project Navigator manages and processes
your design through several steps in the ISE design flow. These steps are Design
Entry, Synthesis, Implementation, Simulation/Verification, and Device
Configuration.

In this project,we are going to create a counter in the Xilinx ISE and how to
simulate it with ISE Simulator. We are going to create a test bench waveform
containing input stimulus we can use to simulate the counter module. This test
bench waveform is a graphical view of a test bench.

INTRODUCTION TO VLSI
Very-Large-Scale Integration (VLSI) is the process of creating
an integratedcircuit (IC) by combining thousands of transistors into a single
chip.
VLSI began in the 1970s when complex semiconductor and
communication technologies were being developed. The microprocessor is a
VLSI device. Before the introduction of VLSI technology most ICs had a
limited set of functions they could perform. An electroniccircuit might consist
of a CPU, ROM, RAM and other gluelogic. VLSI lets IC designers add all of
these into one chip. IT IS the current level of computer microchip
miniaturization and refers to microchips containing in the hundreds of
thousands of transistors.
LSI (Large-Scale Integration) meant microchips containing thousands of
transistors. Earlier, MSI (Medium-Scale Integration) meant a microchip
containing hundreds of transistors and SSI (Small-Scale Integration) meant
transistors in the tens.

DECADE COUNTER IN VLSI

A decade counter is an electronic circuit that counts in tens.

Typically, this type of counter has decoded outputs, meaning that it has 10
outputs, and each one goes high in sequence, all other being low. An example of
an integrated circuit that is of this type is the 4017 in the 4000 series CMOS
logic family.
 FIG: DECADE COUNTER IC

One unusual use for a decade counter is as a demultiplexer in a radio control

receiver. In a classic RC system, each channel is encoded as a pulse of a certain
length, followed by a gap, followed by the next pulse. After 7 pulses, a longer
gap signifies starting the sequence again. By clocking the decade counter with
the pulse train, each output is each separate channel, isolated. The pulse widths
are preserved. Each channel can now connect to its servo, which further
interprets the pulse width as a servo position. The longer gap is detected by a
simple RC timing circuit, which causes the counter to reset, starting over from
the first channel.

SIGNIFICANCE OF DECADE COUNTER

A decade counter is a binary counter that is designed to count from

00002 to10102. An ordinary four-stage counter can be easily modified to a
decade counter by adding a NAND gate as shown in figure 3-25. Notice that
FF2 and FF4 provide the inputs to the NAND gate. The NAND gate outputs are
connected to the CLR input of each of the FFs.
The counter operates as a normal counter until it reaches a count of 10102, or
1010. At that time, both inputs to the NAND gate are HIGH, and the output goes
LOW. This LOW applied to the CLR input of the FFs causes them to reset to 0.
Remember from the discussion of J-K FFs that CLR and PS or PR override any
existing condition of the FF. Once the FFs are reset, the count may begin again.
The following table shows the binary count and the inputs and outputs of the
NAND gate for each count of the decade counter:

BINARY NAND NAND GATE

COUNT GATE OUTPUT
INPUTS
******* A B *******
0000 0 0 1
0001 0 0 1
0010 1 0 1
0011 1 0 1
0100 0 0 1
0101 0 0 1
0110 1 0 1
0111 1 0 1
1000 0 1 1
1001 0 1 1

Changing the inputs to the NAND gate can cause the maximum count to be
changed

PROJECT DESCRIPTION

COMPONENT USED: (1) 4 JK FLIP-FLOP

(2) 31 NOT GATE

(3) 11 4-INPUT AND GATE

(4) 2-INPUT AND GATE

 PROJECT INTERFACE

CODES:
library ieee;

use ieee.std_logic_1164.ALL;

use ieee.numeric_std.ALL;

library UNISIM;

use UNISIM.Vcomponents.ALL;

entity INV4_MXILINX_co is

port ( I0 : in std_logic;

I1 : in std_logic;
 I2 : in std_logic;

I3 : in std_logic;

O0 : out std_logic;

O1 : out std_logic;

O2 : out std_logic;

O3 : out std_logic);

end INV4_MXILINX_co;

architecture BEHAVIORAL of INV4_MXILINX_co is

attribute BOX_TYPE : string ;

component INV

port ( I : in std_logic;

O : out std_logic);

end component;

attribute BOX_TYPE of INV : component is "BLACK_BOX";

begin

I_36_37 : INV

port map (I=>I3,

O=>O3);

I_36_38 : INV

port map (I=>I2,

O=>O2);

I_36_39 : INV

port map (I=>I1,

O=>O1);

I_36_40 : INV

port map (I=>I0,

O=>O0);
 end BEHAVIORAL;

library ieee;

use ieee.std_logic_1164.ALL;

use ieee.numeric_std.ALL;

library UNISIM;

use UNISIM.Vcomponents.ALL;

entity FDC_MXILINX_co is

port ( C : in std_logic;

CLR : in std_logic;

D : in std_logic;

Q : out std_logic);

end FDC_MXILINX_co;

architecture BEHAVIORAL of FDC_MXILINX_co is

attribute BOX_TYPE : string ;

signal XLXN_5 : std_logic;

component GND

port ( G : out std_logic);

end component;

attribute BOX_TYPE of GND : component is "BLACK_BOX";

component FDCP

port ( C : in std_logic;

CLR : in std_logic;

D : in std_logic;

PRE : in std_logic;

Q : out std_logic);

end component;

attribute BOX_TYPE of FDCP : component is "BLACK_BOX";

begin
 I_36_55 : GND

port map (G=>XLXN_5);

U0 : FDCP

port map (C=>C,

CLR=>CLR,

D=>D,

PRE=>XLXN_5,

Q=>Q);

end BEHAVIORAL;

library ieee;

use ieee.std_logic_1164.ALL;

use ieee.numeric_std.ALL;

library UNISIM;

use UNISIM.Vcomponents.ALL;

entity FJKC_MXILINX_co is

port ( C : in std_logic;

CLR : in std_logic;

J : in std_logic;

K : in std_logic;

Q : out std_logic);

end FJKC_MXILINX_co;

architecture BEHAVIORAL of FJKC_MXILINX_co is

attribute HU_SET : string ;

attribute BOX_TYPE : string ;

signal AD : std_logic;

signal A0 : std_logic;

signal A1 : std_logic;

signal A2 : std_logic;
signal Q_DUMMY : std_logic;

component FDC_MXILINX_co

port ( C : in std_logic;

CLR : in std_logic;

D : in std_logic;

Q : out std_logic);

end component;

component AND3B2

port ( I0 : in std_logic;

I1 : in std_logic;

I2 : in std_logic;

O : out std_logic);

end component;

attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";

component AND3B1

port ( I0 : in std_logic;

I1 : in std_logic;

I2 : in std_logic;

O : out std_logic);

end component;

attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";

component OR3

port ( I0 : in std_logic;

I1 : in std_logic;

I2 : in std_logic;

O : out std_logic);

end component;

attribute BOX_TYPE of OR3 : component is "BLACK_BOX";

 component AND2B1

port ( I0 : in std_logic;

I1 : in std_logic;

O : out std_logic);

end component;

attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";

attribute HU_SET of I_36_32 : label is "I_36_32_0";

begin

Q <= Q_DUMMY;

I_36_32 : FDC_MXILINX_co

port map (C=>C,

CLR=>CLR,

D=>AD,

Q=>Q_DUMMY);

I_36_37 : AND3B2

port map (I0=>J,

I1=>K,

I2=>Q_DUMMY,

O=>A0);

I_36_40 : AND3B1

port map (I0=>Q_DUMMY,

I1=>K,

I2=>J,

O=>A1);

I_36_41 : OR3

port map (I0=>A2,

I1=>A1,

I2=>A0,
 O=>AD);

I_36_43 : AND2B1

port map (I0=>K,

I1=>J,

O=>A2);

end BEHAVIORAL

library ieee;

use ieee.std_logic_1164.ALL;

use ieee.numeric_std.ALL;

library UNISIM;

use UNISIM.Vcomponents.ALL;

entity co is

port ( C : in std_logic;

R : in std_logic;

V : in std_logic;

D0 : out std_logic;

D1 : out std_logic;

D2 : out std_logic;

D3 : out std_logic;

D4 : out std_logic;

D5 : out std_logic;

D6 : out std_logic;

D7 : out std_logic;

D8 : out std_logic;

D9 : out std_logic);

end co;

architecture BEHAVIORAL of co is

attribute HU_SET : string ;

attribute BOX_TYPE : string ;

signal XLXN_1 : std_logic;

signal XLXN_2 : std_logic;

signal XLXN_3 : std_logic;

signal XLXN_4 : std_logic;

signal XLXN_5 : std_logic;

signal XLXN_6 : std_logic;

signal XLXN_7 : std_logic;

signal XLXN_8 : std_logic;

signal XLXN_9 : std_logic;

signal XLXN_10 : std_logic;

signal XLXN_11 : std_logic;

signal XLXN_12 : std_logic;

signal XLXN_13 : std_logic;

signal XLXN_14 : std_logic;

signal XLXN_15 : std_logic;

signal XLXN_16 : std_logic;

signal XLXN_17 : std_logic;

signal XLXN_18 : std_logic;

signal XLXN_19 : std_logic;

signal XLXN_20 : std_logic;

signal XLXN_21 : std_logic;

signal XLXN_22 : std_logic;

signal XLXN_23 : std_logic;

signal XLXN_24 : std_logic;

signal XLXN_25 : std_logic;

signal XLXN_26 : std_logic;

signal XLXN_27 : std_logic;

signal XLXN_32 : std_logic;

signal XLXN_33 : std_logic;

signal XLXN_34 : std_logic;

signal XLXN_35 : std_logic;

signal XLXN_43 : std_logic;

signal XLXN_44 : std_logic;

signal XLXN_46 : std_logic;

signal XLXN_62 : std_logic;

signal XLXN_63 : std_logic;

signal XLXN_68 : std_logic;

component FJKC_MXILINX_co

port ( C : in std_logic;

CLR : in std_logic;

J : in std_logic;

K : in std_logic;

Q : out std_logic);

end component;

component AND4

port ( I0 : in std_logic;

I1 : in std_logic;

I2 : in std_logic;

I3 : in std_logic;

O : out std_logic);

end component;

attribute BOX_TYPE of AND4 : component is "BLACK_BOX";

component INV4_MXILINX_co

port ( I0 : in std_logic;

I1 : in std_logic;
 I2 : in std_logic;

I3 : in std_logic;

O0 : out std_logic;

O1 : out std_logic;

O2 : out std_logic;

O3 : out std_logic);

end component;

component INV

port ( I : in std_logic;

O : out std_logic);

end component;

attribute BOX_TYPE of INV : component is "BLACK_BOX";

component AND2

port ( I0 : in std_logic;

I1 : in std_logic;

O : out std_logic);

end component;

attribute BOX_TYPE of AND2 : component is "BLACK_BOX";

attribute HU_SET of XLXI_1 : label is "XLXI_1_1";

attribute HU_SET of XLXI_2 : label is "XLXI_2_2";

attribute HU_SET of XLXI_3 : label is "XLXI_3_3";

attribute HU_SET of XLXI_4 : label is "XLXI_4_4";

attribute HU_SET of XLXI_16 : label is "XLXI_16_5";

begin

XLXI_1 : FJKC_MXILINX_co

port map (C=>C,

CLR=>XLXN_43,

J=>V,
 K=>V,

Q=>XLXN_35);

XLXI_2 : FJKC_MXILINX_co

port map (C=>XLXN_35,

CLR=>XLXN_43,

J=>V,

K=>V,

Q=>XLXN_32);

XLXI_3 : FJKC_MXILINX_co

port map (C=>XLXN_32,

CLR=>XLXN_43,

J=>V,

K=>V,

Q=>XLXN_33);

XLXI_4 : FJKC_MXILINX_co

port map (C=>XLXN_33,

CLR=>XLXN_43,

J=>V,

K=>V,

Q=>XLXN_34);

XLXI_5 : AND4

port map (I0=>XLXN_1,

I1=>XLXN_2,

I2=>XLXN_3,

I3=>XLXN_4,

O=>D0);

XLXI_6 : AND4
 port map (I0=>XLXN_44,

I1=>XLXN_5,

I2=>XLXN_6,

I3=>XLXN_7,

O=>D1);

XLXI_7 : AND4

port map (I0=>XLXN_8,

I1=>XLXN_63,

I2=>XLXN_9,

I3=>XLXN_10,

O=>D2);

XLXI_9 : AND4

port map (I0=>XLXN_13,

I1=>XLXN_14,

I2=>XLXN_46,

I3=>XLXN_15,

O=>D4);

XLXI_10 : AND4

port map (I0=>XLXN_44,

I1=>XLXN_16,

I2=>XLXN_46,

I3=>XLXN_17,

O=>D5);

XLXI_11 : AND4

port map (I0=>XLXN_18,

I1=>XLXN_63,

I2=>XLXN_46,

I3=>XLXN_19,
 O=>D6);

XLXI_12 : AND4

port map (I0=>XLXN_44,

I1=>XLXN_63,

I2=>XLXN_46,

I3=>XLXN_20,

O=>D7);

XLXI_13 : AND4

port map (I0=>XLXN_23,

I1=>XLXN_21,

I2=>XLXN_22,

I3=>XLXN_62,

O=>D8);

XLXI_14 : AND4

port map (I0=>XLXN_44,

I1=>XLXN_24,

I2=>XLXN_25,

I3=>XLXN_62,

O=>D9);

XLXI_16 : INV4_MXILINX_co

port map (I0=>XLXN_44,

I1=>XLXN_63,

I2=>XLXN_46,

I3=>XLXN_62,

O0=>XLXN_1,

O1=>XLXN_2,

O2=>XLXN_3,

O3=>XLXN_4);
XLXI_17 : INV

port map (I=>XLXN_63,

O=>XLXN_5);

XLXI_18 : INV

port map (I=>XLXN_46,

O=>XLXN_6);

XLXI_19 : INV

port map (I=>XLXN_62,

O=>XLXN_7);

XLXI_20 : INV

port map (I=>XLXN_44,

O=>XLXN_8);

XLXI_22 : INV

port map (I=>XLXN_62,

O=>XLXN_10);

XLXI_23 : INV

port map (I=>XLXN_46,

O=>XLXN_11);

XLXI_24 : INV

port map (I=>XLXN_62,

O=>XLXN_12);

XLXI_25 : INV

port map (I=>XLXN_44,

O=>XLXN_13);

XLXI_26 : INV

port map (I=>XLXN_63,

O=>XLXN_14;

XLXI_27 : INV
 port map (I=>XLXN_62,

O=>XLXN_15);

XLXI_28 : INV

port map (I=>XLXN_63,

O=>XLXN_16);

XLXI_29 : INV

port map (I=>XLXN_62,

O=>XLXN_17);

XLXI_30 : INV

port map (I=>XLXN_44,

O=>XLXN_18);

XLXI_31 : INV

port map (I=>XLXN_62,

O=>XLXN_19);

XLXI_32 : INV

port map (I=>XLXN_62,

O=>XLXN_20);

XLXI_33 : INV

port map (I=>XLXN_63,

O=>XLXN_21);

XLXI_34 : INV

port map (I=>XLXN_46,

O=>XLXN_22);

XLXI_35 : INV

port map (I=>XLXN_44,

O=>XLXN_23);

XLXI_36 : INV

port map (I=>XLXN_63,

 O=>XLXN_24);

XLXI_37 : INV

port map (I=>XLXN_46,

O=>XLXN_25);

XLXI_38 : INV

port map (I=>XLXN_44,

O=>XLXN_26);

XLXI_39 : INV

port map (I=>XLXN_46,

O=>XLXN_27);

XLXI_40 : INV

port map (I=>XLXN_35,

O=>XLXN_44);

XLXI_41 : INV

port map (I=>XLXN_32,

O=>XLXN_63);

XLXI_42 : INV

port map (I=>XLXN_33,

O=>XLXN_46);

XLXI_43 : INV

port map (I=>XLXN_34,

O=>XLXN_62);

XLXI_45 : INV

port map (I=>XLXN_46,

O=>XLXN_9);

XLXI_46 : AND4

port map (I0=>XLXN_44,

I1=>XLXN_63,
 I2=>XLXN_11,

I3=>XLXN_12,

O=>D3);

XLXI_48 : AND4

port map (I0=>XLXN_26,

I1=>XLXN_63,

I2=>XLXN_27,

I3=>XLXN_62,

O=>XLXN_68);

XLXI_49 : AND2

port map (I0=>XLXN_68,

I1=>R,

O=>XLXN_43);

end BEHAVIORAL;

map (G=>XLXN_5);

U0 : FDCP

port map (C=>C,

CLR=>CLR,

D=>D,

PRE=>XLXN_5,

Q=>Q);

end BEHAVIORAL;

library ieee;

use ieee.std_logic_1164.ALL;

use ieee.numeric_std.ALL;

library UNISIM;

use UNISIM.Vcomponents.ALL;

entity FJKC_MXILINX_co is
 port ( C : in std_logic;

CLR : in std_logic;

J : in std_logic;

K : in std_logic;

Q : out std_logic);

end FJKC_MXILINX_co;

architecture BEHAVIORAL of FJKC_MXILINX_co is

attribute HU_SET : string ;

attribute BOX_TYPE : string ;

signal AD : std_logic;

signal A0 : std_logic;

signal A1 : std_logic;

signal A2 : std_logic;

signal Q_DUMMY : std_logic;

component FDC_MXILINX_co

port ( C : in std_logic;

CLR : in std_logic;

D : in std_logic;

Q : out std_logic);

end component;

component AND3B2

port ( I0 : in std_logic;

I1 : in std_logic;

I2 : in std_logic;

O : out std_logic);

end component;

attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";

component AND3B1
 port ( I0 : in std_logic;

I1 : in std_logic;

I2 : in std_logic;

O : out std_logic);

end component;

attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";

component OR3

port ( I0 : in std_logic;

I1 : in std_logic;

I2 : in std_logic;

O : out std_logic);

end component;

attribute BOX_TYPE of OR3 : component is "BLACK_BOX";

component AND2B1

port ( I0 : in std_logic;

I1 : in std_logic;

O : out std_logic);

end component;

attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";

attribute HU_SET of I_36_32 : label is "I_36_32_0";

begin

Q <= Q_DUMMY;

I_36_32 : FDC_MXILINX_co

port map (C=>C,

CLR=>CLR,

D=>AD,

Q=>Q_DUMMY);

I_36_37 : AND3B2
 port map (I0=>J,

I1=>K,

I2=>Q_DUMMY,

O=>A0);

I_36_40 : AND3B1

port map (I0=>Q_DUMMY,

I1=>K,

I2=>J,

O=>A1);

I_36_41 : OR3

port map (I0=>A2,

I1=>A1,

I2=>A0,

O=>AD);

I_36_43 : AND2B1

port map (I0=>K,

I1=>J,

O=>A2);

end BEHAVIORAL

library ieee;

use ieee.std_logic_1164.ALL;

use ieee.numeric_std.ALL;

library UNISIM;

use UNISIM.Vcomponents.ALL;

entity co is

port ( C : in std_logic;

R : in std_logic;

V : in std_logic;
 D0 : out std_logic;

D1 : out std_logic;

D2 : out std_logic;

D3 : out std_logic;

D4 : out std_logic;

D5 : out std_logic;

D6 : out std_logic;

D7 : out std_logic;

D8 : out std_logic;

D9 : out std_logic);

end co;

architecture BEHAVIORAL of co is

attribute HU_SET : string ;

attribute BOX_TYPE : string ;

signal XLXN_1 : std_logic;

signal XLXN_2 : std_logic;

signal XLXN_3 : std_logic;

signal XLXN_4 : std_logic;

signal XLXN_5 : std_logic;

signal XLXN_6 : std_logic;

signal XLXN_7 : std_logic;

signal XLXN_8 : std_logic;

signal XLXN_9 : std_logic;

signal XLXN_10 : std_logic;

signal XLXN_11 : std_logic;

signal XLXN_12 : std_logic;

signal XLXN_13 : std_logic;

signal XLXN_14 : std_logic;

signal XLXN_15 : std_logic;

signal XLXN_16 : std_logic;

signal XLXN_17 : std_logic;

signal XLXN_18 : std_logic;

signal XLXN_19 : std_logic;

signal XLXN_20 : std_logic;

signal XLXN_21 : std_logic;

signal XLXN_22 : std_logic;

signal XLXN_23 : std_logic;

signal XLXN_24 : std_logic;

signal XLXN_25 : std_logic;

signal XLXN_26 : std_logic;

signal XLXN_27 : std_logic;

signal XLXN_32 : std_logic;

signal XLXN_33 : std_logic;

signal XLXN_34 : std_logic;

signal XLXN_35 : std_logic;

signal XLXN_43 : std_logic;

signal XLXN_44 : std_logic;

signal XLXN_46 : std_logic;

signal XLXN_62 : std_logic;

signal XLXN_63 : std_logic;

signal XLXN_68 : std_logic;

component FJKC_MXILINX_co

port ( C : in std_logic;

CLR : in std_logic;

J : in std_logic;

K : in std_logic;
 Q : out std_logic);

end component;

component AND4

port ( I0 : in std_logic;

I1 : in std_logic;

I2 : in std_logic;

I3 : in std_logic;

O : out std_logic);

end component;

attribute BOX_TYPE of AND4 : component is "BLACK_BOX";

component INV4_MXILINX_co

port ( I0 : in std_logic;

I1 : in std_logic;

I2 : in std_logic;

I3 : in std_logic;

O0 : out std_logic;

O1 : out std_logic;

O2 : out std_logic;

O3 : out std_logic);

end component;

component INV

port ( I : in std_logic;

O : out std_logic);

end component;

attribute BOX_TYPE of INV : component is "BLACK_BOX";

component AND2

port ( I0 : in std_logic;

I1 : in std_logic;
 O : out std_logic);

end component;

attribute BOX_TYPE of AND2 : component is "BLACK_BOX";

attribute HU_SET of XLXI_1 : label is "XLXI_1_1";

attribute HU_SET of XLXI_2 : label is "XLXI_2_2";

attribute HU_SET of XLXI_3 : label is "XLXI_3_3";

attribute HU_SET of XLXI_4 : label is "XLXI_4_4";

attribute HU_SET of XLXI_16 : label is "XLXI_16_5";

begin

XLXI_1 : FJKC_MXILINX_co

port map (C=>C,

CLR=>XLXN_43,

J=>V,

K=>V,

Q=>XLXN_35);

XLXI_2 : FJKC_MXILINX_co

port map (C=>XLXN_35,

CLR=>XLXN_43,

J=>V,

K=>V,

Q=>XLXN_32);

XLXI_3 : FJKC_MXILINX_co

port map (C=>XLXN_32,

CLR=>XLXN_43,

J=>V,

K=>V,

Q=>XLXN_33);
XLXI_4 : FJKC_MXILINX_co

port map (C=>XLXN_33,

CLR=>XLXN_43,

J=>V,

K=>V,

Q=>XLXN_34);

XLXI_5 : AND4

port map (I0=>XLXN_1,

I1=>XLXN_2,

I2=>XLXN_3,

I3=>XLXN_4,

O=>D0);

XLXI_6 : AND4

port map (I0=>XLXN_44,

I1=>XLXN_5,

I2=>XLXN_6,

I3=>XLXN_7,

O=>D1);

XLXI_7 : AND4

port map (I0=>XLXN_8,

I1=>XLXN_63,

I2=>XLXN_9,

I3=>XLXN_10,

O=>D2);

XLXI_9 : AND4

port map (I0=>XLXN_13,

I1=>XLXN_14,

I2=>XLXN_46,
 I3=>XLXN_15,

O=>D4);

XLXI_10 : AND4

port map (I0=>XLXN_44,

I1=>XLXN_16,

I2=>XLXN_46,

I3=>XLXN_17,

O=>D5);

XLXI_11 : AND4

port map (I0=>XLXN_18,

I1=>XLXN_63,

I2=>XLXN_46,

I3=>XLXN_19,

O=>D6);

XLXI_12 : AND4

port map (I0=>XLXN_44,

I1=>XLXN_63,

I2=>XLXN_46,

I3=>XLXN_20,

O=>D7);

XLXI_13 : AND4

port map (I0=>XLXN_23,

I1=>XLXN_21,

I2=>XLXN_22,

I3=>XLXN_62,

O=>D8);

XLXI_14 : AND4

port map (I0=>XLXN_44,

 I1=>XLXN_24,

I2=>XLXN_25,

I3=>XLXN_62,

O=>D9);

XLXI_16 : INV4_MXILINX_co

port map (I0=>XLXN_44,

I1=>XLXN_63,

I2=>XLXN_46,

I3=>XLXN_62,

O0=>XLXN_1,

O1=>XLXN_2,

O2=>XLXN_3,

O3=>XLXN_4);

XLXI_17 : INV

port map (I=>XLXN_63,

O=>XLXN_5);

XLXI_18 : INV

port map (I=>XLXN_46,

O=>XLXN_6);

XLXI_19 : INV

port map (I=>XLXN_62,

O=>XLXN_7);

XLXI_20 : INV

port map (I=>XLXN_44,

O=>XLXN_8);

XLXI_22 : INV

port map (I=>XLXN_62,

O=>XLXN_10);
XLXI_23 : INV

port map (I=>XLXN_46,

O=>XLXN_11);

XLXI_24 : INV

port map (I=>XLXN_62,

O=>XLXN_12);

XLXI_25 : INV

port map (I=>XLXN_44,

O=>XLXN_13);

XLXI_26 : INV

port map (I=>XLXN_63,

O=>XLXN_14;

XLXI_27 : INV

port map (I=>XLXN_62,

O=>XLXN_15);

XLXI_28 : INV

port map (I=>XLXN_63,

O=>XLXN_16);

XLXI_29 : INV

port map (I=>XLXN_62,

O=>XLXN_17);

XLXI_30 : INV

port map (I=>XLXN_44,

O=>XLXN_18);

XLXI_31 : INV

port map (I=>XLXN_62,

O=>XLXN_19);

XLXI_32 : INV
 port map (I=>XLXN_62,

O=>XLXN_20);

XLXI_33 : INV

port map (I=>XLXN_63,

O=>XLXN_21);

XLXI_34 : INV

port map (I=>XLXN_46,

O=>XLXN_22);

XLXI_35 : INV

port map (I=>XLXN_44,

O=>XLXN_23);

XLXI_36 : INV

port map (I=>XLXN_63,

O=>XLXN_24);

XLXI_37 : INV

port map (I=>XLXN_46,

O=>XLXN_25);

XLXI_38 : INV

port map (I=>XLXN_44,

O=>XLXN_26);

XLXI_39 : INV

port map (I=>XLXN_46,

O=>XLXN_27);

XLXI_40 : INV

port map (I=>XLXN_35,

O=>XLXN_44);

XLXI_41 : INV

port map (I=>XLXN_32,

 O=>XLXN_63);

XLXI_42 : INV

port map (I=>XLXN_33,

O=>XLXN_46);

XLXI_43 : INV

port map (I=>XLXN_34,

O=>XLXN_62);

XLXI_45 : INV

port map (I=>XLXN_46,

O=>XLXN_9);

XLXI_46 : AND4

port map (I0=>XLXN_44,

I1=>XLXN_63,

I2=>XLXN_11,

I3=>XLXN_12,

O=>D3);

XLXI_48 : AND4

port map (I0=>XLXN_26,

I1=>XLXN_63,

I2=>XLXN_27,

I3=>XLXN_62,

O=>XLXN_68);

XLXI_49 : AND2

port map (I0=>XLXN_68,

I1=>R,

O=>XLXN_43);

end BEHAVIORAL;
TECHNOLOGY SCHEMATIC:

SIMULATED OUTPUT :
CONCLUSION
From this project, we have learned the various technologies,application and
scope of VLSI and also the application of VLSI design software and
programming code language. Doing this project we also came to know that
there is ample opportunity and growth for those who choose VLSI design as a
career.

REFERENCE:

[1] "Synchronous counter", Digital, Play hookey.

[2] 1076-1987 – IEEE Standard VHDL Language Reference Manual. 1988. ISBN 0-
7381-4324-3. doi:10.1109/IEEESTD.1988.122645.

[3]"The History of the Integrated Circuit". Nobelprize.org. Retrieved 21 Apr 2012.

[4]Pedroni Volnei A. (2008). Digital electronics and design with VHDL. Morgan

Kaufmann. p. 329. ISBN 978-0-12-374270-4.

[5] ^ a b Latches and Flip Flops (EE 42/100 Lecture 24 from Berkeley) "...Sometimes

the terms flip-flop and latch are used interchangeably..."