INTERRUPT HANDLING

AND CLOCK
CONFIGURATION
Lecturer: Dr. Bui Ha Duc
Dept. of Mechatronics
Email: [email protected]

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Outline
• Memory organization

• Clock configuration

• Interrupt handling

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3
Bus Systems in the Cortex-M0+

Advanced High-performance Bus

Advanced Peripheral Bus

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Bus Systems in the Cortex-M0+
• Bus system in Cortex-M consists:
• 32-bit system bus
• 32-bit peripheral bus
• The system bus
• Based on a AHB protocol
• Connect the processor with different types of memories
• support read/write transfers with 32-, 16-, and 8-bit data
• The peripheral bus
• Based on APB protocol
• The APB is connected to the AHB-Lite via a bus bridge
• Can run at a different clock speed compared to the AHB system
bus

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Bus Systems in the Cortex-M0+
• In real applications
• Peripheral bus segments may run at different clock frequencies
• Some part of the system may run in a slower speed to achieve
power reduction
• Application might need to initialize clock control hardware
before accessing main program

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Memory map
• Code Region (0x00000000 - 0x1FFFFFFF)
• Up to 512MB
• Store program code, can also put data here
• Store vector table at address 0x00000000

• SRAM Region (0x20000000 - 0x3FFFFFFF)

• Up to 512MB
• Store data, can also put program code here

• Peripheral Region (0x40000000 -0x5FFFFFFF)

• Up to 512MB
• Primarily used for peripherals

• RAM Region (0x60000000 - 0x9FFFFFFF)

• consists of two 512 MB blocks
• primarily used to stored data
• The only differences between the two halves of
theRAM region are the memory attributes

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Memory map
• Device Region (0xA0000000 - 0xDFFFFFF)
• consists of two 512 MB memory blocks
• primarily used for peripherals
• two halves of the device region have different memory
attributes.
• Internal Private Peripheral Bus (0xE0000000
- 0xE00FFFFF)
• allocated for peripherals inside the processor
• Size is 1 MB

• System Space (0xE0100000 - 0xFFFFFFFF)

• Up to 512MB
• Reserve for microcontroller vendor specific
usages

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Memory map

Memory map of the Cortex-M0/M0+ processor

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Holtek HT32F
memory map

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11
Objectives
• All MCU modules are driven by the clock
• In Cortex-M microcontroller, every module uses
independent clock
• to meet the low-power requirement
• more flexible and precise in control
• It is crucial to understand MCU Clock system in detail

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HT32F Clock system
• There are 5 clock sources in HT32F MCU
• HSI (High Speed Internal): internal 8 MHz RC oscillator

• HSE (High Speed External): 4~16 MHz external crystal

• LSI (Low Speed Internal): internal 32KHz RC oscillator

• LSE (Low Speed External): 32768 Hz external crystal

• PLL (Phase Locked Loop) from HSE or HSI

• HIS, HSE, and PLL can be used as System Clock.

• LSI and LSE for Watchdog Timer, RTC or second level

system clock.

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External Oscillator Circuit

External Crystal, Ceramic, and External Crystal, Ceramic, and

Resonators for HSE Resonators for LSE

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Clock System Block Diagram 15
Phase Locked Loop – PLL
• PLL Block Diagram

• Frequency of the PLL output clock

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Control Register

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Clock configuration
• In theory, Clock can be configured by setting control
registers.
• However, each ARM vendor has different control register
names for its MCU.
• ARM licenses the processor designs to >160 partners.

How to avoid confusion?

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Cortex Microcontroller System
Interface Standard

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CMSIS CORE
startup_<device>.s

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Create a project in Keil MDK
• Refer to Keil MDK-ARM Quick Start for Holtek MCU for
more detail

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CMSIS device startup file
• startup_<device>.s : define what will be done before
main code
• Interrupt vector
• Interrupt handler
• System Initialization
• startup_ht32f5xxxx_01.s:

System clock is
configured here

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System initialization
• system_<device>.c : Code for system clock cpnfiguration
• system_ht32f5xxxx_01.c:

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24
Communicate with physical world

inputs

Physical Microcontroller
world

outputs

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Software flow
Method 1: Polling
• Simple, easy to
setup
• Work well for
simple tasks

Polling method for simple

application processing

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Software flow
• Can be expanded to
support multiple
processes

Disavantages?
• Hard to apply to
complex task
• difficult to define
priorities between
different services
• poor responsiveness
• Waste energy Polling method for application with
multiple devices that need processing
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Interrupt Driven
Method 2: Interrupt
• Waste energy -> sleep
mode, peripheral can
wake up the processor
when it requires a service

• difficult to define priorities

between different
services
-> peripherals are Simple interrupt-driven application
assigned with different
interrupt priority levels
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Multi-tasking systems
• Task need to be processes concurrently
-> Real-time operating system (RTOS) to create schedules

Using an RTOS to handle multiple tasks 31

How CPU processes the Interrupt
1. Finish processing 2. Run interrupt 3. Resume
current instruction. Save service routine. main program
program counter and Restore Program
flags to stack counter and flags
from stack

http://learn.mikroe.com/ebooks/piccprogramming/chapter/pic16f887-basic-features/ 32
Interrupt Service Routine (ISR)
• Subroutines used to service an interrupt are call
IRQHandler
e.g. ADC_IRQHandler, UART0_IRQHandler
• Each interrupt has an IRQHandler which has an address
listed in Interrupt Vector Table
• Processor obtains the subroutine address from the vector
table and directs the execution to the ISR
• Nested Interrupts: divide interrupts and exceptions into
multiple levels of priority,
• Nested Vectored Interrupt Controller (NVIC): A
programmable hardware unit inside the Cortex-M
processors to handle the management of interrupts and
exception requests
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Cortex M NVIC

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Cortex-M CPU and peripheral exceptions

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Holtek HT32F523352 exception types (partial)
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Vector table
• 32-bit vector (handler address)

• Declare in startup_<device>.s

• Peripherals use positive IRQ #s

• CPU exceptions use negative
IRQ #s
• IRQ # used in CMSIS function
calls
• Cortex-M0+ allows up to 32 IRQs

• IRQ priority is programmable

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Vector table from startup code

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Priority Levels
• IRQ priority is programmable

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Interrupt Priority Registers
• The NVIC_IPR0-NVIC_IPR7 registers provide an 8-bit
priority field for each interrupt.

In Cortex-M0, the processor

implements only bits [7:6] of
each field, bits [5:0] read as
zero and ignore writes.

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Interrupt Priority

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Interrupt Signal Flow
In each peripheral device:
• Each potential interrupt source has a separate enable bit
• Set for devices from which interrupts are to be accepted
• Clear to prevent the peripheral from interrupting the CPU

• Each potential interrupt source has a separate flag bit

• hardware sets the flag when an “event” occurs
• Interrupt request = (flag & enable)
• ISR software must clear the flag to acknowledge the request
• test flags in software if interrupts not desired

Nested Vectored Interrupt Controller (NVIC)

• Receives all interrupt requests
• Each has an enable bit and a priority within the VIC
• Highest priority enabled interrupt sent to the CPU

Within the CPU:

• Global interrupt enable bit in PRIMASK register
• Interrupt if priority of IRQ < that of current thread
• Access interrupt vector table with IRQ#

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Nested Vectored Interrupt Controller
• NVIC manages and prioritizes external interrupts in
Cortex-M0+
• 32 IRQ sources from peripherals
• NVIC interrupts CPU with IRQ# of highest-priority IRQ
signal
• CPU uses IRQ# to access the vector table & get intr. handler start
address

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NVIC Register

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CMSIS functions for NVIC control
CMSIS provides functions for enable/disable Interrupts

And NVIC control

a. The input parameter IRQn is the IRQ number

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CMSIS functions for NVIC control
Examples:
NVIC_EnableIRQ(8); //enable ADC interrupt
NVIC_DisableIRQ(4);//disable external interrupt 0~1
// Set ADC interrupt at highest priority
NVIC_SetPriority (8, 0);

For convenient, CMSIS define a name for IRQ number in

<device>.h file
e.g. USB_IRQn = 29
Usage:
• NVIC_EnableIRQ(USB_IRQn); //enable external interrupt USB

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Example

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