CSE211: COMPUTER ORGANIZATION AND DESIGN

Unit II
Computer Organization :
instruction codes, computer registers,
common bus system, computer instructions,
timing and control, instruction cycle,
Memory reference instructions,
input-output and interrupt
 Instruction codes

• The Internal organization of a digital system is defined by the sequence of

microoperations it performs on data stored in its registers.

• The user of a computer can control the process by means of a program.

• A program is a set of instructions that specify the operations, operands,

and the processing sequence.

• A computer instruction is a binary code that specifies a sequence of micro-

operations for the computer. Each computer has its unique instruction set.
 Instruction codes

• Instruction codes and data are stored in memory.

• The computer reads each instruction from memory and places it in a

control register.

• The control unit interprets the binary code of the instruction and proceeds
to execute it by issuing a sequence of micro-operations.

• An Instruction code is a group of bits that instructs the computer to

perform a specific operation (sequence of microoperations). It is divided
into parts (basic part is the operation part).
 Instruction codes

• The operation code of an instruction is a group of bits that defines

certain operations such as add, subtract, shift, and complement.

• The number of bits required for the operation code depends on the
total number of operations available in the computer

• 2n (or little less) distinct operations → n bit operation code

 Instruction codes
Memory
Op code
110010?????????
Control
Unit

Read instruction
from memory
 Instruction codes
• An operation must be performed on some data stored in processor
registers or in memory.

• An instruction code must therefore specify not only the operation, but
also the location of the operands (in registers or in the memory), and
where the result will be stored (registers/memory).

• Memory words can be specified in instruction codes by their address.

• Processor registers can be specified by assigning to the instruction

another binary code of k bits that specifies one of 2k registers.
 Instruction codes
• Each computer has its own particular instruction code format.

• Instruction code formats are conceived by computer designers who

specify the architecture of the computer.

• An instruction code is usually divided into operation code, operand

address, addressing mode, etc.

• The simplest way to organize a computer is to have one processor

register (accumulator AC) and an instruction code format with two parts
(op code, address).
 Instruction codes
Instruction Codes Stored Program Organization
Opcode Address 15 0

Instruction Format
Instructions
15 0
(program)
Binary Operand

Operands
(data)

15 0

Processor register
(Accumulator AC)
 Instruction codes
Instruction Codes Addressing Modes
• There are three Addressing Modes used for address portion of the
instruction code:
• Direct: the address points to the operand stored in the
memory
• Indirect: the address points to the pointer (another
address) stored in the memory that references the
operand in memory.
• One bit of the instruction code can be used to distinguish between
direct & indirect addresses.
• Effective address: the address of the operand in a computation-type
instruction or the target address in a branch-type instruction.
 Instruction codes
Instruction Codes Addressing Modes
Effective
Address
Definition - What does Macro Instruction mean?
A macro instruction is a group of programming instructions that have been compressed into a simpler form and
appear as a single instruction. When used, a macro expands from its compressed form into its actual instruction
details. Both the name of the macro definition and other variable parameter attributes are included within the
macro statement.
Explanation:
Macro instructions were first used in the assembler language rather than a higher-level programming language.
The way a macro expands to a set of instructions depends on the macro definition, which converts the macro into
its detailed instructional form.

Macros save developers much time and effort, especially when dealing with a certain sequence of commands
that is repeated more than once within the program body. Macros also save space and spare the programmer
time spent on a long code block that may pertain to performing a single function.

The concept of macros is used within some pre-compilers, while higher-level languages focus on simplifying
program and function writing, which makes the macro instruction a common element among most high-level
programming languages. Macro instructions are generated together with the rest of the program by the
assembler.
Share this:
 Computer Registers
• Computer instructions are normally stored in consecutive memory
locations and executed sequentially one at a time.

• The control reads an instruction from a specific address in memory and

executes it, and so on.

• This type of sequencing needs a counter to calculate the address of the

next instruction after execution of the current instruction is completed.

• It is also necessary to provide a register in the control unit for storing the
instruction code after it is read from memory.

• The computer needs processor registers for manipulating data and a

 Computer Registers

Registers in the Basic Computer

DR 16 Data Register Holds memory operand

AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
 Computer Registers
Computer Registers : Common Bus System
• S2S1S0: Selects the register/memory that would use the bus

• LD (load): When enabled, the particular register receives

the data from the bus during the next clock pulse transition

• E (extended AC bit): flip-flop holds the carry

• DR, AC, IR, and TR: have 16 bits each

• AR and PC: have 12 bits each since they hold a memory

address
 Computer Registers : Common Bus System
• When the contents of AR or PC are applied to the 16-bit common bus, the four
most significant bits are set to zeros
• When AR or PC receives information from the bus, only the 12 least significant
bits are transferred into the register
• INPR and OUTR: communicate with the eight least significant bits in the bus.
• INPR: Receives a character from the input device (keyboard,…etc) which is then
transferred to AC
• OUTR: Receives a character from AC and delivers it to an output device (say a
Monitor)
• Five registers have three control inputs: LD (load), INR (increment), and CLR (clear)
• Register  binary counter with parallel load and synchronous clear
 Computer Registers : Memory Addressing
• The input data and output data of the memory are connected to the common bus
But the memory address is connected to AR therefore, AR must always be used to
specify a memory address
• By using a single register for the address, we eliminate the need for an address bus
that would have been needed otherwise.
• Register → Memory: Write operation
• Memory → Register: Read operation (note that AC cannot directly read from
memory!!)
• Note that the content of any register can be applied onto the bus and an operation
can be performed in the adder and logic circuit during the same clock cycle.
• The transition at the end of the cycle transfers the content of the bus into the
destination register, and the output of the adder and logic circuit into the AC
For example, the two micro-operations
DR←AC and AC←DR (Exchange) can be executed at the same time
 Computer Registers : Memory Addressing

• This is done by:

1- place the contents of AC on the bus (S2S1S0=100)
2- enabling the LD (load) input of DR
3- Transferring the contents of the DR through the adder and logic
circuit into AC
4- enabling the LD (load) input of AC all during the same clock cycle
• The two transfers occur upon the arrival of the clock pulse transition at
the end of the clock cycle.
Basic Computer Instruction code format
Computer Instructions : Instruction Set Completeness
The set of instructions are said to be complete if the computer
includes a sufficient number of instructions in each of the
following categories:
• Arithmetic, logical, and shift instructions
• Instructions for moving information to and from memory and
processor registers
• Program control instructions together with instructions that
check status conditions
• Input & output instructions
 Timing & Control
• The timing for all registers in the basic computer is
controlled by a master clock generator
• The clock pulses are applied to all flip-flops and registers
in the system, including the flip-flops and registers in the
control unit
• The clock pulses do not change the state of a register
unless the register is enabled by a control signal (i.e.,
Load)
 Timing & Control
• The control signals are generated in the control unit
and provide control inputs for the multiplexers in the
common bus, control inputs in processor registers,
and micro-operations for the accumulator.
• There are two major types of control organization:
• Hardwired control
• Microprogrammed control
 Timing & Control
• In the hardwired organization, the control logic is
implemented with gates, flip-flops, decoders, and
other digital circuits.
• In the microprogrammed organization, the control
information is stored in a control memory (if the
design is modified, the microprogram in control
memory has to be updated)
• D3T4: SC←0
The Control Unit for the basic computer
 Timing & Control
- Generated by 4-bit sequence counter and 4x16 decoder
- The SC can be incremented or cleared.
- Example: T0, T1, T2, T3, T4, T0, T1, . . . Assume: At time T4, SC is cleared to
0 if decoder output D3 is active
T0 T1 T2 T3 T4 T0
Clo ck

T0

T1

T2

T3

T4

D3

CLR
SC
 Timing & Control
• A memory read or write cycle will be initiated with the rising
edge of a timing signal
• Assume: memory cycle time < clock cycle time!
• So, a memory read or write cycle initiated by a timing signal will
be completed by the time the next clock goes through its positive
edge.
• The clock transition will then be used to load the memory word
into a register.
• The memory cycle time is usually longer than the processor clock
cycle → wait cycles
 Timing & Control
T0: AR←PC
• Transfers the content of PC into AR if timing signal T0 is
active
• T0 is active during an entire clock cycle interval
• During this time, the content of PC is placed onto the
bus (with S2S1S0=010) and the LD (load) input of AR is
enabled
• The actual transfer does not occur until the end of the
clock cycle when the clock goes through a positive
transition
• This same positive clock transition increments the
sequence counter SC from 0000 to 0001
• The next clock cycle has T1 active and T0 inactive.
 Instruction Cycle

• A program is a sequence of instructions stored in memory

• The program is executed in the computer by going through a
cycle for each instruction (in most cases)
• Each instruction in turn is subdivided into a sequence of sub-
cycles or phases.
• Instruction Cycle Phases:
1- Fetch an instruction from memory
2- Decode the instruction
3- Read the effective address from memory if the
instruction has an indirect address
4- Execute the instruction
 Instruction Cycle

Above cycle repeats indefinitely unless a

HALT instruction is encountered
Instruction Cycle : Fetch and Decode
• Initially, the Program Counter (PC) is loaded with the
address of the first instruction in the program.
• The sequence counter SC is cleared to 0, providing a
decoded timing signal T0.
• After each clock pulse, SC is incremented by one, so
that the timing signals go through a sequence T0, T1, T2,
and so on.
Instruction Cycle : Fetch and Decode
• T0: AR←PC (this is essential!!)
The address of the instruction is moved to AR.
• T1: IR←M[AR], PC←PC+1
The instruction is fetched from the memory to IR ,
and the PC is incremented.
• T2: D0,…, D7←Decode IR(12-14), AR←IR(0-11),
I←IR(15)
Instruction Cycle : Fetch and Decode

S2

T0 S1 Bus

S0
Memory
7
unit
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Instruction Cycle : Fetch and Decode

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1

I I

T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute
memory-reference
instruction
SC  0
Instruction Cycle : Fetch and Decode
MEMORY REFERENCE INSTRUCTIONS
Operation
Symbol Decoder Symbolic Description

AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to be completed in a CPU cycle
- The execution of MR Instruction starts with T4
AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
Instruction Cycle : Fetch and Decode
- D7 = 1, I = 0
REGISTER REFERENCE INSTRUCTIONS
- Register Ref. Instr. is specified in B0 ~ B11 of IR
- Execution starts with timing signal T3

r = D7 I’ T3 => Register Reference Instruction

Bi = IR(i) , i=0,1,2,...,11, the ith bit of IR.
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop)
Instruction Cycle : Fetch and Decode
MEMORY REFERENCE INSTRUCTIONS

LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
Memory, PC, AR at time T4 Memory, PC after execution D3T4: M[AR]  AC, SC  0
20 0 BSA 135 20 0 BSA 135 BUN: Branch Unconditionally
Return address: PC = 21 Next instruction 21 Next instruction D4T4: PC  AR, SC  0
BSA: Branch and Save Return Address
M[AR]  PC, PC  AR + 1
AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory Memory
Instruction Cycle : Fetch and Decode
MEMORY REFERENCE INSTRUCTIONS

BSA: executed in a sequence of two micro-operations:

D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0
Instruction Cycle : Fetch and Decode
 Input-Output and Interrupt
• Instructions and data stored in memory must come from some
input device
• Computational results must be transmitted to the user
through some output device
• For the system to communicate with an input device, serial
information is shifted into the input register INPR
• To output information, it is stored in the output register OUTR
Input-Output and Interrupt
 Input-Output and Interrupt
• INPR and OUTR communicate with a communication interface serially and
with the AC in parallel. They hold an 8-bit alphanumeric information
• I/O devices are slower than a computer system → we need to synchronize
the timing rate difference between the input/output device and the
computer.
• FGI: 1-bit input flag (Flip-Flop) aimed to control the input operation.
• FGI is set to 1 when a new information is available in the input device and
is cleared to 0 when the information is accepted by the computer
• FGO: 1-bit output flag used as a control flip-flop to control the output
operation
• If FGO is set to 1, then this means that the computer can send out the
information from AC. If it is 0, then the output device is busy and the
computer has to wait!
 Input-Output and Interrupt

• The process of input information transfer:

➢ Initially, FGI is cleared to 0
➢ An 8-bit alphanumeric code is shifted into INPR (Keyboard key strike)
and the input flag FGI is set to 1
➢ As long as the flag is set, the information in INPR cannot be changed by
another data entry
➢ The computer checks the flag bit; if it is 1, the information from INPR is
transferred in parallel into AC and FGI is cleared to 0.
➢ Once the flag is cleared, new information can be shifted into INPR by
the input device (striking another key)
 Input-Output and Interrupt
• The process of outputting information:
➢Initially, the output flag FGO is set to 1
➢ The computer checks the flag bit; if it is 1, the information from AC is
transferred in parallel to OUTR and FGO is cleared to 0
➢ The output accepts the coded information (prints the corresponding
character)
➢ When the operation is completed, the output device sets FGO back to
1
➢ The computer does not load a new data information into OUTR when
FGO is 0 because this condition indicates that the output device is busy
to receive another information at the moment!!
Programmed Controlled Data Transfer
Program controlled Input/output
 Interrupt Initiated Input/output

IEN (Interrupt-enable flip-flop)

Flow Chart of Interrupt Cycle