System Verilog

Developing a Verification Environment

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Verification Plan
● Level of Verification
– Unit
– Sub-system
– System level
● Testcases
● Verification Resources
– Tools
– Specification Documents
● Strategies
– When is the verification considered to be completed
– Time and Human Factor

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Verification Environment
● TODO

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TLM Modelling
● Exchanges information as objects
● Transcations abstract away the low-level RTL
● Easier to Maintain
● Faster design and verification times
● Model – Functionality encapsulated in a class.
– They form the components of the TB
● TLM allows the components to be independent on the way they are connected to
TB
● Connections should be independent of internal implementation of components

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The Testbench to DUT connection
● Virtual Interfaces
– Interfaces
● Clocking blocks
● Modports
– How to use virtual interface
● Program block

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Clocking Block

● A clocking block identifies the clocking signals, captures the timing and
synchronization requirements
● The timing for sampling and driving clocking block signals is implicit and
relative to the clocking block's clock.
● The key operations done using the clocking block are
– Input signals are sampled just before the design executes
– Outputs are driven back into the design during the current time slot
– Any synchronous event
– Bidirection signals are sampled as well as driven

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 Contd...
● Example
clocking bus @(posedge clock1);

default input #10ns output #2ns;

input data, ready, enable = top.mem1.enable;

output negedge ack;

input #1step addr;

endclocking

● The default input skew is 1step and default output skew is zero

●
Diagram from lrm TODO

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 Contd...
● Seperate instanstiation is not required
● Cannot be nested
● Can be declared inside a module, a interface or a program
● Static lifetime and local scope
● Default clocking can be specified within a given module/interface/program
● Signals in multiple clocking blocks ---- TODO

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Program Block
● Entry point to the execution of testbenches
– Seperator between the design and testbench
● Creates the scope that encapsulates program wide data
● Timing ---- TODO

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 Contd...
● Can be nested within modules or interfaces
● Can contain one or more initial blocks
● Cannot have always block
● Cannot have modules or interfaces or other programs
● Program variables can be only assigned using blocking statements --- TODO
●

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Interfaces
● Declaration of wires that logically go together
● A construct used to bundle a large variety of wires and regs into a single name entity
● More than just signals- it can have routines, asssertions
● Can be parameterized
● Facilitates in design re-use
interface base_protocol;
wire [7:0] address;
wire [31:0] data;
wire clock;
wire address_latch_enable;
endinterface

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 Contd...
● Concept of modports
– Provides the direction information
– Controls the use of tasks and functions
interface i2;
wire a, b, c, d;
modport master (input a, b, output c, d);
modport slave (output a, b, input c, d);
endinterface
● interface_name.modport_name is used to access the interface signals in a module header
module m (i2.master i); ....
endmodule
● All the names used in modport declaration should be declared by the interface itself

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 Contd...
● Modports can also be used to specify the direction of clocking blocks
interface A_Bus( input bit clk );
wire req, gnt;
wire [7:0] addr, data;
clocking sb @(posedge clk);
input gnt;
output req, addr;
inout data;
endclocking
modport STB ( clocking sb ); // synchronous testbench modport
modport DUT ( input clk, req, addr,output gnt,inout data );
endinterface
module dev1(A_Bus.DUT b); … endmodule
program T (A_Bus.STB b1) ; … endprogram
module top;
bit clk;
A_Bus b1( clk );
dev1 d1( b1 );
T tb( b1, b2 );
endmodule

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 Contd...
● Tasks and Functions in Interfaces --------- TODO
– Import
– Export

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 Contd...
● Virtual Interfaces
– Mechanism to dynamically control the set of signals associated
– It is a variable that represents an interface instance
– Can be passed as argument to functions, tasks or methods
– Must be initialised.
– Clocking blocks can be referenced by virtual interface
– Modports cant be referenced -- TODO

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Ground Work
● Outline interfaces
– Identify the abstracted basic operations that can be generated with the
interface
– List the fields that are required to describe each transaction
– List the control knobs for the transaction
– Note the fields that can be randomized, ranges and constraints
– Outline all the possible errors
● Using the above information form a transaction class
● A transcation type per interface could be used

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Transaction Generators
● Also called transactors, stimulus generators.
● They generate the transactions and pass it on to the driver.

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Drivers
● Active entities
● Responsible to send the stimuli to DUT
– Receives a data item and drives to the DUT by sampling and driving the DUT signals
● Translates the transcations generated by transaction generator into actual inputs for the
DUT. In addition,
– Inject errors
– Drop the transaction
– Delay the transaction
– Synchronization
● Uses virtual interface

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Monitors
● Passive Entity
● Samples DUT signals
● Translates the information into a transaction
● Generates event to notify the other components when information is available
● Typically consists of protocol checking
● Checkers to verify if the DUT output protocol specifications
● Assertions are used to verify time based protocols
●

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Scoreboard
● Guarentees data integrity
● Can predict, store, and compare data
– Functions to generate expected data
– Store the predicted data
– Comparsion functions to compare actual data and predicted data
● Scoreboarding can be done in two ways
– On-the fly scoreboarding
● Memory efficient
– Post processing
● Can use a reference model

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Considerations while coding scoreboard
● Approach
– Amount of data
– When to sample data
– When to remove data
– When to compare
● Data structure to handle the data
● Latency and ordering Differences
– Tracing packets
● When the test is done, scoreboard should be empty

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Coverage
● Feedback mechanism
– What has not been verified
– Helps to determine how much the specification is covered
– Gives the information on redundant tests

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Test cases
● Top -most file
● Can communicate with all the TB components
● A simple set of instructions to control TB
● Uses the program block
● Could be random or directed

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