Optimization Design and Simulation for a Band-

Pass-Filter with IPD Technology for RF Front-end

Application

Huijuan Wang1,2,*, Jie Pan1,2, Xiaoli Ren1, Anmou Liao1,2,Yuan Lu1,2, Daquan Yu2, Dongkai Shangguan1,2
1
National Center for Advanced Packaging (NCAP China), Wuxi, 214315, China
2
Institute of Microelectronics Chinese Academy of Sciences, Beijing, PR China
*
Email: [email protected]

Abstract—A band-pass-filter (BPF) based on silicon substrate (RF) integrated system. There are many passive devices
was designed and simulated. Different software was applied to integrated in RF circuits, like capacitor, resistor and inductor.
design and simulate the character of the filter. A three-order The fabrication of high factor (Q) inductor and high density
filter was designed dedicating to range 2.4 GHz-2.5 GHz use. The capacitor are the important task to be solved imperatively for
ideal topology circuit was designed with passive inductors and silicon interposer. Fig.1 shows the smart interposer which
capacitors. Moreover, the integrated passive devices (IPDs) were integrated TSV and integrated passive devices (IPDs), which
modeled and simulated with thin film process. To enhance the can be widely used for high density RF systems[7][8].
performance of the IPD, some typical factors were considered to
optimize the physical model. The IC design tool and &$3$&,725 769 %XPSV 5(6,6725 ,1'8&725
electromagnetic simulation software were used and compared to
analysis the character of the filter, which demonstrated that the
BPF can be applied to RF front-end system.

Keywords—2.5D interposer; Integrated passive devices (IPD),

Band-pass-Filter, inductor andcapacitor

I. INTRODUCTION
In a wireless communication system, there are many kinds
of passive modules, such as LCs, filters, baluns and duplexers.
These passive components cover 60%-70% of the area in the
board. These passive components can be made in various Fig. 1. The structure of smart interposer integrated TSV and IPD
substrate and process, such as ceramic, lamination, silicon and
glass [1]. There is clear indication that the overall size- In this paper, we designed the IPD in the 8 inch silicon
reduction relies heavily on the reduction of these passive wafer. BPF from 2.4 GHz to 2.5 GHz (10dB return loss
components. Conventional discrete passive components are bandwidth) is designed using IPD technology on a silicon
the most widely used for wireless products, which are substrate for RF front-end applications. The filter shows 2 dB
typically made using ceramic technology for ceramic’s good insertion loss from 2.4 GHz to 2.5 GHz. The size of the filter
electrical and thermal characteristics [2][3]. However, is 2mm×2mm×0.5mm including bump height. The high
integrated passives devices (IPDs) based on semiconductor resistivity silicon wafer (2Kȍ.cm) is used because it can
processes offer the advantage of excellent parameter control, obtain high Q inductor (35 at 2 GHz) on silicon wafers. To
and allow simplified and compact module design IPD obtain the character above, we modeling and optimization the
processes can be used to make high density capacitors high Q elements of a three order Chebyshev filter. In last part of the
inductors and large value resistors [4]. paper, it simulated the whole circuit with layout which
illustrates the filter can meet the application.
IPD technology based on Silicon wafer process has been in
great interest in the past decade. The process of thin film IPD
is well familiar to the semiconductor industry. Since the II. MODELING AND OPTIMAZATION FOR ELEMENT
silicon interposer which through the though silicon via (TSV) To meet the requirement on wireless communications
and the redistribution wiring (RDL) layers of the silicon has system, the 2.4 GHz band passive module (such as filter, balun
been proposed and applied to the typical electronic products and duplexer, etc.) are widely applied on RF front-end of the
packaging, and due to its unique technology materials and electrical products. BPF is a kind of important passive device
processing technology[5][6]. It is widely used and recognized which used in the ZigBee, Bluetooth and WiFi .The target of
in the industry. However, it is not enough for only TSV and the design of the filter is shows as follows: (1).
RDL in the interposer, especially applied on radio frequency Bandwidth(BW):400-2500 MHz; (2). f0=2.5 GHz; (3). Low

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978-1-4799-4707-2/14/$31.00 ©2014 IEEE
insertion loss < 3 dB; (4). High rejection @ 1 GHz > 35 dB; and capacitance for a inductor based on silicon. The
(5). Return loss> 14 dB impedance is increase with the frequency, which is the reason
for the big loss under high frequency. To get a high Q inductor
A. The Ideal Schematical Model with precise inductance need to consider the shape for a spiral
In order to design a passive BPF, we should choose a inductor. Spiral inductance and geometry are closely related,
proper type of filter. There are many kinds of filters that their accuracy can be obtained by solving Maxwell's equations.
Butterworth filter and Chebyshev filter are the most For the quadrilateral, hexagon and eight octagonal spiral
commonly used in the circuit. Butterworth filter in the pass inductor, \can be calculated from the following formula(1):
band has a smooth inside and outside the amplitude-frequency
characteristics, but there is a longer transition period which is
n 2 d avg
L K1P0 (1)
likely to cause distortion. Compared with the Butterworth 1  k2 U
filter, Chebyshev filter transition band is narrow, but the
internal amplitude-frequency characteristic is very unstable. Where, K1ǃK2 are constants for different turns, which
Cause the target filter need a high rejection, we choose the are shown in the Table.1, ­ 0 represents magnetic
latter one. conductivityˈn represents turnsˈdavg represents an average
The next one is to determine the order of the filter. The value for inner diameter and external diameter, ² represents
order is smaller, the amplitude ripple is bigger. However, the filling rate of turnsˈwhich formula is(2)˖
order is bigger, the circuit is more complex and difficult to
optimize. After calculate and trade-off consideration, we used dout  din
three-order BPF which is shown in Fig.2˄a˅. It shows that
U (2)
dout  din
there seven capacitors and three inductors in the circuit. Each
element of the passive component is ideal model. The
inductance of the inductor is 1.91nHˈand the capacitance is TABLE I. THE VALUE OF K1 AND K2 WITH DIFFERENT SHAPES
also shown in the picture. Fig.2˄b˅is the result of the s Shape of the
Quadrilateral Hexagon Octagon
parameters for the circuit in Fig.2˄a˅, which illustrates the inductor
high rejection can reach -50dB. The other features of the K1 2.34 2.33 2.35
filter can meet the demand of the design. K2 2.75 3.82 3.55

Cause octagonal inductor can get a high Q and easily to

fabricate ˈ we choose octagonal inductor to modeling and
simulation. Fig.3 shows a typical image of the layout for a
octagonal spiral inductor. In the image, it can see that the
diameter 2R, line width W, line separation S and turns form
the mainly structure parameters.

(a) The circuit topology for the 3-order BPF

Fig. 3. The layout for a spiral inductor

TABLE II. PARAMETERS OF THE MATERIAL

(b) S parameters of the ideal circuit topology Material Relative Bulk Conductivity (S/m)
Name Permittivity
Fig. 2. The circuit model of the filter with simulation results IPD-Al 1 34800000

IPD-Cu 1 57000000
B. 3D Model Simulation for Inductors IPD-PI 3.16 0
In the ideal circuit model, it determined the value of the IPD-silicon 11.9 0.1-1000
inductor is 1.91nF. There era parasitical resistance, inductance

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 We used the 3D electromagnetics simulation software operation frequency and increase coupling between inductance
HFSS to set up the model of inductor.TABLE2 given the and substrate, which decrease the Q value.
material name and characteristic parameters with them, which 2.20
L11-width HFSSDesign1 ANSOFT

used in the software. It chooses aluminum as metal pad, plated

Name X Y Curve Info
m1 0.1000 1.9243 L11
m5 Setup1 : Sw eep
m2 1.0000 1.8337
2.15 indu_w ='10um'

copper to form thick spiral, and cured resin PI to insulation. 2.10

m3
m4
m5
0.1000 2.0013
1.0000 1.9156
0.1000 2.1493
L11
Setup1 : Sw eep
indu_w ='20um'

The silicon substrate is changed by bulk conductivity from m6 m6 1.0000 2.0674 L11
Setup1 : Sw eep
indu_w ='30um'

0.1-1000 s/m. Fig.4(a) shows the model of the inductor with

2.05

m3

L11 [n]
2.00

the distribution of surface field. It illustrates the position of

maximum surface electric field is the connection of two metal
1.95
m1
m4

layers. The ground of the inductor also induced the leakage

1.90

current. Fig.4(b) is the simulation of the results between the Q

1.85 m2

and the bulk resistivity from 1 GHz to 4 GHz. Apparently, the

1.80
0.00 1.00 2.00 3.00 4.00 5.00 6.00
Freq [GHz]

Q is higher with the bulk resistivity is increasing. When the (a) Inductance changed with different line width
bulk resistivity is above than 1000¡.cm, the Q can reach 20 at Q11-width HFSSDesign1 ANSOFT

2.5 GHz. Fig.4(c) is the

50.00 Curve Info
Q11
Name X Y
Setup1 : Sw eep
m1 1.0000 12.1127 indu_w ='10um'
m2 1.0000 14.7397 Q11
40.00 m3 1.0000 16.5042
Setup1 : Sw eep
indu_w ='20um'
Q11
Setup1 : Sw eep
indu_w ='30um'

30.00

Q11
20.00
m3
m2
m1

10.00

0.00
0.00 1.00 2.00 3.00 4.00 5.00 6.00
Freq [GHz]

(b) The Q factor changed with different line width

Fig. 5. The inductance and Q changed with the line width

(a) Simulation models for 3D structure
Diameter of inductance 2R is 0.1mm, external diameter is
0.3mm, line width is 30um, and line width is changed with 3-
12um to do simulation calculation. Referring to Fig.5(a),
corresponding inductance increasing as line width increases,
and in a case that the line width is 9 um, change of the
inductance is smallest. Referring to Fig.5(b), the Q value is
increasing as the line width increases since increase of the line
width leads to decrease for resistance of turns which causes
decrease for loss of turns.
m1 0.1000 2.0399
L11-hight HFSSDesign1 ANSOFT
2.05 m1 m2 1.0000 1.9316
Curve Info
m3 0.1000 1.9840
L11
m4 1.0000 1.8952 Setup1 : Sw eep
m5 0.1000 1.9369 indu_h='3um'
2.00 m3 m6 1.0000 1.8501 L11
Setup1 : Sw eep
m7 0.1000 1.9243 indu_h='6um'
m8 1.0000 1.8337 L11
m9 0.1000 1.9003 Setup1 : Sw eep
1.95 m5 indu_h='9um'
m2 m10 1.0000 1.8075
m7 L11
Setup1 : Sw eep
m9 indu_h='10um'
L11 [n]

m4
1.90 L11
Setup1 : Sw eep
indu_h='12um'

m6
1.85 m8

(b) Simulation results for Q change with bulk conductivity m10

1.80

Fig. 4. Simulation model and simulation results of 3D structure 1.75

0.00 1.00 2.00 3.00 4.00 5.00 6.00
Freq [GHz]

Line width is also considered to model the inductance and (a) Inductance changed with different line thicknes
Q of the inductor besides the bulk resistivity. It fixed the 60.00
XY Plot 1 HFSSDesign1
Curve Info
ANSOFT

radius at 0.1 mm, line thick at 0.3 mm, the turn at 2 and 50.00
Q11
Setup1 : Sw eep
indu_h='3um'
Q11

changed the line width from 10 um to 30 um. Fig.5(a) shows Setup1 : Sw eep
indu_h='6um'
Q11
Setup1 : Sw eep

simulation results for relation among the inductance㸪Q and 40.00 indu_h='9um'
Q11
Setup1 : Sw eep

line width. It illustrated the line width is smaller, the

indu_h='10um'
Q11

30.00 Q11
Setup1 : Sw eep
indu_h='12um'

inductance is decrease. For example, when the W=10um, 20.00

L=2.0674nH; W=20um, L=1.9156nH; W=30um, L=1.8337nH. 10.00

(@f=1GHz). The Q is getting higher as line width increases,

which is shown in the Fig.5(b). The bigger the line widthˈthe
0.00
0.00 1.00 2.00 3.00 4.00 5.00 6.00
Freq [GHz]

higher the Q value. Cross section of metal is getting bigger as (b) The Q factor changed with different line thickness
the line width increases, thereby resistance decreases and the
Q value increases. Increase of line width also affects Fig. 6. The inductance and Q changed with the line thickness
integration and increases parasitic capacitance, so as to affect

2014 15th International Conference on Electronic Packaging Technology 131

C. 3D Model Simulation for Capacitors ċ˅The thickness of top metal layer:0.2 um-10 um
The capacitor based on silicon is also simulated in HFSS. In Fig.10, Capacitance is increasing as thickness of bottom
Fig.7 shows cross-section of the 3D model of the capacitor. It metal layer increases, since the edge scattering effect is
used the MIM capacitor with the a thin dielectric layer. In the enhance, which takes a parasitical capacitance. So the total
model, it utilized Si3N4 as the dielectric here and aluminum as capacitance is increasing. However, the edge scattering effect
pad metal to finish the simulation. There are some simulation also causes the loss of the capacitor, which makes the Q is
results show as follows: smaller.
Test Pad
Connect via XY Plot 1 HFSSDesign1 ANSOFT

Top_pad 1.50E-010 Curve Info

C11
Setup1 : Sw eep
HM1='0.2um'
C11
Setup1 : Sw eep
HM1='0.4um'
Dielectric C11
Setup1 : Sw eep
1.00E-010 HM1='1um'
C11
Setup1 : Sw eep
HM1='20um'
Buttom_pad

5.00E-011
SiO2

C11
Si 1.29E-026

-5.00E-011

-1.00E-010
0.00 2.00 4.00 6.00 8.00 10.00
Freq [GHz]
Fig. 7. Cross section of the 3D model of a capacitor in HFSS
Fig. 10. The capacitance changed with the thickness of metal layer
ĉ˅Scalable the bulk resistivity ˖0.1-1000 siemens/m
In Fig.8, it can be seen from the simulation result, III. LAYOUT AND SIMULATION FOR FILTER
change of substrate conductivity has little effect on
After design and simulation for elements, it get the layout
capacitance and quality factor Q value, since main factors for of the filter in Fig.11(a) by chip design tool. In the layout, we
affecting capacitance performance, which has little connection employed the inductor with W=60um, Line space=15nH;
of substrate, are loss for metal and dielectric, and parasitic 2R=120um, N=2, L=1.8337nH. The thickness of the metal pad
inductance in inner part of inductance and capacitance for for capacitor is 3um, and thickness of dielectric layer is 100
input and output ports. nm. In order to ensure the big capacitance of the capacitor, it
used several arrays to connect by parallel. This filter is
fabricated based on 8 inch high resistivity silicon with 2000
¡.cm. Fig.11(b) is the result for the S parameters by both
circuits’ simulation (pre) and layout parasitical simulation
(later), which the insertion loss is -1.7dB at 2.5GHz. This
result is also simulated by the chip simulation tool.

Fig. 8. The capacitance changed with the bulk resistivity

Ċ˅ The thickness of SiO2 layer˖0.2 um-10 um

In Fig.9, change of thickness for an oxide layer has little
effect on capacitance and quality factor Q value, since the
oxide layer, which is located between a bottom metal layer
and substrate, does not have serious parasitic effect for the
capacitance, and main factors for affecting capacitance
performance are loss for metal and dielectric, and parasitic
inductance in inner part of inductance and capacitance for
input and output ports. XY Plot 1 HFSSDesign1 ANSOFT

1.25E-010 Curve Info

C11
Setup1 : Sweep
HSiO2='0.2um'
1.00E-010 C11

7.50E-011
Setup1 : Sweep
HSiO2='0.5um'
C11
(a) The pictures of the Band-Pass-filter with test pads
Setup1 : Sweep
HSiO2='1.5um'
C11
5.00E-011 Setup1 : Sweep
HSiO2='2um'
C11
C11

Setup1 : Sweep
2.50E-011 HSiO2='3um'
C11
Setup1 : Sweep
0.00E+000 HSiO2='5um'
C11
Setup1 : Sweep
HSiO2='10um'
-2.50E-011

-5.00E-011

-7.50E-011
0.00 2.00 4.00 6.00 8.00 10.00
Freq [GHz]

Fig. 9. The capacitance changed with the thickness of insulation layer

2014 15th International Conference on Electronic Packaging Technology 132

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G% 6 
G% 6 



P
IUHT *+]
 G%6 


     
IUHT*+]

(b) Simulation results for S parameters

(b) Simulation results for S parameters
Fig. 12. The 3D model of the filter with simulation results
Fig. 11. The layout of the filter with simulation results

In Figure 12(a), it shows 3D structures for the three steps ACKNOWLEDGMENT

coupled filter in full-wave simulator. Figure 12(b) is the This work is financially supported by the National S&T
simulation results, which shows the insertion loss is -2.85dB at Major Projects under contract No.2013ZX020503. The authors
2.5GHz. The loss is bigger than the calculated results by chip would also like to thank the help of their workmates.
simulation tool. 3D simulation is closer to the real situation,
which some loss didn’t consider by the chip design tool. There
are three kinds of reasons to cause this loss: loss of the
interconnection, the parasitic of the capacitors and the REFERENCES
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