EE 302 - ELECTRONICS II

Homework #1
Due: 1.04.2019 (in class)

1. An NMOS differential amplifier utilizes a bias current of 400 7. Design the circuit of Fig. 1.5 to provide a ifferential output voltage
A. The devices have Vt 0.5 V, W 20 m, and L 0.5 m, in (i.e., one taken between the two collectors) of 1 V when the
a technology for which nCox 200 A/V2. Find VGS, gm and the differential input signal is 10 mV. A current source of 1 mA and a
value of vid for full-current switching.To what value should the positive supply of 5 V are available. What is the largest possible
bias current be changed in order to double the value of vid for full- input common-mode voltage for which operation is as required?
current switching? Assume 1.

2. Figure 1.2 shows a circuit for a differential amplifier with an

active load. Here Q1 and Q2 form the differential pair, while the
current source transistors Q4 and Q5 form the active loads for Q1
and Q2, respectively. The dc bias circuit that establishes an
appropriate dc voltage at the drains of Q1 and Q2 is not shown. It
is required to design the circuit to meet the following
specifications:

a. Differential gain Ad 80 V/V.

b. IREF I 100 A.
c. The dc voltage at the gates of Q6 and Q3 is 1.5 V.
d. The dc voltage at the gates of Q7, Q4, and Q5 is −1.5 V
Figure 1.4 Figure 1.5
The technology available is specified as follows: nCox 3pCox
90 A/V2; Vtn  Vtp0.7 V, VAn  VAp20 V. Specify the 8. A BJT differential amplifier is biased from a 2-mA constant-
required value of R and the WL ratios for all transistors. Also current source and includes a 100-resistor in each emitter.
specify ID and  VGS at which each transistor is operating. For The collectors are connected to VCC via 5-kresistors. A
dc bias calculations you may neglect channel-length mod. differential input signal of 0.1 V is applied between the two
bases.
(a) Find the signal current in the emitters (ie) and the signal voltage
vbe for each BJT.
(b) What is the total emitter current in each BJT?
(c) What is the signal voltage at each collector? Assume 1.
(d) What is the voltage gain realized when the output is taken
between the two collectors?

9. Find the voltage gain and input resistance of the amplifier in

Fig. 1.9 assuming that 100.

Figure 1.2 Figure 1.3

3. A design error has resulted in a gross mismatch in the circuit of

Fig. 1.3. Specifically, Q2 has twice the WL ratio of Q1. If vid is a
small sine-wave signal, find:
(a) ID1 and ID2.
(b) VOV for each of Q1 and Q2.
(c) The differential gain Ad in terms of RD, I, and VOV. Figure 1.9 Figure .11

4. For the differential amplifier of Fig. 1.4 let I 0.5 mA, VCC VEE 10. When the output of a BJT differential amplifier is taken
V, VCM 1 V, RC 8 k, and 100. Assume that the differentially, its CMRR is found to be 40 dB higher than when
BJTs have vBE 0.7 V at iC 1 mA. Find the voltage at the the output is taken single-endedly. If the only source of
emitters and at the outputs. common-mode gain when the output is taken differentially is
the mismatch in collector resistances, what must this mismatch
be (in percent)?
5. For the BJT diferantial amplifier of Fig. 1.5 find the value of
input differential signal vid = vB1 – vB2, that causes iE1 =0.8I.
11. In an active-loaded differential amplifier of the form shown in
Fig. 1.11, all transistors have k′W/L 3.2 mA/V2, and | vA |=
6. A BJT differential amplifier uses a 200-A bias current. What is 𝑣
20V. Find the bias current I for which the gain 𝑜⁄𝑣𝑖𝑑 80
the value of gm of each device? If is 150, what is the differential
input resistance? V/V.
12. Consider the circuit in Fig. 1.12 with the device geometries (in m) 15. Derive the frequency response, magnitude and phase response
shown in the Table 1.12. Let IREF 225 A, | Vt | 0.75 V for all expressions for the circuit in Fig. 1.15a
devices, nCox 180 A/V2, pCox 60 A/V2, | VA | 9 V for all
devices, VDD VSS 1.5 V. Determine the width of Q6, W, that will
ensure that the op amp will not have a systematic offset voltage.
Then, for all devices evaluate ID, | VOV |, | VGS |, gm, and ro. Provide
your results in a table similar to Table 1.12. Also find A1, A2, the
open-loop voltage gain, the input common-mode range, and the
output voltage range. Neglect the effect of VA on the bias current.
Figure 1.15
Table 1.12

16. Consider the circuit in Fig. 1.15a find the cut-off frequencies
(𝑤𝑐 ) and plot magnitude and phase responses for;

a. R = 1K, C =10nF
b. R = 1K, C =10F
c. R = 1K, C =10mF

17. Consider the circuit in Fig. 1.15b find the cut-off frequencies
(𝑤𝑐 ) and plot magnitude and phase responses for;

a. R = 1K, C =10nF
b. R = 1K, C =10F
c. R = 1K, C =10mF

Figure 1.12

13. A BJT differential amplifier, biased to have re 100 and

utilizing two 100-emitter resistors and 5-kloads, drives a  YOU CAN SOLVE AND ANY 10 QUESTİONS FOR YOUR
second differential stage biased to have re 50 . All BJTs have HOMEWORK.
100. What is the voltage gain of the first stage? Also find the
input resistance of the first stage, and the current gain from the  LATE SUBMISSIONS WILL NOT ACCEPTED.
input of the first stage to the collectors of the second stage.
 DUE: 01.04.2019 (@ 17:00)
14. Figure 1.14 shows a three-stage amplifier in which the stages are
directly coupled. Y. Kalkan

(a) Show the each stages and explain the aim of that stage,
(b) Explain the aim of the each capacitors.

Figure 1.14