Lab 8 Report

Author(s): Mikolaj Pal

Course: EE2174
Lab Section: L06
Date of Lab Completion: April 19, 2019
Date Submitted: April 25, 2019
Teaching Assistant: Michael Maurer
 Table of Contents
1 Introduction ............................................................................................................................. 3
2 Background .............................................................................................................................. 4
3 Results ..................................................................................................................................... 5
3.1 Part 1 ................................................................................................................................ 5
3.2 Part 2 ................................................................................................................................ 7
3.3 Part 3 ................................................................................................................................ 9
3.4 Part 4 .............................................................................................................................. 10
3.5 Part 5 .............................................................................................................................. 11
3.6 Part 6 .............................................................................................................................. 11
3.7 Part 7 .............................................................................................................................. 12
4 Discussion .............................................................................................................................. 13
5 Conclusion ............................................................................................................................. 13
6 Appendix ............................................................................................................................... 14

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1 Introduction
With the Verilog language, the DE2-115 board with the Cyclone IV E FPGA, and the
Quartus Prime software, with Library Parametrized Modules, latches and flip-flops are able to be
programmed to store values and to reset them, which was the goal of this lab. These values were
displayed to the user with the green and red LEDs in and on the seven-segment hexadecimal
displays. To be able to increment and reset the values, SR and D latches would be used for the
storage of the input values, which would be input through the slide switches. With the final
program, the built-in Library Parametrized Modules (LPMs) were used to create counters and
instantiate them through the main program for the part.

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2 Background
The DE2-115 board is the main hardware used for Lab 8 and is able to implement logic
circuits for nearly all projects. To connect the board to the computer, a USB cable was used to
program the DE2-115 board with the personal computer in the lab. Across the bottom side of the
board, there are a set of eight green and sixteen red LED lights. They have their own individual
connections and pins, which are labeled at the bottom of each light and are programmable through
the board. To program the Cyclone IV board, Quartus Prime 16.0 CAD software was the software
used and Verilog the programming language. Quartus Prime is able to support various methods of
circuit description, which includes the Verilog language. A hardware description language,
Verilog is specialized for the programming of digital logic circuits and electronics. For this lab,
the programs were created with modular and structural approaches.
On the lower end of the board, a set of 18 vertical slide switches. The switches are
straightforward 1-bit binary input devices with only two settings: DOWN towards the edge and
UP away from the edge. The slide switches were used as inputs for parts 3 through 7 as inputs for
the values for the flip-flop and to increment and reset values. These switches are not debounced,
meaning that they are not corrected for variances that may occur during the changes of their state
by the user. They may wobble between the binary values of 1 and 0, which may cause error. In
Lab 8, a set of debounced inputs were used in parts 5 and 6. These were push-buttons (labeled
KEY on the board) and were used to increment up the values displayed on the red LED lights in
part 5 and the values on the hexadecimal displays in part 6. Above the LEDs and slide switches
are eight 7-segment hexadecimal displays that are in two pairs and a group of four together. Each
segment has a pin connection to the Cyclone IV that is programmable. They are programmable as
a 7 bit value with every bit representing one of the segments on the display. These displays were
used in part 6, where the hexadecimal values from the input were required to be displayed on
displays 0-3 and then copied over to 7-4.
Library Parametrized Modules are custom configurable modules located in the Quartus II
program. There are many different ones that have many different uses, with a counter being created
in the case of this lab. They are configured using a built-in wizard, where the user is able to specify
the inputs, outputs, and their sizes in bits. After completion of the wizard, the code is generated in
a separate program and a template file is created for calling the program through instantiation.
Latches are circuits that are able to store data and contain two stable states. They are used to store
data and to reset the data. A flip-flop is a type of latch that only uses one bit and is used to store a
state.

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3 Results
3.1 Part 1
In Part 1, a simple Gated SR Latch was created using the structural sample code provided
in Listing 1 of the lab manual and the actual program code in Listing 6.1 in the Appendix. The
Gated SR Latch is a simple latch consisting of two and gates and two nor gates, and two numerical
inputs and a clock input. It also relies on a previous output value to generate its output, and the
lack of it is shown in Figure 3.1 below. At first the code included a directive in the signals, defined
as wire in the code, stating “/* synthesis keep */”. This directive preserves the signals and the
defined logic as separate elements, called Look Up Tables (LUTs), which is shown in Figure 3.2
on the following page. When this directive was removed from the code, this resulted in a single
LUT to be generated for the entire program, which is shown in Figure 3.3 on the following page.

Figure 3.1: Functional Simulation for Part 1

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 Figure 3.2: Technology view for Part 1 with synthesis

Figure 3.3: Technology View for Part 1 without Synthesis

Figure 3.4: Implemented Circuit for Part 1

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3.2 Part 2
For Part 2, a Gated D Latch was constructed in Quartus Prime by modification of the code
from Part 1. Initially, the “/* synthesis keep */” directive was included in the code, which resulted
in the LUTs and logic elements to be separate, as shown in Figure 3.6 below. This was done to
implement signals Qa, Qb, R_g, S_g, and R, as shown in the Implemented Circuit in Figure 3.5.
Removal of the directive resulted in a single LUT being created, as shown in Figure 3.7 below.
Between the functional and timing simulations, Figures 3.8 and 3.9 respectably, there is a slight
delay in the time where the output is expected. This can be attributed to either the actual physical
limitations of the board that cause these delays, which are taken into account with the timing
simulation, or the “/* synthesis keep */” directive, which results in multiple LUTs to be created
instead of just one, which could take longer to process. Just like the SR Latch in Part 1, a previous
value is required for the output to be generated.

Figure 3.5: Implemented Circuit for Part 2

Figure 3.6: Technology View for Part 2 with synthesis

Figure 3.7: Technology View for Part 2 without synthesis

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 Figure 3.8: Functional Simulation for Part 2

Figure 3.9: Timing Simulation for Part 2

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3.3 Part 3
Part 3 requires the actual physical implementation of the Gated D Latch into the DE2-115
board. The D input was the slide switch SW[0], and the slide switch for the clock input was SW[1].
A single red LED, LEDR[0], was the final output Q, as shown in Listing 6.3 in the Appendix. The
behavior was as expected in Part 2 for the functional simulation, with no significant structural
errors occurring during compilation of the program and the programming of the board.

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3.4 Part 4
The creation of a counter, required for Part 4, was completed with a flip-flop and sequential
logic in programming. Code from Listing 3 in the lab manual was used as a starting point for the
implementation of this part, with slide switches SW[1] and SW[0] being used for the clock input
and E input respectably. The output needed to be larger than a single bit, and was set to 16 bits as
instructed by the lab manual. The reset used was an asynchronous low reset, and a clock trigger
set to positive edge. In the code, “<=” was used in place of the standard equal sign to allow the
line of code to be executed independently of the other lines. Through a functional simulation, the
program was determined to function properly, with the increase of values functioning as expected.
Shown in Figure 3.10 below is the functional simulation, where the asynchronous low reset is
shown resetting the entirety of the output Q as expected.

Figure 3.10: Functional Simulation for Part 4

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3.5 Part 5
For Part 5, the program from Part 4 was implemented into the DE2-115 board, with the
addition of a second counter that required two instantiations of the main code, resulting in two
counters as shown in Listing 6.5 in the Appendix. Switches SW[0] and SW[1] were the E inputs
while SW[3] was the reset in both instantiations. Switch SW[2] was the clock in the first
instantiation while push button KEY[1] served as the clock in the second instantiation. There were
two outputs in this part, the green LEDs and the red LEDs respectably. They were switched
between with SW[3] with green being active when it was off and red when it was on. The green
LEDs were incremented up by 1 when SW[0] was on and the reds when SW[1] was on. Since the
push buttons were debounced, there was no error or unexpected changes in value when KEY[1]
was triggered. However, when SW[2] was triggered, there were unexpected increases in the value
displayed on the green LEDs when toggled, since additional spikes occurred when the states were
changed.

3.6 Part 6
The aim for Part 6 was to develop a program that displayed the value of a 16 bit input on
the four seven segment displays HEX 4-7, and then copied them onto displays 0-3, while being
able to reset. The value displayed was created through a 16-bit slide switch input, which was copied
onto the 16-bit input B and displayed on HEX 4-7. When push-button KEY[1] was triggered, the
value in B was transferred over to A and displayed on HEX 0-3. KEY[0] was used to reset value
A to zero, and was the asynchronous reset for this program. This was the most complex of all the
programs, as at first the instructions were not clear and resulted in the incorrect program being
created. However, after a considerable effort, this was corrected.

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3.7 Part 7
In Part 7, a Library Parametrized Module (LPM) was created to simulate the 16-bit counter
created in part 4. Using the built-in wizard, options were enabled to have the required
asynchronous low resent and the clock enable. In the main program for the part, shown in Listing
6.7 in the Appendix, the created LPM was called upon to do the bulk of the work. In the
instantiation of the LPM, the variables from the main program were input in replace of the
variables provided in the template generated for the program. The LPM operated as expected,
which is shown by the functional simulation in Figure 3.11: Functional Simulation for Part 7
below.

Figure 3.11: Functional Simulation for Part 7

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4 Discussion
In the prelab assignment for this lab, it was predicted that a benefit of using the LPM was
the simplification of the main program that used instantiations to call upon it instead of having to
manually write the code within that program. Because of this, it was also predicted that diagnosing
errors and fixing them would be easier due to the lack of a complex code structure in the main
program that would’ve otherwise been compromised. This turned out to be true, as some minor
errors occurred when initially writing the main program, which were able to be quickly resolved
and did not affect the module. Additionally, compilation errors occurred with the counting module,
and those were able to be resolved easily with reconfiguration through the wizard. This also applies
to the modular design approach to coding, as the LPM was called upon in the main program
through an instantiation and the bulk of the work was done within the LPM.

5 Conclusion
Library Parametrized Modules are able to be used to easily create components of a program
in a shorter amount of time that would’ve otherwise been consumed by the manual creation of
these components. Quartus has a large library of various LPMs to suit user needs, so productivity
is increased. These LPMs are separate programs that are called upon through instantiation in the
main program to do a large amount of the work. Latches are used in various applications, and for
this lab were used to create a storage element for the storage of values and their reset. Flip-Flops
are used for these purposes but also for the upwards incrementation of the values, especially for
multi-bit outputs. This can then be used as a counter with a clock input, which are useful for various
real-life situations, such as sorting and digital clocks. Using Verilog and Quartus Prime, these are
able to be created and to help the user further educate themselves in the field of Digital Logic.

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6 Appendix

Figure 6.1: First Page of Lab 8 Submission Sheet

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 Figure 6.2: Second Page of Lab 8 Submission Sheet

module Lab8Part1 (Clk, R, S, Q); //module initialization

input Clk, R, S; //clock and R and S are inputs
output Q;
wire R_g, S_g, Qa, Qb /* Synthesis Keep */; //synthesis kept to have individual gates
and (R_g, R, Clk); //and gate
and (S_g, S, Clk); //and gate
nor (Qa, R_g, Qb); //nor gate
nor (Qb, S_g, Qa);//nor gate, end of SR Latch
assign Q = Qa; //main output assigned to Qa from latch
endmodule
Listing 6.1: Code for Part 1

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module Lab8Part2 (Clk, D, Q);
input Clk, D; //input of clock and D
output Q;
wire R, S, R_g, S_g, Qa, Qb /* synthesis keep*/; //synthesis kept to have individual gates
assign S = D; //S is D
assign R = ~D; //R is the opposite of D
nand (R_g, R, Clk); //nand gate
nand (S_g, S, Clk); //nand gate
nand (Qa, S_g, Qb); //nand gate
nand (Qb, R_g, Qa); //nand gate, end of D latch
assign Q = Qa; //main output of Q assigned to Qa output of D latch
endmodule
Listing 6.2: Code for Part 2

module Lab8Part3 (SW, LEDR);

input [1:0]SW; //switches from board are inputs, two bit input
output [1:0]LEDR; //red LEDs are outputs
wire R, S, R_g, S_g, Qa, Qb /* synthesis keep*/; //synthesis kept to have individual gates
assign S = SW[0]; //S is the switch input
assign R = ~SW[0]; //R is the opposite of the switch input
nand (R_g, R, SW[1]); //nand gate
nand (S_g, S, SW[1]); //nand gate
nand (Qa, S_g, Qb); //nand gate
nand (Qb, R_g, Qa); //nand gate
assign LEDR[0] = Qa; //the main output from latch is red LED
endmodule
Listing 6.3: Code for Part 3

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module Lab8Part4 (reset, SW, Q);
input reset;
input [1:0]SW;
output reg [15:0]Q;

always @(posedge SW[1] or negedge reset)

begin
if(reset==0)
Q<=0;
else if(SW[0])
Q<=Q+1;
end
endmodule
Listing 6.4: Code for Part 4

module Lab8Part5 (SW, KEY, LEDR, LEDG);

input [3:0]SW; //switches are inputs
input [1:0]KEY; //push buttons are inputs
output reg [15:0]LEDR; //Red LEDs as outputs
output reg [7:0]LEDG; //Green LEDs as outputs

always @(posedge SW[2] or negedge SW[3]) //when switch 2 increases or switch 3

decreases
begin
if(SW[3]==0) //if switch 3 is not activated
LEDG<=0; //all green LEDs off
else if(SW[0]) //else if switch 0 is toggled
LEDG<=LEDG+1; //increment binary value displayed by green LEDs up by 1
end

always @(negedge KEY[1] or posedge SW[3]) //when push button 1 decreases or switch
3 increases
begin
if(SW[3]==1) //if switch 3 is activated
LEDR<=0; //all red LEDs off
else if(SW[1]) //else if switch 1 is toggled
LEDR<=LEDR+1; //increment binary value displayed by red LEDs up by 1
end
endmodule
Listing 6.5: Code for Part 5

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module Lab8Part6 (SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);
input [15:0]SW; //switches are inputs
input [3:0]KEY; //push buttons are inputs
output [0:6]HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7; //7-segment hex
displays are ouputs
reg [15:0]A, B; //temporary storage values

always @(posedge KEY[0] or negedge KEY[1]) //when push button 1 increases or push
button 2 decreases
begin
A = SW; //values from switch inputs copied over to A
if (KEY[1]==0) //if push button 1 is not activated
begin
B = 0; //displays 5-8 are zero
end
else //if push button 1 is activated
begin
B = A; //values displayed on displays 1-4 are copied over to displays 5-8
end
end

hex7seg inst1(A[3:0], HEX0); //instantiations for value converter program

hex7seg inst2(A[7:4], HEX1);
hex7seg inst3(A[11:8], HEX2);
hex7seg inst4(A[15:12], HEX3);

hex7seg inst5(B[3:0], HEX4);

hex7seg inst6(B[7:4], HEX5);
hex7seg inst7(B[11:8], HEX6);
hex7seg inst8(B[15:12], HEX7);
endmodule
Listing 6.6: Code for Part 6

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module Lab8Part7 (reset, SW, Q);
input reset;
input [1:0]SW;
output wire [15:0]Q;

count1 count1_inst (
.aset ( reset ),
.clk_en ( SW[0] ),
.clock ( SW[1] ),
.q ( Q )
);
endmodule
Listing 6.7: Code for Part 7

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