The STA2051 GPS Controller

Steve Sutton
Marketing Manager GPS and
Navigation

STA2051 2-Chip GPS Solution

Single chip 12 Channel GPS ARM7TDMI

RTC/ XTL
GPS Radio DSP Hardware 16/32 bit
Oscill
(STB5610 or Risc Core
SE4100L)

Interrupt Interrupts
64KB SRAM Controller
Low Power
Wakeup
Controller
Multi Media Card i/f
UARTS/BSPI/I2C
Smart Card i/f
256KB FLASH GPIO
Timer/Counter/PWM
Watchdog Enable
Watchdog HDLC Telepass/Tolling

JTAG CAN

USB 12 bit A/D Gyro

Programmable Memory Interface

 STA2051 Top Level Features
• Features
– CMOS M8T 0.18um Technology
– 60MHz ARM7TDMI 16/32 bit RISC CPU
– 12 Channel GPS Correlation DSP
– Complete Embedded Memory System
• FLASH 256K bytes +16K bytes
– (100K erasing/programming cycles)
• RAM 64K bytes.
– Large array of Peripherals and General Purpose I/O
– 2 package options
• TQFP144
• TQFP64
– External Memory Interface (144pin Only)
– -40°C to +85°C operating temperature range

STA2051 Power Supply Modes

• Power Supply:
– 2.7V to 3.6V operating supply range for Input/Output
periphery
– 3V to 3.6V operating supply range for A/D Converter
reference
– 1.8V operating supply range for core supply provided either
by internal Voltage Regulator with external stabilization
capacitor,or by external supply for higher power efficiency.
 STA2051 Clock Strategy

• 0-66 MHz internal clock frequency managed by a Reset and

Clock Control Unit

• The unit is able to provide low power modes

(WAIT,SLOW,STOP,STANDBY) and to generate the internal
clock from the external reference through integrated PLL.

STA2051 Power Consumption

• Power consumption STA2051

– Working condition approx. 35mA @16MHz
• Assumes operation from internal memory
– WFI Mode @ 1 MHz ~ 5 mA
– Low Power WFI Mode @ 32 KHz ~ 500 uA
– Stop Mode ~ 200 uA
– Stand-by Mode ~ 20 uA
 STA2051 GPS Correlation DSP
• 12 Independent Channels
– 2 Correlators/Channel, One In-Phase and One Quadrature
• Fast Acquisition mode
– 1KHz for tracking
– 16KHz for acquisition
• Numerically Controlled Oscillator (NCO) for fine tuning
• No TCXO Required
• Differential Ready
– Support for RTCA-SC159 WAAS/EGNOS/MSAS
• Software readable timebase registers
• PRN output for testing or optional external correlators
• HW driven One Pulse Per Second (1pps) output accurate to +/- 50ns

1 Pulse Per Second On STA2051

 STA2051 External Memory Interface
• 4 separately configurable external memory regions (Banks)
– Corresponding to 4 available chip selects (CSn.0,..,CSn.3)
– Support for mixed memory, ROM, FLASH, SRAM.

• Each Bank uses all 24 bits of A [23:0 ]

– addressing up to 16 MBytes of external memory space each
bank
– Total external memory space of 64 Mbyte

• Programmable timings
– Up to 15 configurable wait states for each external memory
region.

• 8/16 bit bus width (software selectable)

– External memory transfers are configurable to be 8,16 or 32-
bit wide (multiple cycle access) to 8/16 bit external memory
devices.

STA2051 System Boot Modes

• Four Different Boot Modes available

– USER Mode BOOTEN = 0, BOOT[1:0] = Don’t care

OR BOOTEN = 1, BOOT1 = 0, BOOT0 = 0
• Standard mode of operation
• All user FLASH sectors visible
• Boot-FLASH sector not accessible

– BOOT Mode BOOTEN = 1, BOOT1 = 0, BOOT0 = 1

• Wake up in BOOT Mode when FLASH first programmed
– eg in the manufacturing line
• Boots from internal RAM after config. code (EMBALGO)
executes from reserved BOOT-FLASH sector.
• Allows the internal RAM to be programmed via a UART.
• Necessary to use this mode to program at least one Flash
sector with a boot code including in-system boot-loader, to
allow a normal system start-up or ISP in user mode.
 STA2051 System Boot Modes

– RAM Mode BOOTEN = 1, BOOT1 = 1, BOOT0 = 0

• In RAM mode the system boot is performed from the
internal RAM,which is also visible at address 0h (see
BOOTCONF register).The Ram must be pre-loaded by
the user,for example through the Development System
(MultiICE ™ or equivalent).

– EXTMEM Mode BOOTEN = 1, BOOT1 = 1, BOOT0 = 1

• In EXTMEM mode the system boot is performed from the
external memory,block 0 (CSN0 is activated).The
external memory is also visible at address 0h (see
BOOTCONF register).

STA2051 System Services

• Real Time Clock Module
– Real time clock module with 32KHz low power oscillator and
separate power supply to continue running during stand-by
mode.

• Watchdog Timer Module

– 16-bit Watchdog Timer with 8 bits prescaler for system
reliability and integrity.

• Wake-up Unit
– Wake-up unit allows exiting from power down modes by
detection of an event on one external pins or on internal
Real Time Clock alarm
 STA2051 System Services

• Timers
– Four 16-bit programmable Timers with 7 bit prescaler
– up to two input capture/output compare
– one pulse counter function
– one PWM channel with selectable frequency each.

• Enhanced Interrupt Controller

– supports 2 interrupt vectors, independently maskable, with
interrupt vector table for faster response and 16 priority
levels,SW programmable for each source.Up to 2 maskable
interrupts may be mapped on FIQ.

STA2051 Peripherals
• General Purpose I/O
– 48 programmable General Purpose I/O,
– Each pin programmable independently as digital input or
digital output
– 40 (30 in TQFP64) are multiplexed with peripheral functions
– 16 can generate an interrupt on input level/transition.

• CAN Module
– CAN module compliant with the CAN specification V2.0 part
B (active).
– The bit rate can be programmed up to 1 MBaud.
 STA2051 Peripherals
• A/D Converter
– 4 channels 12-bit sigma-delta Analogue to Digital Converter
– single channel or multi channel conversion modes
– single-shot or continuous conversion modes
– sample rate 1KHz (4 KHz when single channel)
– conversion range 0-2.5V.

• UARTs
– Three UARTs allow full duplex, asynchronous,
communications with external devices
– independently programmable TX and RX baud rates up to
625K baud.
– One UART adapted to suit Smart Card (SC) interface needs,
for asynchronous SC as defined by ISO 7816-3; it includes
SC clock generation.

STA2051 Peripherals
• Serial Peripheral Interfaces
– Two Serial Peripheral Interfaces (SPI) allow full duplex,
synchronous communications with external devices
– master or slave operation
– max baud rate:8Mb/s.
– One SPI may be used as Multimedia Card interface.

• I2C Interfaces
– Two I2C Interfaces provide multi-master and slave functions
– support normal and fast I2C mode (400 KHz)
– 7/10 bit addressing modes
– One I2C Interface is multiplexed with one SPI so either
2xSPI + 1xI2C or 1xSPI + 2xI2C may be used at a time.
 STA2051 Peripherals

• USB unit
– V1.1 compliant
– Software configurable endpoint setting
– USB Suspend/Resume support (TQFP144 only)

• High Level Data Link Controller (HDLC) unit

– supports full duplex operating mode
– NRZ, NRZI, FM0 and MANCHESTER modes
– internal 8bit Baud Rate Generator

GPS Terms
• Almanac
– The database of the complete system, satellite orbits, ionosphere,
health, utc offsets.
9 Transmitted continuously, repeated every 12.5 minutes
9 Updated daily
9 valid 2 weeks for acquisition aiding
9 valid 6 months for satellite selection

• Ephemeris
– Accurate database of the orbit and clocks for the transmitting
satellite only
9 Transmitted continuously in subframes 1,2,3
9 Repeats every 30 seconds
9 Updated every 1 or 2 hours
 GPS Terms
• Cold Start
– As when equipment is first manufactured
– No Almanac, Ephemeris, time of day or position estimates

• Warm Start
– Starting with Almanac and time of day
– No accurate time, no Ephemeris in memory
– Estimated position

• Hot Start
– Starting with Ephemeris data already loaded

GPS Terms

• Re-Acquisition
– After a tunnel or similar blockage
– Position is known to a few 100 metres
– Clock is not interrupted

• TTFF
– Time To First Fix in each of the previous cases
 STA2051 GPS Performance
12 Channel fully Parallel receiver, with carrier phase tracking,
differential and WADGPS facilities
• Accuracy
– With SA 100m (16m RMS)
– Without SA 3m 95% Horizontal
5m 95% Vertical
• Time To First Fix (TTFF) Typical
– Cold start (no data in memory) 90 Seconds
– Power Down Start
• Data in memory Under Test
– Warm start 30 – 40 Seconds
• Find first satellite 0.5 Seconds
• Find Rest 0.5 Seconds
• Download time 30 – 40 Seconds
– Hot start, no download time 3 Seconds
– Obscuration recovery 2 Seconds (150ms internal)

STA2051 Sensitivity

• Current STA2051 SW tuned for automotive applications

– Acquire first satellite @ 41dB C/No
– Acquire following satellites @ 33dB C/No
– Track down to 25dB C/No

• New release of software currently under development

– Improvements to acquisition of first satellite
• Acquire first satellite @ 35db C/No
– High Sensitivity SW written and under test
• Sensitivity Management SW currently under development
– Try normal sensitivity/fast mode first
– Switch to high sensitivity if fast mode time-out
– User selectable
 STA2051/ST5610 Sensitivity vs
Sample rate vs Integration time

ST GPS Software – The Complete Solution

• Represents a complete implementation of a GPS receiver

– Digital signal processing
– GPS positioning maths
– Handling for differential corrections
– Management and I/O processes

• Customer Choice
– 2 levels of license available
• Binary
• Object code (libraries)
 STA2051 Development tools

• SW Toolset
– ARM Real View Developer Suite US$6750

• Host Interface
– ARM Real View MultiICE US$3500

STA2051 Low Cost Development tools

• Rowley Associates (www.rowley.co.uk)

– SW Toolset
• CrossWorks for ARM US$795
– GNU based toolset, includes:
» Compiler, Debugger,
» Linker, Editor etc.
– Host Interface
• Wiggler in place of MultiICE
– Macraigor Systems OCDemon (US$150)
» www.macraigor.com, www.ocdemon.com,
www.ocdemon.net
– ACM Microsystems £60
» www.acm-micros.com
– Can debug from Flash
 GPS RF IC’s for STA2051
• Currently 2 options:

– ST Microelectronics STB5610 Single Chip GPS radio

• Mature stable design in Hi-Speed Bi-Polar
• Fully automotive qualified
• Recommended for all automotive applications
• Fully supported by ST Microelectronics

– SiGe Semiconductor SE4100 Low power Single Chip GPS radio

• Ultra Low power design in Silicon Germanium process
• Not Automotive qualified
• Recommended for applications where ultra-low power
consumption is paramount e.g. Hand held portable applications
• Supported by SiGe Semiconductor

STB5610 Block Diagram

SAW Discrete IF Discrete IF

Filter filter filter

Data@4 MHz
CMOS levels
Dualgain RF Amp. Mixer Lim.amp. D Latch Output buffer
LNA
D Q
CK
Gain 1.57 20
Select GHz MHz
1.55
.
GHz

~ Lim.amp. CLK@16MHz
PLL VCO CMOS levels

Loop Frequency Power Down 1 Power Down 2

Filter Select. External Tank

Pure Si Bipolar Technology

TQFP48 Package
 STB5610 Features and Benefits

• Features ¾ Resulting Benefits

– Min Supply Voltage = 2.7V ¾ Compatible with Portable applications

– Switched gain LNA ¾ Support for Passive or Active Antennas

– 16.368MHz Crystal ¾ Support for standard crystals or TCXO’s

– Integrated Local Oscillator ¾ Reduced Bill of materials

– Active current ~35mA ¾ Reduced power consumption

– On chip VCO/PLL circuitry ¾ Reduced Bill of materials

– Separate CE pins for clock ¾ Allows Interval mode for very low power
and Signal

STB5610 Status

• Maturity Level 29 – Pre-Production

• Datasheet available
• BOM available
• Application schematic available
• STB5610/STA2051 Reference Design available
 GPS RF DOWN CONVERTER ROAD-MAP
compatible with ST GPS correlators
STB58xx

STB56xx
BiCMOS/CMOS
Integration

technology
STB5610
Bipolar
STB5600 technology
Bipolar
technology
3V Discrete
GPS radio
design

1996 1998 2000 2002 2004

SE4100L Single Chip GPS RF

• SE4100L: Single Chip GPS RF using SiGe process

• Fully compatible with ST Microelectronics STA2051

• Excellent
– BOM Cost
– Power Consumption
– Size
– Ease of use
 SE4100L Block Diagram

LowGain

LNAOut
MixIn

RF Amp
LNAIn LNA Mixers IF Filter

AntOK ~
~
AntDetP ÷96
~
AntDetN +45? / -45
I Q Phase
Ant current
Σ
Shift /
monitor Phase Quadrature
Xtal1 Combiner
Det. ÷2

~
D DataOut
Clk Q

Xtal2 Xtal ~ VCO D-type

Oscillator

RxEnb
OscEnb

ClkOut
Vtune

SE4100L Features
Optional
• On-Chip LNA SAW Filter

– 1.9dB NF allows direct

BP Filter
connection to passive LNA
RF
Amp
+45°/ -45°
antenna Active +45°/-45°
Antenna Σ
• Filtering ÷96 Digital
Detect D
Out
FF
– No SAW XTAL PD LPF VCO
OSC
– No LC BPF
Clock
• RF PLL components on-chip Out

– No resonator
– No varactor
– No off-chip LO components
– No EMC issues!
• All in a 4mm x 4mm LPCC
package
 SE4100L Integration with STA2051

Regulator/Switch Vcc

PCB Passive Antenna

Power Control
NMEA

SE4100L Clock 16.368MHz STA2051

RF Data 16.368Mbit Baseband
Remote Active Antenna
Antenna OK

Antenna Switch

SE4100L + STA2051 Example PCB

• 9 – 15V supply
• Twin UARTs
NMEA and debug
• Battery-backed RTC
• Flash upload
• JTAG for software
development
• Phantom antenna power over-
current protection
 SE4100L + STA2051
- THE Low Power Solution
80
- SE4100L + STA2051 design
gives low power without
Baseband
70 compromising performance
RF
Supply current @ 3V (mA)

60 - Typical RF supply current

10 mA @ 3V
50
– Including on-chip LNA
40 - Typical Baseband supply
30 current 16mA @ 3V
20
- True 2-chip design with internal
memory
10
– No off-chip memory buses
0 - Ideal for
9 PDA / laptop
SiGe
Motorola Valence
+ Sony
SiRF
+ 9 Cellular
ST 9 Tracking & Security

Applications Support
• SE4100L example RF schematic and PCB layout
provided by SiGe

• STA2051 example schematic and layout provided

by SiGe in conjunction with ST Microelectronics

• GPS SW support provided by ST Microelectronics

 SE4100L Availability and Sampling

• Demo PCBs available May 2003

• 1 – 10 off samples available now to active developments
• Pre-production sampling September 2003
• Production available December 2003