74F191 Up/Down Binary Counter with Preset and Ripple Clock

April 1988
Revised September 2000

74F191
Up/Down Binary Counter with Preset and Ripple Clock
General Description Features
The 74F191 is a reversible modulo-16 binary counter fea- ■ High-Speed—125 MHz typical count frequency
turing synchronous counting and asynchronous presetting. ■ Synchronous counting
The preset feature allows the 74F191 to be used in pro-
■ Asynchronous parallel load
grammable dividers. The Count Enable input, the Terminal
Count output and Ripple Clock output make possible a ■ Cascadable
variety of methods of implementing multistage counters. In
the counting modes, state changes are initiated by the ris-
ing edge of the clock.

Ordering Code:
Order Number Package Number Package Description
74F191SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F191SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F191PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols Connection Diagram

IEEE/IEC

© 2000 Fairchild Semiconductor Corporation DS009495 www.fairchildsemi.com

74F191
Unit Loading/Fan Out
U.L. Input IIH/IIL
Pin Names Description
HIGH/LOW Output IOH/IOL

CE Count Enable Input (Active LOW) 1.0/3.0 20 µA/−1.8 mA

CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA
P0–P3 Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA
PL Asynchronous Parallel Load Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
U/D Up/Down Count Control Input 1.0/1.0 20 µA/−0.6 mA
Q0–Q3 Flip-Flop Outputs 50/33.3 −1 mA/20 mA
RC Ripple Clock Output (Active LOW) 50/33.3 −1 mA/20 mA
TC Terminal Count Output (Active HIGH) 50/33.3 −1 mA/20 mA

Functional Description
The 74F191 is a synchronous up/down 4-bit binary allow the negative-going edge of the carry/borrow signal to
counter. It contains four edge-triggered flip-flops, with inter- ripple through to the last stage before the clock goes HIGH.
nal gating and steering logic to provide individual preset, There is no such restriction on the HIGH state duration of
count-up and count-down operations. the clock, since the RC output of any device goes HIGH
Each circuit has an asynchronous parallel load capability shortly after its CP input goes HIGH.
permitting the counter to be preset to any desired number. The configuration shown in Figure 3 avoids ripple delays
When the Parallel Load (PL) input is LOW, information and their associated restrictions. The CE input for a given
present on the Parallel Data inputs (P0–P3) is loaded into stage is formed by combining the TC signals from all the
the counter and appears on the Q outputs. This operation preceding stages. Note that in order to inhibit counting an
overrides the counting functions, as indicated in the Mode enable signal must be included in each carry gate. The
Select Table. simple inhibit scheme of Figure 1 and Figure 2 doesn't
A HIGH signal on the CE input inhibits counting. When CE apply, because the TC output of a given stage is not
is LOW, internal state changes are initiated synchronously affected by its own CE.
by the LOW-to-HIGH transition of the clock input. The
direction of counting is determined by the U/D input signal, Mode Select Table
as indicated in the Mode Select Table. CE and U/D can be
changed with the clock in either state, provided only that Inputs
Mode


the recommended setup and hold times are observed. PL CE U/D CP


Two types of outputs are provided as overflow/underflow H L L Count Up
indicators. The Terminal Count (TC) output is normally
LOW and goes HIGH when a circuit reaches zero in the H L H Count Down
count-down mode or reaches 15 in the count-up mode. The L X X X Preset (Asyn.)
TC output will then remain HIGH until a state change H H X X No Change (Hold)
occurs, whether by counting or presetting or until U/D is
changed. The TC output should not be used as a clock sig-
nal because it is subject to decoding spikes.
RC Truth Table
The TC signal is also used internally to enable the Ripple Inputs Output
Clock (RC) output. The RC output is normally HIGH. When

CE is LOW and TC is HIGH, the RC output will go LOW CE TC* CP RC
when the clock next goes LOW and will stay LOW until the L H
clock goes HIGH again. This feature simplifies the design H X X H
of multistage counters, as indicated in Figure 1 and
X L X H
Figure 2. In Figure 1, each RC output is used as the clock
input for the next higher stage. This configuration is particu- *TC is generated internally
H = HIGH Voltage Level
larly advantageous when the clock source has a limited L = LOW Voltage Level


drive capability, since it drives only the first stage. To pre- X = Immaterial
vent counting in all stages it is only necessary to inhibit the = LOW-to-HIGH Clock Transition
first stage, since a HIGH signal on CE inhibits the RC out- = LOW Pulse
put pulse, as indicated in the RC Truth Table. A disadvan-
tage of this configuration, in some applications, is the
timing skew between state changes in the first and last
stages. This represents the cumulative delay of the clock
as it ripples through the preceding stages.
A method of causing state changes to occur simulta-
neously in all stages is shown in Figure 2. All clock inputs
are driven in parallel and the RC outputs propagate the
carry/borrow signals in ripple fashion. In this configuration
the LOW state duration of the clock must be long enough to

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 74F191
FIGURE 1. n-Stage Counter Using Ripple Clock

FIGURE 2. Synchronous n-Stage Counter Using Ripple Carry/Borrow

FIGURE 3. Synchronous n-Stage Counter with Gated Carry/Borrow

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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74F191
Absolute Maximum Ratings(Note 1) Recommended Operating
Storage Temperature −65°C to +150°C Conditions
Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature 0°C to +70°C
Junction Temperature under Bias −55°C to +150°C Supply Voltage +4.5V to +5.5V
VCC Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V) Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
Standard Output −0.5V to VCC under these conditions is not implied.
3-STATE Output −0.5V to +5.5V Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max) twice the rated IOL (mA)

DC Electrical Characteristics
Symbol Parameter Min Typ Max Units VCC Conditions
VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal
VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
VOH Output HIGH 10% VCC 2.5 IOH = −1 mA
V Min
Voltage 5% VCC 2.7 IOH = −1 mA
VOL Output LOW Voltage 10% VCC 0.5 V Min IOL = 20 mA
IIH Input HIGH
5.0 µA Max VIN = 2.7V
Current
IBVI Input HIGH Current
7.0 µA Max VIN = 7.0V
Breakdown Test
ICEX Output HIGH
50 µA Max VOUT = VCC
Leakage Current
VID Input Leakage IID = 1.9 µA,
4.75 V 0.0
Test All Other Pins Grounded
IOD Output Leakage VIOD = 150 mV
3.75 µA 0.0
Circuit Current All Other Pins Grounded

IIL Input LOW Current −0.6 VIN = 0.5V (except CE)

mA Max
−1.8 VIN = 0.5V (CE)
IOS Output Short-Circuit Current −60 −150 mA Max VOUT = 0V
ICC Power Supply Current 38 55 mA Max

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 74F191
AC Electrical Characteristics
TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C
VCC = +5.0V VCC = +5.0V VCC = +5.0V
Symbol Parameter Units
CL = 50 pF CL = 50 pF CL = 50 pF
Min Typ Max Min Max Min Max
fMAX Maximum Count Frequency 100 125 75 90 MHz
tPLH Propagation Delay 3.0 5.5 7.5 3.0 9.5 3.0 8.5
tPHL CP to Qn 5.0 8.5 11.0 5.0 13.5 5.0 12.0
ns
tPLH Propagation Delay 6.0 10.0 13.0 6.0 16.5 6.0 14.0
tPHL CP to TC 5.0 8.5 11.0 5.0 13.5 5.0 12.0
tPLH Propagation Delay 3.0 5.5 7.5 3.0 9.5 3.0 8.5
tPHL CP to RC 3.0 5.0 7.0 3.0 9.0 3.0 8.0
ns
tPLH Propagation Delay 3.0 5.0 7.0 3.0 9.0 3.0 8.0
tPHL CE to RC 3.0 5.5 7.0 3.0 9.0 3.0 8.0
tPLH Propagation Delay 7.0 11.0 18.0 7.0 22.0 7.0 20.0
tPHL U/D to RC 5.5 9.0 12.0 5.5 14.0 5.5 13.0
ns
tPLH Propagation Delay 4.0 7.0 10.0 4.0 13.5 4.0 11.0
tPHL U/D to TC 4.0 6.5 10.0 4.0 12.5 4.0 11.0
tPLH Propagation Delay 3.0 4.5 7.0 3.0 9.0 3.0 8.0
ns
tPHL Pn to Qn 6.0 10.0 13.0 6.0 16.0 6.0 14.0
tPLH Propagation Delay 5.0 8.5 11.0 5.0 13.0 5.0 12.0
ns
tPHL PL to Qn 5.5 9.0 12.0 5.5 14.5 5.5 13.0
tPLH Propagation Delay 5.0 14.0 5.0 15.0
ns
tPHL Pn to TC 6.5 13.0 6.0 14.0
tPLH Propagation Delay 6.5 19.0 6.5 20.0
ns
tPHL Pn to RC 6.0 14.0 6.0 15.0
tPLH Propagation Delay 8.0 16.5 8.0 17.5
ns
tPHL PL to TC 6.0 13.5 6.0 14.5
tPLH Propagation Delay 10.0 20.0 10.0 21.0
ns
tPHL PL to RC 9.0 15.5 9.0 16.0

AC Operating Requirements
TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C
Symbol Parameter VCC = +5.0V VCC = +5.0V VCC = +5.0V Units
Min Max Min Max Min Max
tS(H) Setup Time, HIGH or LOW 4.5 6.0 5.0
tS(L) Pn to PL 4.5 6.0 5.0
ns
tH(H) Hold Time, HIGH or LOW 2.0 2.0 2.0
tH(L) Pn to PL 2.0 2.0 2.0
tS(L) Setup Time LOW
10.0 10.5 10.0
CE to CP
ns
tH(L) Hold Time LOW
0 0 0
CE to CP
tS(H) Setup Time, HIGH or LOW 12.0 12.0 12.0
tS(L) U/D to CP 12.0 12.0 12.0
ns
tH(H) Hold Time, HIGH or LOW 0 0 0
tH(L) U/D to CP 0 0 0

tW(L) PL Pulse Width LOW 6.0 8.5 6.0 ns

tW(L) CP Pulse Width LOW 5.0 7.0 5.0 ns
tREC Recovery Time 6.0 7.5 6.0 ns
PL to CP

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74F191
Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A

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 74F191
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D

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74F191 Up/Down Binary Counter with Preset and Ripple Clock
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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