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Bharath Niketan Engineering College: Hours

This document contains a model examination for the subject Digital Logic Circuits. It has 3 parts - Part A contains 10 multiple choice questions worth 2 marks each. Part B contains 5 questions worth 13 marks each related to digital logic concepts like gates, flip-flops, multiplexers etc. Part C contains 1 question worth 15 marks to design an asynchronous sequential circuit. The examination tests concepts like binary conversion, logic gate operation, minimization techniques, sequential circuit design and VHDL modeling. Students are asked to answer questions related to logic gates, multiplexers, flip-flops, hazards, PROM/EPROM/EEPROM and behavioral/structural modeling in VHDL

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56 views

Bharath Niketan Engineering College: Hours

This document contains a model examination for the subject Digital Logic Circuits. It has 3 parts - Part A contains 10 multiple choice questions worth 2 marks each. Part B contains 5 questions worth 13 marks each related to digital logic concepts like gates, flip-flops, multiplexers etc. Part C contains 1 question worth 15 marks to design an asynchronous sequential circuit. The examination tests concepts like binary conversion, logic gate operation, minimization techniques, sequential circuit design and VHDL modeling. Students are asked to answer questions related to logic gates, multiplexers, flip-flops, hazards, PROM/EPROM/EEPROM and behavioral/structural modeling in VHDL

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© © All Rights Reserved
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BHARATH NIKETAN ENGINEERING COLLEGE, Aundipatty - 625536.

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

Model Examination

Sub. Code & Name : EE8351 / Digital Logic Circuits Date : -10-2018
Class : II Year / III Sem. Time : 03:00 Hours
Max. Marks : 100 Marks
PART - A (10X02=20)
Answer all the Questions

1) Determine (377)10 in Octal and Hexa-decimal equivalent.


2) Compare the totem-pole output with open –collector output.
3) Write the POS representation of the following SOP function: F(X,Y,Z)=∑m(0,1,3,5,7).
4) Design a half subtractor.
5) Differentiate mealy and moore model.
6) Write the excitation table of JK,SR,T and D flipflop.
7) What is static and dynamic hazard?
8) Define race.
9) Write the VHDL coding for a logical gate which gives high output only when both inputs are
high.
10) Write the VHDL coding for 2 X 1 MUX.
PART – B (5X13=65)
11a) i) With circuit schematic explain the operation of a two input TTL NAND gate with totem
pole output (7)
ii) With circuit schematic explain the operation of ECL gate. (6)
(or)
b) i)Convert (1010111011101100)2 into Octal, decimal, and hexadecimal. (7)
ii) With circuit schematic explain the operation of CMOS. (6)

12a) i)Simplify the function using K-map f(w,x,y,z)=∑m(0,1,3,9,10,12,13,14)+ ∑d(2,5,6,11) (6)


ii) Design full adder and implement in using suitable multiplexer. (7)

(or)
(b) i) Design half and full subtractor and realize using logic gates. (13)

13(a) i) Explain the various of triggering with suitable diagrams. (6)


ii) Explain the realiation of D flipflop from JK flipflop. (7)
(or)
(b) Write the short notes on Shift register. (13)
14) (a) i) Explain about various types of hazards in sequential circuits design and methods to
eliminate them. (08)
ii) Explain the PROM,EPROM,EEPROM. (05)
(or)
(b) ) Design a PAL structure using AND and OR logic for the following functions.
F1= m(0,1,2,3,4,7,8,11,12,15)
F2=m(2,3,6,7,8,9,12,13)
F3=m(1,3,8,11,12,15) . (13)

15 (a) Explain in detail the concept of behavioral, structural modeling in VHDL for full adder. (13)
(or)
(b) Explain in detail the concept of behavioral, structural modeling in VHDL for 8x1 MUX. (13)

PART - C (1X15=15)
16 Design an asynchronous sequential circuit with two inputs X1 and X2 and one output Z.
initially Z=0 both inputs are equal to zero. When X1 or X2 becomes 1 the output Z becomes
1.When second input also one, the output changes to zero. The output say at 0 until the
circuit goes back to the initial state.

Prepared by Verified by

(S.Harini, Asst.Prof/EEE) (R.Maya,HOD/EEE)

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