International Symposnrm on Communications

and Jnformatbn Technobps 2004 ( ISClT 2004 )

Sappum, Japan, October 26- 29,2004

A Design of Four-Quadrant Analog Multiplier

Kobchai Dejhan, Pipat Prommee, Wanlop Tiamvorratat, Somsak Mitatha, Ittipong Chaisayun*
Faculty of Engineering and Research Center for Communicationsand Information Technology
King Mongkut’s Institutc of Technology Ladkrabang, Bangkok 10520, Thailand
Tel: +66-2-326-4238,66-2-326-4242, Fax: 66-2-326-4554
E-mail: {pipat, kobchai}@telecom.kmitl.ac.th
*Faculty of Engineering, South East Asia University, Bangkok 10160, Thailand
Tel: 66-2-807-4500. Far: 6 6 - 2 - 807-4528

Absfmd- This paper proposes a new four quadrants analog

multiplier which consists of P multiplier ceU, a mixed signal
circuit and three signal subtraction circuits Its advantages are :
The multiplier cell is sbo&k Fig. 1

q rc,
.
this design has single ended inputs, the geometry of all
transistors are equal, and its output can be the prduct of hvo
signal voltage, or the product of P signal current and a signal
voltage. Simulation results are demonstrated by PSpice to
confirm the operation of the circuit.

I. INTRODUCTION
A four-quadrant analog multiplier is a key element in the
construction of many signal-processing circuits. It can be
applied in analog filters, frequency doubles, modulators etc. L
- -
In recent years, MOS multipliers based on MOS transistors
and operating in the saturation region [l-31 have been Fig.1 Multiplieroell
proposed. These circuits require a power supply voltage of
several volts, which restricts their application to hgh-voltage The output voltage of the multiplier cell is
systems. Due to the rapid growth of battery operated portable
systems, low-voltage high-performance analog multipliers are v, = 4KRLV*Vb (2)
required. Almost all low-voltage multipliers [4-71 operate on
two power supplies. A few multipliers [E-91 can operate on Consider Fig. 1, the circuit requires the signals V., -Vo, V,-V,,
either a single power supply or two power supplies. In this and Vb+V.. To generate these signals, the signal subtraction
paper, we propose an analog multiplier which can operate on circuits are used.
a low-voltage power supply, and on either a single power
supply or two power supplies. Additionally, we propose a B. Signal subtraction circuit
multiplier unlike other designs of multiplier. The output can The signal subtraction circuit is shown in Fig.2
be either the product of two voltage signals or the product of a
signal current and a signal voltage. Therefore, t h s multiplier
can be applied widely. vm

11. THEORY
All devices have thc same geometry and operate in the
saturation region. The drain current is written as follows;

The proposed multiplier consists of a multiplier cell, a

mixed signal circuit and three signal subtraction circuits. The
operating principle of each of suh-circuit is described as
follows; --+-
Fig.2 Signal rubtraulion circuit
A . Alrrltiplier cell

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 The relationship of the drain currents of &I and Mb is

ID, ‘IDb (3)

Using Eq. (1)
K V O -VDD -VT)’ = K V b -vo -v~) (4)

The output voltage of the signal subtraction circuit is;

v, =vb-v* +v0, (9
While Vb4, the signal subtraction circuit acts as signal
inverter circuit and the output voltage will be rewritten as

C. Mixed signal circuit

The mixed signal circuit is shown in Fig.3. Their inputs
are Vx and IX ,and its output is VI

Substitute Eqs. (9)-(12) into Eqs. (13)-(16), respectively.

The output voltage of the proposed circuit can be rewritten
and expressed as;
-
-

Fig.3 Mixed signal circuit

The relationship of IDS, ILXand Ix can be written as;

v, =4KRL ;E. y

I X ‘ID5 -IDb (7) Eq. (18) can be considered as fallows;

Set I& or there is no input current, the multiplier
Substitute Eq. (I) into Eq. (3,
the expression ofthe output functions as the voltage multiplier.
voltage V, is;
vo = 2KRLv‘yvy (19)

Set V& or Connecting Vx to ground, the multiplier

functions as cunent and voltage multiplier.
D.Completed multiplier
The completed multiplier is shown in Fig.4. -4KRLvy I ‘y
The voltages of various nodes of the proposed multiplier
v, =
A1
can express as follows;
E. Inpul range
The input range of the multiplier is restricted by the
saturation condition of MI-M4, M8 and MI 1. Therefore, the
input range can be derived as;

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 Vw and the VTp are threshold voltage of NMOS and
PMOS, respectively. Eq. (21) indicates that the less the Vm
and the VS, the wider the input range, Eqs. (22) and (23)
suggest that the lowest supply voltage V Das~ maximum input
-wTP Fig. 5 DC transfer charactenstios
range is VDD = - .
2

111. RESULTS
Simulation results of the circuit are carried out by using
PSpice simulation program. The transistor model based on 0.5
gm, Vm = 0.67 V, VTp= -0.93 V and the dimension of all
transistors are W=I pm and L=2 pm. The simulation
conditions are; a single power supply, for VoD= 2.5 volts, the
current source IS = 10 pA and load resistance RL are 10kR.
Fig. 5 shows dc transfer characteristics when VX, Vy and IX
arevaned. Fig. 6 shows frequency response which also shows
that cutoff frequency of Vy is 173 MHz and of Vx is 47 m.
The total harmonic distortion (THD) of VXand Vy are 0.69 %
and 0.68 % respectively, whereas Vx is 200mVsin2000nt, Ix
is zero, and VU is 200 mV. Fig. 7 shows the amplitude
modulation where V, is 200mVsin20krrt, IX is zero and Vy is

Fig. 6 Freqvency response

Fig. 7 Amplitude modulation whpn V, is ZOomVsin600!m, In is zcm, and Vx

is ZoOmVsinZokm

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 IV. Conclusions
A new four quadrant analog multiplier is described. Its
advantages are; this design has single ended inputs, the
geometry of all transistors are equal, and its output can be the
product of two signal voltage, or the product of a signal
current and a signal voltage. Simulation results show that the
circuit can operate with a 2.5 V single power supply, the -
3dB bandwidth is 4 7 M b for Vx and 173MHz for Vy and the
THD of the circuit is lower than 1%. This circuit is expected
to be useful for low voltage signal processing application.

REFERENCE
[I] J. S. Pew-Find, J. A. Connelly, “A MOS four-quadrant analog
multiplier using the quarter-square technique,” IEEE J Solid-
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quadrant multiplier using pool circuits,” IEEE J Solid-Slate
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[3] S:I. Liu, C:C. Chang “CMOS four-quadrant multiplier using
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