Int. J. Electron. Commun.

(AEÜ) 98 (2019) 8–18

Contents lists available at ScienceDirect

International Journal of Electronics and

Communications (AEÜ)
journal homepage: www.elsevier.com/locate/aeue

Regular paper

An ultra-low power, low voltage DC-DC converter circuit for energy

harvesting applications
Elham Kordetoodeshki, Alireza Hassanzadeh ⇑
EE Department, Shahid Beheshti University, Tehran, Iran

a r t i c l e i n f o a b s t r a c t

Article history: In this paper a compact, fully-integrated voltage multiplier with a low start-up voltage is presented for
Received 24 April 2018 energy harvesting applications. Two voltage doublers are cascaded with the overall conversion ratio of
Accepted 20 October 2018 2 and 4. The voltage multiplier has a 2-phase clock signal with a wide range of operating frequency from
1 kHz to 1 MHz. Cascading and positive feedback with cross-coupled gates have been used to increase the
efficiency and conversion ratio of the converter. The DC-DC converter has an efficiency of more than 70%
Keywords: when operating from a 0.34 V input voltage and generating 1.28 V output voltage. The proposed voltage
DC-DC converter
multiplier has a power consumption of 36 nW to 1.24 lW for input voltage range of 280–450 mV in
Boost converter
Energy harvesting
0.18 lm CMOS technology.
Thermoelectric generator (TEG) Ó 2018 Elsevier GmbH. All rights reserved.
Nested connection
Body effect

1. Introduction integrated on-chip by removing circuit inductors [5–7]. On-chip

devices have better performance and less noise than those outside
With recent progress in technology, demand for wired devices the chip.
and small-scale wireless systems and internet of things (IoT) have Fully integrated switched capacitor converters have been
increased dramatically. On the other hand, due to the reduction of reported with different control forms in previous publications.
resources with fossil fuels and rising energy costs, the need for Charge pumps have been widely used in DC-DC converting circuits
high-end batteries and sustainable energies such as hydroelectric, and power management systems. In [8], a new design of SRAM is
fuel cells, photovoltaic (PV), piezoelectric and thermoelectric is presented that integrates charge pump circuits to harvest and
much higher than before [1]. The main problem in using sustain- reuse bit-line charge to reduce power consumption. In [9], a volt-
able resources is the low voltage level generation, which is an age tripler is achieved by connecting a series of Charging Pumps
obstacle to the usage of these devices. Hence, in the recent years, (CP) with a relatively high power dissipation and input voltage
a great effort has been done on the design of efficient DC-DC con- range of 0.45–0.7 V. In [10], the voltage doubler is used as a nega-
verters, which are able to convert very small input voltages to the tive charge pump to reduce on-resistor of PMOS load switch. The
high output voltage with high efficiency and low power consump- maximum efficiency of this circuit is 52%. In [11], an integrated
tion. There are many reports for DC-DC converters. Self-biased switched capacitor converter is presented, which consists of a volt-
switching regulator has been used for efficient DC-DC converter age doubler. In this circuit different clocks are used that do not
despite cost and complexity. Wesley et al. presented a small model require additional circuits with the efficiency of 37.4% and output
of DC-DC convertor, which employs the three-state switching cell power of 0.45 mW. In [6], an on-chip charge pump with parallel
(3SSC) operating in continuous conduction mode (CCM) [2]. Some connection has been used to boost the harvested voltage. The
efforts have been done to eliminate external inductor switching power consumption of the circuit is 2.58 mW.
[3]. Due to the high resistance of the series inductor, the losses In this paper, a fully integrated switched-capacitor energy har-
in the inductor switching are high and needs costly construction vester voltage doubler has been presented for Thermo-Electric
process such as thick metals or integrating ferrite core inductors Generator (TEG) applications in wearable and implantable sys-
on-chip [4]. Therefore, capacitive DC-DC converters have attracted tems. The converter consists of a cascaded self-oscillating clock
industry and academia attention, which can be completely generator. To reduce power consumption and increase the output
voltage and efficiency of the circuit, different techniques have been
⇑ Corresponding author. used including nested connections, transistor body biasing and adi-
E-mail address: [email protected] (A. Hassanzadeh). abatic technique.

https://doi.org/10.1016/j.aeue.2018.10.029
1434-8411/Ó 2018 Elsevier GmbH. All rights reserved.
 E. Kordetoodeshki, A. Hassanzadeh / Int. J. Electron. Commun. (AEÜ) 98 (2019) 8–18 9

This paper has been arranged as follows. Section 2 presents an in the previous step (clk1 = 1 and clk2 = 0). Hence, Vout is charged
overview of DC-DC converter and adiabatic technique. Section 3 to 2Vs through Mp1.
describes the architecture of the proposed circuit. In Section 4 ther-
mal effects on the performance of the proposed circuit are 2) When clk1 = 1 and clk2 = 0:
described. Section 5 is the simulation results and discussions. Con-
cluding remarks are at the end. M2 and Mp1 are turned off. M1 and Mp2 are turned on. Cu1 is
charged to Vs through M1, so Vt1 = Vs. Vt2 is the sum of the output
of the right inverter Vs and voltage of Cu2 that was charged to Vs in
2. Prior art overview the previous step. Hence, Vout is charged to 2Vs through Mp2.
Fig. 3 shows a voltage tripler nesting two voltage doubler
Three basic structures are described in this section. The first switch fs = 150 kHz, Vout/Vin = 2.6.
structure is a DC-DC converter. Then, the operation of the voltage
doubler circuit will be explained. Finally, to minimize power con-
2.3. Adiabatic technique
sumption of the circuit, the adiabatic technique is described.

The adiabatic technique provides a way to reduce the power

2.1. Basic structure of a DC-DC boost converter consumption in the capacitive nodes of the MOSFET inverter cir-
cuit. In a CMOS inverter, when an input transition from 1 to 0
As shown in Fig. 1, a fully integrated capacitive DC-DC boost occurs, energy is transferred from the supply voltage to charge
converter usually consists of three sections: the clock generator, the output capacitor C to the supply voltage V s . The total output
clock buffer and charge pump circuit. The clock generator gener- energy is:
ates the required clock and timing of the voltage multiplier circuit
from the low DC input voltage. Clock buffers are needed between EV s ¼ CV s 2 ð1Þ
clock generator and switched capacitor circuit to provide higher The energy dissipated across the PMOS transistor during charg-
drive, isolation, and generate an ideal square wave. The charge ing is [14]:
pump with switched capacitor structure converts low DC input
voltage to high DC output voltage. The charge pumps are different EC ¼ 1=2CV s 2 ð2Þ
types and can include multi-step or multi-phase structures. In this
Charging a capacitor using a current source is the most efficient
paper, a voltage multiplier circuit with 2-phase clock is used. All
way to charge it. This can be achieved by charging the capacitor
three sections in the integrated circuit are supplied by the TEG
from a time-varying supply voltage simulating a constant current
energy harvester used in biomedical applications.
source as shown in Fig. 4. When charging from a constant current
source, the energy dissipation will be as follow:
2.2. The charge pump
Ron  C
EC ¼ ð Þ  C  V s2 ð3Þ
A circuit schematic of a one-stage voltage doubler is shown in T
Fig. 2. Vck1 and Vck2 are complements. Operation of the circuit Ron is the equivalent ON resistance of the PMOS transistor and T
can be defined in two steps: is the time for charging capacitor from 0 to V s . When the capacitor
is charged with a slow ramp voltage source during a very long time
1) When clk1 = 0 and clk2 = 1: period, the energy dissipated according to Eq. (3) is diminished.
Even though this can only be achieved with slow switching
M1 and Mp2 are turned off. M2 and Mp1 are turned on. Cu2 is speed, but the reduction of power loss P Ron in on-resistance of the
charged to Vs through M2 so Vt2 = Vs. Vt1 is the sum of the output PMOS transistor in Eq. (4) is significant. Due to the inverse relation
of the left inverter Vs and voltage of Cu1 that was charged to Vs of power to the square of time, the power loss is tangible.

CLK Charg Pump

Pump
CLK Vout
Clock generator
C
Energy Clock
Harvesting /CLK Buffer /CLK
CL

IC

Fig. 1. Structure of an integrated DC-DC converter.

10 E. Kordetoodeshki, A. Hassanzadeh / Int. J. Electron. Commun. (AEÜ) 98 (2019) 8–18

T
Vs Vs
Vck1
GND

M1 M2 Vs
WS WS Vck2
GND
Vt1 Vt2 2Vs
Cu2 Vt1
Cu1 Vs
GND

WP Mp1 Mp2 2Vs

WP
Vck1 Vck1 Vck2 Vck2 Vt2 Vs
GND
Wn Vout=2Vs Wn
Vout=2Vs
CL RL 2X boosng
GND

Fig. 2. The voltage doubler circuit [12].

Vs
Vs Vs Vs ø Vt
ø
0 in
in
2Vs
Cu Cu
Vin out
Vth,p out
C
Vck1 Vck2
Vout=3Vs

Fig. 4. Schematic of a CMOS inverter with a time varying supply voltage.

Vs Vs
Cu Cu been performed using 180 nm TSMC technology parameters and
HSPICE simulation environment. Clk1 and clk2 have 180° phase
Vck1
difference and have been generated using a simple inverter from
Vck2
Vck1 Vck2 the original clock. The proposed circuit structure is shown in
Fig. 5. The first circuit output is applied to the second circuit input.
Vout=3Vs
As shown in Fig. 5, sources of transistors Ms3 and Ms4 are con-
CL RL nected to the output of the voltage doubler circuit. Sources of tran-
sistors Mp3 and Mp4 are connected to Vcpo, gates of transistors Mp3
and Mn3 are connected to Vt1 and gates of transistors Mp4 and Mn4
are connected to Vt2 . In this situation, the pulse amplitude of Vt1
and Vt2 are two times the pulses of clk1 and clk2. Cu3 and Cu4 are
Fig. 3. Generic structure of the nested voltage tripler built with two voltage charged through driver transistors Mn3 ; Mp3 and Mn4 ; Mp4 . Circuit
doublers [13]. behavior is investigated in two cases:

ðCVÞ2 1) When clk1 = 0 and clk2 = 1:

PRon ¼ Ron I2 ¼ Ron ð4Þ
t2
Cu is charged through driver transistors Mn1,Mp1 and Vt1 reaches
2Vs . Therefore, Ms2 is turned on and raises Vt2 to Vs by charging Cu
3. The proposed capacitive voltage multiplier and Mp5 that allows the voltage to reach 2Vs. Then driver transis-
tors Mp4 and Mn4 charge Cu3 and raise Vt4 to 4Vs. Next transistor
In this paper in order to increase the voltage level, two voltage Mp8 allows conducting voltage to reach 4Vs.
doublers are cascaded. The only modification from Fig. 2 is that
drain and source terminals of transistors Ms1-4 and Mp5-8 are 2) When clk1 ¼ 1 and clk2 ¼ 0:
switched. The reason is that Vs toward Vout is increasing so drain
of NMOS transistors is connected to higher voltage and source of Cu is charged through driver transistors Mn2, Mp2 and Vt2
PMOS transistors is connected to lower voltage. Simulations have reaches 2Vs. Therefore, Ms1 is turned on and Vt2 reaches 2Vs by
 E. Kordetoodeshki, A. Hassanzadeh / Int. J. Electron. Commun. (AEÜ) 98 (2019) 8–18 11

Vs and consumes smaller power. However, high gain increases non-

linearly and instability issues.
Ms1 The circuit of Fig. 5 is primary charge pump and the circuit of
Ms2 Mp2
Mp1 Fig. 6 is nested charge pump circuit. Voltage gain variation versus
Cu2 input voltage is shown in Fig. 7(a). The maximum output voltage of
Cu1
clk1 clk2 the primary circuit is 2.3 times of input voltage at Vin = 0.43 V. In
Vt1 Vt2 the nested connection circuit, the maximum output voltage has
Mp5 Vck1 Vck2 Mp6 increased 3.8 times input voltage with Vin = 0.43 V.
Mn1 Power consumption according to Fig. 7(b) results, has been
Mn2
Vcpo optimized.
The total output impedance Rout is equal to [15]:
Mp3 Ms3 Ms4 Mp4 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Rout ¼ R2SSL þ R2FSL ð5Þ
Cu3 Cu4
Vt1 Vt2 where RSSL is Slow Switching Limit of the output impedance and RFSL
Vt3 Vt4 is the Fast Switching Limit of the output impedance [15].
Mp7 clk1 clk2 Mp8 In Eq. (6), c quantifies the difference between the actual and
Mn3 Mn4 ideal output voltage. The Ideal Voltage Conversion Ratio IVCR of
Vout the input voltage and output voltage equals N of the topology used.
V out
CL RL c¼ ð6Þ
NV in
The power loss due to the finite output impedance is defined in
Eq. (7). By using a nested connection, c increases, so power loss
decreases [15].
Fig. 5. The proposed capacitive voltage multiplier circuit.
ðNV in  cNV in Þ2
PLoss ¼ ð7Þ
Rout
charging Cu and Mp6 that allows conducting voltage to reach 2Vs. As shown in Fig. 7(c), maximum power consumption decrease
Then driver transistors Mp3 and Mn3 charge Cu3 and raise Vt3 to at Vin = 0.43 V is 48%. In Fig. 7(d), an efficiency of 65% has been
4Vs. Next transistor Ms4 is turned on and Mp8 allows conducting achieved at Vin = 0.33 V by using a nested connection. PLoad is load
voltage to reach 4Vs. resistance power dissipation in Eq. (8) that has been increased
The range of input voltage that can be applied to the circuit is because of output voltage V out increase. Hence, efficiency g in Eq.
between 280 and 500 mV. The frequency is considered to be (9) increases.
50 kHz. In order to optimize the gain, power loss and efficiency,
V 2out
some alterations have been done. These changes include the use PLoad ¼ ð8Þ
RLoad
of nested connections, the use of body effects and the adiabatic
technique that are explained in the next section. Transistor sizes
PLoad
used in the design are listed in Table 1. g¼ ð9Þ
PLoad þ PLoss
Since the nested connection circuit has been optimized for
3.1. The effects of nested connection on the proposed circuit power, gain, and efficiency, the circuit has been considered for fur-
ther improvements in the next section.
The first change we are considering is a nested connection. In
this way gates of transistors Mp7 and Mp8 in Fig. 5 are connected 3.2. Switching transistor body effect
to Vt4 and Vt3 respectively, as shown in Fig. 6. By doing these con-
nections, the circuit of Fig. 6 is built, which is a flip-flop configura- The second change we are considering is the connection of the
tion. It has two stable modes: 1)Q ¼ 0; Q 0 ¼ 1. 2)Q ¼ 1; Q 0 ¼ 0. transistor body to the ground (Fig. 8).
This circuit has two features: a gain larger than one and positive By connecting switching transistors body to the ground, accord-
feedback. The circuit has two inverters, which are connected cross- ing to Eq. (10) due to increase in V sb , threshold voltage V th
wise. By using 4 transistors Mp3, Mn3, Mp4 and Mn4, the flip-flop increases. Where V th is the threshold voltage when substrate bias
state can be changed. The FF circuit is sensitive to the positive level is present and V th0 is threshold voltage without body bias. V sb is
of the clock. When Vt4 and Vt2 are high, the combination of Ms4 and the source-to-body bias voltage,c is the body effect parameter
Mp4 transistors make an inverter. To change the output state, the and /f is the surface potential in Eq. (10). Drain-source current
value of Vt4 should be reduced to a lower extent than the Ms4- IDS is proportional to the square of overdrive voltage and decreases
Mp8 threshold voltage. When this happens, positive feedback will as threshold voltage increases as shown in Eq. (11).
change the flip-flop state. To achieve this, the size of the transistors qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffi
   
Mn3, Mp3, mn4, and mp4 should be enlarged. Therefore, the output V th ¼ V th0 þ c 2/f  þ V sb  2Uf  ð10Þ
voltage increases with positive feedback and circuit will be faster

Table 1
DC-DC converter transistor sizes.

Tr. sizes Mp1 = Mp2 Mn1 = Mn2 Ms1 = Ms2 Mp5 = Mp6 Mp3 = Mp4 Mn3 = Mn4 Ms3 = Ms4 Mp7 = Mp8
W/L (mm) 100/0.18 5/0.18 50/0.18 1/0.18 50/0.18 0.54/0.18 20/0.18 1/0.18
12 E. Kordetoodeshki, A. Hassanzadeh / Int. J. Electron. Commun. (AEÜ) 98 (2019) 8–18

Vs

Ms1 Ms2 Mp2

Mp1
Cu1 Cu2
clk1 clk2
Vt1 Vt2
Mp5 Vck1 Vck2 Mp6
Mn1
Mn2

Mp3 Ms3 Ms4 Mp4

Q
Cu3 Cu4
Vt1 Vt2
Vt3 Vt4
Mp7
p7 Mp8
Mp Q’
Mn3 Mn4

Vout CL RL

Fig. 6. The proposed capacitive voltage multiplier circuit using nested connection.

Fig. 7. Comparison of two circuits: proposed primary circuit and nested connection (a) Output voltage to input voltage ratio versus input voltage, (b) power consumption
versus input voltage, (c) percentage of power decrease by using nested connection in comparison to primary circuit versus input voltage, (d) efficiency versus input voltage.

IDS / ðV gs  V th Þ2 ð11Þ V th increase. The ratio of IDS reduction to the Ron increase is much
higher, hence, transistor overall power consumption P Ron decreases.
The on-resistance of transistor Ron is:
PRon ¼ Ron I2DS ð13Þ
1
Ron ¼   ð12Þ According to Eq. (14), when V th increases, leakage current Ileakage
kn ðw=lÞ v gs  v thn decreases and so the leakage power. Where x is a fairly constant
value.
kn is the device transconductance coefficient, w and l are the switch Ileakage / ðW=LÞexpðxV th Þ ð14Þ
sizes and v gs is the switch gate-source voltage. Ron increases due to
 E. Kordetoodeshki, A. Hassanzadeh / Int. J. Electron. Commun. (AEÜ) 98 (2019) 8–18 13

Vs and output voltage declines a bit. Since power and efficiency have
been optimized, output voltage drop is negligible as shown in
Fig. 9(a).
Ms1 Ms2 Mp2
Mp1 Relation between leakage power and delay versus threshold
Cu2 voltage variations are contrary.
Cu1
clk1 clk2  2
Vt1 Vt2 V th
delay ¼ kn :cL =V s 1  ð17Þ
Mp5 Vck1 Vck2 Mp6 Vs
Mn1
Mn2 Fig. 9(b) shows that the efficiency of the body biased circuit has
increased by 8% at Vin = 0.33 V. Fig. 9(c) compares power loss of cir-
cuit with body effect and without body effect. As shown in Fig. 9(d)
Mp3 Ms3 Ms4 Mp4 maximum power decrease with body bias is 23%.
Therefore, this circuit with body effect has been used for better
Cu3 Cu4
efficiency.
Vt1 Vt2
Vt3 Vt4 The body bias technique implementation on the chip requires
Mp7 Mp8 separate body of NMOS transistors by using triple well or SOI
Mn3 Mn4 technology.

3.3. Capacitive voltage multiplier using adiabatic technique

Vout CL RL
In order to apply the adiabatic technique to the circuit, the
power supply of the converter is a pulse with long rise time and fall
times. Rise and fall times of clk3 and clk4 are designed considering
maximum output voltage as shown in Fig. 10.
Fig. 8. Circuit with body bias technique.
The circuit of Fig. 8 has been used with a clocked power to
decrease power consumption and increase efficiency. Sources of
When threshold voltage increases the short circuit current as transistors Mp1 and Mp2 in Fig. 8, are connected to clk3 and clk4
well as short circuit power decrease as shown in Eqs. (15) and (16). instead of Vs and the source of transistors Mp3 and Mp4 is con-
nected to Vt2 and Vt1, as shown in Fig. 10(a). Power dissipation of
1 the circuit decreases, because of lower switch dissipation when
Isc ¼ kn :sðV s  2V th Þ3 :f ð15Þ
12:V s using the adiabatic technique. Rise and fall times of clk3 and clk4
are designed as shown in Fig. 10(b).
Psc ¼ Isc :V s ¼ ð1=12Þkn :sðV s  2V th Þ3 :f ð16Þ Rise and fall times have been adjusted for the best performance.
The adiabatic technique is based on the efficient charging of capac-
where f is the frequency of the clock and s is the rise time and fall itors in the circuit in a way that power dissipation in the series
time. However, delay of the circuit according to Eq. (17) increases, switches for charging capacitors is minimized. Instead of applying

Fig. 9. Comparison of circuit performance with and without body effect (a) output voltage to input voltage ratio versus input voltage (b) efficiency versus input voltage (c)
power consumption versus input voltage (d) percentage of power decrease using body effect.
14 E. Kordetoodeshki, A. Hassanzadeh / Int. J. Electron. Commun. (AEÜ) 98 (2019) 8–18

Vs
clk3 clk4
Ms1 Ms2 Mp2
Mp1
Cu1 Cu2
clk1 clk2
Vt1 Vt2
Mp5 Vck1 Vck2 Mp6
Mn1
Mn2
Vt2 Vt1
Mp3 Ms3 Ms4 Mp4

Cu3 Cu4
Vt1 Vt2
Vt3 Vt4
Mp7 Mp8
Mn3 Mn4

Vout CL RL

(a)

(b)
Fig. 10. (a) The proposed circuit using adiabatic technique (b) pulse with rise
time = fall time = 10 ns and f = 50 kHz.

fast input pulses, pulses with longer rise time and fall times have
been used. This lowers power dissipation in the connecting transis-
tor switches. Long rise and fall times emulate constant current
charging of capacitors, which is the most efficient way of charging
capacitors. However, for the DC-DC converter, very long charging
time is not acceptable. Fig. 11. (a) Output voltage versus rise time and fall time (b) power consumption
In order to investigate the effects of clock rise and fall times on versus rise time and fall time (c) efficiency versus rise time and fall time.
circuit performance, power dissipation, efficiency, and output volt-
age of the DC-DC converter have been simulated versus clock rise 4. Temperature effects
and fall times. As shown in Fig. 11, these parameters are in the
acceptable range when the rise and fall times are less than 50 ns. In this section temperature variation effect on the output volt-
These parameters are vital for the correct operation of the DC-DC age, power consumption and efficiency have been investigated.
converter. Therefore, clock rise and fall times have been adjusted The range of temperature change is from 10 °C to 80 °C, even
by using some delay of buffers to be in the proper range of opera- though for implantable applications, the range can be more
tion. In general, charging time should be more than twice the time limited.
constant of the capacitor being charged.
In Fig. 12, voltage gain, power consumption, and efficiency of
4.1. Temperature effects on delay and output voltage
the proposed circuit with adiabatic and without adiabatic tech-
nique are shown. As it can be seen in Fig. 12(a) and (b) the pro-
The current in a MOS transistor is a function of temperature T,
posed circuit without adiabatic and circuit with adiabatic have
which is defined as follows:
approximately similar output voltage and efficiency.
 b
Fig. 12(c) shows the reduction of power consumption using the Ion ðT Þ ¼ lðT Þ V gs  V th ðT Þ If V gs > V th ð18Þ
adiabatic technique in the proposed circuit. Using adiabatic tech-
nique in the circuit leads to power consumption reduction up to where V gs the gate-source voltage, b is the velocity saturation effect
14.3% at Vin = 0.28 V. The circuit in Fig. 10 uses all the above- factor and m is mobility of the transistor [16].
mentioned techniques for higher output voltage, efficiency, and Mobility m and Vth are temperature dependent. By increasing
power consumption. temperature, the threshold voltage decreases while m changes
 E. Kordetoodeshki, A. Hassanzadeh / Int. J. Electron. Commun. (AEÜ) 98 (2019) 8–18 15

Fig. 12. Comparison of circuits with and without adiabatic, (a) Output voltage to input voltage ratio versus input voltage, (b) efficiency versus input voltage, (c) Reduction of
power consumption using adiabatic technique in the proposed circuit.

slightly, so Ion increases. According to Eq. (17), delay decreases by In Fig. 14(a) for the proposed circuit maximum efficiency hap-
reducing V th . As temperature rises, both m and Vth decrease, but the pens at room temperature and decreases for higher and lower tem-
effects of Vth reduction is more than m. peratures. However, the efficiency of the primary circuit decreases
Fig. 13(a) shows the Vout/Vin versus temperature for the primary monotonically by increasing temperature. Fig. 14(b) shows the
circuit and the final circuit. Vout/Vin increase versus temperature percentage of the final circuit efficiency increase to primary circuit
for the final circuit is higher than the primary circuit. Therefore, versus temperature. This shows a higher value for mid-range tem-
it is advantageous to achieve high output voltage at a higher tem- peratures. In Fig. 14(c), the power consumption of primary circuit
perature of the chip. Fig. 13(b) shows the percentage of the final and final circuit are compared. In Fig. 14(d) percentage of power
circuit gain increase to the primary circuit versus temperature. In dissipation decrease for the final circuit and the primary circuit
Fig. 13(c) the output voltage is increased at higher temperatures. has been shown versus temperature, which increases as tempera-
Furthermore, the circuit delay is lower at higher temperatures, ture increases. In higher temperatures, the effect is higher. There-
because of higher circuit current. fore, the final circuit will operate at much lower power
consumption compared to the primary circuit at high tempera-
4.2. Temperature effects on power and efficiency tures. With the modifications in the primary circuit, the sensitivity
of the circuit decreases with temperature. The final circuit is better
Two major leakage sources in static power model are consid- than the primary circuit with respect to temperature change.
ered. One is subthreshold leakage and other is gate leakage. The
die temperature T die is an important factor in the static power con- 5. Simulation results
sumption, which can be expressed as follows:
 !
C 2 V s þC 3 The energy harvesting DC-DC converter circuit has been
Pstatic ðT die Þ ¼ V s C 1 T 2die e T die
þ C4e ðC 5 V s þC 6 Þ
ð19Þ designed in a standard 0.18-lm CMOS process. In this section,
the improvement of the proposed circuit is investigated using
nested connection and body effect besides adiabatic technique.
C 1 to C 6 are technology constants [17].
The percentage improvement in the circuit is obtained in terms
Eq. (19) can be written in the linear form:
of the output voltage, power consumption, and efficiency. As it
dPstatic ðT ref Þ can be seen in Fig. 15(a) by using the three methods, the output
Pstatic ðT die Þ  P static ðT ref Þ þ ðT die  T ref Þ ð20Þ
dT die voltage is increased by 39.2% at 0.45 V input voltage. Furthermore,
the efficiency in Fig. 15(b) is increased to 53% at the input voltage
where T ref is reference temperature [17].
of 0.35 V. Power consumption in Fig. 15(c) is reduced to a maxi-
According to Eq. (20) by increasing temperature, the power con-
mum of 62% at the input voltage of 0.4 V with respect to the pri-
sumption increases. Temperature effect on efficiency is shown Eq.
mary circuit. The frequency range that can be used in this circuit
(21).
is between 2 kHz and 1 MHz. Power consumption for the primary
 
g ¼ gref  l T c  T ref ð21Þ circuit is in the range of 50 nW to 3 mW and 36 nW to 1.24 mW in
the proposed circuit.
where l is the overall chip temperature coefficient, T ref = 25 °C, gref Table 2, summarizes the voltage multiplier performance and
is efficiency at T ref and T c is current temperature [18]. compares it to prior related works. The lowest power consumption
16 E. Kordetoodeshki, A. Hassanzadeh / Int. J. Electron. Commun. (AEÜ) 98 (2019) 8–18

Fig. 13. The effect of temperature on output voltage for Vin = 0.34 V, (a) Vout/Vin versus temperature for the primary and the final circuit (b) final circuit gain increase to
primary circuit versus temperature (c) Vout at different temperatures versus time for the final circuit.

Fig. 14. The effect of temperature on primary circuit and final circuit for Vin = 0.34 V, (a) efficiency variation with temperature, (b) efficiency percentage increase for primary
circuit and final circuit versus temperature, (c) power consumption at different temperatures, (d) power consumption percentage decrease for primary circuit and final circuit
versus temperature.
 E. Kordetoodeshki, A. Hassanzadeh / Int. J. Electron. Commun. (AEÜ) 98 (2019) 8–18 17

Fig. 15. Circuit performance simulation results using nested connection, body effect and adiabatic technique, (a) percentage of Vout increase versus Vin, (b) percentage of
efficiency increase versus Vin, (c) percentage of power decrease versus Vin.

Table 2
Performance summary and comparison of the proposed circuit.

Ref. # [6] [9] [11] [12] [19] [20] [21] This work
Technology 180 nm 180 nm 180 nm 180 nm 180 nm 180 nm 180 nm 180 nm
Vin (V) Min Vin = 0.25 0.45–0.7 0.22 1–1.5 0.3–1.5 0.14–0.5 1–1.8 0.28–0.5
Fully integrated Yes Yes Yes Yes Yes Yes Yes Yes
*
Vo =Vin 4 2.6 8.6 2.6 2.63 N/R 2 3.77 @ VIN= 0.43 V
*
Max efficiency (%) 67@ VIN = 0.31 V 75@ VIN = 0.45 V 37.4 N/R 36@ VIN = 0.32 V 50@ VIN = 0.45 V 52 72.5 @ VIN= 0.34 V
* * *
Power consumption (W) 2.58 m N/R 4.7 m 0–29 m 29–380 m N/R N/R 36 n–1.24m
* * *
Output power range (W) 1.65 m 72 m–192 m 10.45 m N/R N/R 5 n–5 m N/R 8n-280n
/>40% efficiency />25% efficiency
Frequency (Hz) 800 k 90 k–1.4 M 3.3 M @ VIN = 0.22 V 150 k 50 K 70–19 M 5 M–60 M 1 K–1 M
*
N/R: Not reported.

has been achieved in the proposed circuit, which is in the range of The TEG harvester chip will be integrated into an actual wireless
36 nW to 1.24 lW. Efficiency is 72.5% at Vin = 0.34 V and body sensor node. Longer sensor node lifetime can be obtained
the desired output to input voltage ratio at Vin = 0.43 V is using TEG energy harvester circuit. Because of the limited temper-
Vout/Vin = 3.77. ature range of the TEG for a body area network application, circuit
performance will be more accurate.
6. Conclusion

This paper presents an ultra-low power, fully integrated DC-DC References

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