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Under The Esteemed Guidance Of: Design of A Novel Energy Efficient Hybrid Adder

The document describes the design of a novel hybrid adder circuit that aims to improve energy efficiency. It combines low-cost ripple carry and carry lookahead circuits. In the hybrid adder, addition considers carry propagating both forward from LSB and backward from MSB. This design accelerates addition compared to other adder architectures. Simulation results show the hybrid adder has lower power, area, and delay compared to traditional ripple carry and carry lookahead adders, especially at high clock frequencies, making it more energy efficient.

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35 views

Under The Esteemed Guidance Of: Design of A Novel Energy Efficient Hybrid Adder

The document describes the design of a novel hybrid adder circuit that aims to improve energy efficiency. It combines low-cost ripple carry and carry lookahead circuits. In the hybrid adder, addition considers carry propagating both forward from LSB and backward from MSB. This design accelerates addition compared to other adder architectures. Simulation results show the hybrid adder has lower power, area, and delay compared to traditional ripple carry and carry lookahead adders, especially at high clock frequencies, making it more energy efficient.

Uploaded by

Dlisha
Copyright
© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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DESIGN OF A NOVEL ENERGY EFFICIENT

HYBRID ADDER
Under the Esteemed Guidance of
Dr.S.GOVINDARAJULU,
Professor, Dept. Of ECE,
RGMCET.
Submitted by
Y. Krishna Kalpana (11091A0455)
A. Guru Sai Prasanth (12095A0405)
G. Greeshma (11091A0436)
M. Harinath Reddy (11091A0438)
B. Anjan Kumar (11091A0406)
Introduction:
• An energy efficient adder is designed based on a hybrid carry
computation.
• In this design, addition takes place by considering the carry as
propagating forwards from LSB and backwards from MSB.
• The incidence at a midpoint significantly accelerates the
addition.
• This acceleration together with combining low cost ripple carry
and carry chain circuits, yields energy efficiency compared to
other adder architectures.
• The adder is enhanced in a tree-like structure for further
acceleration.
Block Diagram

Fig: The architecture of a complete n-bit hybrid adder.


Fig: A ripple carry adder (LSB’s) Fig: Carry look ahead adder (MSB’s)
Ripple Carry Adder :
The ripple carry adder is constructed by
cascading full adder blocks in series
The carryout of one stage is fed directly to the
carry-in of the next stage
For an n-bit ripple adder, it requires n full
adders
DSCH of RCA(4 Bit) in Static Mode
RCA (8 BIT)
RCA(16 Bit)
Carry Look Ahead Adder

• A carry-look ahead adder improves speed by


reducing the amount of time required to determine
carry bits.
• The carry-look ahead adder calculates one or more
carry bits before the sum, which reduces the wait
time to calculate the result of the larger value bits.
Sum & Carry Generation :
• Propagate P and Generate G in a CLA is given by,
Pi=Ai Bi Ai
Pi
Gi=Ai Bi Bi
Gi

• The new expressions for the output sum and the


carryout is given by,
Si = Pi Ci-1 Pi Si
Ci-1 Ci+1
Ci+1 = Gi +Pi Ci Ci+1
Gi
Advantage of carry look ahead adder

• Like ripple carry adder we need not to wait for


the propagation of carries to get the sum.
• That means it speed up the carry generation.
DSCH of Carry look ahead adder
CLA(8 Bit)
CLA (16 Bit)
HYBRID ADDER

• This is the combination of low-cost ripple


–carry and carry-chain (carry look ahead)
circuits, yields energy efficient compared
to existing adders.
8 BIT
16 BIT
HYBRID ADDER POWER
COMPARISON
ADDER Bits DELAY AREA POWER PDP
(ns) (Ws)
RCA 8 2.276 4297920 8.135uW 18.51x
BIT (Lambda2) 10-15
5264.95 (um2 )
RCA 16 2.94 4868976 30.75uW 90.405
BIT (Lambda2) x10-15
5964.49 (um2 )
CLA 8 2.118 3581212 6.507uW 13.781
BIT (Lambda2) x10-15
4386.98 (um2 )
CLA 16 2.361 6571752 21.96uW 51.84x
BIT (Lambda2) 10-15
8050.39 (um2 )
HYBRID 8 2.13 4389480 8.212uW 17.491
ADDER BIT (Lambda2) x10-15
537.113(um2 )
HYBRID 16 2.514 4389480 13.24uW 33.28x
ADDER BIT (Lambda2) 10-15
5377.13(um2 )
DYNAMIC
RCA(8 BIT)
RCA (16 BIT)
CLA (8 BIT)
CLA (16 BIT)
DYNAMIC HYBRID ADDER (8 BIT)
DYNAMIC HYBRID ADDER (16 BIT)
COMPARISON
ADDER BITS DELAY AREA POWER(mW) PDP (Ws)
(ns)
RCA 8 BITS 1.282 4033080(Lambda2) 1.98 2.53x10-12
4940.5234 (um)2

RCA 16BITS 2.111 5192748(Lambda2) 5.093 10.75x10-12


6361.1163 (um)2

CLA 8 BITS 6.497 3792201(Lambda2) 0.352 2.286x10-12


4645.44 (um)2
CLA 16BITS 21.47 7626895(Lambda2) 0.702 15.07x10-12
9342.94 (um)2
HYBRID ADDER 8 BITS 4.857 4407191(Lambda2) 0.352 1.709x10-12
5398.2280 (um)2

HYBRID ADDER 16BITS 13.185 8211225(Lambda2) 1.043 14.37x10-12


10058.75 (um)2
Differences:
• General arithmetic circuits will consume
power and energy.
• The hybrid adder can provide high energy
efficiency compared with design compiler,
different adders at high clock frequencies.
• Smaller area and power is achieved by using
this hybrid architecture.
Advantages:
• Reduces time delay.
• Has low energy and power consumption.
• Smaller area can be achieved.
• Addition can be made faster.
OPTIMIZATION RESULTS
STATIC:
56.94% power efficient than RCA
39.7% power efficient than CLA
14.48% less delay than RCA

DYNAMIC:
38.58% less delay than CLA
79.52% power efficient than RCA
CONCLUSION
• An energy efficient hybrid adder was studied.

• Comparison of 8 bit, 16 bit with existing


adders to the hybrid adder, targeting high
frequencies showed less energy consumption
was studied.
Thank you

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