IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 65, NO.

6, JUNE 2018 1239

Proposing a Solution for Single-Event Upset

in 1T1R RRAM Memory Arrays
Amr M. S. Tosson , Shimeng Yu, Member, IEEE, Mohab H. Anis, Member, IEEE, and Lan Wei, Member, IEEE

Abstract— Resistive random access memory (RRAM) is a

promising emerging technology to provide nonvolatile and scal-
able data storage in advanced technologies. As a noncharge-based
device, the intrinsic RRAM device is immune to single-event
effects. However, single-event upset (SEU) due to the MOSFET
in the one-transistor-one-RRAM (1T1R) array can be observed.
A novel methodology, which can be easily integrated to the other
memory system components, is proposed in this paper to detect
and correct SEU in 1T1R RRAM memory array. Using the
HfO x 1T1R RRAM array as an example, our simulation results
show that, for an 8-Gb memory array, the proposed technique
can detect and fix the soft errors induced by the heavy ion
strikes with 0.66% increase in the chip area. Also, the suggested
methodology minimally increases the energy consumption of the
read and write operations by 0.2% and 0.1%, respectively.
Index Terms— Heavy ions, nonvolatile memory, resistive ran-
dom access memory (RRAM) one-transistor-one-RRAM (1T1R)
array, single-event upset (SEU), soft errors.

I. I NTRODUCTION

W ITH the technology advancement, the interest in incor-

porating nonvolatile memories in different designs
increases due to their ability of retaining data in the absence
Fig. 1. RRAM device. (a) Device structure and its circuit symbol.
(b) 3-D integration of the RRAM in the contact vias of the MOSFET device
(1T1R cell layout) [15]. (c) I–V characteristics curve of the RRAM device.
of power supply [1]–[3]. To provide a highly granular power
efficient solution, very dense memory arrays need to be
device has a metal–oxide–metal structure with the transitional
employed. Such high-capacity memory arrays can be used
oxide material (e.g., HfO2 , TiO2 , etc.) containing oxygen
to implement fast yet low-power crossbar arrays, which are
vacancies which create the conductive filaments in the oxide
required for large connectivity networks incorporated in field-
material between the metallic electrodes. In the case of
programmable gate arrays (FPGA) [4]–[6] and neuromorphic
HfOx RRAM device, applying a voltage >1.3 V between
systems [7]–[10].
P and N terminals of the RRAM device generates more oxygen
Resistive random access memory (RRAM) device has
vacancies, which spawn more conductive filaments. Hence,
many attractive features including its compact size, fast
the resistance between the electrodes decreases to its LRS
switching speed, low programming voltage, ease of inte-
(typical resistance is in the order of 10 K and below).
gration with the CMOS fabrication process, and high ratio
This is also known as SET process. Oppositely, the RESET
between its high-resistive state (HRS) and low-resistive
process is about applying a voltage >1.4 V from N to P
state (LRS) [11]–[14]. Fig. 1 shows the basic structure of
terminal of the device. Accordingly, oxygen vacancies are
the RRAM device and its I–V characteristics. The RRAM
pushed away from the top electrode increasing the device
Manuscript received September 11, 2017; revised October 20, 2017; resistance to its HRS (typical resistance is in the order
accepted November 6, 2017. Date of publication April 27, 2018; date of of 100 K and above). Due to their simple structure and
current version June 13, 2018.
A. M. S. Tosson, M. H. Anis, and L. Wei are with the Department low programming voltages, RRAM devices can be integrated
of Electrical and Computer Engineering, University of Waterloo, Waterloo, within the metal layers or within the contact vias to the source
ON N2L 3G1, Canada (e-mail: [email protected]; [email protected]; and/or drain of a metal–oxide–semiconductor field effect tran-
[email protected].)
S. Yu is with the Department of Electrical and Computer Engineering, sistor (MOSFET) [14]–[17] forming the one-transistor-one-
Arizona State University, Tempe, AZ 85281 USA (e-mail:shimeng.yu@ RRAM (1T1R) memory cell illustrated in Fig. 1(b).
asu.edu). Despite its intrinsic immunity to single-event effect (SEE),
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. the data of 1T1R cell can be unintentionally changed due to
Digital Object Identifier 10.1109/TNS.2018.2830791 the heavy ion strikes on the junction of the MOSFET access
0018-9499 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1240 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 65, NO. 6, JUNE 2018

transistor [12], [18]. Heavy ions can create enough voltage

drop across the RRAM devices in the half-select 1T1R cells
triggering the change in their saved data. Once detected, those
soft errors can be fixed by rewriting the original data. In this
paper, a novel methodology, which can be easily integrated to
the other 1T1R memory system components, is proposed to:
1) detect when the heavy ion strikes cause a change in the
RRAM data and 2) recover the information originally saved
on the affected cell.
The rest of this paper is organized as follows. In Section II,
a brief description is provided on how the heavy ions strikes
can toggle the data of the 1T1R array. Following this,
in Section III, the proposed methodology to detect and fix
SEE is explained. Then, the required circuit modifications to
support the suggested methodology is detailed in Section IV.
After this, the conducted simulation results to validate our
proposal are detailed in Section V. Finally, in Section VI,
Fig. 2. Example of SEU scenario in a half-select 1T1R cell sharing the same
the various discussions are concluded. BL bias voltage as fully select cell undergoing a SET operation. The current
source in the figure models the SEU effect caused by the electron–hole pairs
generated by the heavy ions strikes [12].
II. E FFECTS OF H EAVY I ON S TRIKES ON THE 1T1R C ELL
Highly energetic heavy ions are mainly generated by cosmic
rays [19]. Depending on the energy of the striking particles, the half-select cells, one of the terminals of the RRAM
the saved information in the memory cell can either switch device is connected to a high potential while the other is
directly to the opposite logic state (i.e., from logic “1” to left floating. In such scenario, SEU can occur.
logic “0” or vice versa) or change to an unidentified logic Fig. 2 illustrates the bias voltages of half-select cell whose
level. For the 1T1R HfOx RRAM array, logic “1” or “0” RRAM device is at HRS. This cell shares the same BL as
refers to the resistive state of the RRAM device when it is at a fully select cell undergoing a SET operation. Heavy ion
LRS (≤10 K) or HRS (≥100 K), respectively. Single-event strike with enough energy at node N generates electron–hole
upsets (SEUs) define the case when the energy of the striking pairs at the MOSFET junction which causes a current to
particles is high enough to directly toggle the data of the flow to the substrate reducing the potential at node N
memory cell from LRS to HRS or vice versa. For the case to −0.7 V (the threshold voltage of the drain-substrate
of intermediate changes in the saved data of the 1T1R cell, p-n junction) [12], [18]. Hence, the RRAM device of the
multiple strikes must occur to completely flip the logic state of half-select cell switches to LRS since the voltage applied on
the memory cell from one state to the other. Those soft errors it is >1.3 V (3.2 V).
are classified as multiple-event upsets (MEUs) [12], [18]. During the read operation, SEE cannot occur. This is
Based on the detailed analysis and experimental results because, by precharging the BL to a relatively small voltage
in [12] and [18], the 1T1R cells, during the write operation, (typically around 0.5 V), even if heavy ion strikes occur,
can be classified as follows. the voltage drop across the RRAM device will not be high
• Fully select cells are the cells which are intended to enough to cause changes in its resistive state.
change through the write operation. SEU cannot be To automatically detect and fix the MEU in the half-select
observed due to the bias conditions of the cell where the cells of the 1T1R array, a refresh circuit, similar to the one
access transistor is turned on and one of the terminals in [20], can be used. However, in the case of SEU, there are no
of the RRAM device is connected to ground. (Select- previous works discussing how it can be detected and fixed.
line (SL) is connected to ground during SET process In this paper, a new methodology is proposed to repair the SEU
while bitline (BL) is connected to ground during RESET induced by the heavy ions strikes in the half-select 1T1R cells
operation.) Hence, any generated charges will flow to the during the write operation.
ground without impacting the voltage across the RRAM
device. III. P ROPOSED M ETHODOLOGY FOR D ETECTING AND
• Unselected cells are the cells which are not intended to F IXING S INGLE -E VENT U PSET
change by the write process and they do not share any of The proposed methodology to detect and fix SEU in
control signals with the fully select cells. The unselected the 1T1R RRAM arrays consists of two parts: First part is
1T1R cells are not susceptible to SEU since the voltages related to modifying the memory cell itself and the second
on the terminals of the RRAM devices are not high part is about the required changes in the read circuit to work
enough (<1.2 V) to change their states. with the newly suggested cell design. In this section, the newly
• Half-select cells are the cells which are not intended to proposed structure of the memory cell is explained. Fig. 3
change by the write operation but share one or more of illustrates the schematic of the proposed 1T2R cell. Other than
the control lines with the fully select cells. In the case of the RRAM device of 1T1R cell storing the data (cellRRAM
TOSSON et al.: PROPOSING A SOLUTION FOR SEU IN 1T1R RRAM MEMORY ARRAYS 1241

Fig. 3. Schematic of the 1T2R cell.

Fig. 5. Four possible scenarios for the half-select cells during the write
operation. (a) Case 1. (b) Case 2. (c) Case 3. (d) Case 4.

The increase in the cell area depends on three main foundry

fabrication constraints (i.e., design rules) indicated in Fig. 4
by the markers “d1,” “d2,” and “d3.” “d1” represents the
minimum space between the metal layers used for routing the
control signals SL and WE. “d2” describes the minimum area
of the via layer, while “d3” determines the minimum overlap
of the diffusion layer around the via. Design rules “d1,” “d2,”
Fig. 4. Layout of the proposed 1T2R cell (1T2R). Using a 65-nm PDK, and “d3” are not special for the RRAM device but they are
the RRAM device is integrated between metal levels 4 and 5 (M4 and M5 in
the figure). Lower layers of metal (M1 and M2) are omitted for simple related to the basic foundry design rules guaranteeing the cor-
illustration. rect fabrication of the given patterns for the vias (i.e., RRAM
device) [22]. For a 65-nm process design kit (PDK) with
in Fig. 3), another RRAM device (senseRRAM) is added to seven-routing metal layers, the RRAM device is integrated
detect SEU. By reading the senseRRAM state, it can be easily between the fourth and fifth metal routing levels, respectively.
detected whether the cellRRAM data has been changed by The lower level metal layers are not shown in Fig. 4 to keep
SEU or not. Initially, the senseRRAM is at HRS to minimize the figure clear. Also, to establish the opposite connectivity
its impact on the read and write operations but it switches to to the source of MOSFET device for the senseRRAM and
LRS only when SEU occurs. To control the change in the state cellRRAM devices, instead of depositing HfO2 then Hf layer
of the senseRRAM, an extra column signal write enable (WE) as in the case of cellRRAM, the Hf layer for the senseRRAM
is connected to its “P” terminal (i.e., all the cells in the same is deposited before the HfO2 layer [14], [18]. Using the design
columns share this extra WE control signal). Also, compared rules available in the PDK, the area of the 1T2R cell is 18%
to the 1T1R cell in Fig. 2, the cellRRAM of the 1T2R cell larger compared to the 1T1R cell.
is connected to the SL control line instead of BL to read the There are four cases by which the heavy ion strikes can
state of the senseRRAM independently of that of cellRRAM change the voltage across the RRAM device of the half-select
during the same read operation. In addition to this, having the cells in the following.
WE and BL/SL signals independent of each other gives the • Case 1: RRAM of the half-select cell is at LRS during
opportunity to electroform the cellRRAM and senseRRAM SET operation on the corresponding fully select cell.
separately using a methodology similar to the one described • Case 2: RRAM of the half-select cell is at HRS during
in [21]. SET operation on the corresponding fully select cell.
Fig. 4 illustrates the typical layout for the 1T2R cell. The • Case 3: RRAM of the half-select cell is at LRS during
RRAM device is integrated between the metal layers for RESET operation on the corresponding fully select cell.
3-D integration [14]–[16]. Using W/L ratio of 3, to lower • Case 4: RRAM of the half-select cell is at HRS during
the required programming voltages for the SET operation of RESET operation on the corresponding fully select cell.
the 1T2R [12], the width and length of the channel of the Fig. 5 illustrates the four possible cases for the half-select cell
access nMOS device (WnMOS and L nMOS in Fig. 4) are chosen with the different write operation modes (SET, RESET) with
to be 195 and 65 nm, respectively. Also, the size of the RRAM the biasing voltages for the wordline (WL), BL, and SL in the
device is 105 nm × 120 nm. various scenarios.
1242 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 65, NO. 6, JUNE 2018

TABLE I
S UMMARY OF THE V OLTAGE A CROSS THE SENSE RRAM AND CELL R-
RAM FOR THE D IFFERENT S CENARIOS OF THE H ALF -S ELECT C ELLS
A SSUMING H IGHLY E NERGETIC H EAVY I ONS ARE I NCIDENT ON
THE 1T2R C ELL

Fig. 6. Waveforms of the control signals for the half-select cells in case 3.
The numbers in the figure represent the sequence of the operations performed.

A. Impact of Heavy Ions Strikes in Cases 1 and 2

In cases 1 and 2, the half-select cell shares the same high
potential voltage of the BL as the cell which undergoes a SET
operation. As both WE and SL are grounded, the voltage drop
across the cellRRAM and senseRRAM is not high enough to
trigger any change in their states (i.e., no SEU can occur). Fig. 7. Waveforms for the read operation with the proposed methodology.
The numbers in the figure show the sequence of operations in two regions of
the read process: upset detection region and normal read region.
B. Impact of Heavy Ions Strikes in Cases 3 and 4
In cases 3 and 4, the half-select cell shares the same high
potential voltage of WL and SL as those for the fully select Table I summarizes the voltages across the cellRRAM and
cells undergoing the RESET operation. As for the BL voltage the senseRRAM for the four cases of the half-select cells
of the half-select cells, it is connected to VDD/2 to prevent assuming highly energetic heavy ions strikes are incident on
them from being programmed. In those scenarios, a read the 1T2R cell. The voltage of WE signal for each of the four
operation is required for all the cells sharing the WL and SL cases is also listed in Table I.
lines.
Fig. 6 illustrates the waveforms describing the sequence of
C. Impact of the Proposed Methodology on the
operation for cases 3. The sequence of steps in Fig. 6 is as
Write Operation
follows.
1) A read operation is initiated by charging the BL to Due to the HRS of the senseRRAM, the delay and energy
VDD while the WE signal is disconnected from the consumption of the 1T2R memory remains practically the
cell and kept floating. Since the cellRRAM in case 3 is same as that of the 1T1R. However, by increasing the voltage
at LRS, the BL discharges to a small voltage close to of WE during the RESET process in case 3, the delay and
ground(≈ 0.2 V). energy consumption of the RESET operation also increases.
2) The proper voltage of the signal WE is set as the inverted
version of the BL voltage after the read operation. D. Impact of the Proposed Methodology on the
3) If heavy ion strikes occur in case 3, the cellRRAM Read Operation
switches from its LRS to its HRS while the senseRRAM The read cycle is divided into two regions as illustrated
changes from its HRS to its LRS since the voltage drop in Fig. 7. In the first region (upset detection region), only the
across both of the RRAM devices is high enough to senseRRAM state is read by connecting the WE to ground
change in their states as listed in Table I. In case 4, while disconnecting the SL. The BL discharges to a low
the voltage drop across the senseRRAM is around 0.7 V voltage when senseRRAM is at LRS which (i.e., SEU has
(VDDWE = 0 V since the cellRRAM is at HRS). As for occurred) while it remains at VDD otherwise.
the cellRRAM in case 4, since it is already at HRS, any When the voltage of BL is at VDD (step 1), the read
heavy ions strike causes no change in its state. operation proceeds to the normal read region. The cellRRAM
Accordingly, case 3 is the only case which is affected by resistance is sensed by disconnecting the WE and connecting
SEU resulting from heavy ion strikes. the SL to ground (step 2). The BL drops to a low potential
TOSSON et al.: PROPOSING A SOLUTION FOR SEU IN 1T1R RRAM MEMORY ARRAYS 1243

Fig. 8. Architecture of the modified read circuit.

voltage since the cellRRAM, in this example, is assumed to

be at LRS.

IV. R EQUIRED M ODIFICATIONS TO THE R EAD C IRCUITRY Fig. 9. Schematic of the UDU circuit.

To support the change in the read and RESET operations of

the 1T2R cell, the read circuit is required to be modified. Fig. 8
shows the schematic of the newly proposed read circuit. Other
than the standard read circuit, i.e., Read Unit (RU) in Fig. 8,
two main components are added to it as follows.
• Upset Detection Unit (UDU) checks the state of the
senseRRAM. The signal “EN_SENSE” is used to enable
the sense amplifier of this unit.
• WE Generation Unit (WGU) sets the appropriate bias
for the WE signal during the write operation. The
“connect_WE” signal is used to control when to con-
nect/disconnect the WE signal during the read operation.
Fig. 10. Schematic of the WGU circuit.
The sequence of operations for the suggested read circuit
in Fig. 8 can be summarized as follows.
1) The senseRRAM state is read by the UDU. The A. UDU Circuit
“UPSET” signal is raised to VDD when the senseRRAM The UDU circuit is a latch-based sense amplifier which has
is at LRS (i.e., SEU has occurred). In this case, the read the structure shown in Fig. 9 [23].
operation ends and a SET operation is initiated to The reference voltage (Vref ) is chosen to correspond to the
restore the states of the senseRRAM and the cellRRAM voltage of the RRAM device when it is at the upper resistance
(i.e., senseRRAM to HRS and cellRRAM to LRS). limit of its LRS. Based on the studies conducted in [24]–[26]
2) The enable signal “EN_RU” is set to VDD when the for the HfOx RRAM device, Vref is chosen to be 0.65 V.
senseRRAM is at HRS to activate the RU. The RU has To enable the sense amplifier, the “EN_sense” signal
two modes of operations. in Fig. 9 should be raised to VDD (i.e., 1.2 V) to
compare the BL voltage (VBL ) with Vref . When VBL > Vref
• Normal Read Operation: In this mode, the read
(i.e., the resistance of senseRRAM is at higher state than its
process is terminated after sensing the state of the
LRS), the signal “EN_RU,” which enables the RDU unit, is set
cellRRAM.
to VDD while the “UPSET” signal is connected to ground.
• RESET Read Operation: In this mode, the
Oppositely, when VBL <Vref , “UPSET” is raised to logic “1”
cellRRAM state is read first before initiating
indicating the occurrence of SEU since the senseRRAM is at
the RESET process to set the right bias of
LRS. In this case, the read operation is suspended until the
the WE signal. The signal “LRS_CELLRAM”
cellRRAM and senseRRAM state are restored to LRS and
in Fig. 8 is used to enable the WGU unit. The
HRS, respectively.
“LRS_CELLRRAM” signal is raised to logic “1”
when the cellRRAM is at LRS. Accordingly,
the voltage of WGU is set to VDDWE . Otherwise, B. WGU Circuit
the WE signal is grounded for any other write Fig. 10 illustrates the schematic of the WGU circuit.
operation. The circuit structure in Fig. 10 consists of two main parts.
1244 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 65, NO. 6, JUNE 2018

• cellRRAM detection part is a D-Latch which stores the

state of LRS_cellRRAM signal from the RU unit. The
D-Latch is enabled through the control signal “R/W̄ ”
which is set to VDD/ground whenever a read/write
operation is initiated. When the cellRRAM is at LRS,
the output signal “ Q̄” is at 0 V and vice versa.
• Control part is responsible of setting the right bias
voltage to the WE signal.
The control part of WGU consists of a three-input NOR gate
whose inputs are: 1) the output from cellRRAM detection part;
2) a down-graded version of the BL voltage through a two
diode connected nMOS devices to scale the BL voltage during
the SET operation; and 3) the same “R/W̄ ” control signal Fig. 11. Effect of VDDWE voltage on the correctness of our proposed
used for the cellRRAM detection part to distinguish between methodology in detecting the upset events.
read and write operations. The enable signal “connect_WE”
connects the WE signal during the read operation. The inset
in Fig. 10 shows the CMOS structure of the three-input NOR
electron charge and G is the rate of generation of electron–hole
gate. For the write operation, the signal “connect_WE” is set
pairs which is a function of the incident LET. The values
to high voltage (i.e., VDDWE ) to attach the pull-down and
of x j , L e , A, and the equation of G are taken from the work
pull-up networks of the NOR gate. Hence, in case if: 1) the
in [12]
cellRRAM device is at LRS ( Q̄ is at logic “0”); 2) the BL
is not at high potential voltage indicating a RESET operation I ph = q ∗ A ∗ G ∗ (x j ∗ L e ). (1)
is initiated; and 3) a write operation is initiated (R/W̄ is at
logic “0”), the WE voltage is raised to VDDWE . Otherwise, A. Selection of the High Voltage of the WE Signal (V D DW E )
the WE signal is connected to 0 V during the write operation.
To study the effect of the voltage VDDWE on the operation
As for the read operation, when the cellRRAM state is read,
of the 1T2R cell, different voltage levels are applied on the
the “connect_WE” signal is grounded to set the WE voltage
WE signal. For each of the voltage levels, two experiments
to high-impedance state (i.e., floating state) as illustrated in
are conducted as follows.
the “Normal Read” region in Fig. 7.
• Heavy ions with LET greater than or equal to threshold
V. S IMULATION R ESULTS LET (≤4 MeV · cm2 /mg for the HfOx 1T1R array [18])
The simulation setup in this paper is based on the results are assumed to be incident on the half-select cells
published in [12] and [18]. In [18], various laboratory exper- susceptible to SEU (case 3 in Table I).
iments and simulations are run to understand the root causes • Estimate the delay and energy consumption of the RESET
for the SEE in 1T1R memory arrays. Using the experimental operation with the WE voltage set to VDDWE .
results in [18], Liu et al. [12] propose a SPICE model which Fig. 11 demonstrates how the VDDWE voltage impacts
describes the effect of electron–hole generation due to SEE. the change in the senseRRAM of the half-select cells
In our analysis, the SPICE model in [12] is used while consid- in response to SEU. The “Min cellRRAM LET” and
ering the LRS and HRS range of the HfOx RRAM device to “Min senseRRAM LET” curves in Fig. 11 refer to the
be <20 K and >200 K, respectively. Changing the RRAM minimum threshold LET required for the cellRRAM
device integrated in the 1T2R memory array or changing the and senseRRAM to change their states, respectively. For
voltages used in the memory system could alter the HRS–LRS heavy ions strikes with LET ≥4 MeV · cm2 /mg, both the
resistance range. However, this does not change the main senseRRAM and cellRRAM of the half-select cells will unin-
concepts behind the design proposed in this paper or the tentionally change their state. When VDDWE is set to 1 V,
generality of the simulation results discussed in this section. the senseRRAM device of the half-select cells will switch
The detailed results for the modified memory array can be from its HRS to LRS, indicating that SEU has occurred, only
obtained by repeating the experiments in this paper with the for LET ≥3.85 MeV · cm2 /mg. Yet, the cellRRAM state will
adjusted voltage levels. In addition to this, to calculate the change from LRS to HRS for LET as low as 0.5 MeV·cm2 /mg.
threshold linear energy transfer (LET) for the incident heavy By increasing VDDWE to a voltage close to that of SL
ions which can cause SEU, the same methodology in [12] (1.9 V in our example), the difference between the minimum
is adopted. The threshold LET is computed by considering threshold LET causing the cellRRAM and senseRRAM to
the case when the LET of the incident heavy ions is high switch their states becomes smaller.
enough to cause the resistance of the cellRRAM to change However, Fig. 12 demonstrates that increasing VDDWE
from 20 to 200 K. Equation (1) [12] is used to model the can negatively impact the delay and energy consump-
generated current at MOS junction due to the heavy ions tion of the RESET process. The “Orig.Write Delay” and
strikes. The parameters x j , L e , and A describe the junction “Orig.Write Energy” curves refer to the delay and energy
depth, the electron diffusion length, and the area of the MOS consumption of the RESET process for the conventional 1T1R
junction subject to heavy ions strike, respectively. q is the cell.
TOSSON et al.: PROPOSING A SOLUTION FOR SEU IN 1T1R RRAM MEMORY ARRAYS 1245

TABLE II
C OMPARISON OF THE W RITE P ERFORMANCE FOR THE C ONVENTIONAL
1T1R AND 1T2R 128 × 128 A RRAY

current drive of the transistor. For a fixed programming pulse

Fig. 12. Effect of VDDWE voltage on the performance of the RESET process. (10 ns in [12], [18], and [28]), the portion of this pulse, during
which both of the RRAM devices are at HRS, increases.
By consequence, the amount of current drawn from the BL
The increase in the delay is caused by the current injected during the fixed programming pulse has decreased leading to a
by WE signal which combats the programming current from reduction in the energy consumption. The fixed pulse duration
the SL signal. The stronger the WE current the longer is the is required to account for the delay introduced by the wire
time required to complete the RESET process. capacitance in the memory array [12], [18], [28].
Due to: 1) the extension in the duration of the RESET Oppositely, for the RESET operation, since the time, during
operation and 2) the increase in the total current drawn from which the cellRRAM is at LRS, is prolonged, the energy
the control signals WE and SL, the average energy consumed consumption increases.
during RESET also increases. In order to minimize the impact of the read process initiated
Based on the results shown in Figs. 11 and 12, the biasing before RESET operation, the size of the macro memory array
voltage of WE is set to 1.5 V as a compromise between is reduced from 1024 × 1024 to 128 × 128, as in [12].
minimizing the impact of the WE signal on the RESET Accordingly, the required write pulsewidth decreases to
process and guaranteeing a correct operation of the proposed almost 6.4 ns and the delay of the write process, together
methodology. Choosing the VDDWE voltage to be at 1.5 V with extra read operation, can remain as 10 ns. Taking into
results in reducing the difference between the minimum account the read operation before RESET, the write energy
required LET for the incident particles to switch the state of for a 128 × 128 array is increased by 19% due to the extra
cellRRAM and senseRRAM to ≈0.09 MeV · cm2 /mg. Such WGU and UDU units added to the read circuit. However,
small difference in the LET of the heavy ion strikes does not when the 128 × 128 macro is integrated in the design of 8-Gb
impact our design since the senseRRAM still changes toward memory, the net increase in the energy consumption for the
LRS (≈25 K compared to 200 k at HRS). write operation is less than 0.2% due to the overhead of the
other memory components such as the address decoders and
B. Simulation Results for the Write Operation the repeaters.
Using a 65-nm PTM model [27] and W/L ratio of 3 (to lower
the required programming voltages for the SET operation of C. Simulation Results for the Read Operation
the 1T2R [12]), the SET and RESET biasing conditions are The period of read operation in our proposed methodology
as follows: is divided into: Upset Detection period (TUD ) and Normal
• SET Operation: WL = 3.0 V, BL = 2.5 V, SL = 0 V; Read period (Tnorm ). Longer TUD is required in order to
• RESET Operation: WL = 3.0 V, BL = 0 V, SL = 1.9 V. have better separation between the read voltage levels for the
The SET operation uses a higher voltage biasing conditions different states of the senseRRAM. Yet, Fig. 13 shows that
to account for the voltage drop across the nMOS transistor of increasing TUD can rapidly increase the energy consumption
the memory cell [12]. However, a read operation precedes the specially if SEU occurs (i.e., senseRRAM is at LRS).
initiation of the RESET process to set the voltage of the WE The Vsense curve in Fig. 13 defines the difference between
signal. In this section, the performance of the write operation the read voltage on the BL when the senseRRAM is at
is studied after the voltage of WE signal is set. HRS and when it is at LRS. Based on the results illustrated
Table II summarizes the comparison results between the per- in Fig. 13, the duration of TUD is set to 1 ns since the minimum
formance of the write operation for the conventional 1T1R [28] sensing voltage difference should be in the range between
and for the new 1T2R cell for a 128 × 128 array. For 0.02 and 0.1 V for a bulk CMOS technologies [29].
the SET operation, since the WE voltage is connected to Our SPICE simulation results show that, for
ground, the programming current drawn from BL is divided a 128 × 128 memory array, the energy consumption of
between the cellRRAM and senseRRAM devices which both the newly proposed read circuit design increases the energy
are at HRS. Accordingly, the voltage at the MOSFET junction consumption by only 18% (compared to the design in [20]
connected to RRAM devices increases which lowers the which heps resolving the MEU in a conventional 1T1R
1246 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 65, NO. 6, JUNE 2018

Fig. 13. Impact of increasing the TUD on detecting the change in the Fig. 15. System-level simulation for the impact of the proposed technique
senseRRAM state. Read Energy curve is calculated assuming worst case when on the chip area of various memory arrays with different capacities.
the senseRRAM is at LRS.

the other peripheral circuits (address decoders, Multiplixers,

repeaters, . . .) of the memory system. Hence, the smaller the
size of the memory array, the higher will be the increase in
the energy consumption. Although more peripheral circuits
are used compared to the case of 1T1R array in [20] (since
the memory macro block size decreases from 1024 × 1024
to 128×128), the increase in energy and delay is still minimal
due the decrease in the duration of the write pulse from
10 to 6.4 ns.
By modifying the area calculation for the sense amplifier
and the cell dimensions in the area class of the
CACTI C++ files, Fig. 15 shows the CACTI simulation
Fig. 14. System-level simulation for the impact of the proposed technique on results for the estimated percentage of increase in the
the energy consumption of various memory arrays with different capacities. chip area. Fig. 15 demonstrates that the increase in the
chip area is about 0.66% for an 8-Gb array since the contribu-
tion from the other memory components (decoders, repeaters,
design). This is due to: 1) the reduction in the duration of
and etc.) in the area calculation is much higher than that
Tnorm from 3 to 2 ns which reduces the current discharging
resulting from the read circuit updates. The increase in the
the BL during the read cycle; 2) the small current passing
chip area grows with the decrease in the memory capacity
through the senseRRAM during TUD since it is at HRS; and
due to the reduced effect of the other peripheral circuits on
3) the impact of the WGU on the increase of the read energy
the area computation.
consumption is minimal (<2%).
It is worth mentioning that having more sensitive peripheral
circuits to SEE require deploying more radiation-hardening
D. System-Level Simulation Results techniques. On the system level, using error correction codes
Using the CACTI C++ files [30] and the results for to detect and fix the induced soft errors is required [31], [32].
the write and read operations for the 128 × 128 memory On the circuit level, many techniques can be incorporated
block, the impact of the newly proposed methodology on the including the usage of radiation tolerant technologies such as
performance of various memory arrays is studied. The main fully depleted silicon on insulator (FDSOI) [33]. Although
modifications to the C++ files are in the following. using the FDSOI can increase the tolerance of the 1T2R
• Change the write pulse 6.4 ns instead of 10 ns.
cell up to 50 MeV · cm2 /mg [33], if the 1T2R memory
• Account for the energy consumption and delay for the
array is deployed in applications subject to higher radiations,
read operation before the RESET process our proposed methodology for detecting and fixing SEU
• Split the read operation into two separate regions
will still be needed. As for the the peripheral circuits, their
(i.e., Upset detection regions and Normal read regions) layout can be also modified to account for SEE as discussed
and compute the energy consumption of each process in [34] and [35].
separately then combining them.
Fig. 14 shows that, for a 1T2R memory array as large as 8 Gb, VI. C ONCLUSION
the increase in the energy consumption is only 0.2% and 0.1% In this paper, a novel methodology, which can be easily inte-
for the read and write operations, respectively, compared to grated to the other memory system components, is discussed
the results of a conventional 1T1R memory array. The small to detect and fix SEU in the 1T1R RRAM memory arrays.
energy increase is caused by the high energy overhead from The proposed technique is based on adding an extra RRAM
TOSSON et al.: PROPOSING A SOLUTION FOR SEU IN 1T1R RRAM MEMORY ARRAYS 1247

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